The native Linux/GNU toolchain also supports the value ‘ native ’, which selects the best architecture option for the host processor. -march=native has no effect if GCC does not recognize the processor.
In processor names, a final ‘ 000 ’ can be abbreviated as ‘ k ’ (for example, -march=r2k ). Prefixes are optional, and ‘ vr ’ may be written ‘ r ’.
Names of the form ‘ n f2_1 ’ refer to processors with FPUs clocked at half the rate of the core, names of the form ‘ n f1_1 ’ refer to processors with FPUs clocked at the same rate as the core, and names of the form ‘ n f3_2 ’ refer to processors with FPUs clocked a ratio of 3:2 with respect to the core. For compatibility reasons, ‘ n f ’ is accepted as a synonym for ‘ n f2_1 ’ while ‘ n x ’ and ‘ b fx ’ are accepted as synonyms for ‘ n f1_1 ’.
GCC defines two macros based on the value of this option. The first is
, which gives the name of target architecture, as a string. The second has the form
, where foo
is the capitalized value of
. For example,
and defines the macro
Note that the
macro uses the processor names given above. In other words, it has the full prefix and does not abbreviate ‘
’ as ‘
’. In the case of ‘
’, the macro names the resolved architecture (either
). It names the default architecture when no
option is given.
When this option is not used, GCC optimizes for the processor specified by -march . By using -march and -mtune together, it is possible to generate code that runs on a family of processors, but optimize the code for one particular member of that family.
defines the macros
, which work in the same way as the
ones described above.
MIPS16 code generation can also be controlled on a per-function basis by means of
attributes. See Function Attributes
, for more information.
For example, code using the standard ISA encoding cannot jump directly to MIPS16 or microMIPS code; it must either use a call or an indirect jump.
therefore disables direct jumps unless GCC knows that the target of the jump is not compressed.
Note that the EABI has a 32-bit and a 64-bit variant. GCC normally generates 64-bit code when you select a 64-bit architecture, but you can use -mgp32 to get 32-bit code instead.
For information about the O64 ABI, see http://gcc.gnu.org/projects/mipso64-abi.html .
GCC supports a variant of the o32 ABI in which floating-point registers are 64 rather than 32 bits wide. You can select this combination with
. This ABI relies on the
instructions and is therefore only supported for MIPS32R2, MIPS32R3 and MIPS32R5 processors.
The register assignments for arguments and return values remain the same, but each scalar value is passed in a single 64-bit register rather than a pair of 32-bit registers. For example, scalar floating-point values are returned in ‘ $f0 ’ only, not a ‘ $f0 ’/‘ $f1 ’ pair. The set of call-saved registers also remains the same in that the even-numbered double-precision registers are saved.
Two additional variants of the o32 ABI are supported to enable a transition from 32-bit to 64-bit registers. These are FPXX (
) and FP64A (
). The FPXX extension mandates that all code must execute correctly when run using 32-bit or 64-bit registers. The code can be interlinked with either FP32 or FP64, but not both. The FP64A extension is similar to the FP64 extension but forbids the use of odd-numbered single-precision registers. This can be used in conjunction with the
mode of FPUs in MIPS32R5 processors and allows both FP32 and FP64A code to interlink and run in the same process without changing FPU modes.
All -mabicalls code has traditionally been position-independent, regardless of options like -fPIC and -fpic . However, as an extension, the GNU toolchain allows executables to use absolute accesses for locally-binding symbols. It can also use shorter GP initialization sequences and generate direct calls to locally-defined functions. This mode is selected by -mno-shared .
-mno-shared depends on binutils 2.16 or higher and generates objects that can only be linked by the GNU linker. However, the option does not affect the ABI of the final executable; it only affects the ABI of relocatable objects. Using -mno-shared generally makes executables both smaller and quicker.
is the default.
You can make
the default by configuring GCC with
. The default is
GCC normally uses a single instruction to load values from the GOT. While this is relatively efficient, it only works if the GOT is smaller than about 64k. Anything larger causes the linker to report an error such as:
relocation truncated to fit: R_MIPS_GOT16 foobar
If this happens, you should recompile your code with -mxgot . This works with very large GOTs, although the code is also less efficient, since it takes three instructions to fetch the value of a global symbol.
Note that some linkers can create multiple GOTs. If you have such a linker, you should only need to use -mxgot when a single object file accesses more than 64k's worth of GOT entries. Very few do.
These options have no effect unless GCC is generating position independent code.
printfformats). If code compiled with -mno-float accidentally contains floating-point operations, it is likely to suffer a link-time or run-time failure.
neg.fmt machine instructions.
By default or when -mabs=legacy is used the legacy treatment is selected. In this case these instructions are considered arithmetic and avoided where correct operation is required and the input operand might be a NaN. A longer sequence of instructions that manipulate the sign bit of floating-point datum manually is used instead unless the -ffinite-math-only option has also been specified.
option selects the IEEE 754-2008 treatment. In this case these instructions are considered non-arithmetic and therefore operating correctly in all cases, including in particular where the input operand is a NaN. These instructions are therefore always used for the respective operations.
The -mnan=legacy option selects the legacy encoding. In this case quiet NaNs (qNaNs) are denoted by the first bit of their trailing significand field being 0, whereas signaling NaNs (sNaNs) are denoted by the first bit of their trailing significand field being 1.
The -mnan=2008 option selects the IEEE 754-2008 encoding. In this case qNaNs are denoted by the first bit of their trailing significand field being 1, whereas sNaNs are denoted by the first bit of their trailing significand field being 0.
The default is
unless GCC has been configured with
is useful if the runtime environment can emulate the instructions and
can be useful when compiling for nonstandard ISAs. You can make either option the default by configuring GCC with
is the default for some configurations; see the installation documentation for details.
__mips_dsp. It also defines
__mips_dspr2. It also defines
MicroMIPS code generation can also be controlled on a per-function basis by means of
attributes. See Function Attributes
, for more information.
longtypes to be 64 bits wide. See -mlong32 for an explanation of the default and the way that the pointer size is determined.
int, and pointer types to be 32 bits wide.
The default size of
s and pointers depends on the ABI. All the supported ABIs use 32-bit
s. The n64 ABI uses 64-bit
s, as does the 64-bit EABI; the others use 32-bit
s. Pointers are the same size as
s, or the same size as integer registers, whichever is smaller.
option depends on the configuration.
If the linker complains that an application is using too much small data, you might want to try rebuilding the less performance-critical parts with
. You might also want to build large libraries with
, so that the libraries leave more room for the main program.
If you compile a module Mod
, and Mod
references a variable Var
that is no bigger than num
bytes, you must make sure that Var
is placed in a small data section. If Var
is defined by another module, you must either compile that module with a high-enough
setting or attach a
attribute to Var
's definition. If Var
is common, you must link the application with a high-enough
The easiest way of satisfying these restrictions is to compile and link every module with the same
option. However, you may wish to build a library that supports several different small data limits. You can do this by compiling the library with the highest supported
setting and additionally using
to stop the library from making assumptions about externally-defined data.
is useful for cases where the
register might not hold the value of
. For example, if the code is part of a library that might be used in a boot monitor, programs that call boot monitor routines pass an unknown value in
. (In such situations, the boot monitor itself is usually compiled with
constvariables in the read-only data section. This option is only meaningful in conjunction with -membedded-data .
%lo()assembler relocation operators. This option has been superseded by -mexplicit-relocs but is retained for backwards compatibility.
is the default if GCC was configured to use an assembler that supports relocation operators.
The default is
SIGFPE). Use -mdivide-traps to allow conditional traps on architectures that support them and -mdivide-breaks to force the use of breaks.
The default is usually
, but this can be overridden at configure time using
. Divide-by-zero checks can be completely disabled using
memcpyfor non-trivial block moves. The default is -mno-memcpy , which allows GCC to inline most constant-sized copies.
jalinstruction. Calling functions using
jalis more efficient but requires the caller and callee to be in the same 256 megabyte segment.
This option has no effect on abicalls code. The default is
mulinstructions, as provided by the R4650 ISA.
msubinteger instructions. The default is -mimadd on architectures that support
msubexcept for the 74k architecture where it was found to generate slower code.
On the R8000 CPU when multiply-accumulate instructions are used, the intermediate product is calculated to infinite precision and is not subject to the FCSR Flush to Zero bit. This may be undesirable in some circumstances. On other processors the result is numerically identical to the equivalent computation using separate multiply, add, subtract and negate instructions.
scsequences may not behave atomically on revisions prior to 3.0. They may deadlock on revisions 2.6 and earlier.
This option can only be used if the target architecture supports branch-likely instructions.
is the default when
is the default otherwise.
dmultuerrata. The workarounds are implemented by the assembler rather than by GCC.
dmultudoes not always produce the correct result.
ddivdo not always produce the correct result if one of the operands is negative.
Other VR4120 errata require a NOP to be inserted between certain pairs of instructions. These errata are handled by the assembler, not by GCC itself.
mfhierrata. The workarounds are implemented by the assembler rather than by GCC, although GCC avoids using
mfhiif the VR4130
dmacchiinstructions are available instead.
In common with many processors, the R10K tries to predict the outcome of a conditional branch and speculatively executes instructions from the “taken” branch. It later aborts these instructions if the predicted outcome is wrong. However, on the R10K, even aborted instructions can have side effects.
This problem only affects kernel stores and, depending on the system, kernel loads. As an example, a speculatively-executed store may load the target memory into cache and mark the cache line as dirty, even if the store itself is later aborted. If a DMA operation writes to the same area of memory before the “dirty” line is flushed, the cached data overwrites the DMA-ed data. See the R10K processor manual for a full description, including other potential problems.
One workaround is to insert cache barrier instructions before every memory access that might be speculatively executed and that might have side effects even if aborted. -mr10k-cache-barrier= setting controls GCC's implementation of this workaround. It assumes that aborted accesses to any byte in the following regions does not have side effects:
It is the kernel's responsibility to ensure that speculative accesses to these regions are indeed safe.
If the input program contains a function declaration such as:
void foo (void);
then the implementation of
to be executed speculatively. GCC honors this restriction for functions it compiles itself. It expects non-GCC functions (such as hand-written assembly code) to do the same.
The option has three forms:
_flush_func, that is, the address of the memory range for which the cache is being flushed, the size of the memory range, and the number 3 (to flush both caches). The default depends on the target GCC was configured for, but commonly is either
The -mcompact-branches=never option ensures that compact branch instructions will never be generated.
The -mcompact-branches=always option ensures that a compact branch instruction will be generated if available. If a compact branch instruction is not available, a delay slot form of the branch will be used instead.
This option is supported from MIPS Release 6 onwards.
option will cause a delay slot branch to be used if one is available in the current ISA and the delay slot is successfully filled. If the delay slot is not filled, a compact branch will be chosen if one is available.
For instance, on the SB-1, if FP exceptions are disabled, and we are emitting 64-bit code, then we can use both FP pipes. Otherwise, we can only use one FP pipe.
This option only has an effect when optimizing for the VR4130. It normally makes code faster, but at the expense of making it bigger. It is enabled by default at optimization level
synciinstructions on architectures that support it. The
synciinstructions (if enabled) are generated when
This option defaults to -mno-synci , but the default can be overridden by configuring GCC with --with-synci .
When compiling code for single processor systems, it is generally safe to use
. However, on many multi-core (SMP) systems, it does not invalidate the instruction caches on all cores and may lead to undefined behavior.
$25into direct calls. This is only possible if the linker can resolve the destination at link time and if the destination is within range for a direct call.
is the default if GCC was configured to use an assembler and a linker that support the
assembly directive and
is in effect. With
, this optimization can be performed by the assembler and the linker alone without help from the compiler.
_mcountto modify the calling function's return address. When enabled, this option extends the usual
_mcountinterface with a new ra-address parameter, which has type
intptr_t *and is passed in register
_mcountcan then modify the return address by doing both of the following:
*ra-address , if ra-address is nonnull.
The default is
This optimization is off by default at all optimization levels.
sdxc1instructions. Enabled by default.
madd.dand related instructions. Enabled by default.