NXP LPC3200 CPU Support Package
2.4 (2021-11-08)
Fixed HCLKPLL_CTRL bitfield sizes in memory map and header files.
2.3 (2014-02-03)
Added samples.
Changed default debug handler for new projects to be None and added a coprocessor execute address property to enable VFP registers to be viewed.
Added OnConnect function to target script to enable ETM usage.
Changed default access to None for read-sensitive UART registers.
2.2 (2011-08-16)
Changed section placement files to support ARM EABI C++ exception scheme and thread local storage.
Corrected address of P0_INTR_ER in memory map and header files.
2.1 (2010-06-08)
Added (optional) support for saving VFP state on interrupt.
MMU TLB is now placed at the end of IRAM. The secondary boot loader executes at the end of IRAM hence allowing IRAM programs to be booted from NAND. The section placement files use a macro defined in the Target property group to determine the size of IRAM and as such you will need to reselect the Target if you have an existing project.
2.0 (2009-06-17)
Initial Release.