i386-Arch (Using as)

9.16.15 Specifying CPU Architecture

as may be told to assemble for a particular CPU (sub-)architecture with the .arch cpu_type directive. This directive enables a warning when gas detects an instruction that is not supported on the CPU specified. The choices for cpu_type are:

`default`	`push`	`pop`
`i8086`	`i186`	`i286`	`i386`
`i486`	`i586`	`i686`	`pentium`
`pentiumpro`	`pentiumii`	`pentiumiii`	`pentium4`
`prescott`	`nocona`	`core`	`core2`
`corei7`	`iamcu`
`k6`	`k6_2`	`athlon`	`k8`
`amdfam10`	`bdver1`	`bdver2`	`bdver3`
`bdver4`	`znver1`	`znver2`	`znver3`
`znver4`	`btver1`	`btver2`	`generic32`
`generic64`	`.cmov`	`.fxsr`	`.mmx`
`.sse`	`.sse2`	`.sse3`	`.sse4a`
`.ssse3`	`.sse4.1`	`.sse4.2`	`.sse4`
`.avx`	`.vmx`	`.smx`	`.ept`
`.clflush`	`.movbe`	`.xsave`	`.xsaveopt`
`.aes`	`.pclmul`	`.fma`	`.fsgsbase`
`.rdrnd`	`.f16c`	`.avx2`	`.bmi2`
`.lzcnt`	`.popcnt`	`.invpcid`	`.vmfunc`
`.monitor`	`.hle`	`.rtm`	`.tsx`
`.lahf_sahf`	`.adx`	`.rdseed`	`.prfchw`
`.smap`	`.mpx`	`.sha`	`.prefetchwt1`
`.clflushopt`	`.xsavec`	`.xsaves`	`.se1`
`.avx512f`	`.avx512cd`	`.avx512er`	`.avx512pf`
`.avx512vl`	`.avx512bw`	`.avx512dq`	`.avx512ifma`
`.avx512vbmi`	`.avx512_4fmaps`	`.avx512_4vnniw`
`.avx512_vpopcntdq`	`.avx512_vbmi2`	`.avx512_vnni`
`.avx512_bitalg`	`.avx512_bf16`	`.avx512_vp2intersect`
`.tdx`	`.avx_vnni`	`.avx512_fp16`
`.clwb`	`.rdpid`	`.ptwrite`	`.ibt`
`.prefetchi`	`.avx_ifma`	`.avx_vnni_int8`
`.cmpccxadd`	`.wrmsrns`	`.msrlist`
`.avx_ne_convert`	`.rao_int`
`.fred`	`.lkgs`
`.wbnoinvd`	`.pconfig`	`.waitpkg`	`.cldemote`
`.shstk`	`.gfni`	`.vaes`	`.vpclmulqdq`
`.movdiri`	`.movdir64b`	`.enqcmd`	`.tsxldtrk`
`.amx_int8`	`.amx_bf16`	`.amx_fp16`
`.amx_complex`	`.amx_tile`
`.kl`	`.widekl`	`.uintr`	`.hreset`
`.3dnow`	`.3dnowa`	`.sse4a`	`.sse5`
`.syscall`	`.rdtscp`	`.svme`
`.lwp`	`.fma4`	`.xop`	`.cx16`
`.padlock`	`.clzero`	`.mwaitx`	`.rdpru`
`.mcommit`	`.sev_es`	`.snp`	`.invlpgb`
`.tlbsync`

Apart from the warning, there are only two other effects on as operation; Firstly, if you specify a CPU other than i486, then shift by one instructions such as sarl $1, %eax will automatically use a two byte opcode sequence. The larger three byte opcode sequence is used on the 486 (and when no architecture is specified) because it executes faster on the 486. Note that you can explicitly request the two byte opcode by writing sarl %eax. Secondly, if you specify i8086, i186, or i286, and .code16 or .code16gcc then byte offset conditional jumps will be promoted when necessary to a two instruction sequence consisting of a conditional jump of the opposite sense around an unconditional jump to the target.

Note that the sub-architecture specifiers (starting with a dot) can be prefixed with no to revoke the respective (and any dependent) functionality.

Following the CPU architecture (but not a sub-architecture, which are those starting with a dot), you may specify jumps or nojumps to control automatic promotion of conditional jumps. jumps is the default, and enables jump promotion; All external jumps will be of the long variety, and file-local jumps will be promoted as necessary. (see i386-Jumps) nojumps leaves external conditional jumps as byte offset jumps, and warns about file-local conditional jumps that as promotes. Unconditional jumps are treated as for jumps.

For example

 .arch i8086,nojumps