9.43.3.2 Register Names

The Sparc integer register file is broken down into global, outgoing, local, and incoming.

Floating point registers are simply referred to as ‘ %f n ’. When assembling for pre-V9, only 32 floating point registers are available. For V9 and later there are 64, but there are restrictions when referencing the upper 32 registers. They can only be accessed as double or quad, and thus only even or quad numbered accesses are allowed. For example, ‘ %f34 ’ is a legal floating point register, but ‘ %f35 ’ is not.

Floating point registers accessed as double can also be referred using the ‘ %d n ’ notation, where n is even. Similarly, floating point registers accessed as quad can be referred using the ‘ %q n ’ notation, where n is a multiple of 4. For example, ‘ %f4 ’ can be denoted as both ‘ %d4 ’ and ‘ %q4 ’. On the other hand, ‘ %f2 ’ can be denoted as ‘ %d2 ’ but not as ‘ %q2 ’.

Certain V9 instructions allow access to ancillary state registers. Most simply they can be referred to as ‘ %asr n ’ where n can be from 16 to 31. However, there are some aliases defined to reference ASR registers defined for various UltraSPARC processors:

Various V9 branch and conditional move instructions allow specification of which set of integer condition codes to test. These are referred to as ‘ %xcc ’ and ‘ %icc ’.

Additionally, GAS supports the so-called “natural” condition codes; these are referred to as ‘ %ncc ’ and reference to ‘ %icc ’ if the word size is 32, ‘ %xcc ’ if the word size is 64.

In V9, there are 4 sets of floating point condition codes which are referred to as ‘ %fcc n ’.

Several special privileged and non-privileged registers exist:

Several special register names exist for hypervisor mode code: