9.24.2.2 Addressing Modes

The following addressing modes are understood for the S12Z.

Immediate
# number
Immediate Bit Field
# width : offset

Bit field instructions in the immediate mode require the width and offset to be specified. The width parameter specifies the number of bits in the field. It should be a number in the range [1,32]. Offset determines the position within the field where the operation should start. It should be a number in the range [0,31].

Relative
* symbol ’, or ‘ *[+-] digits

Program counter relative addresses have a width of 15 bits. Thus, they must be within the range [-32768, 32767].

Register
reg

Some instructions accept a register as an operand. In general, reg may be a data register (‘ D0 ’, ‘ D1 ... D7 ’), the ‘ X ’ register or the ‘ Y ’ register.

A few instructions accept as an argument the stack pointer register (‘ S ’), and/or the program counter (‘ P ’).

Some very special instructions accept arguments which refer to the condition code register. For these arguments the syntax is ‘ CCR ’, ‘ CCH ’ or ‘ CCL ’ which refer to the complete condition code register, the condition code register high byte and the condition code register low byte respectively.

Absolute Direct
symbol ’, or ‘ digits
Absolute Indirect
[ symbol ’, or ‘ digits ]
Constant Offset Indexed
( number , reg )

Reg may be either ‘ X ’, ‘ Y ’, ‘ S ’ or ‘ P ’ or one of the data registers ‘ D0 ’, ‘ D1 ... D7 ’. If any of the registers ‘ D2 ... D5 ’ are specified, then the register value is treated as a signed value. Otherwise it is treated as unsigned. Number may be any integer in the range [-8388608,8388607].

Offset Indexed Indirect
[ number , reg ]

Reg may be either ‘ X ’, ‘ Y ’, ‘ S ’ or ‘ P ’. Number may be any integer in the range [-8388608,8388607].

Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement
- reg ’, ‘ + reg ’, ‘ reg - ’ or ‘ reg +

This addressing mode is typically used to access a value at an address, and simultaneously to increment/decrement the register pointing to that address. Thus reg may be any of the 24 bit registers ‘ X ’, ‘ Y ’, or ‘ S ’. Pre-increment and post-decrement are not available for register ‘ S ’ (only post-increment and pre-decrement are available).

Register Offset Direct
( data-reg , reg )

Reg can be either ‘ X ’, ‘ Y ’, or ‘ S ’. Data-reg must be one of the data registers ‘ D0 ’, ‘ D1 ... D7 ’. If any of the registers ‘ D2 ... D5 ’ are specified, then the register value is treated as a signed value. Otherwise it is treated as unsigned.

Register Offset Indirect
[ data-reg , reg ]

Reg can be either ‘ X ’ or ‘ Y ’. Data-reg must be one of the data registers ‘ D0 ’, ‘ D1 ... D7 ’. If any of the registers ‘ D2 ... D5 ’ are specified, then the register value is treated as a signed value. Otherwise it is treated as unsigned.

For example:

      trap    #197        ;; Immediate mode
        bra     *+49        ;; Relative mode
        bra     .L0         ;;     ditto
        jmp     0xFE0034    ;; Absolute direct mode
        jmp     [0xFD0012]  ;; Absolute indirect mode
        inc.b   (4,x)       ;; Constant offset indexed mode
        jsr     (45, d0)    ;;     ditto
        dec.w   [4,y]       ;; Constant offset indexed indirect mode
        clr.p   (-s)        ;; Pre-decrement mode
        neg.l   (d0, s)     ;; Register offset direct mode
        com.b   [d1, x]     ;; Register offset indirect mode
        psh     cch         ;; Register mode