The FET target interface provides access to MSP430 targets via TI's parallel port to JTAG MSP430 Flash Emulation Tool or any compatible such as the Olimex MSP-JTAG or the SoftBaugh FETP. This target interface supports program loading and debugging.

###### Connection property group

Parallel Port
  Specifies which parallel port to use.
Target Driver DLL Path
  The filename of the DLL used as the device driver.

###### Current property group

Device Type
  The identified device type.

###### Emulation property group

Clock Control
  The level of debug clock control supported by the device.
Emulation Level
  The debug capabilities of supported by the device.

###### General clock control property group

ACLK
  If set to Yes, ACLK is stopped when CPU is stopped.
FLL Off
  If set to Yes, FLL is switched off when CPU is stopped.
MCLK
  If set to Yes, MCLK is stopped when CPU is stopped.
SMCLK
  If set to Yes, SMCLK is stopped when CPU is stopped.
TACLK
  If set to Yes, TACLK is stopped when CPU is stopped.

###### Loader property group

Erase All
  If true erase all memory. If false just erase the pages that are to be programmed.
RAM End Address
  The last address of RAM.
RAM Fill Value
  The byte to fill RAM with before downloading the application. If this property is left empty, RAM is not filled when downloading the application.
RAM Start Address
  The first address of RAM.
Release JTAG
  Release the JTAG signals.

###### Module clock control property group

8bit Timer/Counter
  If set to Yes, 8bit Timer/Counter is stopped when its clock source is stopped.
ACLK on Pin
  If set to Yes, ACLK on Pin is stopped when its clock source is stopped.
ADC
  If set to Yes, ADC is stopped when its clock source is stopped.
Basic Timer
  If set to Yes, Basic Timer is stopped when its clock source is stopped.
Flash Cntrl
  If set to Yes, Flash Cntrl is stopped when its clock source is stopped.
LCD Freq
  If set to Yes, LCD Frequency is stopped when its clock source is stopped.
MCLK on Pin
  If set to Yes, MCLK is stopped when its clock source is stopped.
SMCLK on Pin
  If set to Yes, SMCLK is stopped when its clock source is stopped.
Timer A
  If set to Yes, Timer A is stopped when its clock source is stopped.
Timer B
  If set to Yes, Timer B is stopped when its clock source is stopped.
Timer Port
  If set to Yes, Timer Port is stopped when its clock source is stopped.
USART0
  If set to Yes, USART0 is stopped when its clock source is stopped.
USART1
  If set to Yes, USART1 is stopped when its clock source is stopped.
WDT
  If set to Yes, WDT is stopped when its clock source is stopped.

###### Software clock control property group

Hold Basic Timer
  If set to Yes, Basic Timer is stopped on breakpoint and restarted on go.
Stop Timer A
  If set to Yes, Timer A is stopped on breakpoint and restarted on go.
Stop Timer B
  If set to Yes, Timer B is stopped on breakpoint and restarted on go.