#include  "msp430x12x.h"
;******************************************************************************
;   MSP-FET430P120 Demo - USART0 UART 19200 Echo ISR, 32kHz ACLK + DCO
;
;   Description; Echo a received character, USART0 RX ISR at high-speed using 
;   32kHz XTAL and DCO. Normal operation in LMP0, DCO continously stabalized,
;   interrupt driven using CCR2. DCO used for UART baud generation. On valid 
;   RX character, character echoed back. 
;   ACLK = LFXT1/8 = 32768/8,  MCLK = SMCLK = UCLK0 = DCOCLK  = 1048576
;   Baud rate divider with 1048576hz = 1048576Hz/19200 ~ 55 (0036h)
;   //*USART0 interrupt flags are in different SFR's from MSP430F14x/13x*// 
;   //*An external 32kHz watch crystal on XIN XOUT is required for ACLK*//	  
;
Delta   equ   256    ; Delta = (target DCO)/(4096) = 1048576
;              
;                MSP430F123(2)
;             -----------------
;         /|\|              XIN|-  
;          | |                 | 32768Hz  
;          --|RST          XOUT|-
;            |                 |
;            |             P3.4|------------> 
;            |                 |  19200 - 8N1
;            |             P3.5|<------------
;
;   M.Buccini
;   Texas Instruments, Inc
;   February 2002
;******************************************************************************
;------------------------------------------------------------------------------ 
            ORG     0E000h                  ; Program Start
;------------------------------------------------------------------------------ 
RESET       mov.w   #300h,SP                ; Initialize stackpointer
            call    #Init_Sys               ;
                                            ;
Mainloop    bis.b   #LPM0,SR                ; Enter LPM0
            nop                             ; Needed only for C-spy            
                                            ;
;------------------------------------------------------------------------------ 
Init_Sys;   Initalize MSP430 system
;------------------------------------------------------------------------------ 
StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop WDT
SetupBC     bis.b   #DIVA1+DIVA0,&BCSCTL1   ; ACLK = LFXT1CLK/8 
Setup_TA    mov.w   #TASSEL1+MC1,&TACTL     ; SMCLK, Continous Mode
Setup_CC2   mov.w   #CCIS0+CM0+CAP+CCIE,&CCTL2   ; CAP,ACLK, with interrupt
SetupUART0  mov.b   #CHAR,&UCTL0            ; 8-bit char
            mov.b   #SSEL1,&UTCTL0          ; UCLK = SMCLK
            mov.b   #036h,&UBR00            ; 1MHz 19200 
            mov.b   #000h,&UBR10            ; 1MHz 19200
            mov.b   #000h,&UMCTL0           ; 1MHz 19200 modulation 
            bis.b   #UTXE0+URXE0,&ME2       ; Enable USART0 TXD/RXD
            bis.b   #URXIE0,&IE2            ; Enable USART0 RX interrupt
SetupP3     bis.b   #030h,&P3SEL            ; P3.4,5 = USART0 TXD/RXD
            bis.b   #010h,&P3DIR            ; P3.4 = output direction 
            eint                            ; General enable interrupts
            ret                             ; Return from subroutine
                                            ;             
;------------------------------------------------------------------------------ 
USART0RX_ISR;  Echo back RXed character, confirm TX buffer is ready first
;------------------------------------------------------------------------------ 
TX1         bit.b   #UTXIFG0,&IFG2          ; USART0 TX buffer ready?
            jz      TX1                     ; Jump is TX buffer not ready
            mov.b   &RXBUF0,&TXBUF0         ; TX -> RXed character
            reti                            ; 
                                            ;
;----------------------------------------------------------------------------- 
TA2_ISR
;----------------------------------------------------------------------------- 
AdjDCO      push.w  &CCR2                   ;
            sub.w   R15,&CCR2               ;
            cmp.w   #Delta,&CCR2            ; Delta = SMCLK/(32768/8)
            pop.w   R15                     ;            
            jlo     IncDCO                  ;
            jeq     DoneDCO                 ;
DecDCO      dec.b   &DCOCTL                 ; Slow DCO with DCO and MOD
            jnz     DoneDCO                 ; Slower?
            bit.b   #07h,&BCSCTL1           ; Can RSEL.x be decremented?
            jz      DoneDCO                 ; jump>DCO at slowest setting
            dec.b   &BCSCTL1                ; Decrement RSEL.x 
            reti                            ; Return from interrrupt
IncDCO      inc.b   &DCOCTL                 ; Speed DCO with DCO and MOD
            jnc     DoneDCO                 ; Faster?
            cmp.b   #07h,&BCSCTL1           ; Can RSEL.x be increased?
            jz      DoneDCO                 ; jump> DCO at fastest settting
            inc.b   &BCSCTL1                ; Increment RSEL.x
DoneDCO     reti                            ; Return from interrrupt
                                            ;
;------------------------------------------------------------------------------
TAX_ISR;    Common ISR for CCR1-4 and overflow
;------------------------------------------------------------------------------
            add.w   &TAIV,PC                ; Add Timer_A offset vector
            reti                            ; CCR0 - no source
            reti                            ; CCR1
            jmp     TA2_ISR                 ; CCR2
;            reti                            ; CCR3
;            reti                            ; CCR4
;            reti                            ; Return from overflow ISR		 
                                            ;
;------------------------------------------------------------------------------ 
;           Interrupt Vectors Used MSP430x12x(2)        
;------------------------------------------------------------------------------ 
            ORG     0FFFEh                  ; 
            DW      RESET                   ; POR, ext. Reset, Watchdog
            ORG     0FFEEh                  ; 
            DW      USART0RX_ISR            ; USART0 receive
            ORG     0FFF0h                  ; Timer_AX Vector
            DW      TAX_ISR                 ; 
            end