#include  "msp430x12x.h"
;******************************************************************************
;   MSP-FET430P120 Demo - BasicClock Implement Continous SW FLL with Auto RSEL   
;
;   Description; Set DCO clock to (Delta)*(4096) using software FLL. DCO clock 
;   is output on P1.4 as SMCLK.  DCO clock, which is the selected SMCLK source 
;   for timer_A is integrated over ACLK/8 (4096) continously. CCR2 captures 
;   ACLK/8.  To use this SW FLL, Timer_A must be operating in continous mode 
;   with a watch crystal used for ACLK. Delta must be kept in a  range that
;   allows possible DCO speeds.  Minimum Delta must be 64 or greater  to ensure 
;   the AdjDCO ISR can complete. Maximum delta  can be calculated by 
;   f(DCOx7) / 4096.  f(DCOx7) found in device specific datasheet. To measure 
;   SMCLK on P1.4 with the FET, JTAG must be released, and the debugger stopped
;   and re-started to clear breakpoint logic.
;   ACLK = LFXT1/8 = 32768/8, MCLK = SMCLK = DCO = 4096xDelta
;   //*An external watch crystal on XIN XOUT is required for ACLK*//	  
;   
;Delta   equ   977    ; Delta = (target DCO)/(4096) = 4000000
;Delta   equ   900    ; Delta = (target DCO)/(4096) = 3686400
;Delta   equ   600    ; Delta = (target DCO)/(4096) = 2457600
;Delta   equ   256    ; Delta = (target DCO)/(4096) = 1048576
Delta   equ   250    ; Delta = (target DCO)/(4096) = 1024000
;Delta   equ   244    ; Delta = (target DCO)/(4096) = 1000000
;Delta   equ   078    ; Delta = (target DCO)/(4096) =  319488
;Delta   equ   064    ; Delta = (target DCO)/(4096) =  262144
;
;               MSP430F123(2)
;             -----------------
;         /|\|              XIN|-  
;          | |                 | 32k
;          --|RST          XOUT|-
;            |                 |
;            |             P1.4|-->SMCLK
;
;   M.Buccini
;   Texas Instruments, Inc
;   January 2002
;******************************************************************************
;------------------------------------------------------------------------------ 
            ORG     0E000h                  ; Program Start
;------------------------------------------------------------------------------ 
RESET       mov.w   #300h,SP                ; Initialize stackpointer
StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop WDT
SetupBC     bis.b   #DIVA1+DIVA0,&BCSCTL1   ; ACLK=LFXT1CLK/8 
Setup_TA    mov.w   #TASSEL1+MC1,&TACTL     ; SMCLK, Continous Mode
Setup_CC2   mov.w   #CCIS0+CM0+CAP+CCIE,&CCTL2   ; CAP,ACLK, with interrupt
SetupP1     bis.b   #010h,&P1DIR            ; P1.4 output
            bis.b   #010h,&P1SEL            ; P1.4 SMCLK output
            eint                            ; Enable interrupts
                                            ;													  
Mainloop    bis.w   #CPUOFF,SR              ; CPU is not required
            nop                             ; Needed only for C-spy
                                            ;
;----------------------------------------------------------------------------- 
TA2_ISR
;----------------------------------------------------------------------------- 
AdjDCO      push.w  &CCR2                   ;
            sub.w   R15,&CCR2               ;
            cmp.w   #Delta,&CCR2            ; Delta = SMCLK/(32768/4)
            pop.w   R15                     ;            
            jlo     IncDCO                  ;
            jeq     DoneDCO                 ;
DecDCO      dec.b   &DCOCTL                 ; Slow DCO with DCO and MOD
            jnz     DoneDCO                 ; Slower?
            bit.b   #07h,&BCSCTL1           ; Can RSEL.x be decremented?
            jz      DoneDCO                 ; jump>DCO at slowest setting
            dec.b   &BCSCTL1                ; Decrement RSEL.x 
            reti                            ; Return from interrrupt
IncDCO      inc.b   &DCOCTL                 ; Speed DCO with DCO and MOD
            jnc     DoneDCO                 ; Faster?
            cmp.b   #07h,&BCSCTL1           ; Can RSEL.x be increased?
            jz      DoneDCO                 ; jump> DCO at fastest settting
            inc.b   &BCSCTL1                ; Increment RSEL.x
DoneDCO     reti                            ; Return from interrrupt
                                            ;
;------------------------------------------------------------------------------
TAX_ISR;    Common ISR for CCR1-4 and overflow
;------------------------------------------------------------------------------
            add.w   &TAIV,PC                ; Add Timer_A offset vector
            reti                            ; CCR0 - no source
            reti                            ; CCR1
            jmp     TA2_ISR                 ; CCR2
;            reti                            ; CCR3
;            reti                            ; CCR4
;            reti                            ; Return from overflow ISR		 
                                            ;
;------------------------------------------------------------------------------
;           Interrupt Vectors Used MSP430x12x(2)          
;------------------------------------------------------------------------------
            ORG     0FFFEh                  ; MSP430 RESET Vector
            DW      RESET                   ; 
            ORG     0FFF0h                  ; Timer_AX Vector
            DW      TAX_ISR                 ; 
            END

