#include  "msp430x12x.h"
;******************************************************************************
;   MSP-FET430P120 Demo - BasicClock MCLK configured with HF XTAL
;
;   Description; Proper selection of an external HF XTAL for MCLK is shown by
;   first polling the OSC fault until XTAL is stable - only then is MCLK
;   sourced by LFXT1.  MCLK/10 is on P1.1 driven by a software loop taking 
;   exactly 10 CPU cycles. 
;   ACLK = MCLK = LFXT1 = HF XTAL, SMCLK = DCO  
;   //** HF XTAL NOT INSTALLED ON FET **//
;
;                MSP430F123(2)
;             -----------------
;         /|\|              XIN|-  
;          | |                 | HF XTAL (455k - 8Mhz)
;          --|RST          XOUT|-
;            |                 |
;            |             P1.1|-->MCLK/10 = HFXTAL/10
;            |             P2.0|-->ACLK = HFXTAL
;
;   M.Buccini
;   Texas Instruments, Inc
;   February 2002
;******************************************************************************
;------------------------------------------------------------------------------ 
            ORG     0E000h                  ; Program Start
;------------------------------------------------------------------------------ 
RESET       mov.w   #300h,SP                ; Initialize stackpointer
SetupWDT    mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop WDT
                                            ;           
SetupBC     bis.b   #XTS,&BCSCTL1           ; LFXT1 = HF XTAL
SetupOsc    bic.b   #OFIFG,&IFG1            ; Clear OSC fault flag 
            mov.w   #0FFh,R15               ; R15 = Delay 
SetupOsc1   dec.w   R15                     ; Additional delay to ensure start 
            jnz     SetupOsc1               ;
            bit.b   #OFIFG,&IFG1            ; OSC fault flag set? 
            jnz     SetupOsc                ; OSC Fault, clear flag again 
            bis.b   #SELM1+SELM0,&BCSCTL2   ; MCLK = LFXT1
                                            ;           
            bis.b   #001h,&P2DIR            ; P2.0 = output direction
            bis.b   #001h,&P2SEL            ; P2.0 = ACLK function
            bis.b   #002h,&P1DIR            ; P1.1 = output direction
                                            ;           
Mainloop    bis.b   #002h,&P1OUT            ; P1.1 = 1
            bic.b   #002h,&P1OUT            ; P1.1 = 0
            jmp     Mainloop                ; Repeat
                                            ;           
;------------------------------------------------------------------------------ 
;           Interrupt Vectors Used MSP430x12x(2)         
;------------------------------------------------------------------------------ 
            ORG     0FFFEh                  ; MSP430 RESET Vector
            DW      RESET                   ; 
            END     
