#include  "msp430x11x1.h"
;******************************************************************************
;   MSP-FET430x110 Demo - Timer_A Output 40khz square wave, UpMode SMCLK DCO 
;
;   Description; Generate a 40khz square wave on P1.2 using Timer_A.  The DCO
;   is first set to 2.56Mhz using "Set_DCO" software FLL.  Timer_A is then 
;   configured to operate in the up-mode.  CCR0 defines the period, CCR1 the 
;   duty cycle which is 50%.  CCR1 is output on P1.2. The 40khz square 
;   wave is generated in hardware and does not require any CPU resources.  
;   MCLK = SMCLK = TACLK = DCOCLK = 2.56MHz
;   //*An external watch crystal on XIN XOUT is required for ACLK*//	  
;
Delta    equ   625         ; Delta = (target DCO)/(32768/8)
;
;                MSP430F1121
;             -----------------
;         /|\|              XIN|-  
;          | |                 | 32kHz
;          --|RST          XOUT|-
;            |                 |
;            |             P1.2|--> 40khz
;
;   M.Buccini
;   Texas Instruments, Inc
;   January 2002
;******************************************************************************
;------------------------------------------------------------------------------ 
            ORG     0F000h                  ; Program Start
;------------------------------------------------------------------------------ 
RESET       mov.w   #300h,SP                ; Initialize stackpointer
SetupWDT    mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop WDT
SetupBC     bis.b   #DIVA1+DIVA0,&BCSCTL1   ; ACLK = LFXT1
            call    #Delay                  ; Time for crystal to stabilize
            call    #Set_DCO                ; Set DCO clock
SetupTA     mov.w   #TASSEL1+TACLR,&TACTL   ; SMCLK, Clear TAR
SetupC0     mov.w   #64-1,&CCR0             ; PWM Period 
SetupC1     mov.w   #OUTMOD2+OUTMOD1+OUTMOD0,&CCTL1 ; CCR1 Reset\Set
            mov.w   #32,&CCR1               ; CCR1 PWM Duty Cycle	  
SetupP1     bis.b   #004h,&P1DIR            ; P1.2 output
            bis.b   #004h,&P1SEL            ; P1.2/TA1 port function
            bis.w   #MC0,&TACTL             ; Start TA up Mode
                                            ;				
Mainloop    bis.w   #CPUOFF,SR              ; CPU not required
            nop                             ; Required only for C-spy
                                            ;
;----------------------------------------------------------------------------- 
Delay;       Software delay
;----------------------------------------------------------------------------- 
            push.w  #0FFFFh                 ; Delay to TOS
L1          dec.w   0(SP)                   ; Decrement TOS
            jnz     L1                      ; Delay over?
            incd.w  SP                      ; Clean TOS
            ret                             ;
                                            ;
;----------------------------------------------------------------------------- 
Set_DCO;    Subroutine: Sets DCO to selected frequency based on Delta.
;           R14 and R15 are used, ACLK= 32768/8 Timer_A clocked by DCOCLK
;----------------------------------------------------------------------------- 
            clr.w   R15                     ;							
Setup_TA    mov.w   #TASSEL1+TACLR,&TACTL   ; SMCLK
Setup_CC2   mov.w   #CCIS0+CM0+CAP,&CCTL2   ; Define CCR2,CAP,ACLK									
            bis.w   #MC1,&TACTL             ; Start timer_A: Continous Mode
Test_DCO    bit.w   #CCIFG,&CCTL2           ; Test capture flag
            jz      Test_DCO                ;
            bic.w   #CCIFG,&CCTL2           ; Clear capture flag
                                            ;
AdjDCO      mov.w   &CCR2,R14               ; R14 = captured SMCLK
            sub.w   R15,R14                 ; R14 = capture difference
            mov.w   &CCR2,R15               ; R15 = captured SMCLK
            cmp.w   #Delta,R14              ; Delta = SMCLK/(32768/4)
            jlo     IncDCO                  ;
            jeq     DoneDCO                 ;
DecDCO      dec.b   &DCOCTL                 ; Slow DCO with DCO and MOD
            jnz     Test_DCO                ; Slower?
            bit.b   #07h,&BCSCTL1           ; Can RSEL.x be decremented?
            jz      DoneDCO                 ; jmp>DCO at slowest setting
            dec.b   &BCSCTL1                ; Decrement RSEL.x 
            jmp     Test_DCO                ;
IncDCO      inc.b   &DCOCTL                 ; Speed DCO with DCO and MOD
            jnc     Test_DCO                ; Faster?
            cmp.b   #07h,&BCSCTL1           ; Can RSEL.x be increased?
            jz      DoneDCO                 ; jmp> DCO at fastest settting
            inc.b   &BCSCTL1                ; Increment RSEL.x
            jmp     Test_DCO                ;
DoneDCO     clr.w   &CCTL2                  ; Stop CCR2
            clr.w   &TACTL                  ; Stop timer_A
            ret                             ; Return from subroutine
                                            ;
;----------------------------------------------------------------------------- 
;           Interrupt Vectors Used MSP430x11x1         
;----------------------------------------------------------------------------- 
            ORG     0FFFEh                  ; MSP430 RESET Vector
            DW      RESET                   ; 
            END

