This documentation was generated automatically from the AVR Studio part description file `ATtiny84.pdf`.

## PORTA

### PORTA - Port A Data Register

`sfrb PORTA = $1B;`

##### PORTA0 - Port A Data Register bit 0

`#define PORTA0_BIT 0`

`#define PORTA0_MASK 1`

##### PORTA1 - Port A Data Register bit 1

`#define PORTA1_BIT 1`

`#define PORTA1_MASK 2`

##### PORTA2 - Port A Data Register bit 2

`#define PORTA2_BIT 2`

`#define PORTA2_MASK 4`

##### PORTA3 - Port A Data Register bit 3

`#define PORTA3_BIT 3`

`#define PORTA3_MASK 8`

##### PORTA4 - Port A Data Register bit 4

`#define PORTA4_BIT 4`

`#define PORTA4_MASK 16`

##### PORTA5 - Port A Data Register bit 5

`#define PORTA5_BIT 5`

`#define PORTA5_MASK 32`

##### PORTA6 - Port A Data Register bit 6

`#define PORTA6_BIT 6`

`#define PORTA6_MASK 64`

##### PORTA7 - Port A Data Register bit 7

`#define PORTA7_BIT 7`

`#define PORTA7_MASK 128`

### DDRA - Port A Data Direction Register

`sfrb DDRA = $1A;`

##### DDA0 - Data Direction Register, Port A, bit 0

`#define DDA0_BIT 0`

`#define DDA0_MASK 1`

##### DDA1 - Data Direction Register, Port A, bit 1

`#define DDA1_BIT 1`

`#define DDA1_MASK 2`

##### DDA2 - Data Direction Register, Port A, bit 2

`#define DDA2_BIT 2`

`#define DDA2_MASK 4`

##### DDA3 - Data Direction Register, Port A, bit 3

`#define DDA3_BIT 3`

`#define DDA3_MASK 8`

##### DDA4 - Data Direction Register, Port A, bit 4

`#define DDA4_BIT 4`

`#define DDA4_MASK 16`

##### DDA5 - Data Direction Register, Port A, bit 5

`#define DDA5_BIT 5`

`#define DDA5_MASK 32`

##### DDA6 - Data Direction Register, Port A, bit 6

`#define DDA6_BIT 6`

`#define DDA6_MASK 64`

##### DDA7 - Data Direction Register, Port A, bit 7

`#define DDA7_BIT 7`

`#define DDA7_MASK 128`

### PINA - Port A Input Pins

`sfrb PINA = $19;`

##### PINA0 - Input Pins, Port A bit 0

`#define PINA0_BIT 0`

`#define PINA0_MASK 1`

##### PINA1 - Input Pins, Port A bit 1

`#define PINA1_BIT 1`

`#define PINA1_MASK 2`

##### PINA2 - Input Pins, Port A bit 2

`#define PINA2_BIT 2`

`#define PINA2_MASK 4`

##### PINA3 - Input Pins, Port A bit 3

`#define PINA3_BIT 3`

`#define PINA3_MASK 8`

##### PINA4 - Input Pins, Port A bit 4

`#define PINA4_BIT 4`

`#define PINA4_MASK 16`

##### PINA5 - Input Pins, Port A bit 5

`#define PINA5_BIT 5`

`#define PINA5_MASK 32`

##### PINA6 - Input Pins, Port A bit 6

`#define PINA6_BIT 6`

`#define PINA6_MASK 64`

##### PINA7 - Input Pins, Port A bit 7

`#define PINA7_BIT 7`

`#define PINA7_MASK 128`

## PORTB

### PORTB - Data Register, Port B

`sfrb PORTB = $18;`

##### PORTB0

`#define PORTB0_BIT 0`

`#define PORTB0_MASK 1`

##### PORTB1

`#define PORTB1_BIT 1`

`#define PORTB1_MASK 2`

##### PORTB2

`#define PORTB2_BIT 2`

`#define PORTB2_MASK 4`

##### PORTB3

`#define PORTB3_BIT 3`

`#define PORTB3_MASK 8`

### DDRB - Data Direction Register, Port B

`sfrb DDRB = $17;`

##### DDB0

`#define DDB0_BIT 0`

`#define DDB0_MASK 1`

##### DDB1

`#define DDB1_BIT 1`

`#define DDB1_MASK 2`

##### DDB2

`#define DDB2_BIT 2`

`#define DDB2_MASK 4`

##### DDB3

`#define DDB3_BIT 3`

`#define DDB3_MASK 8`

### PINB - Input Pins, Port B

`sfrb PINB = $16;`

##### PINB0

`#define PINB0_BIT 0`

`#define PINB0_MASK 1`

##### PINB1

`#define PINB1_BIT 1`

`#define PINB1_MASK 2`

##### PINB2

`#define PINB2_BIT 2`

`#define PINB2_MASK 4`

##### PINB3

`#define PINB3_BIT 3`

`#define PINB3_MASK 8`

## ANALOG COMPARATOR

### ADCSRB - ADC Control and Status Register B

`sfrb ADCSRB = $03;`

##### ACME - Analog Comparator Multiplexer Enable

`#define ACME_BIT 6`

`#define ACME_MASK 64`

When this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see ?Analog Comparator Multiplexed Input? on page 186.

### ACSR - Analog Comparator Control And Status Register

`sfrb ACSR = $08;`

##### ACIS0 - Analog Comparator Interrupt Mode Select bit 0

`#define ACIS0_BIT 0`

`#define ACIS0_MASK 1`

These bits determine which comparator events that trigger the Analog Comparator interrupt.

##### ACIS1 - Analog Comparator Interrupt Mode Select bit 1

`#define ACIS1_BIT 1`

`#define ACIS1_MASK 2`

These bits determine which comparator events that trigger the Analog Comparator interrupt.

##### ACIC - Analog Comparator Input Capture Enable

`#define ACIC_BIT 2`

`#define ACIC_MASK 4`

When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the Analog Comparator.

##### ACIE - Analog Comparator Interrupt Enable

`#define ACIE_BIT 3`

`#define ACIE_MASK 8`

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.

##### ACI - Analog Comparator Interrupt Flag

`#define ACI_BIT 4`

`#define ACI_MASK 16`

This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

##### ACO - Analog Compare Output

`#define ACO_BIT 5`

`#define ACO_MASK 32`

The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.

##### ACBG - Analog Comparator Bandgap Select

`#define ACBG_BIT 6`

`#define ACBG_MASK 64`

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See ?Internal Voltage Reference? on page 42.

##### ACD - Analog Comparator Disable

`#define ACD_BIT 7`

`#define ACD_MASK 128`

When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

### DIDR0 -

`sfrb DIDR0 = $01;`

##### ADC0D - ADC 0 Digital input buffer disable

`#define ADC0D_BIT 0`

`#define ADC0D_MASK 1`

When this bit is written logic one,the digital input buffer on the AIN0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

##### ADC1D - ADC 1 Digital input buffer disable

`#define ADC1D_BIT 1`

`#define ADC1D_MASK 2`

When this bit is written logic one,the digital input buffer on the AIN1 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

## AD CONVERTER

### ADMUX - ADC Multiplexer Selection Register

`sfrb ADMUX = $07;`

##### MUX0 - Analog Channel and Gain Selection Bit 0

`#define MUX0_BIT 0`

`#define MUX0_MASK 1`

##### MUX1 - Analog Channel and Gain Selection Bit 1

`#define MUX1_BIT 1`

`#define MUX1_MASK 2`

##### MUX2 - Analog Channel and Gain Selection Bit 2

`#define MUX2_BIT 2`

`#define MUX2_MASK 4`

##### MUX3 - Analog Channel and Gain Selection Bit 3

`#define MUX3_BIT 3`

`#define MUX3_MASK 8`

##### MUX4 - Analog Channel and Gain Selection Bit 4

`#define MUX4_BIT 4`

`#define MUX4_MASK 16`

##### MUX5 - Analog Channel and Gain Selection Bit 5

`#define MUX5_BIT 5`

`#define MUX5_MASK 32`

##### REFS0 - Reference Selection Bit 0

`#define REFS0_BIT 6`

`#define REFS0_MASK 64`

##### REFS1 - Reference Selection Bit 1

`#define REFS1_BIT 7`

`#define REFS1_MASK 128`

### ADCSRA - ADC Control and Status Register A

`sfrb ADCSRA = $06;`

##### ADPS0 - ADC Prescaler Select Bit 0

`#define ADPS0_BIT 0`

`#define ADPS0_MASK 1`

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

##### ADPS1 - ADC Prescaler Select Bit 1

`#define ADPS1_BIT 1`

`#define ADPS1_MASK 2`

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

##### ADPS2 - ADC Prescaler Select Bit 2

`#define ADPS2_BIT 2`

`#define ADPS2_MASK 4`

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

##### ADIE - ADC Interrupt Enable

`#define ADIE_BIT 3`

`#define ADIE_MASK 8`

When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.

##### ADIF - ADC Interrupt Flag

`#define ADIF_BIT 4`

`#define ADIF_MASK 16`

This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.

##### ADATE - ADC Auto Trigger Enable

`#define ADATE_BIT 5`

`#define ADATE_MASK 32`

When this bit is written to one,Auto Triggering of the ADC is enabled.The ADC will start a conversion on a positive edge of the selected trigger signal.The trigger source is selected by setting the ADC Trigger Select bits,ADTS in ADCSRB.

##### ADSC - ADC Start Conversion

`#define ADSC_BIT 6`

`#define ADSC_MASK 64`

In Single Conversion Mode, a logical ?1? must be written to this bit to start each conversion. In Free Running Mode, a logical ?1? must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effec

##### ADEN - ADC Enable

`#define ADEN_BIT 7`

`#define ADEN_MASK 128`

Writing a logical ?1? to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.

### ADCH - ADC Data Register High Byte

`sfrb ADCH = $05;`

##### ADCH0 - ADC Data Register High Byte Bit 0

`#define ADCH0_BIT 0`

`#define ADCH0_MASK 1`

##### ADCH1 - ADC Data Register High Byte Bit 1

`#define ADCH1_BIT 1`

`#define ADCH1_MASK 2`

##### ADCH2 - ADC Data Register High Byte Bit 2

`#define ADCH2_BIT 2`

`#define ADCH2_MASK 4`

##### ADCH3 - ADC Data Register High Byte Bit 3

`#define ADCH3_BIT 3`

`#define ADCH3_MASK 8`

##### ADCH4 - ADC Data Register High Byte Bit 4

`#define ADCH4_BIT 4`

`#define ADCH4_MASK 16`

##### ADCH5 - ADC Data Register High Byte Bit 5

`#define ADCH5_BIT 5`

`#define ADCH5_MASK 32`

##### ADCH6 - ADC Data Register High Byte Bit 6

`#define ADCH6_BIT 6`

`#define ADCH6_MASK 64`

##### ADCH7 - ADC Data Register High Byte Bit 7

`#define ADCH7_BIT 7`

`#define ADCH7_MASK 128`

### ADCL - ADC Data Register Low Byte

`sfrb ADCL = $04;`

##### ADCL0 - ADC Data Register Low Byte Bit 0

`#define ADCL0_BIT 0`

`#define ADCL0_MASK 1`

##### ADCL1 - ADC Data Register Low Byte Bit 1

`#define ADCL1_BIT 1`

`#define ADCL1_MASK 2`

##### ADCL2 - ADC Data Register Low Byte Bit 2

`#define ADCL2_BIT 2`

`#define ADCL2_MASK 4`

##### ADCL3 - ADC Data Register Low Byte Bit 3

`#define ADCL3_BIT 3`

`#define ADCL3_MASK 8`

##### ADCL4 - ADC Data Register Low Byte Bit 4

`#define ADCL4_BIT 4`

`#define ADCL4_MASK 16`

##### ADCL5 - ADC Data Register Low Byte Bit 5

`#define ADCL5_BIT 5`

`#define ADCL5_MASK 32`

##### ADCL6 - ADC Data Register Low Byte Bit 6

`#define ADCL6_BIT 6`

`#define ADCL6_MASK 64`

##### ADCL7 - ADC Data Register Low Byte Bit 7

`#define ADCL7_BIT 7`

`#define ADCL7_MASK 128`

### ADCSRB - ADC Control and Status Register B

`sfrb ADCSRB = $03;`

##### ADTS0 - ADC Auto Trigger Source bit 0

`#define ADTS0_BIT 0`

`#define ADTS0_MASK 1`

If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set .

##### ADTS1 - ADC Auto Trigger Source bit 1

`#define ADTS1_BIT 1`

`#define ADTS1_MASK 2`

If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set .

##### ADTS2 - ADC Auto Trigger Source bit 2

`#define ADTS2_BIT 2`

`#define ADTS2_MASK 4`

If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set .

##### ADLAR - ADC Left Adjust Result

`#define ADLAR_BIT 4`

`#define ADLAR_MASK 16`

##### BIN - Bipolar Input Mode

`#define BIN_BIT 7`

`#define BIN_MASK 128`

The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected by writing the BIN bit in the ADCSRB register.

### DIDR0 - Digital Input Disable Register 0

`sfrb DIDR0 = $01;`

##### ADC0D - ADC0 Digital Input Disable

`#define ADC0D_BIT 0`

`#define ADC0D_MASK 1`

##### ADC1D - ADC1 Digital Input Disable

`#define ADC1D_BIT 1`

`#define ADC1D_MASK 2`

##### ADC2D - ADC2 Digital Input Disable

`#define ADC2D_BIT 2`

`#define ADC2D_MASK 4`

##### ADC3D - ADC3 Digital Input Disable

`#define ADC3D_BIT 3`

`#define ADC3D_MASK 8`

##### ADC4D - ADC4 Digital Input Disable

`#define ADC4D_BIT 4`

`#define ADC4D_MASK 16`

##### ADC5D - ADC5 Digital Input Disable

`#define ADC5D_BIT 5`

`#define ADC5D_MASK 32`

##### ADC6D - ADC6 Digital Input Disable

`#define ADC6D_BIT 6`

`#define ADC6D_MASK 64`

##### ADC7D - ADC7 Digital Input Disable

`#define ADC7D_BIT 7`

`#define ADC7D_MASK 128`

## USI

Universal Serial Interface

### USIBR - USI Buffer Register

`sfrb USIBR = $10;`

##### USIBR0 - USI Buffer Register bit 0

`#define USIBR0_BIT 0`

`#define USIBR0_MASK 1`

##### USIBR1 - USI Buffer Register bit 1

`#define USIBR1_BIT 1`

`#define USIBR1_MASK 2`

##### USIBR2 - USI Buffer Register bit 2

`#define USIBR2_BIT 2`

`#define USIBR2_MASK 4`

##### USIBR3 - USI Buffer Register bit 3

`#define USIBR3_BIT 3`

`#define USIBR3_MASK 8`

##### USIBR4 - USI Buffer Register bit 4

`#define USIBR4_BIT 4`

`#define USIBR4_MASK 16`

##### USIBR5 - USI Buffer Register bit 5

`#define USIBR5_BIT 5`

`#define USIBR5_MASK 32`

##### USIBR6 - USI Buffer Register bit 6

`#define USIBR6_BIT 6`

`#define USIBR6_MASK 64`

##### USIBR7 - USI Buffer Register bit 7

`#define USIBR7_BIT 7`

`#define USIBR7_MASK 128`

### USIDR - USI Data Register

`sfrb USIDR = $0F;`

##### USIDR0 - USI Data Register bit 0

`#define USIDR0_BIT 0`

`#define USIDR0_MASK 1`

##### USIDR1 - USI Data Register bit 1

`#define USIDR1_BIT 1`

`#define USIDR1_MASK 2`

##### USIDR2 - USI Data Register bit 2

`#define USIDR2_BIT 2`

`#define USIDR2_MASK 4`

##### USIDR3 - USI Data Register bit 3

`#define USIDR3_BIT 3`

`#define USIDR3_MASK 8`

##### USIDR4 - USI Data Register bit 4

`#define USIDR4_BIT 4`

`#define USIDR4_MASK 16`

##### USIDR5 - USI Data Register bit 5

`#define USIDR5_BIT 5`

`#define USIDR5_MASK 32`

##### USIDR6 - USI Data Register bit 6

`#define USIDR6_BIT 6`

`#define USIDR6_MASK 64`

##### USIDR7 - USI Data Register bit 7

`#define USIDR7_BIT 7`

`#define USIDR7_MASK 128`

### USISR - USI Status Register

`sfrb USISR = $0E;`

##### USICNT0 - USI Counter Value Bit 0

`#define USICNT0_BIT 0`

`#define USICNT0_MASK 1`

##### USICNT1 - USI Counter Value Bit 1

`#define USICNT1_BIT 1`

`#define USICNT1_MASK 2`

##### USICNT2 - USI Counter Value Bit 2

`#define USICNT2_BIT 2`

`#define USICNT2_MASK 4`

##### USICNT3 - USI Counter Value Bit 3

`#define USICNT3_BIT 3`

`#define USICNT3_MASK 8`

##### USIDC - Data Output Collision

`#define USIDC_BIT 4`

`#define USIDC_MASK 16`

##### USIPF - Stop Condition Flag

`#define USIPF_BIT 5`

`#define USIPF_MASK 32`

##### USIOIF - Counter Overflow Interrupt Flag

`#define USIOIF_BIT 6`

`#define USIOIF_MASK 64`

##### USISIF - Start Condition Interrupt Flag

`#define USISIF_BIT 7`

`#define USISIF_MASK 128`

### USICR - USI Control Register

`sfrb USICR = $0D;`

##### USITC - Toggle Clock Port Pin

`#define USITC_BIT 0`

`#define USITC_MASK 1`

##### USICLK - Clock Strobe

`#define USICLK_BIT 1`

`#define USICLK_MASK 2`

##### USICS0 - USI Clock Source Select Bit 0

`#define USICS0_BIT 2`

`#define USICS0_MASK 4`

##### USICS1 - USI Clock Source Select Bit 1

`#define USICS1_BIT 3`

`#define USICS1_MASK 8`

##### USIWM0 - USI Wire Mode Bit 0

`#define USIWM0_BIT 4`

`#define USIWM0_MASK 16`

##### USIWM1 - USI Wire Mode Bit 1

`#define USIWM1_BIT 5`

`#define USIWM1_MASK 32`

##### USIOIE - Counter Overflow Interrupt Enable

`#define USIOIE_BIT 6`

`#define USIOIE_MASK 64`

##### USISIE - Start Condition Interrupt Enable

`#define USISIE_BIT 7`

`#define USISIE_MASK 128`

## EXTERNAL INTERRUPT

### MCUCR - MCU Control Register

`sfrb MCUCR = $35;`

##### ISC00 - Interrupt Sense Control 0 Bit 0

`#define ISC00_BIT 0`

`#define ISC00_MASK 1`

##### ISC01 - Interrupt Sense Control 0 Bit 1

`#define ISC01_BIT 1`

`#define ISC01_MASK 2`

### GIMSK - General Interrupt Mask Register

`sfrb GIMSK = $3B;`

##### PCIE0 - Pin Change Interrupt Enable 0

`#define PCIE0_BIT 4`

`#define PCIE0_MASK 16`

##### PCIE1 - Pin Change Interrupt Enable 1

`#define PCIE1_BIT 5`

`#define PCIE1_MASK 32`

##### INT0 - External Interrupt Request 0 Enable

`#define INT0_BIT 6`

`#define INT0_MASK 64`

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also ?External Interrupts.? ? Bits 5..0 - Res: Reserved bits

### GIFR - General Interrupt Flag register

`sfrb GIFR = $3A;`

##### PCIF0 - Pin Change Interrupt Flag 0

`#define PCIF0_BIT 4`

`#define PCIF0_MASK 16`

##### PCIF1 - Pin Change Interrupt Flag 1

`#define PCIF1_BIT 5`

`#define PCIF1_MASK 32`

##### INTF0 - External Interrupt Flag 0

`#define INTF0_BIT 6`

`#define INTF0_MASK 64`

When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

### PCMSK1 - Pin Change Enable Mask 1

`sfrb PCMSK1 = $20;`

##### PCINT8 - Pin Change Enable Mask Bit 8

`#define PCINT8_BIT 0`

`#define PCINT8_MASK 1`

##### PCINT9 - Pin Change Enable Mask Bit 9

`#define PCINT9_BIT 1`

`#define PCINT9_MASK 2`

##### PCINT10 - Pin Change Enable Mask Bit 10

`#define PCINT10_BIT 2`

`#define PCINT10_MASK 4`

##### PCINT11 - Pin Change Enable Mask Bit 11

`#define PCINT11_BIT 3`

`#define PCINT11_MASK 8`

### PCMSK0 - Pin Change Enable Mask 0

`sfrb PCMSK0 = $12;`

##### PCINT0 - Pin Change Enable Mask Bit 0

`#define PCINT0_BIT 0`

`#define PCINT0_MASK 1`

##### PCINT1 - Pin Change Enable Mask Bit 1

`#define PCINT1_BIT 1`

`#define PCINT1_MASK 2`

##### PCINT2 - Pin Change Enable Mask Bit 2

`#define PCINT2_BIT 2`

`#define PCINT2_MASK 4`

##### PCINT3 - Pin Change Enable Mask Bit 3

`#define PCINT3_BIT 3`

`#define PCINT3_MASK 8`

##### PCINT4 - Pin Change Enable Mask Bit 4

`#define PCINT4_BIT 4`

`#define PCINT4_MASK 16`

##### PCINT5 - Pin Change Enable Mask Bit 5

`#define PCINT5_BIT 5`

`#define PCINT5_MASK 32`

##### PCINT6 - Pin Change Enable Mask Bit 6

`#define PCINT6_BIT 6`

`#define PCINT6_MASK 64`

##### PCINT7 - Pin Change Enable Mask Bit 7

`#define PCINT7_BIT 7`

`#define PCINT7_MASK 128`

## EEPROM

EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See ?Preventing EEPROM Corruption? on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execut

### EEARH - EEPROM Address Register High Byte

`sfrb EEARH = $1F;`

##### EEAR8 - EEPROM Read/Write Access Bit 0

`#define EEAR8_BIT 0`

`#define EEAR8_MASK 1`

### EEARL - EEPROM Address Register Low Byte

`sfrb EEARL = $1E;`

##### EEAR0 - EEPROM Read/Write Access Bit 0

`#define EEAR0_BIT 0`

`#define EEAR0_MASK 1`

##### EEAR1 - EEPROM Read/Write Access Bit 1

`#define EEAR1_BIT 1`

`#define EEAR1_MASK 2`

##### EEAR2 - EEPROM Read/Write Access Bit 2

`#define EEAR2_BIT 2`

`#define EEAR2_MASK 4`

##### EEAR3 - EEPROM Read/Write Access Bit 3

`#define EEAR3_BIT 3`

`#define EEAR3_MASK 8`

##### EEAR4 - EEPROM Read/Write Access Bit 4

`#define EEAR4_BIT 4`

`#define EEAR4_MASK 16`

##### EEAR5 - EEPROM Read/Write Access Bit 5

`#define EEAR5_BIT 5`

`#define EEAR5_MASK 32`

##### EEAR6 - EEPROM Read/Write Access Bit 6

`#define EEAR6_BIT 6`

`#define EEAR6_MASK 64`

##### EEAR7 - EEPROM Read/Write Access Bit 7

`#define EEAR7_BIT 7`

`#define EEAR7_MASK 128`

### EEDR - EEPROM Data Register

`sfrb EEDR = $1D;`

##### EEDR0 - EEPROM Data Register bit 0

`#define EEDR0_BIT 0`

`#define EEDR0_MASK 1`

##### EEDR1 - EEPROM Data Register bit 1

`#define EEDR1_BIT 1`

`#define EEDR1_MASK 2`

##### EEDR2 - EEPROM Data Register bit 2

`#define EEDR2_BIT 2`

`#define EEDR2_MASK 4`

##### EEDR3 - EEPROM Data Register bit 3

`#define EEDR3_BIT 3`

`#define EEDR3_MASK 8`

##### EEDR4 - EEPROM Data Register bit 4

`#define EEDR4_BIT 4`

`#define EEDR4_MASK 16`

##### EEDR5 - EEPROM Data Register bit 5

`#define EEDR5_BIT 5`

`#define EEDR5_MASK 32`

##### EEDR6 - EEPROM Data Register bit 6

`#define EEDR6_BIT 6`

`#define EEDR6_MASK 64`

##### EEDR7 - EEPROM Data Register bit 7

`#define EEDR7_BIT 7`

`#define EEDR7_MASK 128`

### EECR - EEPROM Control Register

`sfrb EECR = $1C;`

##### EERE - EEPROM Read Enable

`#define EERE_BIT 0`

`#define EERE_MASK 1`

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU

##### EEPE - EEPROM Write Enable

`#define EEPE_BIT 1`

`#define EEPE_MASK 2`

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See ?Boot Loader Support - Read While Write self-programming? on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed

##### EEMPE - EEPROM Master Write Enable

`#define EEMPE_BIT 2`

`#define EEMPE_MASK 4`

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

##### EERIE - EEPROM Ready Interrupt Enable

`#define EERIE_BIT 3`

`#define EERIE_MASK 8`

EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.

##### EEPM0 - EEPROM Programming Mode Bit 0

`#define EEPM0_BIT 4`

`#define EEPM0_MASK 16`

The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

##### EEPM1 - EEPROM Programming Mode Bit 1

`#define EEPM1_BIT 5`

`#define EEPM1_MASK 32`

The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

## WATCHDOG

### WDTCSR - Watchdog Timer Control Register

`sfrb WDTCSR = $21;`

##### WDP0 - Watch Dog Timer Prescaler bit 0

`#define WDP0_BIT 0`

`#define WDP0_MASK 1`

##### WDP1 - Watch Dog Timer Prescaler bit 1

`#define WDP1_BIT 1`

`#define WDP1_MASK 2`

##### WDP2 - Watch Dog Timer Prescaler bit 2

`#define WDP2_BIT 2`

`#define WDP2_MASK 4`

##### WDE - Watch Dog Enable

`#define WDE_BIT 3`

`#define WDE_MASK 8`

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog

##### WDCE - Watchdog Change Enable

`#define WDCE_BIT 4`

`#define WDCE_MASK 16`

##### WDP3 - Watchdog Timer Prescaler Bit 3

`#define WDP3_BIT 5`

`#define WDP3_MASK 32`

##### WDIE - Watchdog Timeout Interrupt Enable

`#define WDIE_BIT 6`

`#define WDIE_MASK 64`

##### WDIF - Watchdog Timeout Interrupt Flag

`#define WDIF_BIT 7`

`#define WDIF_MASK 128`

## TIMER COUNTER 0

### TIMSK0 - Timer/Counter Interrupt Mask Register

`sfrb TIMSK0 = $39;`

##### TOIE0 - Timer/Counter0 Overflow Interrupt Enable

`#define TOIE0_BIT 0`

`#define TOIE0_MASK 1`

##### OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable

`#define OCIE0A_BIT 1`

`#define OCIE0A_MASK 2`

##### OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable

`#define OCIE0B_BIT 2`

`#define OCIE0B_MASK 4`

### TIFR0 - Timer/Counter0 Interrupt Flag Register

`sfrb TIFR0 = $38;`

##### TOV0 - Timer/Counter0 Overflow Flag

`#define TOV0_BIT 0`

`#define TOV0_MASK 1`

##### OCF0A - Timer/Counter0 Output Compare Flag A

`#define OCF0A_BIT 1`

`#define OCF0A_MASK 2`

##### OCF0B - Timer/Counter0 Output Compare Flag B

`#define OCF0B_BIT 2`

`#define OCF0B_MASK 4`

### TCCR0A - Timer/Counter Control Register A

`sfrb TCCR0A = $30;`

##### WGM00 - Waveform Generation Mode bit 0

`#define WGM00_BIT 0`

`#define WGM00_MASK 1`

##### WGM01 - Waveform Generation Mode bit 1

`#define WGM01_BIT 1`

`#define WGM01_MASK 2`

##### COM0B0 - Compare Match Output B Mode bit 0

`#define COM0B0_BIT 4`

`#define COM0B0_MASK 16`

##### COM0B1 - Compare Match Output B Mode bit 1

`#define COM0B1_BIT 5`

`#define COM0B1_MASK 32`

##### COM0A0 - Compare Match Output A Mode bit 0

`#define COM0A0_BIT 6`

`#define COM0A0_MASK 64`

##### COM0A1 - Compare Match Output A Mode bit 1

`#define COM0A1_BIT 7`

`#define COM0A1_MASK 128`

### TCCR0B - Timer/Counter Control Register B

`sfrb TCCR0B = $33;`

##### CS00 - Clock Select bit 0

`#define CS00_BIT 0`

`#define CS00_MASK 1`

##### CS01 - Clock Select bit 1

`#define CS01_BIT 1`

`#define CS01_MASK 2`

##### CS02 - Clock Select bit 2

`#define CS02_BIT 2`

`#define CS02_MASK 4`

##### WGM02 - Waveform Generation Mode bit 2

`#define WGM02_BIT 3`

`#define WGM02_MASK 8`

##### FOC0B - Force Output Compare B

`#define FOC0B_BIT 6`

`#define FOC0B_MASK 64`

##### FOC0A - Force Output Compare A

`#define FOC0A_BIT 7`

`#define FOC0A_MASK 128`

### TCNT0 - Timer/Counter0

`sfrb TCNT0 = $32;`

##### TCNT0_0

`#define TCNT0_0_BIT 0`

`#define TCNT0_0_MASK 1`

##### TCNT0_1

`#define TCNT0_1_BIT 1`

`#define TCNT0_1_MASK 2`

##### TCNT0_2

`#define TCNT0_2_BIT 2`

`#define TCNT0_2_MASK 4`

##### TCNT0_3

`#define TCNT0_3_BIT 3`

`#define TCNT0_3_MASK 8`

##### TCNT0_4

`#define TCNT0_4_BIT 4`

`#define TCNT0_4_MASK 16`

##### TCNT0_5

`#define TCNT0_5_BIT 5`

`#define TCNT0_5_MASK 32`

##### TCNT0_6

`#define TCNT0_6_BIT 6`

`#define TCNT0_6_MASK 64`

##### TCNT0_7

`#define TCNT0_7_BIT 7`

`#define TCNT0_7_MASK 128`

### OCR0A - Timer/Counter0 Output Compare Register A

`sfrb OCR0A = $36;`

##### OCR0_0

`#define OCR0_0_BIT 0`

`#define OCR0_0_MASK 1`

##### OCR0_1

`#define OCR0_1_BIT 1`

`#define OCR0_1_MASK 2`

##### OCR0_2

`#define OCR0_2_BIT 2`

`#define OCR0_2_MASK 4`

##### OCR0_3

`#define OCR0_3_BIT 3`

`#define OCR0_3_MASK 8`

##### OCR0_4

`#define OCR0_4_BIT 4`

`#define OCR0_4_MASK 16`

##### OCR0_5

`#define OCR0_5_BIT 5`

`#define OCR0_5_MASK 32`

##### OCR0_6

`#define OCR0_6_BIT 6`

`#define OCR0_6_MASK 64`

##### OCR0_7

`#define OCR0_7_BIT 7`

`#define OCR0_7_MASK 128`

### OCR0B - Timer/Counter0 Output Compare Register B

`sfrb OCR0B = $3C;`

##### OCR0_0

`#define OCR0_0_BIT 0`

`#define OCR0_0_MASK 1`

##### OCR0_1

`#define OCR0_1_BIT 1`

`#define OCR0_1_MASK 2`

##### OCR0_2

`#define OCR0_2_BIT 2`

`#define OCR0_2_MASK 4`

##### OCR0_3

`#define OCR0_3_BIT 3`

`#define OCR0_3_MASK 8`

##### OCR0_4

`#define OCR0_4_BIT 4`

`#define OCR0_4_MASK 16`

##### OCR0_5

`#define OCR0_5_BIT 5`

`#define OCR0_5_MASK 32`

##### OCR0_6

`#define OCR0_6_BIT 6`

`#define OCR0_6_MASK 64`

##### OCR0_7

`#define OCR0_7_BIT 7`

`#define OCR0_7_MASK 128`

### GTCCR - General Timer/Counter Control Register

`sfrb GTCCR = $23;`

##### PSR10 - Prescaler Reset Timer/CounterN

`#define PSR10_BIT 0`

`#define PSR10_MASK 1`

When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.

##### TSM - Timer/Counter Synchronization Mode

`#define TSM_BIT 7`

`#define TSM_MASK 128`

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneousl

## TIMER COUNTER 1

### TIMSK1 - Timer/Counter1 Interrupt Mask Register

`sfrb TIMSK1 = $0C;`

##### TOIE1 - Timer/Counter1 Overflow Interrupt Enable

`#define TOIE1_BIT 0`

`#define TOIE1_MASK 1`

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

##### OCIE1A - Timer/Counter1 Output Compare A Match Interrupt Enable

`#define OCIE1A_BIT 1`

`#define OCIE1A_MASK 2`

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

##### OCIE1B - Timer/Counter1 Output Compare B Match Interrupt Enable

`#define OCIE1B_BIT 2`

`#define OCIE1B_MASK 4`

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

##### ICIE1 - Timer/Counter1 Input Capture Interrupt Enable

`#define ICIE1_BIT 5`

`#define ICIE1_MASK 32`

When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

### TIFR1 - Timer/Counter Interrupt Flag register

`sfrb TIFR1 = $0B;`

##### TOV1 - Timer/Counter1 Overflow Flag

`#define TOV1_BIT 0`

`#define TOV1_MASK 1`

The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.

##### OCF1A - Timer/Counter1 Output Compare A Match Flag

`#define OCF1A_BIT 1`

`#define OCF1A_MASK 2`

The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed.

##### OCF1B - Timer/Counter1 Output Compare B Match Flag

`#define OCF1B_BIT 2`

`#define OCF1B_MASK 4`

The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.

##### ICF1 - Timer/Counter1 Input Capture Flag

`#define ICF1_BIT 5`

`#define ICF1_MASK 32`

The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.

### TCCR1A - Timer/Counter1 Control Register A

`sfrb TCCR1A = $2F;`

##### WGM10 - Pulse Width Modulator Select Bit 0

`#define WGM10_BIT 0`

`#define WGM10_MASK 1`

##### WGM11 - Pulse Width Modulator Select Bit 1

`#define WGM11_BIT 1`

`#define WGM11_MASK 2`

##### COM1B0 - Comparet Ouput Mode 1B, bit 0

`#define COM1B0_BIT 4`

`#define COM1B0_MASK 16`

##### COM1B1 - Compare Output Mode 1B, bit 1

`#define COM1B1_BIT 5`

`#define COM1B1_MASK 32`

##### COM1A0 - Comparet Ouput Mode 1A, bit 0

`#define COM1A0_BIT 6`

`#define COM1A0_MASK 64`

The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in the databook.

##### COM1A1 - Compare Output Mode 1A, bit 1

`#define COM1A1_BIT 7`

`#define COM1A1_MASK 128`

The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in the databook.

### TCCR1B - Timer/Counter1 Control Register B

`sfrb TCCR1B = $2E;`

##### CS10 - Clock Select bit 0

`#define CS10_BIT 0`

`#define CS10_MASK 1`

##### CS11 - Clock Select 1 bit 1

`#define CS11_BIT 1`

`#define CS11_MASK 2`

##### CS12 - Clock Select1 bit 2

`#define CS12_BIT 2`

`#define CS12_MASK 4`

##### WGM12 - Waveform Generation Mode Bit 2

`#define WGM12_BIT 3`

`#define WGM12_MASK 8`

##### WGM13 - Waveform Generation Mode Bit 3

`#define WGM13_BIT 4`

`#define WGM13_MASK 16`

##### ICES1 - Input Capture 1 Edge Select

`#define ICES1_BIT 6`

`#define ICES1_MASK 64`

While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.

##### ICNC1 - Input Capture 1 Noise Canceler

`#define ICNC1_BIT 7`

`#define ICNC1_MASK 128`

When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.

### TCCR1C - Timer/Counter1 Control Register C

`sfrb TCCR1C = $22;`

##### FOC1B - Force Output Compare for Channel B

`#define FOC1B_BIT 6`

`#define FOC1B_MASK 64`

The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero

##### FOC1A - Force Output Compare for Channel A

`#define FOC1A_BIT 7`

`#define FOC1A_MASK 128`

The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero

### TCNT1H - Timer/Counter1 High Byte

`sfrb TCNT1H = $2D;`

##### TCNT1H0 - Timer/Counter1 High Byte bit 0

`#define TCNT1H0_BIT 0`

`#define TCNT1H0_MASK 1`

##### TCNT1H1 - Timer/Counter1 High Byte bit 1

`#define TCNT1H1_BIT 1`

`#define TCNT1H1_MASK 2`

##### TCNT1H2 - Timer/Counter1 High Byte bit 2

`#define TCNT1H2_BIT 2`

`#define TCNT1H2_MASK 4`

##### TCNT1H3 - Timer/Counter1 High Byte bit 3

`#define TCNT1H3_BIT 3`

`#define TCNT1H3_MASK 8`

##### TCNT1H4 - Timer/Counter1 High Byte bit 4

`#define TCNT1H4_BIT 4`

`#define TCNT1H4_MASK 16`

##### TCNT1H5 - Timer/Counter1 High Byte bit 5

`#define TCNT1H5_BIT 5`

`#define TCNT1H5_MASK 32`

##### TCNT1H6 - Timer/Counter1 High Byte bit 6

`#define TCNT1H6_BIT 6`

`#define TCNT1H6_MASK 64`

##### TCNT1H7 - Timer/Counter1 High Byte bit 7

`#define TCNT1H7_BIT 7`

`#define TCNT1H7_MASK 128`

### TCNT1L - Timer/Counter1 Low Byte

`sfrb TCNT1L = $2C;`

##### TCNT1L0 - Timer/Counter1 Low Byte bit 0

`#define TCNT1L0_BIT 0`

`#define TCNT1L0_MASK 1`

##### TCNT1L1 - Timer/Counter1 Low Byte bit 1

`#define TCNT1L1_BIT 1`

`#define TCNT1L1_MASK 2`

##### TCNT1L2 - Timer/Counter1 Low Byte bit 2

`#define TCNT1L2_BIT 2`

`#define TCNT1L2_MASK 4`

##### TCNT1L3 - Timer/Counter1 Low Byte bit 3

`#define TCNT1L3_BIT 3`

`#define TCNT1L3_MASK 8`

##### TCNT1L4 - Timer/Counter1 Low Byte bit 4

`#define TCNT1L4_BIT 4`

`#define TCNT1L4_MASK 16`

##### TCNT1L5 - Timer/Counter1 Low Byte bit 5

`#define TCNT1L5_BIT 5`

`#define TCNT1L5_MASK 32`

##### TCNT1L6 - Timer/Counter1 Low Byte bit 6

`#define TCNT1L6_BIT 6`

`#define TCNT1L6_MASK 64`

##### TCNT1L7 - Timer/Counter1 Low Byte bit 7

`#define TCNT1L7_BIT 7`

`#define TCNT1L7_MASK 128`

### OCR1AH - Timer/Counter1 Output Compare Register A High Byte

`sfrb OCR1AH = $2B;`

##### OCR1AH0 - Timer/Counter1 Output Compare Register High Byte bit 0

`#define OCR1AH0_BIT 0`

`#define OCR1AH0_MASK 1`

##### OCR1AH1 - Timer/Counter1 Output Compare Register High Byte bit 1

`#define OCR1AH1_BIT 1`

`#define OCR1AH1_MASK 2`

##### OCR1AH2 - Timer/Counter1 Output Compare Register High Byte bit 2

`#define OCR1AH2_BIT 2`

`#define OCR1AH2_MASK 4`

##### OCR1AH3 - Timer/Counter1 Output Compare Register High Byte bit 3

`#define OCR1AH3_BIT 3`

`#define OCR1AH3_MASK 8`

##### OCR1AH4 - Timer/Counter1 Output Compare Register High Byte bit 4

`#define OCR1AH4_BIT 4`

`#define OCR1AH4_MASK 16`

##### OCR1AH5 - Timer/Counter1 Output Compare Register High Byte bit 5

`#define OCR1AH5_BIT 5`

`#define OCR1AH5_MASK 32`

##### OCR1AH6 - Timer/Counter1 Output Compare Register High Byte bit 6

`#define OCR1AH6_BIT 6`

`#define OCR1AH6_MASK 64`

##### OCR1AH7 - Timer/Counter1 Output Compare Register High Byte bit 7

`#define OCR1AH7_BIT 7`

`#define OCR1AH7_MASK 128`

### OCR1AL - Timer/Counter1 Output Compare Register A Low Byte

`sfrb OCR1AL = $2A;`

##### OCR1AL0 - Timer/Counter1 Output Compare Register Low Byte Bit 0

`#define OCR1AL0_BIT 0`

`#define OCR1AL0_MASK 1`

##### OCR1AL1 - Timer/Counter1 Output Compare Register Low Byte Bit 1

`#define OCR1AL1_BIT 1`

`#define OCR1AL1_MASK 2`

##### OCR1AL2 - Timer/Counter1 Output Compare Register Low Byte Bit 2

`#define OCR1AL2_BIT 2`

`#define OCR1AL2_MASK 4`

##### OCR1AL3 - Timer/Counter1 Output Compare Register Low Byte Bit 3

`#define OCR1AL3_BIT 3`

`#define OCR1AL3_MASK 8`

##### OCR1AL4 - Timer/Counter1 Output Compare Register Low Byte Bit 4

`#define OCR1AL4_BIT 4`

`#define OCR1AL4_MASK 16`

##### OCR1AL5 - Timer/Counter1 Output Compare Register Low Byte Bit 5

`#define OCR1AL5_BIT 5`

`#define OCR1AL5_MASK 32`

##### OCR1AL6 - Timer/Counter1 Output Compare Register Low Byte Bit 6

`#define OCR1AL6_BIT 6`

`#define OCR1AL6_MASK 64`

##### OCR1AL7 - Timer/Counter1 Output Compare Register Low Byte Bit 7

`#define OCR1AL7_BIT 7`

`#define OCR1AL7_MASK 128`

### OCR1BH - Timer/Counter1 Output Compare Register B High Byte

`sfrb OCR1BH = $29;`

##### OCR1AH0 - Timer/Counter1 Output Compare Register High Byte bit 0

`#define OCR1AH0_BIT 0`

`#define OCR1AH0_MASK 1`

##### OCR1AH1 - Timer/Counter1 Output Compare Register High Byte bit 1

`#define OCR1AH1_BIT 1`

`#define OCR1AH1_MASK 2`

##### OCR1AH2 - Timer/Counter1 Output Compare Register High Byte bit 2

`#define OCR1AH2_BIT 2`

`#define OCR1AH2_MASK 4`

##### OCR1AH3 - Timer/Counter1 Output Compare Register High Byte bit 3

`#define OCR1AH3_BIT 3`

`#define OCR1AH3_MASK 8`

##### OCR1AH4 - Timer/Counter1 Output Compare Register High Byte bit 4

`#define OCR1AH4_BIT 4`

`#define OCR1AH4_MASK 16`

##### OCR1AH5 - Timer/Counter1 Output Compare Register High Byte bit 5

`#define OCR1AH5_BIT 5`

`#define OCR1AH5_MASK 32`

##### OCR1AH6 - Timer/Counter1 Output Compare Register High Byte bit 6

`#define OCR1AH6_BIT 6`

`#define OCR1AH6_MASK 64`

##### OCR1AH7 - Timer/Counter1 Output Compare Register High Byte bit 7

`#define OCR1AH7_BIT 7`

`#define OCR1AH7_MASK 128`

### OCR1BL - Timer/Counter1 Output Compare Register B Low Byte

`sfrb OCR1BL = $28;`

##### OCR1AL0 - Timer/Counter1 Output Compare Register Low Byte Bit 0

`#define OCR1AL0_BIT 0`

`#define OCR1AL0_MASK 1`

##### OCR1AL1 - Timer/Counter1 Output Compare Register Low Byte Bit 1

`#define OCR1AL1_BIT 1`

`#define OCR1AL1_MASK 2`

##### OCR1AL2 - Timer/Counter1 Output Compare Register Low Byte Bit 2

`#define OCR1AL2_BIT 2`

`#define OCR1AL2_MASK 4`

##### OCR1AL3 - Timer/Counter1 Output Compare Register Low Byte Bit 3

`#define OCR1AL3_BIT 3`

`#define OCR1AL3_MASK 8`

##### OCR1AL4 - Timer/Counter1 Output Compare Register Low Byte Bit 4

`#define OCR1AL4_BIT 4`

`#define OCR1AL4_MASK 16`

##### OCR1AL5 - Timer/Counter1 Output Compare Register Low Byte Bit 5

`#define OCR1AL5_BIT 5`

`#define OCR1AL5_MASK 32`

##### OCR1AL6 - Timer/Counter1 Output Compare Register Low Byte Bit 6

`#define OCR1AL6_BIT 6`

`#define OCR1AL6_MASK 64`

##### OCR1AL7 - Timer/Counter1 Output Compare Register Low Byte Bit 7

`#define OCR1AL7_BIT 7`

`#define OCR1AL7_MASK 128`

### ICR1H - Timer/Counter1 Input Capture Register High Byte

`sfrb ICR1H = $25;`

##### ICR1H0 - Timer/Counter1 Input Capture Register High Byte bit 0

`#define ICR1H0_BIT 0`

`#define ICR1H0_MASK 1`

##### ICR1H1 - Timer/Counter1 Input Capture Register High Byte bit 1

`#define ICR1H1_BIT 1`

`#define ICR1H1_MASK 2`

##### ICR1H2 - Timer/Counter1 Input Capture Register High Byte bit 2

`#define ICR1H2_BIT 2`

`#define ICR1H2_MASK 4`

##### ICR1H3 - Timer/Counter1 Input Capture Register High Byte bit 3

`#define ICR1H3_BIT 3`

`#define ICR1H3_MASK 8`

##### ICR1H4 - Timer/Counter1 Input Capture Register High Byte bit 4

`#define ICR1H4_BIT 4`

`#define ICR1H4_MASK 16`

##### ICR1H5 - Timer/Counter1 Input Capture Register High Byte bit 5

`#define ICR1H5_BIT 5`

`#define ICR1H5_MASK 32`

##### ICR1H6 - Timer/Counter1 Input Capture Register High Byte bit 6

`#define ICR1H6_BIT 6`

`#define ICR1H6_MASK 64`

##### ICR1H7 - Timer/Counter1 Input Capture Register High Byte bit 7

`#define ICR1H7_BIT 7`

`#define ICR1H7_MASK 128`

### ICR1L - Timer/Counter1 Input Capture Register Low Byte

`sfrb ICR1L = $24;`

##### ICR1L0 - Timer/Counter1 Input Capture Register Low Byte bit 0

`#define ICR1L0_BIT 0`

`#define ICR1L0_MASK 1`

##### ICR1L1 - Timer/Counter1 Input Capture Register Low Byte bit 1

`#define ICR1L1_BIT 1`

`#define ICR1L1_MASK 2`

##### ICR1L2 - Timer/Counter1 Input Capture Register Low Byte bit 2

`#define ICR1L2_BIT 2`

`#define ICR1L2_MASK 4`

##### ICR1L3 - Timer/Counter1 Input Capture Register Low Byte bit 3

`#define ICR1L3_BIT 3`

`#define ICR1L3_MASK 8`

##### ICR1L4 - Timer/Counter1 Input Capture Register Low Byte bit 4

`#define ICR1L4_BIT 4`

`#define ICR1L4_MASK 16`

##### ICR1L5 - Timer/Counter1 Input Capture Register Low Byte bit 5

`#define ICR1L5_BIT 5`

`#define ICR1L5_MASK 32`

##### ICR1L6 - Timer/Counter1 Input Capture Register Low Byte bit 6

`#define ICR1L6_BIT 6`

`#define ICR1L6_MASK 64`

##### ICR1L7 - Timer/Counter1 Input Capture Register Low Byte bit 7

`#define ICR1L7_BIT 7`

`#define ICR1L7_MASK 128`

## BOOT LOAD

The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppo

### SPMCSR - Store Program Memory Control Register

`sfrb SPMCSR = $37;`

##### SPMEN - Store Program Memory Enable

`#define SPMEN_BIT 0`

`#define SPMEN_MASK 1`

This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than ?10001?, "01001", "00101", "00011" or "00001" in the lower five bits will have no eff

##### PGERS - Page Erase

`#define PGERS_BIT 1`

`#define PGERS_MASK 2`

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.

##### PGWRT - Page Write

`#define PGWRT_BIT 2`

`#define PGWRT_MASK 4`

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.

##### RFLB - Read fuse and lock bits

`#define RFLB_BIT 3`

`#define RFLB_MASK 8`

##### CTPB - Clear temporary page buffer

`#define CTPB_BIT 4`

`#define CTPB_MASK 16`

## CPU

### PRR - Power Reduction Register

`sfrb PRR = $00;`

##### PRADC - Power Reduction ADC

`#define PRADC_BIT 0`

`#define PRADC_MASK 1`

##### PRUSI - Power Reduction USI

`#define PRUSI_BIT 1`

`#define PRUSI_MASK 2`

##### PRTIM0 - Power Reduction Timer/Counter0

`#define PRTIM0_BIT 2`

`#define PRTIM0_MASK 4`

##### PRTIM1 - Power Reduction Timer/Counter1

`#define PRTIM1_BIT 3`

`#define PRTIM1_MASK 8`

### OSCCAL - Oscillator Calibration Value

`sfrb OSCCAL = $31;`

##### CAL0 - Oscillator Calibration Value Bit0

`#define CAL0_BIT 0`

`#define CAL0_MASK 1`

##### CAL1 - Oscillator Calibration Value Bit1

`#define CAL1_BIT 1`

`#define CAL1_MASK 2`

##### CAL2 - Oscillator Calibration Value Bit2

`#define CAL2_BIT 2`

`#define CAL2_MASK 4`

##### CAL3 - Oscillator Calibration Value Bit3

`#define CAL3_BIT 3`

`#define CAL3_MASK 8`

##### CAL4 - Oscillator Calibration Value Bit4

`#define CAL4_BIT 4`

`#define CAL4_MASK 16`

##### CAL5 - Oscillator Calibration Value Bit5

`#define CAL5_BIT 5`

`#define CAL5_MASK 32`

##### CAL6 - Oscillator Calibration Value Bit6

`#define CAL6_BIT 6`

`#define CAL6_MASK 64`

##### CAL7 - Oscillator Calibration Value Bit7

`#define CAL7_BIT 7`

`#define CAL7_MASK 128`

### CLKPR - Clock Prescale Register

`sfrb CLKPR = $26;`

##### CLKPS0 - Clock Prescaler Select Bit 0

`#define CLKPS0_BIT 0`

`#define CLKPS0_MASK 1`

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.

##### CLKPS1 - Clock Prescaler Select Bit 1

`#define CLKPS1_BIT 1`

`#define CLKPS1_MASK 2`

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.

##### CLKPS2 - Clock Prescaler Select Bit 2

`#define CLKPS2_BIT 2`

`#define CLKPS2_MASK 4`

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.

##### CLKPS3 - Clock Prescaler Select Bit 3

`#define CLKPS3_BIT 3`

`#define CLKPS3_MASK 8`

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.

##### CLKPCE - Clock Prescaler Change Enable

`#define CLKPCE_BIT 7`

`#define CLKPCE_MASK 128`

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.

### SREG - Status Register

`sfrb SREG = $3F;`

### SPH - Stack Pointer High

`sfrb SPH = $3E;`

##### SP8 - Stack pointer bit 8

`#define SP8_BIT 0`

`#define SP8_MASK 1`

##### SP9 - Stack pointer bit 9

`#define SP9_BIT 1`

`#define SP9_MASK 2`

### SPL - Stack Pointer Low

`sfrb SPL = $3D;`

##### SP0 - Stack pointer bit 0

`#define SP0_BIT 0`

`#define SP0_MASK 1`

##### SP1 - Stack pointer bit 1

`#define SP1_BIT 1`

`#define SP1_MASK 2`

##### SP2 - Stack pointer bit 2

`#define SP2_BIT 2`

`#define SP2_MASK 4`

##### SP3 - Stack pointer bit 3

`#define SP3_BIT 3`

`#define SP3_MASK 8`

##### SP4

`#define SP4_BIT 4`

`#define SP4_MASK 16`

##### SP5 - Stack pointer bit 5

`#define SP5_BIT 5`

`#define SP5_MASK 32`

##### SP6 - Stack pointer bit 6

`#define SP6_BIT 6`

`#define SP6_MASK 64`

##### SP7 - Stack pointer bit 7

`#define SP7_BIT 7`

`#define SP7_MASK 128`

### MCUCR - MCU Control Register

`sfrb MCUCR = $35;`

##### SM0 - Sleep Mode Select Bit 0

`#define SM0_BIT 3`

`#define SM0_MASK 8`

##### SM1 - Sleep Mode Select Bit 1

`#define SM1_BIT 4`

`#define SM1_MASK 16`

##### SE - Sleep Enable

`#define SE_BIT 5`

`#define SE_MASK 32`

##### PUD

`#define PUD_BIT 6`

`#define PUD_MASK 64`

### MCUSR - MCU Status Register

`sfrb MCUSR = $34;`

##### PORF - Power-on reset flag

`#define PORF_BIT 0`

`#define PORF_MASK 1`

This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.

##### EXTRF - External Reset Flag

`#define EXTRF_BIT 1`

`#define EXTRF_MASK 2`

This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

##### BORF - Brown-out Reset Flag

`#define BORF_BIT 2`

`#define BORF_MASK 4`

This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

##### WDRF - Watchdog Reset Flag

`#define WDRF_BIT 3`

`#define WDRF_MASK 8`

This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

### GPIOR2 - General Purpose I/O Register 2

`sfrb GPIOR2 = $15;`

##### GPIOR20

`#define GPIOR20_BIT 0`

`#define GPIOR20_MASK 1`

##### GPIOR21

`#define GPIOR21_BIT 1`

`#define GPIOR21_MASK 2`

##### GPIOR22

`#define GPIOR22_BIT 2`

`#define GPIOR22_MASK 4`

##### GPIOR23

`#define GPIOR23_BIT 3`

`#define GPIOR23_MASK 8`

##### GPIOR24

`#define GPIOR24_BIT 4`

`#define GPIOR24_MASK 16`

##### GPIOR25

`#define GPIOR25_BIT 5`

`#define GPIOR25_MASK 32`

##### GPIOR26

`#define GPIOR26_BIT 6`

`#define GPIOR26_MASK 64`

##### GPIOR27

`#define GPIOR27_BIT 7`

`#define GPIOR27_MASK 128`

### GPIOR1 - General Purpose I/O Register 1

`sfrb GPIOR1 = $14;`

##### GPIOR10

`#define GPIOR10_BIT 0`

`#define GPIOR10_MASK 1`

##### GPIOR11

`#define GPIOR11_BIT 1`

`#define GPIOR11_MASK 2`

##### GPIOR12

`#define GPIOR12_BIT 2`

`#define GPIOR12_MASK 4`

##### GPIOR13

`#define GPIOR13_BIT 3`

`#define GPIOR13_MASK 8`

##### GPIOR14

`#define GPIOR14_BIT 4`

`#define GPIOR14_MASK 16`

##### GPIOR15

`#define GPIOR15_BIT 5`

`#define GPIOR15_MASK 32`

##### GPIOR16

`#define GPIOR16_BIT 6`

`#define GPIOR16_MASK 64`

##### GPIOR17

`#define GPIOR17_BIT 7`

`#define GPIOR17_MASK 128`

### GPIOR0 - General Purpose I/O Register 0

`sfrb GPIOR0 = $13;`

##### GPIOR00

`#define GPIOR00_BIT 0`

`#define GPIOR00_MASK 1`

##### GPIOR01

`#define GPIOR01_BIT 1`

`#define GPIOR01_MASK 2`

##### GPIOR02

`#define GPIOR02_BIT 2`

`#define GPIOR02_MASK 4`

##### GPIOR03

`#define GPIOR03_BIT 3`

`#define GPIOR03_MASK 8`

##### GPIOR04

`#define GPIOR04_BIT 4`

`#define GPIOR04_MASK 16`

##### GPIOR05

`#define GPIOR05_BIT 5`

`#define GPIOR05_MASK 32`

##### GPIOR06

`#define GPIOR06_BIT 6`

`#define GPIOR06_MASK 64`

##### GPIOR07

`#define GPIOR07_BIT 7`

`#define GPIOR07_MASK 128`