This documentation was generated automatically from the AVR Studio part description file `AT90USB162.pdf`.

## PORTB

### PORTB - Port B Data Register

`sfrb PORTB = $05;`

##### PORTB0 - Port B Data Register bit 0

`#define PORTB0_BIT 0`

`#define PORTB0_MASK 1`

##### PORTB1 - Port B Data Register bit 1

`#define PORTB1_BIT 1`

`#define PORTB1_MASK 2`

##### PORTB2 - Port B Data Register bit 2

`#define PORTB2_BIT 2`

`#define PORTB2_MASK 4`

##### PORTB3 - Port B Data Register bit 3

`#define PORTB3_BIT 3`

`#define PORTB3_MASK 8`

##### PORTB4 - Port B Data Register bit 4

`#define PORTB4_BIT 4`

`#define PORTB4_MASK 16`

##### PORTB5 - Port B Data Register bit 5

`#define PORTB5_BIT 5`

`#define PORTB5_MASK 32`

##### PORTB6 - Port B Data Register bit 6

`#define PORTB6_BIT 6`

`#define PORTB6_MASK 64`

##### PORTB7 - Port B Data Register bit 7

`#define PORTB7_BIT 7`

`#define PORTB7_MASK 128`

### DDRB - Port B Data Direction Register

`sfrb DDRB = $04;`

##### DDB0 - Port B Data Direction Register bit 0

`#define DDB0_BIT 0`

`#define DDB0_MASK 1`

##### DDB1 - Port B Data Direction Register bit 1

`#define DDB1_BIT 1`

`#define DDB1_MASK 2`

##### DDB2 - Port B Data Direction Register bit 2

`#define DDB2_BIT 2`

`#define DDB2_MASK 4`

##### DDB3 - Port B Data Direction Register bit 3

`#define DDB3_BIT 3`

`#define DDB3_MASK 8`

##### DDB4 - Port B Data Direction Register bit 4

`#define DDB4_BIT 4`

`#define DDB4_MASK 16`

##### DDB5 - Port B Data Direction Register bit 5

`#define DDB5_BIT 5`

`#define DDB5_MASK 32`

##### DDB6 - Port B Data Direction Register bit 6

`#define DDB6_BIT 6`

`#define DDB6_MASK 64`

##### DDB7 - Port B Data Direction Register bit 7

`#define DDB7_BIT 7`

`#define DDB7_MASK 128`

### PINB - Port B Input Pins

`sfrb PINB = $03;`

##### PINB0 - Port B Input Pins bit 0

`#define PINB0_BIT 0`

`#define PINB0_MASK 1`

##### PINB1 - Port B Input Pins bit 1

`#define PINB1_BIT 1`

`#define PINB1_MASK 2`

##### PINB2 - Port B Input Pins bit 2

`#define PINB2_BIT 2`

`#define PINB2_MASK 4`

##### PINB3 - Port B Input Pins bit 3

`#define PINB3_BIT 3`

`#define PINB3_MASK 8`

##### PINB4 - Port B Input Pins bit 4

`#define PINB4_BIT 4`

`#define PINB4_MASK 16`

##### PINB5 - Port B Input Pins bit 5

`#define PINB5_BIT 5`

`#define PINB5_MASK 32`

##### PINB6 - Port B Input Pins bit 6

`#define PINB6_BIT 6`

`#define PINB6_MASK 64`

##### PINB7 - Port B Input Pins bit 7

`#define PINB7_BIT 7`

`#define PINB7_MASK 128`

## PORTC

### PORTC - Port C Data Register

`sfrb PORTC = $08;`

##### PORTC0 - Port C Data Register bit 0

`#define PORTC0_BIT 0`

`#define PORTC0_MASK 1`

##### PORTC1 - Port C Data Register bit 1

`#define PORTC1_BIT 1`

`#define PORTC1_MASK 2`

##### PORTC2 - Port C Data Register bit 2

`#define PORTC2_BIT 2`

`#define PORTC2_MASK 4`

##### PORTC3 - Port C Data Register bit 3

`#define PORTC3_BIT 3`

`#define PORTC3_MASK 8`

##### PORTC4 - Port C Data Register bit 4

`#define PORTC4_BIT 4`

`#define PORTC4_MASK 16`

##### PORTC5 - Port C Data Register bit 5

`#define PORTC5_BIT 5`

`#define PORTC5_MASK 32`

##### PORTC6 - Port C Data Register bit 6

`#define PORTC6_BIT 6`

`#define PORTC6_MASK 64`

##### PORTC7 - Port C Data Register bit 7

`#define PORTC7_BIT 7`

`#define PORTC7_MASK 128`

### DDRC - Port C Data Direction Register

`sfrb DDRC = $07;`

##### DDC0 - Port C Data Direction Register bit 0

`#define DDC0_BIT 0`

`#define DDC0_MASK 1`

##### DDC1 - Port C Data Direction Register bit 1

`#define DDC1_BIT 1`

`#define DDC1_MASK 2`

##### DDC2 - Port C Data Direction Register bit 2

`#define DDC2_BIT 2`

`#define DDC2_MASK 4`

##### DDC3 - Port C Data Direction Register bit 3

`#define DDC3_BIT 3`

`#define DDC3_MASK 8`

##### DDC4 - Port C Data Direction Register bit 4

`#define DDC4_BIT 4`

`#define DDC4_MASK 16`

##### DDC5 - Port C Data Direction Register bit 5

`#define DDC5_BIT 5`

`#define DDC5_MASK 32`

##### DDC6 - Port C Data Direction Register bit 6

`#define DDC6_BIT 6`

`#define DDC6_MASK 64`

##### DDC7 - Port C Data Direction Register bit 7

`#define DDC7_BIT 7`

`#define DDC7_MASK 128`

### PINC - Port C Input Pins

`sfrb PINC = $06;`

##### PINC0 - Port C Input Pins bit 0

`#define PINC0_BIT 0`

`#define PINC0_MASK 1`

##### PINC1 - Port C Input Pins bit 1

`#define PINC1_BIT 1`

`#define PINC1_MASK 2`

##### PINC2 - Port C Input Pins bit 2

`#define PINC2_BIT 2`

`#define PINC2_MASK 4`

##### PINC3 - Port C Input Pins bit 3

`#define PINC3_BIT 3`

`#define PINC3_MASK 8`

##### PINC4 - Port C Input Pins bit 4

`#define PINC4_BIT 4`

`#define PINC4_MASK 16`

##### PINC5 - Port C Input Pins bit 5

`#define PINC5_BIT 5`

`#define PINC5_MASK 32`

##### PINC6 - Port C Input Pins bit 6

`#define PINC6_BIT 6`

`#define PINC6_MASK 64`

##### PINC7 - Port C Input Pins bit 7

`#define PINC7_BIT 7`

`#define PINC7_MASK 128`

## PORTD

### PORTD - Port D Data Register

`sfrb PORTD = $0B;`

##### PORTD0 - Port D Data Register bit 0

`#define PORTD0_BIT 0`

`#define PORTD0_MASK 1`

##### PORTD1 - Port D Data Register bit 1

`#define PORTD1_BIT 1`

`#define PORTD1_MASK 2`

##### PORTD2 - Port D Data Register bit 2

`#define PORTD2_BIT 2`

`#define PORTD2_MASK 4`

##### PORTD3 - Port D Data Register bit 3

`#define PORTD3_BIT 3`

`#define PORTD3_MASK 8`

##### PORTD4 - Port D Data Register bit 4

`#define PORTD4_BIT 4`

`#define PORTD4_MASK 16`

##### PORTD5 - Port D Data Register bit 5

`#define PORTD5_BIT 5`

`#define PORTD5_MASK 32`

##### PORTD6 - Port D Data Register bit 6

`#define PORTD6_BIT 6`

`#define PORTD6_MASK 64`

##### PORTD7 - Port D Data Register bit 7

`#define PORTD7_BIT 7`

`#define PORTD7_MASK 128`

### DDRD - Port D Data Direction Register

`sfrb DDRD = $0A;`

##### DDD0 - Port D Data Direction Register bit 0

`#define DDD0_BIT 0`

`#define DDD0_MASK 1`

##### DDD1 - Port D Data Direction Register bit 1

`#define DDD1_BIT 1`

`#define DDD1_MASK 2`

##### DDD2 - Port D Data Direction Register bit 2

`#define DDD2_BIT 2`

`#define DDD2_MASK 4`

##### DDD3 - Port D Data Direction Register bit 3

`#define DDD3_BIT 3`

`#define DDD3_MASK 8`

##### DDD4 - Port D Data Direction Register bit 4

`#define DDD4_BIT 4`

`#define DDD4_MASK 16`

##### DDD5 - Port D Data Direction Register bit 5

`#define DDD5_BIT 5`

`#define DDD5_MASK 32`

##### DDD6 - Port D Data Direction Register bit 6

`#define DDD6_BIT 6`

`#define DDD6_MASK 64`

##### DDD7 - Port D Data Direction Register bit 7

`#define DDD7_BIT 7`

`#define DDD7_MASK 128`

### PIND - Port D Input Pins

`sfrb PIND = $09;`

##### PIND0 - Port D Input Pins bit 0

`#define PIND0_BIT 0`

`#define PIND0_MASK 1`

##### PIND1 - Port D Input Pins bit 1

`#define PIND1_BIT 1`

`#define PIND1_MASK 2`

##### PIND2 - Port D Input Pins bit 2

`#define PIND2_BIT 2`

`#define PIND2_MASK 4`

##### PIND3 - Port D Input Pins bit 3

`#define PIND3_BIT 3`

`#define PIND3_MASK 8`

##### PIND4 - Port D Input Pins bit 4

`#define PIND4_BIT 4`

`#define PIND4_MASK 16`

##### PIND5 - Port D Input Pins bit 5

`#define PIND5_BIT 5`

`#define PIND5_MASK 32`

##### PIND6 - Port D Input Pins bit 6

`#define PIND6_BIT 6`

`#define PIND6_MASK 64`

##### PIND7 - Port D Input Pins bit 7

`#define PIND7_BIT 7`

`#define PIND7_MASK 128`

## SPI

The Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: ? Full-duplex, 3-wire Synchronous Data Transfer ? Master or Slave Operation ? LSB First or MSB First Data Transfer ? Four Programmable Bit Rates ? End of Transmission Interrupt Flag ? Write Collision Flag Protection ? Wakeup from Idle Mode (Slave Mode Only)

### SPCR - SPI Control Register

`sfrb SPCR = $2C;`

##### SPR0 - SPI Clock Rate Select 0

`#define SPR0_BIT 0`

`#define SPR0_MASK 1`

These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.

##### SPR1 - SPI Clock Rate Select 1

`#define SPR1_BIT 1`

`#define SPR1_MASK 2`

These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.

##### CPHA - Clock Phase

`#define CPHA_BIT 2`

`#define CPHA_MASK 4`

Refer to Figure 36 or Figure 37 for the functionality of this bit.

##### CPOL - Clock polarity

`#define CPOL_BIT 3`

`#define CPOL_MASK 8`

When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.

##### MSTR - Master/Slave Select

`#define MSTR_BIT 4`

`#define MSTR_MASK 16`

This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.

##### DORD - Data Order

`#define DORD_BIT 5`

`#define DORD_MASK 32`

When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.

##### SPE - SPI Enable

`#define SPE_BIT 6`

`#define SPE_MASK 64`

When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.

##### SPIE - SPI Interrupt Enable

`#define SPIE_BIT 7`

`#define SPIE_MASK 128`

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.

### SPSR - SPI Status Register

`sfrb SPSR = $2D;`

##### SPI2X - Double SPI Speed Bit

`#define SPI2X_BIT 0`

`#define SPI2X_MASK 1`

When this bit is written logic one the SPI speed (SCK Frequency)will be doubled when the SPI is in master mode .This means that the minimum SCK period will be 2 CPU clock periods.When the SPI is configured as Slave,the SPI is only guaranteed to work at f osc /4orlower. The SPI interface on the ATmega162 is also used for program memory and EEPROM downloading or uploading.

##### WCOL - Write Collision Flag

`#define WCOL_BIT 6`

`#define WCOL_MASK 64`

The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.

##### SPIF - SPI Interrupt Flag

`#define SPIF_BIT 7`

`#define SPIF_MASK 128`

When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).

### SPDR - SPI Data Register

`sfrb SPDR = $2E;`

##### SPDR0 - SPI Data Register bit 0

`#define SPDR0_BIT 0`

`#define SPDR0_MASK 1`

##### SPDR1 - SPI Data Register bit 1

`#define SPDR1_BIT 1`

`#define SPDR1_MASK 2`

##### SPDR2 - SPI Data Register bit 2

`#define SPDR2_BIT 2`

`#define SPDR2_MASK 4`

##### SPDR3 - SPI Data Register bit 3

`#define SPDR3_BIT 3`

`#define SPDR3_MASK 8`

##### SPDR4 - SPI Data Register bit 4

`#define SPDR4_BIT 4`

`#define SPDR4_MASK 16`

##### SPDR5 - SPI Data Register bit 5

`#define SPDR5_BIT 5`

`#define SPDR5_MASK 32`

##### SPDR6 - SPI Data Register bit 6

`#define SPDR6_BIT 6`

`#define SPDR6_MASK 64`

##### SPDR7 - SPI Data Register bit 7

`#define SPDR7_BIT 7`

`#define SPDR7_MASK 128`

## BOOT LOAD

The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppor

### SPMCSR - Store Program Memory Control Register

`sfrb SPMCSR = $37;`

##### SPMEN - Store Program Memory Enable

`#define SPMEN_BIT 0`

`#define SPMEN_MASK 1`

This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than ?10001?, "01001", "00101", "00011" or "00001" in the lower five bits will have no effec

##### PGERS - Page Erase

`#define PGERS_BIT 1`

`#define PGERS_MASK 2`

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.

##### PGWRT - Page Write

`#define PGWRT_BIT 2`

`#define PGWRT_MASK 4`

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.

##### BLBSET - Boot Lock Bit Set

`#define BLBSET_BIT 3`

`#define BLBSET_MASK 8`

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See ?Reading the Fuse and Lock Bits from Software? on page 235 for details

##### RWWSRE - Read While Write section read enable

`#define RWWSRE_BIT 4`

`#define RWWSRE_MASK 16`

When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lo

##### SIGRD - Signature Row Read

`#define SIGRD_BIT 5`

`#define SIGRD_MASK 32`

If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read a byte from the signature row into the destination register. see ?Reading the Signature Row from Software? in the datasheet for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. This operation is reserved for future use and should not be used.

##### RWWSB - Read While Write Section Busy

`#define RWWSB_BIT 6`

`#define RWWSB_MASK 64`

When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated.

##### SPMIE - SPM Interrupt Enable

`#define SPMIE_BIT 7`

`#define SPMIE_MASK 128`

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared.

## EEPROM

EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See ?Preventing EEPROM Corruption? on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execute

### EEARH - EEPROM Address Register Low Byte

`sfrb EEARH = $22;`

##### EEAR8 - EEPROM Read/Write Access Bit 8

`#define EEAR8_BIT 0`

`#define EEAR8_MASK 1`

##### EEAR9 - EEPROM Read/Write Access Bit 9

`#define EEAR9_BIT 1`

`#define EEAR9_MASK 2`

##### EEAR10 - EEPROM Read/Write Access Bit 10

`#define EEAR10_BIT 2`

`#define EEAR10_MASK 4`

##### EEAR11 - EEPROM Read/Write Access Bit 11

`#define EEAR11_BIT 3`

`#define EEAR11_MASK 8`

### EEARL - EEPROM Address Register Low Byte

`sfrb EEARL = $21;`

##### EEAR0 - EEPROM Read/Write Access Bit 0

`#define EEAR0_BIT 0`

`#define EEAR0_MASK 1`

##### EEAR1 - EEPROM Read/Write Access Bit 1

`#define EEAR1_BIT 1`

`#define EEAR1_MASK 2`

##### EEAR2 - EEPROM Read/Write Access Bit 2

`#define EEAR2_BIT 2`

`#define EEAR2_MASK 4`

##### EEAR3 - EEPROM Read/Write Access Bit 3

`#define EEAR3_BIT 3`

`#define EEAR3_MASK 8`

##### EEAR4 - EEPROM Read/Write Access Bit 4

`#define EEAR4_BIT 4`

`#define EEAR4_MASK 16`

##### EEAR5 - EEPROM Read/Write Access Bit 5

`#define EEAR5_BIT 5`

`#define EEAR5_MASK 32`

##### EEAR6 - EEPROM Read/Write Access Bit 6

`#define EEAR6_BIT 6`

`#define EEAR6_MASK 64`

##### EEAR7 - EEPROM Read/Write Access Bit 7

`#define EEAR7_BIT 7`

`#define EEAR7_MASK 128`

### EEDR - EEPROM Data Register

`sfrb EEDR = $20;`

##### EEDR0 - EEPROM Data Register bit 0

`#define EEDR0_BIT 0`

`#define EEDR0_MASK 1`

##### EEDR1 - EEPROM Data Register bit 1

`#define EEDR1_BIT 1`

`#define EEDR1_MASK 2`

##### EEDR2 - EEPROM Data Register bit 2

`#define EEDR2_BIT 2`

`#define EEDR2_MASK 4`

##### EEDR3 - EEPROM Data Register bit 3

`#define EEDR3_BIT 3`

`#define EEDR3_MASK 8`

##### EEDR4 - EEPROM Data Register bit 4

`#define EEDR4_BIT 4`

`#define EEDR4_MASK 16`

##### EEDR5 - EEPROM Data Register bit 5

`#define EEDR5_BIT 5`

`#define EEDR5_MASK 32`

##### EEDR6 - EEPROM Data Register bit 6

`#define EEDR6_BIT 6`

`#define EEDR6_MASK 64`

##### EEDR7 - EEPROM Data Register bit 7

`#define EEDR7_BIT 7`

`#define EEDR7_MASK 128`

### EECR - EEPROM Control Register

`sfrb EECR = $1F;`

##### EERE - EEPROM Read Enable

`#define EERE_BIT 0`

`#define EERE_MASK 1`

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU

##### EEPE - EEPROM Write Enable

`#define EEPE_BIT 1`

`#define EEPE_MASK 2`

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See ?Boot Loader Support - Read While Write self-programming? on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed

##### EEMPE - EEPROM Master Write Enable

`#define EEMPE_BIT 2`

`#define EEMPE_MASK 4`

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

##### EERIE - EEPROM Ready Interrupt Enable

`#define EERIE_BIT 3`

`#define EERIE_MASK 8`

EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.

##### EEPM0 - EEPROM Programming Mode Bit 0

`#define EEPM0_BIT 4`

`#define EEPM0_MASK 16`

The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

##### EEPM1 - EEPROM Programming Mode Bit 1

`#define EEPM1_BIT 5`

`#define EEPM1_MASK 32`

The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

## TIMER COUNTER 0

### OCR0B - Timer/Counter0 Output Compare Register

`sfrb OCR0B = $28;`

##### OCR0B_0

`#define OCR0B_0_BIT 0`

`#define OCR0B_0_MASK 1`

##### OCR0B_1

`#define OCR0B_1_BIT 1`

`#define OCR0B_1_MASK 2`

##### OCR0B_2

`#define OCR0B_2_BIT 2`

`#define OCR0B_2_MASK 4`

##### OCR0B_3

`#define OCR0B_3_BIT 3`

`#define OCR0B_3_MASK 8`

##### OCR0B_4

`#define OCR0B_4_BIT 4`

`#define OCR0B_4_MASK 16`

##### OCR0B_5

`#define OCR0B_5_BIT 5`

`#define OCR0B_5_MASK 32`

##### OCR0B_6

`#define OCR0B_6_BIT 6`

`#define OCR0B_6_MASK 64`

##### OCR0B_7

`#define OCR0B_7_BIT 7`

`#define OCR0B_7_MASK 128`

### OCR0A - Timer/Counter0 Output Compare Register

`sfrb OCR0A = $27;`

##### OCROA_0

`#define OCROA_0_BIT 0`

`#define OCROA_0_MASK 1`

##### OCROA_1

`#define OCROA_1_BIT 1`

`#define OCROA_1_MASK 2`

##### OCROA_2

`#define OCROA_2_BIT 2`

`#define OCROA_2_MASK 4`

##### OCROA_3

`#define OCROA_3_BIT 3`

`#define OCROA_3_MASK 8`

##### OCROA_4

`#define OCROA_4_BIT 4`

`#define OCROA_4_MASK 16`

##### OCROA_5

`#define OCROA_5_BIT 5`

`#define OCROA_5_MASK 32`

##### OCROA_6

`#define OCROA_6_BIT 6`

`#define OCROA_6_MASK 64`

##### OCROA_7

`#define OCROA_7_BIT 7`

`#define OCROA_7_MASK 128`

### TCNT0 - Timer/Counter0

`sfrb TCNT0 = $26;`

##### TCNT0_0

`#define TCNT0_0_BIT 0`

`#define TCNT0_0_MASK 1`

##### TCNT0_1

`#define TCNT0_1_BIT 1`

`#define TCNT0_1_MASK 2`

##### TCNT0_2

`#define TCNT0_2_BIT 2`

`#define TCNT0_2_MASK 4`

##### TCNT0_3

`#define TCNT0_3_BIT 3`

`#define TCNT0_3_MASK 8`

##### TCNT0_4

`#define TCNT0_4_BIT 4`

`#define TCNT0_4_MASK 16`

##### TCNT0_5

`#define TCNT0_5_BIT 5`

`#define TCNT0_5_MASK 32`

##### TCNT0_6

`#define TCNT0_6_BIT 6`

`#define TCNT0_6_MASK 64`

##### TCNT0_7

`#define TCNT0_7_BIT 7`

`#define TCNT0_7_MASK 128`

### TCCR0B - Timer/Counter Control Register B

`sfrb TCCR0B = $25;`

##### CS00 - Clock Select

`#define CS00_BIT 0`

`#define CS00_MASK 1`

##### CS01 - Clock Select

`#define CS01_BIT 1`

`#define CS01_MASK 2`

##### CS02 - Clock Select

`#define CS02_BIT 2`

`#define CS02_MASK 4`

##### WGM02

`#define WGM02_BIT 3`

`#define WGM02_MASK 8`

##### FOC0B - Force Output Compare B

`#define FOC0B_BIT 6`

`#define FOC0B_MASK 64`

##### FOC0A - Force Output Compare A

`#define FOC0A_BIT 7`

`#define FOC0A_MASK 128`

### TCCR0A - Timer/Counter Control Register A

`sfrb TCCR0A = $24;`

##### WGM00 - Waveform Generation Mode

`#define WGM00_BIT 0`

`#define WGM00_MASK 1`

##### WGM01 - Waveform Generation Mode

`#define WGM01_BIT 1`

`#define WGM01_MASK 2`

##### COM0B0 - Compare Output Mode, Fast PWm

`#define COM0B0_BIT 4`

`#define COM0B0_MASK 16`

##### COM0B1 - Compare Output Mode, Fast PWm

`#define COM0B1_BIT 5`

`#define COM0B1_MASK 32`

##### COM0A0 - Compare Output Mode, Phase Correct PWM Mode

`#define COM0A0_BIT 6`

`#define COM0A0_MASK 64`

##### COM0A1 - Compare Output Mode, Phase Correct PWM Mode

`#define COM0A1_BIT 7`

`#define COM0A1_MASK 128`

### TIMSK0 - Timer/Counter0 Interrupt Mask Register

`sfrb TIMSK0 = $6E;`

##### TOIE0 - Timer/Counter0 Overflow Interrupt Enable

`#define TOIE0_BIT 0`

`#define TOIE0_MASK 1`

##### OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable

`#define OCIE0A_BIT 1`

`#define OCIE0A_MASK 2`

##### OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable

`#define OCIE0B_BIT 2`

`#define OCIE0B_MASK 4`

### TIFR0 - Timer/Counter0 Interrupt Flag register

`sfrb TIFR0 = $15;`

##### TOV0 - Timer/Counter0 Overflow Flag

`#define TOV0_BIT 0`

`#define TOV0_MASK 1`

##### OCF0A - Timer/Counter0 Output Compare Flag 0A

`#define OCF0A_BIT 1`

`#define OCF0A_MASK 2`

##### OCF0B - Timer/Counter0 Output Compare Flag 0B

`#define OCF0B_BIT 2`

`#define OCF0B_MASK 4`

### GTCCR - General Timer/Counter Control Register

`sfrb GTCCR = $23;`

##### PSRSYNC - Prescaler Reset Timer/Counter1 and Timer/Counter0

`#define PSRSYNC_BIT 0`

`#define PSRSYNC_MASK 1`

When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.

##### TSM - Timer/Counter Synchronization Mode

`#define TSM_BIT 7`

`#define TSM_MASK 128`

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneousl

## TIMER COUNTER 1

### TCCR1A - Timer/Counter1 Control Register A

`sfrb TCCR1A = $80;`

##### WGM10 - Waveform Generation Mode

`#define WGM10_BIT 0`

`#define WGM10_MASK 1`

Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.

##### WGM11 - Waveform Generation Mode

`#define WGM11_BIT 1`

`#define WGM11_MASK 2`

Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.

##### COM1C0 - Compare Output Mode 1C, bit 0

`#define COM1C0_BIT 2`

`#define COM1C0_MASK 4`

The COM1C1 and COM1C0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.

##### COM1C1 - Compare Output Mode 1C, bit 1

`#define COM1C1_BIT 3`

`#define COM1C1_MASK 8`

The COM1C1 and COM1C0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.

##### COM1B0 - Compare Output Mode 1B, bit 0

`#define COM1B0_BIT 4`

`#define COM1B0_MASK 16`

The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.

##### COM1B1 - Compare Output Mode 1B, bit 1

`#define COM1B1_BIT 5`

`#define COM1B1_MASK 32`

The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.

##### COM1A0 - Compare Output Mode 1A, bit 0

`#define COM1A0_BIT 6`

`#define COM1A0_MASK 64`

The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.

##### COM1A1 - Compare Output Mode 1A, bit 1

`#define COM1A1_BIT 7`

`#define COM1A1_MASK 128`

The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.

### TCCR1B - Timer/Counter1 Control Register B

`sfrb TCCR1B = $81;`

##### CS10 - Prescaler source of Timer/Counter 1

`#define CS10_BIT 0`

`#define CS10_MASK 1`

Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.

##### CS11 - Prescaler source of Timer/Counter 1

`#define CS11_BIT 1`

`#define CS11_MASK 2`

Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.

##### CS12 - Prescaler source of Timer/Counter 1

`#define CS12_BIT 2`

`#define CS12_MASK 4`

Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.

##### WGM12 - Waveform Generation Mode

`#define WGM12_BIT 3`

`#define WGM12_MASK 8`

Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.

##### WGM13 - Waveform Generation Mode

`#define WGM13_BIT 4`

`#define WGM13_MASK 16`

Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.

##### ICES1 - Input Capture 1 Edge Select

`#define ICES1_BIT 6`

`#define ICES1_MASK 64`

While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.

##### ICNC1 - Input Capture 1 Noise Canceler

`#define ICNC1_BIT 7`

`#define ICNC1_MASK 128`

When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.

### TCCR1C - Timer/Counter 1 Control Register C

`sfrb TCCR1C = $82;`

##### FOC1C - Force Output Compare 1C

`#define FOC1C_BIT 5`

`#define FOC1C_MASK 32`

Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM1B1 and COM1B0.If the COM1B1 and COM1B0 bits are written in the same cycle as FOC1B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1B1 and COM1B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC1B bit to have effect on the pin. The FOC1B bit will always be read as zero. The setting of the FOC1B bit has no effect in PWM mo

##### FOC1B - Force Output Compare 1B

`#define FOC1B_BIT 6`

`#define FOC1B_MASK 64`

Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM1B1 and COM1B0.If the COM1B1 and COM1B0 bits are written in the same cycle as FOC1B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1B1 and COM1B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC1B bit to have effect on the pin. The FOC1B bit will always be read as zero. The setting of the FOC1B bit has no effect in PWM mo

##### FOC1A - Force Output Compare 1A

`#define FOC1A_BIT 7`

`#define FOC1A_MASK 128`

Writing a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM1A1 and COM1A0.If the COM1A1 and COM1A0 bits are written in the same cycle as FOC1A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1A1 and COM1A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC1 in TCCR1B is set. The corresponding I/O pin must be set as an output pin for the FOC1A bit to have effect on the pin. The FOC1A bit will always be read as zero. The setting of the FOC1A bit has no effect in PWM m

### TCNT1H - Timer/Counter1 High Byte

`sfrb TCNT1H = $85;`

##### TCNT1H0 - Timer/Counter1 High Byte bit 0

`#define TCNT1H0_BIT 0`

`#define TCNT1H0_MASK 1`

##### TCNT1H1 - Timer/Counter1 High Byte bit 1

`#define TCNT1H1_BIT 1`

`#define TCNT1H1_MASK 2`

##### TCNT1H2 - Timer/Counter1 High Byte bit 2

`#define TCNT1H2_BIT 2`

`#define TCNT1H2_MASK 4`

##### TCNT1H3 - Timer/Counter1 High Byte bit 3

`#define TCNT1H3_BIT 3`

`#define TCNT1H3_MASK 8`

##### TCNT1H4 - Timer/Counter1 High Byte bit 4

`#define TCNT1H4_BIT 4`

`#define TCNT1H4_MASK 16`

##### TCNT1H5 - Timer/Counter1 High Byte bit 5

`#define TCNT1H5_BIT 5`

`#define TCNT1H5_MASK 32`

##### TCNT1H6 - Timer/Counter1 High Byte bit 6

`#define TCNT1H6_BIT 6`

`#define TCNT1H6_MASK 64`

##### TCNT1H7 - Timer/Counter1 High Byte bit 7

`#define TCNT1H7_BIT 7`

`#define TCNT1H7_MASK 128`

### TCNT1L - Timer/Counter1 Low Byte

`sfrb TCNT1L = $84;`

##### TCNT1L0 - Timer/Counter1 Low Byte bit 0

`#define TCNT1L0_BIT 0`

`#define TCNT1L0_MASK 1`

##### TCNT1L1 - Timer/Counter1 Low Byte bit 1

`#define TCNT1L1_BIT 1`

`#define TCNT1L1_MASK 2`

##### TCNT1L2 - Timer/Counter1 Low Byte bit 2

`#define TCNT1L2_BIT 2`

`#define TCNT1L2_MASK 4`

##### TCNT1L3 - Timer/Counter1 Low Byte bit 3

`#define TCNT1L3_BIT 3`

`#define TCNT1L3_MASK 8`

##### TCNT1L4 - Timer/Counter1 Low Byte bit 4

`#define TCNT1L4_BIT 4`

`#define TCNT1L4_MASK 16`

##### TCNT1L5 - Timer/Counter1 Low Byte bit 5

`#define TCNT1L5_BIT 5`

`#define TCNT1L5_MASK 32`

##### TCNT1L6 - Timer/Counter1 Low Byte bit 6

`#define TCNT1L6_BIT 6`

`#define TCNT1L6_MASK 64`

##### TCNT1L7 - Timer/Counter1 Low Byte bit 7

`#define TCNT1L7_BIT 7`

`#define TCNT1L7_MASK 128`

### OCR1AH - Timer/Counter1 Outbut Compare Register A High Byte

`sfrb OCR1AH = $89;`

##### OCR1AH0 - Timer/Counter1 Outbut Compare Register High Byte bit 0

`#define OCR1AH0_BIT 0`

`#define OCR1AH0_MASK 1`

##### OCR1AH1 - Timer/Counter1 Outbut Compare Register High Byte bit 1

`#define OCR1AH1_BIT 1`

`#define OCR1AH1_MASK 2`

##### OCR1AH2 - Timer/Counter1 Outbut Compare Register High Byte bit 2

`#define OCR1AH2_BIT 2`

`#define OCR1AH2_MASK 4`

##### OCR1AH3 - Timer/Counter1 Outbut Compare Register High Byte bit 3

`#define OCR1AH3_BIT 3`

`#define OCR1AH3_MASK 8`

##### OCR1AH4 - Timer/Counter1 Outbut Compare Register High Byte bit 4

`#define OCR1AH4_BIT 4`

`#define OCR1AH4_MASK 16`

##### OCR1AH5 - Timer/Counter1 Outbut Compare Register High Byte bit 5

`#define OCR1AH5_BIT 5`

`#define OCR1AH5_MASK 32`

##### OCR1AH6 - Timer/Counter1 Outbut Compare Register High Byte bit 6

`#define OCR1AH6_BIT 6`

`#define OCR1AH6_MASK 64`

##### OCR1AH7 - Timer/Counter1 Outbut Compare Register High Byte bit 7

`#define OCR1AH7_BIT 7`

`#define OCR1AH7_MASK 128`

### OCR1AL - Timer/Counter1 Outbut Compare Register A Low Byte

`sfrb OCR1AL = $88;`

##### OCR1AL0 - Timer/Counter1 Outbut Compare Register Low Byte Bit 0

`#define OCR1AL0_BIT 0`

`#define OCR1AL0_MASK 1`

##### OCR1AL1 - Timer/Counter1 Outbut Compare Register Low Byte Bit 1

`#define OCR1AL1_BIT 1`

`#define OCR1AL1_MASK 2`

##### OCR1AL2 - Timer/Counter1 Outbut Compare Register Low Byte Bit 2

`#define OCR1AL2_BIT 2`

`#define OCR1AL2_MASK 4`

##### OCR1AL3 - Timer/Counter1 Outbut Compare Register Low Byte Bit 3

`#define OCR1AL3_BIT 3`

`#define OCR1AL3_MASK 8`

##### OCR1AL4 - Timer/Counter1 Outbut Compare Register Low Byte Bit 4

`#define OCR1AL4_BIT 4`

`#define OCR1AL4_MASK 16`

##### OCR1AL5 - Timer/Counter1 Outbut Compare Register Low Byte Bit 5

`#define OCR1AL5_BIT 5`

`#define OCR1AL5_MASK 32`

##### OCR1AL6 - Timer/Counter1 Outbut Compare Register Low Byte Bit 6

`#define OCR1AL6_BIT 6`

`#define OCR1AL6_MASK 64`

##### OCR1AL7 - Timer/Counter1 Outbut Compare Register Low Byte Bit 7

`#define OCR1AL7_BIT 7`

`#define OCR1AL7_MASK 128`

### OCR1BH - Timer/Counter1 Output Compare Register B High Byte

`sfrb OCR1BH = $8B;`

##### OCR1BH0 - Timer/Counter1 Output Compare Register High Byte bit 0

`#define OCR1BH0_BIT 0`

`#define OCR1BH0_MASK 1`

##### OCR1BH1 - Timer/Counter1 Output Compare Register High Byte bit 1

`#define OCR1BH1_BIT 1`

`#define OCR1BH1_MASK 2`

##### OCR1BH2 - Timer/Counter1 Output Compare Register High Byte bit 2

`#define OCR1BH2_BIT 2`

`#define OCR1BH2_MASK 4`

##### OCR1BH3 - Timer/Counter1 Output Compare Register High Byte bit 3

`#define OCR1BH3_BIT 3`

`#define OCR1BH3_MASK 8`

##### OCR1BH4 - Timer/Counter1 Output Compare Register High Byte bit 4

`#define OCR1BH4_BIT 4`

`#define OCR1BH4_MASK 16`

##### OCR1BH5 - Timer/Counter1 Output Compare Register High Byte bit 5

`#define OCR1BH5_BIT 5`

`#define OCR1BH5_MASK 32`

##### OCR1BH6 - Timer/Counter1 Output Compare Register High Byte bit 6

`#define OCR1BH6_BIT 6`

`#define OCR1BH6_MASK 64`

##### OCR1BH7 - Timer/Counter1 Output Compare Register High Byte bit 7

`#define OCR1BH7_BIT 7`

`#define OCR1BH7_MASK 128`

### OCR1BL - Timer/Counter1 Output Compare Register B Low Byte

`sfrb OCR1BL = $8A;`

##### OCR1BL0 - Timer/Counter1 Output Compare Register Low Byte bit 0

`#define OCR1BL0_BIT 0`

`#define OCR1BL0_MASK 1`

##### OCR1BL1 - Timer/Counter1 Output Compare Register Low Byte bit 1

`#define OCR1BL1_BIT 1`

`#define OCR1BL1_MASK 2`

##### OCR1BL2 - Timer/Counter1 Output Compare Register Low Byte bit 2

`#define OCR1BL2_BIT 2`

`#define OCR1BL2_MASK 4`

##### OCR1BL3 - Timer/Counter1 Output Compare Register Low Byte bit 3

`#define OCR1BL3_BIT 3`

`#define OCR1BL3_MASK 8`

##### OCR1BL4 - Timer/Counter1 Output Compare Register Low Byte bit 4

`#define OCR1BL4_BIT 4`

`#define OCR1BL4_MASK 16`

##### OCR1BL5 - Timer/Counter1 Output Compare Register Low Byte bit 5

`#define OCR1BL5_BIT 5`

`#define OCR1BL5_MASK 32`

##### OCR1BL6 - Timer/Counter1 Output Compare Register Low Byte bit 6

`#define OCR1BL6_BIT 6`

`#define OCR1BL6_MASK 64`

##### OCR1BL7 - Timer/Counter1 Output Compare Register Low Byte bit 7

`#define OCR1BL7_BIT 7`

`#define OCR1BL7_MASK 128`

### OCR1CH - Timer/Counter1 Output Compare Register B High Byte

`sfrb OCR1CH = $8D;`

##### OCR1CH0 - Timer/Counter1 Output Compare Register High Byte bit 0

`#define OCR1CH0_BIT 0`

`#define OCR1CH0_MASK 1`

##### OCR1CH1 - Timer/Counter1 Output Compare Register High Byte bit 1

`#define OCR1CH1_BIT 1`

`#define OCR1CH1_MASK 2`

##### OCR1CH2 - Timer/Counter1 Output Compare Register High Byte bit 2

`#define OCR1CH2_BIT 2`

`#define OCR1CH2_MASK 4`

##### OCR1CH3 - Timer/Counter1 Output Compare Register High Byte bit 3

`#define OCR1CH3_BIT 3`

`#define OCR1CH3_MASK 8`

##### OCR1CH4 - Timer/Counter1 Output Compare Register High Byte bit 4

`#define OCR1CH4_BIT 4`

`#define OCR1CH4_MASK 16`

##### OCR1CH5 - Timer/Counter1 Output Compare Register High Byte bit 5

`#define OCR1CH5_BIT 5`

`#define OCR1CH5_MASK 32`

##### OCR1CH6 - Timer/Counter1 Output Compare Register High Byte bit 6

`#define OCR1CH6_BIT 6`

`#define OCR1CH6_MASK 64`

##### OCR1CH7 - Timer/Counter1 Output Compare Register High Byte bit 7

`#define OCR1CH7_BIT 7`

`#define OCR1CH7_MASK 128`

### OCR1CL - Timer/Counter1 Output Compare Register B Low Byte

`sfrb OCR1CL = $8C;`

##### OCR1CL0 - Timer/Counter1 Output Compare Register Low Byte bit 0

`#define OCR1CL0_BIT 0`

`#define OCR1CL0_MASK 1`

##### OCR1CL1 - Timer/Counter1 Output Compare Register Low Byte bit 1

`#define OCR1CL1_BIT 1`

`#define OCR1CL1_MASK 2`

##### OCR1CL2 - Timer/Counter1 Output Compare Register Low Byte bit 2

`#define OCR1CL2_BIT 2`

`#define OCR1CL2_MASK 4`

##### OCR1CL3 - Timer/Counter1 Output Compare Register Low Byte bit 3

`#define OCR1CL3_BIT 3`

`#define OCR1CL3_MASK 8`

##### OCR1CL4 - Timer/Counter1 Output Compare Register Low Byte bit 4

`#define OCR1CL4_BIT 4`

`#define OCR1CL4_MASK 16`

##### OCR1CL5 - Timer/Counter1 Output Compare Register Low Byte bit 5

`#define OCR1CL5_BIT 5`

`#define OCR1CL5_MASK 32`

##### OCR1CL6 - Timer/Counter1 Output Compare Register Low Byte bit 6

`#define OCR1CL6_BIT 6`

`#define OCR1CL6_MASK 64`

##### OCR1CL7 - Timer/Counter1 Output Compare Register Low Byte bit 7

`#define OCR1CL7_BIT 7`

`#define OCR1CL7_MASK 128`

### ICR1H - Timer/Counter1 Input Capture Register High Byte

`sfrb ICR1H = $87;`

##### ICR1H0 - Timer/Counter1 Input Capture Register High Byte bit 0

`#define ICR1H0_BIT 0`

`#define ICR1H0_MASK 1`

##### ICR1H1 - Timer/Counter1 Input Capture Register High Byte bit 1

`#define ICR1H1_BIT 1`

`#define ICR1H1_MASK 2`

##### ICR1H2 - Timer/Counter1 Input Capture Register High Byte bit 2

`#define ICR1H2_BIT 2`

`#define ICR1H2_MASK 4`

##### ICR1H3 - Timer/Counter1 Input Capture Register High Byte bit 3

`#define ICR1H3_BIT 3`

`#define ICR1H3_MASK 8`

##### ICR1H4 - Timer/Counter1 Input Capture Register High Byte bit 4

`#define ICR1H4_BIT 4`

`#define ICR1H4_MASK 16`

##### ICR1H5 - Timer/Counter1 Input Capture Register High Byte bit 5

`#define ICR1H5_BIT 5`

`#define ICR1H5_MASK 32`

##### ICR1H6 - Timer/Counter1 Input Capture Register High Byte bit 6

`#define ICR1H6_BIT 6`

`#define ICR1H6_MASK 64`

##### ICR1H7 - Timer/Counter1 Input Capture Register High Byte bit 7

`#define ICR1H7_BIT 7`

`#define ICR1H7_MASK 128`

### ICR1L - Timer/Counter1 Input Capture Register Low Byte

`sfrb ICR1L = $86;`

##### ICR1L0 - Timer/Counter1 Input Capture Register Low Byte bit 0

`#define ICR1L0_BIT 0`

`#define ICR1L0_MASK 1`

##### ICR1L1 - Timer/Counter1 Input Capture Register Low Byte bit 1

`#define ICR1L1_BIT 1`

`#define ICR1L1_MASK 2`

##### ICR1L2 - Timer/Counter1 Input Capture Register Low Byte bit 2

`#define ICR1L2_BIT 2`

`#define ICR1L2_MASK 4`

##### ICR1L3 - Timer/Counter1 Input Capture Register Low Byte bit 3

`#define ICR1L3_BIT 3`

`#define ICR1L3_MASK 8`

##### ICR1L4 - Timer/Counter1 Input Capture Register Low Byte bit 4

`#define ICR1L4_BIT 4`

`#define ICR1L4_MASK 16`

##### ICR1L5 - Timer/Counter1 Input Capture Register Low Byte bit 5

`#define ICR1L5_BIT 5`

`#define ICR1L5_MASK 32`

##### ICR1L6 - Timer/Counter1 Input Capture Register Low Byte bit 6

`#define ICR1L6_BIT 6`

`#define ICR1L6_MASK 64`

##### ICR1L7 - Timer/Counter1 Input Capture Register Low Byte bit 7

`#define ICR1L7_BIT 7`

`#define ICR1L7_MASK 128`

### TIMSK1 - Timer/Counter1 Interrupt Mask Register

`sfrb TIMSK1 = $6F;`

##### TOIE1 - Timer/Counter1 Overflow Interrupt Enable

`#define TOIE1_BIT 0`

`#define TOIE1_MASK 1`

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

##### OCIE1A - Timer/Counter1 Output Compare A Match Interrupt Enable

`#define OCIE1A_BIT 1`

`#define OCIE1A_MASK 2`

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

##### OCIE1B - Timer/Counter1 Output Compare B Match Interrupt Enable

`#define OCIE1B_BIT 2`

`#define OCIE1B_MASK 4`

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

##### OCIE1C - Timer/Counter1 Output Compare C Match Interrupt Enable

`#define OCIE1C_BIT 3`

`#define OCIE1C_MASK 8`

When the OCIE1C bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

##### ICIE1 - Timer/Counter1 Input Capture Interrupt Enable

`#define ICIE1_BIT 5`

`#define ICIE1_MASK 32`

When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

### TIFR1 - Timer/Counter1 Interrupt Flag register

`sfrb TIFR1 = $16;`

##### TOV1 - Timer/Counter1 Overflow Flag

`#define TOV1_BIT 0`

`#define TOV1_MASK 1`

The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.

##### OCF1A - Output Compare Flag 1A

`#define OCF1A_BIT 1`

`#define OCF1A_MASK 2`

The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed.

##### OCF1B - Output Compare Flag 1B

`#define OCF1B_BIT 2`

`#define OCF1B_MASK 4`

The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.

##### OCF1C - Output Compare Flag 1C

`#define OCF1C_BIT 3`

`#define OCF1C_MASK 8`

The OCF1C bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.

##### ICF1 - Input Capture Flag 1

`#define ICF1_BIT 5`

`#define ICF1_MASK 32`

The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.

## ANALOG COMPARATOR

### ADCSRB - ADC Control and Status Register B

`sfrb ADCSRB = $7B;`

##### ACME - Analog Comparator Multiplexer Enable

`#define ACME_BIT 6`

`#define ACME_MASK 64`

When this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see ?Analog Comparator Multiplexed Input? on page 186.

### ACSR - Analog Comparator Control And Status Register

`sfrb ACSR = $30;`

##### ACIS0 - Analog Comparator Interrupt Mode Select bit 0

`#define ACIS0_BIT 0`

`#define ACIS0_MASK 1`

These bits determine which comparator events that trigger the Analog Comparator interrupt.

##### ACIS1 - Analog Comparator Interrupt Mode Select bit 1

`#define ACIS1_BIT 1`

`#define ACIS1_MASK 2`

These bits determine which comparator events that trigger the Analog Comparator interrupt.

##### ACIC - Analog Comparator Input Capture Enable

`#define ACIC_BIT 2`

`#define ACIC_MASK 4`

When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the analog comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set

##### ACIE - Analog Comparator Interrupt Enable

`#define ACIE_BIT 3`

`#define ACIE_MASK 8`

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.

##### ACI - Analog Comparator Interrupt Flag

`#define ACI_BIT 4`

`#define ACI_MASK 16`

This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

##### ACO - Analog Compare Output

`#define ACO_BIT 5`

`#define ACO_MASK 32`

The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.

##### ACBG - Analog Comparator Bandgap Select

`#define ACBG_BIT 6`

`#define ACBG_MASK 64`

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See ?Internal Voltage Reference? on page 42.

##### ACD - Analog Comparator Disable

`#define ACD_BIT 7`

`#define ACD_MASK 128`

When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

## PLL

### PLLCSR - PLL Status and Control register

`sfrb PLLCSR = $29;`

##### PLOCK - PLL Lock Status Bit

`#define PLOCK_BIT 0`

`#define PLOCK_MASK 1`

##### PLLE - PLL Enable Bit

`#define PLLE_BIT 1`

`#define PLLE_MASK 2`

##### PLLP0 - PLL prescaler Bit 0

`#define PLLP0_BIT 2`

`#define PLLP0_MASK 4`

##### PLLP1 - PLL prescaler Bit 1

`#define PLLP1_BIT 3`

`#define PLLP1_MASK 8`

##### PLLP2 - PLL prescaler Bit 2

`#define PLLP2_BIT 4`

`#define PLLP2_MASK 16`

## USB DEVICE

### UEINT -

`sfrb UEINT = $F4;`

##### UEINT_0

`#define UEINT_0_BIT 0`

`#define UEINT_0_MASK 1`

##### UEINT_1

`#define UEINT_1_BIT 1`

`#define UEINT_1_MASK 2`

##### UEINT_2

`#define UEINT_2_BIT 2`

`#define UEINT_2_MASK 4`

##### UEINT_3

`#define UEINT_3_BIT 3`

`#define UEINT_3_MASK 8`

##### UEINT_4

`#define UEINT_4_BIT 4`

`#define UEINT_4_MASK 16`

##### UEINT_5

`#define UEINT_5_BIT 5`

`#define UEINT_5_MASK 32`

##### UEINT_6

`#define UEINT_6_BIT 6`

`#define UEINT_6_MASK 64`

### UEBCHX -

`sfrb UEBCHX = $F3;`

##### UEBCHX_0

`#define UEBCHX_0_BIT 0`

`#define UEBCHX_0_MASK 1`

##### UEBCHX_1

`#define UEBCHX_1_BIT 1`

`#define UEBCHX_1_MASK 2`

##### UEBCHX_2

`#define UEBCHX_2_BIT 2`

`#define UEBCHX_2_MASK 4`

### UEBCLX -

`sfrb UEBCLX = $F2;`

##### UEBCLX_0

`#define UEBCLX_0_BIT 0`

`#define UEBCLX_0_MASK 1`

##### UEBCLX_1

`#define UEBCLX_1_BIT 1`

`#define UEBCLX_1_MASK 2`

##### UEBCLX_2

`#define UEBCLX_2_BIT 2`

`#define UEBCLX_2_MASK 4`

##### UEBCLX_3

`#define UEBCLX_3_BIT 3`

`#define UEBCLX_3_MASK 8`

##### UEBCLX_4

`#define UEBCLX_4_BIT 4`

`#define UEBCLX_4_MASK 16`

##### UEBCLX_5

`#define UEBCLX_5_BIT 5`

`#define UEBCLX_5_MASK 32`

##### UEBCLX_6

`#define UEBCLX_6_BIT 6`

`#define UEBCLX_6_MASK 64`

##### UEBCLX_7

`#define UEBCLX_7_BIT 7`

`#define UEBCLX_7_MASK 128`

### UEDATX -

`sfrb UEDATX = $F1;`

##### UEDATX_0

`#define UEDATX_0_BIT 0`

`#define UEDATX_0_MASK 1`

##### UEDATX_1

`#define UEDATX_1_BIT 1`

`#define UEDATX_1_MASK 2`

##### UEDATX_2

`#define UEDATX_2_BIT 2`

`#define UEDATX_2_MASK 4`

##### UEDATX_3

`#define UEDATX_3_BIT 3`

`#define UEDATX_3_MASK 8`

##### UEDATX_4

`#define UEDATX_4_BIT 4`

`#define UEDATX_4_MASK 16`

##### UEDATX_5

`#define UEDATX_5_BIT 5`

`#define UEDATX_5_MASK 32`

##### UEDATX_6

`#define UEDATX_6_BIT 6`

`#define UEDATX_6_MASK 64`

##### UEDATX_7

`#define UEDATX_7_BIT 7`

`#define UEDATX_7_MASK 128`

### UEIENX -

`sfrb UEIENX = $F0;`

##### TXINE

`#define TXINE_BIT 0`

`#define TXINE_MASK 1`

##### STALLEDE

`#define STALLEDE_BIT 1`

`#define STALLEDE_MASK 2`

##### RXOUTE

`#define RXOUTE_BIT 2`

`#define RXOUTE_MASK 4`

##### RXSTPE

`#define RXSTPE_BIT 3`

`#define RXSTPE_MASK 8`

##### NAKOUTE

`#define NAKOUTE_BIT 4`

`#define NAKOUTE_MASK 16`

##### NAKINE

`#define NAKINE_BIT 6`

`#define NAKINE_MASK 64`

##### FLERRE

`#define FLERRE_BIT 7`

`#define FLERRE_MASK 128`

### UESTA1X -

`sfrb UESTA1X = $EF;`

##### CURRBK0

`#define CURRBK0_BIT 0`

`#define CURRBK0_MASK 1`

##### CURRBK1

`#define CURRBK1_BIT 1`

`#define CURRBK1_MASK 2`

##### CTRLDIR

`#define CTRLDIR_BIT 2`

`#define CTRLDIR_MASK 4`

### UESTA0X -

`sfrb UESTA0X = $EE;`

##### NBUSYBK0

`#define NBUSYBK0_BIT 0`

`#define NBUSYBK0_MASK 1`

##### NBUSYBK1

`#define NBUSYBK1_BIT 1`

`#define NBUSYBK1_MASK 2`

##### DTSEQ0

`#define DTSEQ0_BIT 2`

`#define DTSEQ0_MASK 4`

##### DTSEQ1

`#define DTSEQ1_BIT 3`

`#define DTSEQ1_MASK 8`

##### ZLPSEEN

`#define ZLPSEEN_BIT 4`

`#define ZLPSEEN_MASK 16`

##### UNDERFI

`#define UNDERFI_BIT 5`

`#define UNDERFI_MASK 32`

##### OVERFI

`#define OVERFI_BIT 6`

`#define OVERFI_MASK 64`

##### CFGOK

`#define CFGOK_BIT 7`

`#define CFGOK_MASK 128`

### UECFG1X -

`sfrb UECFG1X = $ED;`

##### ALLOC

`#define ALLOC_BIT 1`

`#define ALLOC_MASK 2`

##### EPBK0

`#define EPBK0_BIT 2`

`#define EPBK0_MASK 4`

##### EPBK1

`#define EPBK1_BIT 3`

`#define EPBK1_MASK 8`

##### EPSIZE0

`#define EPSIZE0_BIT 4`

`#define EPSIZE0_MASK 16`

##### EPSIZE1

`#define EPSIZE1_BIT 5`

`#define EPSIZE1_MASK 32`

##### EPSIZE2

`#define EPSIZE2_BIT 6`

`#define EPSIZE2_MASK 64`

### UECFG0X -

`sfrb UECFG0X = $EC;`

##### EPDIR

`#define EPDIR_BIT 0`

`#define EPDIR_MASK 1`

##### EPTYPE0

`#define EPTYPE0_BIT 6`

`#define EPTYPE0_MASK 64`

##### EPTYPE1

`#define EPTYPE1_BIT 7`

`#define EPTYPE1_MASK 128`

### UECONX -

`sfrb UECONX = $EB;`

##### EPEN

`#define EPEN_BIT 0`

`#define EPEN_MASK 1`

##### RSTDT

`#define RSTDT_BIT 3`

`#define RSTDT_MASK 8`

##### STALLRQC

`#define STALLRQC_BIT 4`

`#define STALLRQC_MASK 16`

##### STALLRQ

`#define STALLRQ_BIT 5`

`#define STALLRQ_MASK 32`

### UERST -

`sfrb UERST = $EA;`

##### EPRST0

`#define EPRST0_BIT 0`

`#define EPRST0_MASK 1`

##### EPRST1

`#define EPRST1_BIT 1`

`#define EPRST1_MASK 2`

##### EPRST2

`#define EPRST2_BIT 2`

`#define EPRST2_MASK 4`

##### EPRST3

`#define EPRST3_BIT 3`

`#define EPRST3_MASK 8`

##### EPRST4

`#define EPRST4_BIT 4`

`#define EPRST4_MASK 16`

##### EPRST5

`#define EPRST5_BIT 5`

`#define EPRST5_MASK 32`

##### EPRST6

`#define EPRST6_BIT 6`

`#define EPRST6_MASK 64`

### UENUM -

`sfrb UENUM = $E9;`

##### UENUM_0

`#define UENUM_0_BIT 0`

`#define UENUM_0_MASK 1`

##### UENUM_1

`#define UENUM_1_BIT 1`

`#define UENUM_1_MASK 2`

##### UENUM_2

`#define UENUM_2_BIT 2`

`#define UENUM_2_MASK 4`

### UEINTX -

`sfrb UEINTX = $E8;`

##### TXINI

`#define TXINI_BIT 0`

`#define TXINI_MASK 1`

##### STALLEDI

`#define STALLEDI_BIT 1`

`#define STALLEDI_MASK 2`

##### RXOUTI

`#define RXOUTI_BIT 2`

`#define RXOUTI_MASK 4`

##### RXSTPI

`#define RXSTPI_BIT 3`

`#define RXSTPI_MASK 8`

##### NAKOUTI

`#define NAKOUTI_BIT 4`

`#define NAKOUTI_MASK 16`

##### RWAL

`#define RWAL_BIT 5`

`#define RWAL_MASK 32`

##### NAKINI

`#define NAKINI_BIT 6`

`#define NAKINI_MASK 64`

##### FIFOCON

`#define FIFOCON_BIT 7`

`#define FIFOCON_MASK 128`

### UDMFN -

`sfrb UDMFN = $E6;`

##### FNCERR

`#define FNCERR_BIT 4`

`#define FNCERR_MASK 16`

### UDFNUMH -

`sfrb UDFNUMH = $E5;`

##### UDFNUMH_0

`#define UDFNUMH_0_BIT 0`

`#define UDFNUMH_0_MASK 1`

##### UDFNUMH_1

`#define UDFNUMH_1_BIT 1`

`#define UDFNUMH_1_MASK 2`

##### UDFNUMH_2

`#define UDFNUMH_2_BIT 2`

`#define UDFNUMH_2_MASK 4`

### UDFNUML -

`sfrb UDFNUML = $E4;`

##### UDFNUML_0

`#define UDFNUML_0_BIT 0`

`#define UDFNUML_0_MASK 1`

##### UDFNUML_1

`#define UDFNUML_1_BIT 1`

`#define UDFNUML_1_MASK 2`

##### UDFNUML_2

`#define UDFNUML_2_BIT 2`

`#define UDFNUML_2_MASK 4`

##### UDFNUML_3

`#define UDFNUML_3_BIT 3`

`#define UDFNUML_3_MASK 8`

##### UDFNUML_4

`#define UDFNUML_4_BIT 4`

`#define UDFNUML_4_MASK 16`

##### UDFNUML_5

`#define UDFNUML_5_BIT 5`

`#define UDFNUML_5_MASK 32`

##### UDFNUML_6

`#define UDFNUML_6_BIT 6`

`#define UDFNUML_6_MASK 64`

##### UDFNUML_7

`#define UDFNUML_7_BIT 7`

`#define UDFNUML_7_MASK 128`

### UDADDR -

`sfrb UDADDR = $E3;`

##### UDADDR0

`#define UDADDR0_BIT 0`

`#define UDADDR0_MASK 1`

##### UDADDR1

`#define UDADDR1_BIT 1`

`#define UDADDR1_MASK 2`

##### UDADDR2

`#define UDADDR2_BIT 2`

`#define UDADDR2_MASK 4`

##### UDADDR3

`#define UDADDR3_BIT 3`

`#define UDADDR3_MASK 8`

##### UDADDR4

`#define UDADDR4_BIT 4`

`#define UDADDR4_MASK 16`

##### UDADDR5

`#define UDADDR5_BIT 5`

`#define UDADDR5_MASK 32`

##### UDADDR6

`#define UDADDR6_BIT 6`

`#define UDADDR6_MASK 64`

##### ADDEN

`#define ADDEN_BIT 7`

`#define ADDEN_MASK 128`

### UDIEN -

`sfrb UDIEN = $E2;`

##### SUSPE

`#define SUSPE_BIT 0`

`#define SUSPE_MASK 1`

##### MSOFE

`#define MSOFE_BIT 1`

`#define MSOFE_MASK 2`

##### SOFE

`#define SOFE_BIT 2`

`#define SOFE_MASK 4`

##### EORSTE

`#define EORSTE_BIT 3`

`#define EORSTE_MASK 8`

##### WAKEUPE

`#define WAKEUPE_BIT 4`

`#define WAKEUPE_MASK 16`

##### EORSME

`#define EORSME_BIT 5`

`#define EORSME_MASK 32`

##### UPRSME

`#define UPRSME_BIT 6`

`#define UPRSME_MASK 64`

### UDINT -

`sfrb UDINT = $E1;`

##### SUSPI

`#define SUSPI_BIT 0`

`#define SUSPI_MASK 1`

##### MSOFI

`#define MSOFI_BIT 1`

`#define MSOFI_MASK 2`

##### SOFI

`#define SOFI_BIT 2`

`#define SOFI_MASK 4`

##### EORSTI

`#define EORSTI_BIT 3`

`#define EORSTI_MASK 8`

##### WAKEUPI

`#define WAKEUPI_BIT 4`

`#define WAKEUPI_MASK 16`

##### EORSMI

`#define EORSMI_BIT 5`

`#define EORSMI_MASK 32`

##### UPRSMI

`#define UPRSMI_BIT 6`

`#define UPRSMI_MASK 64`

### UDCON -

`sfrb UDCON = $E0;`

##### DETACH

`#define DETACH_BIT 0`

`#define DETACH_MASK 1`

##### RMWKUP

`#define RMWKUP_BIT 1`

`#define RMWKUP_MASK 2`

##### RSTCPU

`#define RSTCPU_BIT 2`

`#define RSTCPU_MASK 4`

### USBCON - USB General Control Register

`sfrb USBCON = $D8;`

##### FRZCLK

`#define FRZCLK_BIT 5`

`#define FRZCLK_MASK 32`

##### USBE

`#define USBE_BIT 7`

`#define USBE_MASK 128`

### REGCR - Regulator Control Register

`sfrb REGCR = $63;`

##### REGDIS

`#define REGDIS_BIT 0`

`#define REGDIS_MASK 1`

## PS2

### UPOE -

`sfrb UPOE = $FB;`

##### DMI

`#define DMI_BIT 0`

`#define DMI_MASK 1`

##### DPI

`#define DPI_BIT 1`

`#define DPI_MASK 2`

##### DATAI

`#define DATAI_BIT 2`

`#define DATAI_MASK 4`

##### SCKI

`#define SCKI_BIT 3`

`#define SCKI_MASK 8`

##### UPDRV0

`#define UPDRV0_BIT 4`

`#define UPDRV0_MASK 16`

##### UPDRV1

`#define UPDRV1_BIT 5`

`#define UPDRV1_MASK 32`

##### UPWE0

`#define UPWE0_BIT 6`

`#define UPWE0_MASK 64`

##### UPWE1

`#define UPWE1_BIT 7`

`#define UPWE1_MASK 128`

.

### PS2CON - PS2 Pad Enable register

`sfrb PS2CON = $FA;`

##### PS2EN - Enable

`#define PS2EN_BIT 0`

`#define PS2EN_MASK 1`

## CPU

### SREG - Status Register

`sfrb SREG = $3F;`

### SPH - Stack Pointer High

`sfrb SPH = $3E;`

##### SP8 - Stack pointer bit 8

`#define SP8_BIT 0`

`#define SP8_MASK 1`

##### SP9 - Stack pointer bit 9

`#define SP9_BIT 1`

`#define SP9_MASK 2`

##### SP10 - Stack pointer bit 10

`#define SP10_BIT 2`

`#define SP10_MASK 4`

##### SP11 - Stack pointer bit 11

`#define SP11_BIT 3`

`#define SP11_MASK 8`

##### SP12

`#define SP12_BIT 4`

`#define SP12_MASK 16`

##### SP13 - Stack pointer bit 13

`#define SP13_BIT 5`

`#define SP13_MASK 32`

##### SP14 - Stack pointer bit 14

`#define SP14_BIT 6`

`#define SP14_MASK 64`

##### SP15 - Stack pointer bit 15

`#define SP15_BIT 7`

`#define SP15_MASK 128`

### SPL - Stack Pointer Low

`sfrb SPL = $3D;`

##### SP0 - Stack pointer bit 0

`#define SP0_BIT 0`

`#define SP0_MASK 1`

##### SP1 - Stack pointer bit 1

`#define SP1_BIT 1`

`#define SP1_MASK 2`

##### SP2 - Stack pointer bit 2

`#define SP2_BIT 2`

`#define SP2_MASK 4`

##### SP3 - Stack pointer bit 3

`#define SP3_BIT 3`

`#define SP3_MASK 8`

##### SP4

`#define SP4_BIT 4`

`#define SP4_MASK 16`

##### SP5 - Stack pointer bit 5

`#define SP5_BIT 5`

`#define SP5_MASK 32`

##### SP6 - Stack pointer bit 6

`#define SP6_BIT 6`

`#define SP6_MASK 64`

##### SP7 - Stack pointer bit 7

`#define SP7_BIT 7`

`#define SP7_MASK 128`

### MCUCR - MCU Control Register

`sfrb MCUCR = $35;`

##### IVCE - Interrupt Vector Change Enable

`#define IVCE_BIT 0`

`#define IVCE_MASK 1`

The IVCE bit must be written to logic one to enable change of the IVSEL bit.IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.Setting the IVCE bit will disable interrupts.

##### IVSEL - Interrupt Vector Select

`#define IVSEL_BIT 1`

`#define IVSEL_MASK 2`

When the IVSEL bit is cleared (zero),the interrupt vectors are placed at the start of the Flash memory.When this bit is set (one),the interrupt vectors are moved to the beginning of the Boot Loader section of the flash.The actual address of the start of the boot flash section is determined by the BOOTSZ fuses.

##### PUD - Pull-up disable

`#define PUD_BIT 4`

`#define PUD_MASK 16`

When this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn,PORTxn}=0b01).

##### JTD - JTAG Interface Disable

`#define JTD_BIT 7`

`#define JTD_MASK 128`

When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed.

### MCUSR - MCU Status Register

`sfrb MCUSR = $34;`

##### PORF - Power-on reset flag

`#define PORF_BIT 0`

`#define PORF_MASK 1`

This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.

##### EXTRF - External Reset Flag

`#define EXTRF_BIT 1`

`#define EXTRF_MASK 2`

This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

##### BORF - Brown-out Reset Flag

`#define BORF_BIT 2`

`#define BORF_MASK 4`

This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

##### WDRF - Watchdog Reset Flag

`#define WDRF_BIT 3`

`#define WDRF_MASK 8`

This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

##### JTRF - JTAG Reset Flag

`#define JTRF_BIT 4`

`#define JTRF_MASK 16`

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on reset, or by writing a logic zero to the flag. ? Bit 3 - WDRF: Watchdog Reset Flag

### OSCCAL - Oscillator Calibration Value

`sfrb OSCCAL = $66;`

##### CAL0 - Oscillator Calibration Value Bit0

`#define CAL0_BIT 0`

`#define CAL0_MASK 1`

##### CAL1 - Oscillator Calibration Value Bit1

`#define CAL1_BIT 1`

`#define CAL1_MASK 2`

##### CAL2 - Oscillator Calibration Value Bit2

`#define CAL2_BIT 2`

`#define CAL2_MASK 4`

##### CAL3 - Oscillator Calibration Value Bit3

`#define CAL3_BIT 3`

`#define CAL3_MASK 8`

##### CAL4 - Oscillator Calibration Value Bit4

`#define CAL4_BIT 4`

`#define CAL4_MASK 16`

##### CAL5 - Oscillator Calibration Value Bit5

`#define CAL5_BIT 5`

`#define CAL5_MASK 32`

##### CAL6 - Oscillator Calibration Value Bit6

`#define CAL6_BIT 6`

`#define CAL6_MASK 64`

##### CAL7 - Oscillator Calibration Value Bit7

`#define CAL7_BIT 7`

`#define CAL7_MASK 128`

### CLKPR -

`sfrb CLKPR = $61;`

##### CLKPS0

`#define CLKPS0_BIT 0`

`#define CLKPS0_MASK 1`

##### CLKPS1

`#define CLKPS1_BIT 1`

`#define CLKPS1_MASK 2`

##### CLKPS2

`#define CLKPS2_BIT 2`

`#define CLKPS2_MASK 4`

##### CLKPS3

`#define CLKPS3_BIT 3`

`#define CLKPS3_MASK 8`

##### CLKPCE

`#define CLKPCE_BIT 7`

`#define CLKPCE_MASK 128`

### SMCR - Sleep Mode Control Register

`sfrb SMCR = $33;`

##### SE - Sleep Enable

`#define SE_BIT 0`

`#define SE_MASK 1`

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.To

##### SM0 - Sleep Mode Select bit 0

`#define SM0_BIT 1`

`#define SM0_MASK 2`

These bits select between the five available sleep modes.

##### SM1 - Sleep Mode Select bit 1

`#define SM1_BIT 2`

`#define SM1_MASK 4`

These bits select between the five available sleep modes.

##### SM2 - Sleep Mode Select bit 2

`#define SM2_BIT 3`

`#define SM2_MASK 8`

These bits select between the five available sleep modes.

### EIND - Extended Indirect Register

`sfrb EIND = $3C;`

##### EIND0 - Bit 0

`#define EIND0_BIT 0`

`#define EIND0_MASK 1`

For EICALL/EIJMP instructions.

### GPIOR2 - General Purpose IO Register 2

`sfrb GPIOR2 = $2B;`

##### GPIOR20 - General Purpose IO Register 2 bit 0

`#define GPIOR20_BIT 0`

`#define GPIOR20_MASK 1`

##### GPIOR21 - General Purpose IO Register 2 bit 1

`#define GPIOR21_BIT 1`

`#define GPIOR21_MASK 2`

##### GPIOR22 - General Purpose IO Register 2 bit 2

`#define GPIOR22_BIT 2`

`#define GPIOR22_MASK 4`

##### GPIOR23 - General Purpose IO Register 2 bit 3

`#define GPIOR23_BIT 3`

`#define GPIOR23_MASK 8`

##### GPIOR24 - General Purpose IO Register 2 bit 4

`#define GPIOR24_BIT 4`

`#define GPIOR24_MASK 16`

##### GPIOR25 - General Purpose IO Register 2 bit 5

`#define GPIOR25_BIT 5`

`#define GPIOR25_MASK 32`

##### GPIOR26 - General Purpose IO Register 2 bit 6

`#define GPIOR26_BIT 6`

`#define GPIOR26_MASK 64`

##### GPIOR27 - General Purpose IO Register 2 bit 7

`#define GPIOR27_BIT 7`

`#define GPIOR27_MASK 128`

### GPIOR1 - General Purpose IO Register 1

`sfrb GPIOR1 = $2A;`

##### GPIOR10 - General Purpose IO Register 1 bit 0

`#define GPIOR10_BIT 0`

`#define GPIOR10_MASK 1`

##### GPIOR11 - General Purpose IO Register 1 bit 1

`#define GPIOR11_BIT 1`

`#define GPIOR11_MASK 2`

##### GPIOR12 - General Purpose IO Register 1 bit 2

`#define GPIOR12_BIT 2`

`#define GPIOR12_MASK 4`

##### GPIOR13 - General Purpose IO Register 1 bit 3

`#define GPIOR13_BIT 3`

`#define GPIOR13_MASK 8`

##### GPIOR14 - General Purpose IO Register 1 bit 4

`#define GPIOR14_BIT 4`

`#define GPIOR14_MASK 16`

##### GPIOR15 - General Purpose IO Register 1 bit 5

`#define GPIOR15_BIT 5`

`#define GPIOR15_MASK 32`

##### GPIOR16 - General Purpose IO Register 1 bit 6

`#define GPIOR16_BIT 6`

`#define GPIOR16_MASK 64`

##### GPIOR17 - General Purpose IO Register 1 bit 7

`#define GPIOR17_BIT 7`

`#define GPIOR17_MASK 128`

### GPIOR0 - General Purpose IO Register 0

`sfrb GPIOR0 = $1E;`

##### GPIOR00 - General Purpose IO Register 0 bit 0

`#define GPIOR00_BIT 0`

`#define GPIOR00_MASK 1`

##### GPIOR01 - General Purpose IO Register 0 bit 1

`#define GPIOR01_BIT 1`

`#define GPIOR01_MASK 2`

##### GPIOR02 - General Purpose IO Register 0 bit 2

`#define GPIOR02_BIT 2`

`#define GPIOR02_MASK 4`

##### GPIOR03 - General Purpose IO Register 0 bit 3

`#define GPIOR03_BIT 3`

`#define GPIOR03_MASK 8`

##### GPIOR04 - General Purpose IO Register 0 bit 4

`#define GPIOR04_BIT 4`

`#define GPIOR04_MASK 16`

##### GPIOR05 - General Purpose IO Register 0 bit 5

`#define GPIOR05_BIT 5`

`#define GPIOR05_MASK 32`

##### GPIOR06 - General Purpose IO Register 0 bit 6

`#define GPIOR06_BIT 6`

`#define GPIOR06_MASK 64`

##### GPIOR07 - General Purpose IO Register 0 bit 7

`#define GPIOR07_BIT 7`

`#define GPIOR07_MASK 128`

### PRR1 - Power Reduction Register1

`sfrb PRR1 = $65;`

##### PRUSART1 - Power Reduction USART1

`#define PRUSART1_BIT 0`

`#define PRUSART1_MASK 1`

##### PRUSB - Power Reduction USB

`#define PRUSB_BIT 7`

`#define PRUSB_MASK 128`

### PRR0 - Power Reduction Register0

`sfrb PRR0 = $64;`

##### PRSPI - Power Reduction Serial Peripheral Interface

`#define PRSPI_BIT 2`

`#define PRSPI_MASK 4`

##### PRTIM1 - Power Reduction Timer/Counter1

`#define PRTIM1_BIT 3`

`#define PRTIM1_MASK 8`

##### PRTIM0 - Power Reduction Timer/Counter0

`#define PRTIM0_BIT 5`

`#define PRTIM0_MASK 32`

### CKSTA -

`sfrb CKSTA = $D2;`

##### EXTON

`#define EXTON_BIT 0`

`#define EXTON_MASK 1`

##### RCON

`#define RCON_BIT 1`

`#define RCON_MASK 2`

### CKSEL1 -

`sfrb CKSEL1 = $D1;`

##### EXCKSEL0

`#define EXCKSEL0_BIT 0`

`#define EXCKSEL0_MASK 1`

##### EXCKSEL1

`#define EXCKSEL1_BIT 1`

`#define EXCKSEL1_MASK 2`

##### EXCKSEL2

`#define EXCKSEL2_BIT 2`

`#define EXCKSEL2_MASK 4`

##### EXCKSEL3

`#define EXCKSEL3_BIT 3`

`#define EXCKSEL3_MASK 8`

##### RCCKSEL0

`#define RCCKSEL0_BIT 4`

`#define RCCKSEL0_MASK 16`

##### RCCKSEL1

`#define RCCKSEL1_BIT 5`

`#define RCCKSEL1_MASK 32`

##### RCCKSEL2

`#define RCCKSEL2_BIT 6`

`#define RCCKSEL2_MASK 64`

##### RCCKSEL3

`#define RCCKSEL3_BIT 7`

`#define RCCKSEL3_MASK 128`

### CKSEL0 -

`sfrb CKSEL0 = $D0;`

##### CLKS

`#define CLKS_BIT 0`

`#define CLKS_MASK 1`

##### EXTE

`#define EXTE_BIT 2`

`#define EXTE_MASK 4`

##### RCE

`#define RCE_BIT 3`

`#define RCE_MASK 8`

##### EXSUT0

`#define EXSUT0_BIT 4`

`#define EXSUT0_MASK 16`

##### EXSUT1

`#define EXSUT1_BIT 5`

`#define EXSUT1_MASK 32`

##### RCSUT0

`#define RCSUT0_BIT 6`

`#define RCSUT0_MASK 64`

##### RCSUT1

`#define RCSUT1_BIT 7`

`#define RCSUT1_MASK 128`

## EXTERNAL INTERRUPT

The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in ?Clock Systems and their Distribution? on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in ?Clock Systems and their Distribution? on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt

### EICRA - External Interrupt Control Register A

`sfrb EICRA = $69;`

##### ISC00 - External Interrupt Sense Control Bit

`#define ISC00_BIT 0`

`#define ISC00_MASK 1`

##### ISC01 - External Interrupt Sense Control Bit

`#define ISC01_BIT 1`

`#define ISC01_MASK 2`

##### ISC10 - External Interrupt Sense Control Bit

`#define ISC10_BIT 2`

`#define ISC10_MASK 4`

##### ISC11 - External Interrupt Sense Control Bit

`#define ISC11_BIT 3`

`#define ISC11_MASK 8`

##### ISC20 - External Interrupt Sense Control Bit

`#define ISC20_BIT 4`

`#define ISC20_MASK 16`

##### ISC21 - External Interrupt Sense Control Bit

`#define ISC21_BIT 5`

`#define ISC21_MASK 32`

##### ISC30 - External Interrupt Sense Control Bit

`#define ISC30_BIT 6`

`#define ISC30_MASK 64`

##### ISC31 - External Interrupt Sense Control Bit

`#define ISC31_BIT 7`

`#define ISC31_MASK 128`

### EICRB - External Interrupt Control Register B

`sfrb EICRB = $6A;`

##### ISC40 - External Interrupt 7-4 Sense Control Bit

`#define ISC40_BIT 0`

`#define ISC40_MASK 1`

##### ISC41 - External Interrupt 7-4 Sense Control Bit

`#define ISC41_BIT 1`

`#define ISC41_MASK 2`

##### ISC50 - External Interrupt 7-4 Sense Control Bit

`#define ISC50_BIT 2`

`#define ISC50_MASK 4`

##### ISC51 - External Interrupt 7-4 Sense Control Bit

`#define ISC51_BIT 3`

`#define ISC51_MASK 8`

##### ISC60 - External Interrupt 7-4 Sense Control Bit

`#define ISC60_BIT 4`

`#define ISC60_MASK 16`

##### ISC61 - External Interrupt 7-4 Sense Control Bit

`#define ISC61_BIT 5`

`#define ISC61_MASK 32`

##### ISC70 - External Interrupt 7-4 Sense Control Bit

`#define ISC70_BIT 6`

`#define ISC70_MASK 64`

##### ISC71 - External Interrupt 7-4 Sense Control Bit

`#define ISC71_BIT 7`

`#define ISC71_MASK 128`

### EIMSK - External Interrupt Mask Register

`sfrb EIMSK = $1D;`

##### INT0 - External Interrupt Request 0 Enable

`#define INT0_BIT 0`

`#define INT0_MASK 1`

##### INT1 - External Interrupt Request 1 Enable

`#define INT1_BIT 1`

`#define INT1_MASK 2`

##### INT2 - External Interrupt Request 2 Enable

`#define INT2_BIT 2`

`#define INT2_MASK 4`

##### INT3 - External Interrupt Request 3 Enable

`#define INT3_BIT 3`

`#define INT3_MASK 8`

##### INT4 - External Interrupt Request 4 Enable

`#define INT4_BIT 4`

`#define INT4_MASK 16`

##### INT5 - External Interrupt Request 5 Enable

`#define INT5_BIT 5`

`#define INT5_MASK 32`

##### INT6 - External Interrupt Request 6 Enable

`#define INT6_BIT 6`

`#define INT6_MASK 64`

##### INT7 - External Interrupt Request 7 Enable

`#define INT7_BIT 7`

`#define INT7_MASK 128`

### EIFR - External Interrupt Flag Register

`sfrb EIFR = $1C;`

##### INTF0 - External Interrupt Flag 0

`#define INTF0_BIT 0`

`#define INTF0_MASK 1`

##### INTF1 - External Interrupt Flag 1

`#define INTF1_BIT 1`

`#define INTF1_MASK 2`

##### INTF2 - External Interrupt Flag 2

`#define INTF2_BIT 2`

`#define INTF2_MASK 4`

##### INTF3 - External Interrupt Flag 3

`#define INTF3_BIT 3`

`#define INTF3_MASK 8`

##### INTF4 - External Interrupt Flag 4

`#define INTF4_BIT 4`

`#define INTF4_MASK 16`

##### INTF5 - External Interrupt Flag 5

`#define INTF5_BIT 5`

`#define INTF5_MASK 32`

##### INTF6 - External Interrupt Flag 6

`#define INTF6_BIT 6`

`#define INTF6_MASK 64`

##### INTF7 - External Interrupt Flag 7

`#define INTF7_BIT 7`

`#define INTF7_MASK 128`

### PCMSK0 - Pin Change Mask Register 0

`sfrb PCMSK0 = $6B;`

##### PCINT0 - Pin Change Enable Mask 0

`#define PCINT0_BIT 0`

`#define PCINT0_MASK 1`

##### PCINT1 - Pin Change Enable Mask 1

`#define PCINT1_BIT 1`

`#define PCINT1_MASK 2`

##### PCINT2 - Pin Change Enable Mask 2

`#define PCINT2_BIT 2`

`#define PCINT2_MASK 4`

##### PCINT3 - Pin Change Enable Mask 3

`#define PCINT3_BIT 3`

`#define PCINT3_MASK 8`

##### PCINT4 - Pin Change Enable Mask 4

`#define PCINT4_BIT 4`

`#define PCINT4_MASK 16`

##### PCINT5 - Pin Change Enable Mask 5

`#define PCINT5_BIT 5`

`#define PCINT5_MASK 32`

##### PCINT6 - Pin Change Enable Mask 6

`#define PCINT6_BIT 6`

`#define PCINT6_MASK 64`

##### PCINT7 - Pin Change Enable Mask 7

`#define PCINT7_BIT 7`

`#define PCINT7_MASK 128`

### PCMSK0 - Pin Change Mask Register 0

`sfrb PCMSK0 = $6C;`

##### PCINT8

`#define PCINT8_BIT 0`

`#define PCINT8_MASK 1`

##### PCINT9

`#define PCINT9_BIT 1`

`#define PCINT9_MASK 2`

##### PCINT10

`#define PCINT10_BIT 2`

`#define PCINT10_MASK 4`

##### PCINT12

`#define PCINT12_BIT 4`

`#define PCINT12_MASK 16`

### PCIFR - Pin Change Interrupt Flag Register

`sfrb PCIFR = $1B;`

##### PCIF0 - Pin Change Interrupt Flag 0

`#define PCIF0_BIT 0`

`#define PCIF0_MASK 1`

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

##### PCIF1 - Pin Change Interrupt Flag 1

`#define PCIF1_BIT 1`

`#define PCIF1_MASK 2`

When a logic change on any PCINT14..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

### PCICR - Pin Change Interrupt Control Register

`sfrb PCICR = $68;`

##### PCIE0 - Pin Change Interrupt Enable 0

`#define PCIE0_BIT 0`

`#define PCIE0_MASK 1`

##### PCIE1 - Pin Change Interrupt Enable 1

`#define PCIE1_BIT 1`

`#define PCIE1_MASK 2`

## USART1

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: ? Full Duplex Operation (Independent Serial Receive and Transmit Registers) ? Asynchronous or Synchronous Operation ? Master or Slave Clocked Synchronous Operation ? High Resolution Baud Rate Generator ? Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits ? Odd or Even Parity Generation and Parity Check Supported by Hardware ? Data OverRun Detection ? Framing Error Detection ? Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter ? Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete ? Multi-processor Communication Mode ? Double Speed Asynchronous Communica

### UDR1 - USART I/O Data Register

`sfrb UDR1 = $CE;`

##### UDR1-0 - USART I/O Data Register bit 0

`#define UDR1-0_BIT 0`

`#define UDR1-0_MASK 1`

##### UDR1-1 - USART I/O Data Register bit 1

`#define UDR1-1_BIT 1`

`#define UDR1-1_MASK 2`

##### UDR1-2 - USART I/O Data Register bit 2

`#define UDR1-2_BIT 2`

`#define UDR1-2_MASK 4`

##### UDR1-3 - USART I/O Data Register bit 3

`#define UDR1-3_BIT 3`

`#define UDR1-3_MASK 8`

##### UDR1-4 - USART I/O Data Register bit 4

`#define UDR1-4_BIT 4`

`#define UDR1-4_MASK 16`

##### UDR1-5 - USART I/O Data Register bit 5

`#define UDR1-5_BIT 5`

`#define UDR1-5_MASK 32`

##### UDR1-6 - USART I/O Data Register bit 6

`#define UDR1-6_BIT 6`

`#define UDR1-6_MASK 64`

##### UDR1-7 - USART I/O Data Register bit 7

`#define UDR1-7_BIT 7`

`#define UDR1-7_MASK 128`

### UCSR1A - USART Control and Status Register A

`sfrb UCSR1A = $C8;`

##### MPCM1 - Multi-processor Communication Mode

`#define MPCM1_BIT 0`

`#define MPCM1_MASK 1`

This bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see ?Multi-processor Communication Mode? on page 152.

##### U2X1 - Double the USART transmission speed

`#define U2X1_BIT 1`

`#define U2X1_MASK 2`

This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.

##### UPE1 - Parity Error

`#define UPE1_BIT 2`

`#define UPE1_MASK 4`

This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A.

##### DOR1 - Data overRun

`#define DOR1_BIT 3`

`#define DOR1_MASK 8`

This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0.

##### FE1 - Framing Error

`#define FE1_BIT 4`

`#define FE1_MASK 16`

This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.

##### UDRE1 - USART Data Register Empty

`#define UDRE1_BIT 5`

`#define UDRE1_MASK 32`

This bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is re

##### TXC1 - USART Transmitt Complete

`#define TXC1_BIT 6`

`#define TXC1_MASK 64`

This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the b

##### RXC1 - USART Receive Complete

`#define RXC1_BIT 7`

`#define RXC1_MASK 128`

This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.

### UCSR1B - USART Control and Status Register B

`sfrb UCSR1B = $C9;`

##### TXB81 - Transmit Data Bit 8

`#define TXB81_BIT 0`

`#define TXB81_MASK 1`

TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.

##### RXB81 - Receive Data Bit 8

`#define RXB81_BIT 1`

`#define RXB81_MASK 2`

RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.

##### UCSZ12 - Character Size

`#define UCSZ12_BIT 2`

`#define UCSZ12_MASK 4`

The UCSZ2 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use.

##### TXEN1 - Transmitter Enable

`#define TXEN1_BIT 3`

`#define TXEN1_MASK 8`

Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.

##### RXEN1 - Receiver Enable

`#define RXEN1_BIT 4`

`#define RXEN1_MASK 16`

Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.

##### UDRIE1 - USART Data register Empty Interrupt Enable

`#define UDRIE1_BIT 5`

`#define UDRIE1_MASK 32`

Writing this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.

##### TXCIE1 - TX Complete Interrupt Enable

`#define TXCIE1_BIT 6`

`#define TXCIE1_MASK 64`

Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.

##### RXCIE1 - RX Complete Interrupt Enable

`#define RXCIE1_BIT 7`

`#define RXCIE1_MASK 128`

Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.

### UCSR1C - USART Control and Status Register C

`sfrb UCSR1C = $CA;`

##### UCPOL1 - Clock Polarity

`#define UCPOL1_BIT 0`

`#define UCPOL1_MASK 1`

This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).

##### UCSZ10 - Character Size

`#define UCSZ10_BIT 1`

`#define UCSZ10_MASK 2`

Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.

##### UCSZ11 - Character Size

`#define UCSZ11_BIT 2`

`#define UCSZ11_MASK 4`

Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.

##### USBS1 - Stop Bit Select

`#define USBS1_BIT 3`

`#define USBS1_MASK 8`

0: 1-bit. 1: 2-bit.

##### UPM10 - Parity Mode Bit 0

`#define UPM10_BIT 4`

`#define UPM10_MASK 16`

This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.

##### UPM11 - Parity Mode Bit 1

`#define UPM11_BIT 5`

`#define UPM11_MASK 32`

This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.

##### UMSEL10 - USART Mode Select

`#define UMSEL10_BIT 6`

`#define UMSEL10_MASK 64`

##### UMSEL11 - USART Mode Select

`#define UMSEL11_BIT 7`

`#define UMSEL11_MASK 128`

### UCSR1D - USART Control and Status Register D

`sfrb UCSR1D = $CB;`

##### RTSEN - RTS Enable

`#define RTSEN_BIT 0`

`#define RTSEN_MASK 1`

##### CTSEN - CTS Enable

`#define CTSEN_BIT 1`

`#define CTSEN_MASK 2`

### UBRR1H - USART Baud Rate Register High Byte

`sfrb UBRR1H = $CD;`

##### UBRR8 - USART Baud Rate Register bit 8

`#define UBRR8_BIT 0`

`#define UBRR8_MASK 1`

##### UBRR9 - USART Baud Rate Register bit 9

`#define UBRR9_BIT 1`

`#define UBRR9_MASK 2`

##### UBRR10 - USART Baud Rate Register bit 10

`#define UBRR10_BIT 2`

`#define UBRR10_MASK 4`

##### UBRR11 - USART Baud Rate Register bit 11

`#define UBRR11_BIT 3`

`#define UBRR11_MASK 8`

### UBRR1L - USART Baud Rate Register Low Byte

`sfrb UBRR1L = $CC;`

##### UBRR0 - USART Baud Rate Register bit 0

`#define UBRR0_BIT 0`

`#define UBRR0_MASK 1`

##### UBRR1 - USART Baud Rate Register bit 1

`#define UBRR1_BIT 1`

`#define UBRR1_MASK 2`

##### UBRR2 - USART Baud Rate Register bit 2

`#define UBRR2_BIT 2`

`#define UBRR2_MASK 4`

##### UBRR3 - USART Baud Rate Register bit 3

`#define UBRR3_BIT 3`

`#define UBRR3_MASK 8`

##### UBRR4 - USART Baud Rate Register bit 4

`#define UBRR4_BIT 4`

`#define UBRR4_MASK 16`

##### UBRR5 - USART Baud Rate Register bit 5

`#define UBRR5_BIT 5`

`#define UBRR5_MASK 32`

##### UBRR6 - USART Baud Rate Register bit 6

`#define UBRR6_BIT 6`

`#define UBRR6_MASK 64`

##### UBRR7 - USART Baud Rate Register bit 7

`#define UBRR7_BIT 7`

`#define UBRR7_MASK 128`

## WATCHDOG

### WDTCSR - Watchdog Timer Control Register

`sfrb WDTCSR = $60;`

##### WDP0 - Watch Dog Timer Prescaler bit 0

`#define WDP0_BIT 0`

`#define WDP0_MASK 1`

##### WDP1 - Watch Dog Timer Prescaler bit 1

`#define WDP1_BIT 1`

`#define WDP1_MASK 2`

##### WDP2 - Watch Dog Timer Prescaler bit 2

`#define WDP2_BIT 2`

`#define WDP2_MASK 4`

##### WDE - Watch Dog Enable

`#define WDE_BIT 3`

`#define WDE_MASK 8`

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog

##### WDCE - Watchdog Change Enable

`#define WDCE_BIT 4`

`#define WDCE_MASK 16`

##### WDP3 - Watchdog Timer Prescaler Bit 3

`#define WDP3_BIT 5`

`#define WDP3_MASK 32`

##### WDIE - Watchdog Timeout Interrupt Enable

`#define WDIE_BIT 6`

`#define WDIE_MASK 64`

##### WDIF - Watchdog Timeout Interrupt Flag

`#define WDIF_BIT 7`

`#define WDIF_MASK 128`

### WDTCKD - Watchdog Timer Clock Divider

`sfrb WDTCKD = $62;`

##### WCLKDO - Watchdog Timer Clock Divider 0

`#define WCLKDO_BIT 0`

`#define WCLKDO_MASK 1`

##### WCLKD1 - Watchdog Timer Clock Divider 1

`#define WCLKD1_BIT 1`

`#define WCLKD1_MASK 2`

##### WDEWIE - Watchdog Early Warning Interrupt Enable

`#define WDEWIE_BIT 2`

`#define WDEWIE_MASK 4`

##### WDEWIF - Watchdog Early Warning Interrupt Flag

`#define WDEWIF_BIT 3`

`#define WDEWIF_MASK 8`