This documentation was generated automatically from the AVR Studio part description file `ATmega406.pdf`.

## AD CONVERTER

12-bit resolution Sigmal-Delta ADC with +/-1 LSB Accuracy. 512 us conversion time.

### VADMUX - The VADC multiplexer Selection Register

`sfrb VADMUX = 0x7C;`

##### VADMUX0 - Analog Channel and Gain Selection Bits

`#define VADMUX0_BIT 0`

`#define VADMUX0_MASK 1`

The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).

##### VADMUX1 - Analog Channel and Gain Selection Bits

`#define VADMUX1_BIT 1`

`#define VADMUX1_MASK 2`

The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).

##### VADMUX2 - Analog Channel and Gain Selection Bits

`#define VADMUX2_BIT 2`

`#define VADMUX2_MASK 4`

The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).

##### VADMUX3 - Analog Channel and Gain Selection Bits

`#define VADMUX3_BIT 3`

`#define VADMUX3_MASK 8`

The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).

### VADCH - VADC Data Register High Byte

`sfrb VADCH = 0x79;`

##### VADC8 - ADC Data Register High Byte Bit 0

`#define VADC8_BIT 0`

`#define VADC8_MASK 1`

##### VADC9 - ADC Data Register High Byte Bit 1

`#define VADC9_BIT 1`

`#define VADC9_MASK 2`

##### VADC10 - ADC Data Register High Byte Bit 2

`#define VADC10_BIT 2`

`#define VADC10_MASK 4`

##### VADC11 - ADC Data Register High Byte Bit 3

`#define VADC11_BIT 3`

`#define VADC11_MASK 8`

### VADCL - VADC Data Register Low Byte

`sfrb VADCL = 0x78;`

##### VADC0 - ADC Data Register Low Byte Bit 0

`#define VADC0_BIT 0`

`#define VADC0_MASK 1`

##### VADC1 - ADC Data Register Low Byte Bit 1

`#define VADC1_BIT 1`

`#define VADC1_MASK 2`

##### VADC2 - ADC Data Register Low Byte Bit 2

`#define VADC2_BIT 2`

`#define VADC2_MASK 4`

##### VADC3 - ADC Data Register Low Byte Bit 3

`#define VADC3_BIT 3`

`#define VADC3_MASK 8`

##### VADC4 - ADC Data Register Low Byte Bit 4

`#define VADC4_BIT 4`

`#define VADC4_MASK 16`

##### VADC5 - ADC Data Register Low Byte Bit 5

`#define VADC5_BIT 5`

`#define VADC5_MASK 32`

##### VADC6 - ADC Data Register Low Byte Bit 6

`#define VADC6_BIT 6`

`#define VADC6_MASK 64`

##### VADC7 - ADC Data Register Low Byte Bit 7

`#define VADC7_BIT 7`

`#define VADC7_MASK 128`

### VADCSR - The VADC Control and Status register

`sfrb VADCSR = 0x7A;`

##### VADCCIE - VADC Conversion Complete Interrupt Enable

`#define VADCCIE_BIT 0`

`#define VADCCIE_MASK 1`

When this bit is written to one and the I-Bit in SREG is set, the V-ADC Conversion Complete Interrupt is activated

##### VADCCIF - VADC Conversion Complete Interrupt Flag

`#define VADCCIF_BIT 1`

`#define VADCCIF_MASK 2`

This bit is set when a V-ADC conversion completes and the data registers are updated.V-ADC Conversion complete Interrupt is executed if the VADCCIE bit and the I-bit in S-REG are set. VADCCIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, VADCCIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on VADCSR, a pending interrupt can be disabled.

##### VADSC - VADC Satrt Conversion

`#define VADSC_BIT 2`

`#define VADSC_MASK 4`

Write this bit to one to start a new conversion of the selected channel. VADSC will read as one as long as the conversion is not finished. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect.

##### VADEN - VADC Enable

`#define VADEN_BIT 3`

`#define VADEN_MASK 8`

Writing this bit to one enables V-ADC Conversion. By writing it to zero, the V-ADC is turned off. Turning the V-ADC off while a conversion is in progress will terminate this conversion

## EXTERNAL INTERRUPT

The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in ?Clock Systems and their Distribution? on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in ?Clock Systems and their Distribution? on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interru

### EICRA - External Interrupt Control Register

`sfrb EICRA = 0x69;`

##### ISC00 - External Interrupt Sense Control 0 Bit 0

`#define ISC00_BIT 0`

`#define ISC00_MASK 1`

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt.

##### ISC01 - External Interrupt Sense Control 0 Bit 1

`#define ISC01_BIT 1`

`#define ISC01_MASK 2`

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt.

##### ISC10 - External Interrupt Sense Control 1 Bit 0

`#define ISC10_BIT 2`

`#define ISC10_MASK 4`

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt.

##### ISC11 - External Interrupt Sense Control 1 Bit 1

`#define ISC11_BIT 3`

`#define ISC11_MASK 8`

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt.

##### ISC20 - External Interrupt Sense Control 2 Bit 0

`#define ISC20_BIT 4`

`#define ISC20_MASK 16`

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt.

##### ISC21 - External Interrupt Sense Control 2 Bit 1

`#define ISC21_BIT 5`

`#define ISC21_MASK 32`

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt.

##### ISC30 - External Interrupt Sense Control 3 Bit 0

`#define ISC30_BIT 6`

`#define ISC30_MASK 64`

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt.

##### ISC31 - External Interrupt Sense Control 3 Bit 1

`#define ISC31_BIT 7`

`#define ISC31_MASK 128`

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt.

### EIMSK - External Interrupt Mask Register

`sfrb EIMSK = 0x1D;`

##### INT0 - External Interrupt Request 0 Enable

`#define INT0_BIT 0`

`#define INT0_MASK 1`

When the INT0 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed.Activity on the pin will cause an interrupt request even if INT0 is configured as an output.The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 interrupt vector.

##### INT1 - External Interrupt Request 1 Enable

`#define INT1_BIT 1`

`#define INT1_MASK 2`

When the INT1 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector.

##### INT2 - External Interrupt Request 1 Enable

`#define INT2_BIT 2`

`#define INT2_MASK 4`

When the INT2 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector.

##### INT3 - External Interrupt Request 1 Enable

`#define INT3_BIT 3`

`#define INT3_MASK 8`

When the INT3 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector.

### EIFR - External Interrupt Flag Register

`sfrb EIFR = 0x1C;`

##### INTF0 - External Interrupt Flag 0

`#define INTF0_BIT 0`

`#define INTF0_MASK 1`

When an edge or logic change on the INT0 pin triggers an interrupt request,INTF0 becomes set (one).If the I-bit in SREG and the INT0 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt.

##### INTF1 - External Interrupt Flag 1

`#define INTF1_BIT 1`

`#define INTF1_MASK 2`

When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt.

##### INTF2 - External Interrupt Flag 2

`#define INTF2_BIT 2`

`#define INTF2_MASK 4`

When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt.

##### INTF3 - External Interrupt Flag 3

`#define INTF3_BIT 3`

`#define INTF3_MASK 8`

When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt.

### PCICR - Pin Change Interrupt Control Register

`sfrb PCICR = 0x68;`

##### PCIE0 - Pin Change Interrupt Enable 0

`#define PCIE0_BIT 0`

`#define PCIE0_MASK 1`

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.

##### PCIE1 - Pin Change Interrupt Enable 1

`#define PCIE1_BIT 1`

`#define PCIE1_MASK 2`

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register.

### PCIFR - Pin Change Interrupt Flag Register

`sfrb PCIFR = 0x1B;`

##### PCIF0 - Pin Change Interrupt Flag 1

`#define PCIF0_BIT 0`

`#define PCIF0_MASK 1`

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

##### PCIF1 - Pin Change Interrupt Flag 1

`#define PCIF1_BIT 1`

`#define PCIF1_MASK 2`

When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

### PCMSK1 - Pin Change Enable Mask Register 1

`sfrb PCMSK1 = 0x6C;`

##### PCINT8 - Pin Change Enable Mask 8

`#define PCINT8_BIT 0`

`#define PCINT8_MASK 1`

##### PCINT9 - Pin Change Enable Mask 9

`#define PCINT9_BIT 1`

`#define PCINT9_MASK 2`

##### PCINT10 - Pin Change Enable Mask 10

`#define PCINT10_BIT 2`

`#define PCINT10_MASK 4`

##### PCINT11 - Pin Change Enable Mask 11

`#define PCINT11_BIT 3`

`#define PCINT11_MASK 8`

##### PCINT12 - Pin Change Enable Mask 12

`#define PCINT12_BIT 4`

`#define PCINT12_MASK 16`

##### PCINT13 - Pin Change Enable Mask 13

`#define PCINT13_BIT 5`

`#define PCINT13_MASK 32`

##### PCINT14 - Pin Change Enable Mask 14

`#define PCINT14_BIT 6`

`#define PCINT14_MASK 64`

##### PCINT15 - Pin Change Enable Mask 15

`#define PCINT15_BIT 7`

`#define PCINT15_MASK 128`

### PCMSK0 - Pin Change Enable Mask Register 0

`sfrb PCMSK0 = 0x6B;`

##### PCINT0 - Pin Change Enable Mask 0

`#define PCINT0_BIT 0`

`#define PCINT0_MASK 1`

##### PCINT1 - Pin Change Enable Mask 1

`#define PCINT1_BIT 1`

`#define PCINT1_MASK 2`

##### PCINT2 - Pin Change Enable Mask 2

`#define PCINT2_BIT 2`

`#define PCINT2_MASK 4`

##### PCINT3 - Pin Change Enable Mask 3

`#define PCINT3_BIT 3`

`#define PCINT3_MASK 8`

##### PCINT4 - Pin Change Enable Mask 4

`#define PCINT4_BIT 4`

`#define PCINT4_MASK 16`

##### PCINT5 - Pin Change Enable Mask 5

`#define PCINT5_BIT 5`

`#define PCINT5_MASK 32`

##### PCINT6 - Pin Change Enable Mask 6

`#define PCINT6_BIT 6`

`#define PCINT6_MASK 64`

##### PCINT7 - Pin Change Enable Mask 7

`#define PCINT7_BIT 7`

`#define PCINT7_MASK 128`

## TIMER COUNTER 1

### TCCR1B - Timer/Counter1 Control Register B

`sfrb TCCR1B = 0x81;`

##### CS10 - Clock Select1 bit 0

`#define CS10_BIT 0`

`#define CS10_MASK 1`

##### CS11 - Clock Select1 bit 1

`#define CS11_BIT 1`

`#define CS11_MASK 2`

##### CS12 - Clock Select1 bit 2

`#define CS12_BIT 2`

`#define CS12_MASK 4`

##### CTC1 - Clear Timer/Counter on Compare Match

`#define CTC1_BIT 3`

`#define CTC1_MASK 8`

### TCNT1H - Timer Counter 1 High Byte

`sfrb TCNT1H = 0x85;`

##### TCNT1H0 - Timer Counter 1 High Byte bit 0

`#define TCNT1H0_BIT 0`

`#define TCNT1H0_MASK 1`

##### TCNT1H1 - Timer Counter 1 High Byte bit 1

`#define TCNT1H1_BIT 1`

`#define TCNT1H1_MASK 2`

##### TCNT1H2 - Timer Counter 1 High Byte bit 2

`#define TCNT1H2_BIT 2`

`#define TCNT1H2_MASK 4`

##### TCNT1H3 - Timer Counter 1 High Byte bit 3

`#define TCNT1H3_BIT 3`

`#define TCNT1H3_MASK 8`

##### TCNT1H4 - Timer Counter 1 High Byte bit 4

`#define TCNT1H4_BIT 4`

`#define TCNT1H4_MASK 16`

##### TCNT1H5 - Timer Counter 1 High Byte bit 5

`#define TCNT1H5_BIT 5`

`#define TCNT1H5_MASK 32`

##### TCNT1H6 - Timer Counter 1 High Byte bit 6

`#define TCNT1H6_BIT 6`

`#define TCNT1H6_MASK 64`

##### TCNT1H7 - Timer Counter 1 High Byte bit 7

`#define TCNT1H7_BIT 7`

`#define TCNT1H7_MASK 128`

### TCNT1L - Timer Counter 1 Low Byte

`sfrb TCNT1L = 0x84;`

##### TCNT1L0 - Timer Counter 1 Low Byte bit 0

`#define TCNT1L0_BIT 0`

`#define TCNT1L0_MASK 1`

##### TCNT1L1 - Timer Counter 1 Low Byte bit 1

`#define TCNT1L1_BIT 1`

`#define TCNT1L1_MASK 2`

##### TCNT1L2 - Timer Counter 1 Low Byte bit 2

`#define TCNT1L2_BIT 2`

`#define TCNT1L2_MASK 4`

##### TCNT1L3 - Timer Counter 1 Low Byte bit 3

`#define TCNT1L3_BIT 3`

`#define TCNT1L3_MASK 8`

##### TCNT1L4 - Timer Counter 1 Low Byte bit 4

`#define TCNT1L4_BIT 4`

`#define TCNT1L4_MASK 16`

##### TCNT1L5 - Timer Counter 1 Low Byte bit 5

`#define TCNT1L5_BIT 5`

`#define TCNT1L5_MASK 32`

##### TCNT1L6 - Timer Counter 1 Low Byte bit 6

`#define TCNT1L6_BIT 6`

`#define TCNT1L6_MASK 64`

##### TCNT1L7 - Timer Counter 1 Low Byte bit 7

`#define TCNT1L7_BIT 7`

`#define TCNT1L7_MASK 128`

### OCR1AL - Output Compare Register 1A Low byte

`sfrb OCR1AL = 0x88;`

##### OCR1AL0

`#define OCR1AL0_BIT 0`

`#define OCR1AL0_MASK 1`

##### OCR1AL1

`#define OCR1AL1_BIT 1`

`#define OCR1AL1_MASK 2`

##### OCR1AL2

`#define OCR1AL2_BIT 2`

`#define OCR1AL2_MASK 4`

##### OCR1AL3

`#define OCR1AL3_BIT 3`

`#define OCR1AL3_MASK 8`

##### OCR1AL4

`#define OCR1AL4_BIT 4`

`#define OCR1AL4_MASK 16`

##### OCR1AL5

`#define OCR1AL5_BIT 5`

`#define OCR1AL5_MASK 32`

##### OCR1AL6

`#define OCR1AL6_BIT 6`

`#define OCR1AL6_MASK 64`

##### OCR1AL7

`#define OCR1AL7_BIT 7`

`#define OCR1AL7_MASK 128`

### OCR1AH - Output Compare Register 1A High byte

`sfrb OCR1AH = 0x89;`

##### OCR1AH0

`#define OCR1AH0_BIT 0`

`#define OCR1AH0_MASK 1`

##### OCR1AH1

`#define OCR1AH1_BIT 1`

`#define OCR1AH1_MASK 2`

##### OCR1AH2

`#define OCR1AH2_BIT 2`

`#define OCR1AH2_MASK 4`

##### OCR1AH3

`#define OCR1AH3_BIT 3`

`#define OCR1AH3_MASK 8`

##### OCR1AH4

`#define OCR1AH4_BIT 4`

`#define OCR1AH4_MASK 16`

##### OCR1AH5

`#define OCR1AH5_BIT 5`

`#define OCR1AH5_MASK 32`

##### OCR1AH6

`#define OCR1AH6_BIT 6`

`#define OCR1AH6_MASK 64`

##### OCR1AH7

`#define OCR1AH7_BIT 7`

`#define OCR1AH7_MASK 128`

### TIMSK1 - Timer/Counter Interrupt Mask Register

`sfrb TIMSK1 = 0x6F;`

##### TOIE1 - Timer/Counter1 Overflow Interrupt Enable

`#define TOIE1_BIT 0`

`#define TOIE1_MASK 1`

##### OCIE1A - Timer/Counter1 Output Compare Interrupt Enable

`#define OCIE1A_BIT 1`

`#define OCIE1A_MASK 2`

### TIFR1 - Timer/Counter Interrupt Flag register

`sfrb TIFR1 = 0x16;`

##### TOV1 - Timer/Counter1 Overflow Flag

`#define TOV1_BIT 0`

`#define TOV1_MASK 1`

##### OCF1A - Timer/Counter1 Output Compare Flag A

`#define OCF1A_BIT 1`

`#define OCF1A_MASK 2`

### GTCCR - General Timer/Counter Control Register

`sfrb GTCCR = 0x23;`

##### PSRSYNC - Prescaler Reset

`#define PSRSYNC_BIT 0`

`#define PSRSYNC_MASK 1`

##### TSM - Timer/Counter Synchronization Mode

`#define TSM_BIT 7`

`#define TSM_MASK 128`

## WAKEUP TIMER

### WUTCSR - Wake-up Timer Control Register

`sfrb WUTCSR = 0x62;`

##### WUTP0 - Wake-up Timer Prescaler Bit 0

`#define WUTP0_BIT 0`

`#define WUTP0_MASK 1`

The WUTP2, WUTP1 and WUTP0 bits determine the Wake-up Timer prescaling when the Wake-up Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in the datasheet.

##### WUTP1 - Wake-up Timer Prescaler Bit 1

`#define WUTP1_BIT 1`

`#define WUTP1_MASK 2`

The WUTP2, WUTP1 and WUTP0 bits determine the Wake-up Timer prescaling when the Wake-up Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in the datasheet.

##### WUTP2 - Wake-up Timer Prescaler Bit 2

`#define WUTP2_BIT 2`

`#define WUTP2_MASK 4`

The WUTP2, WUTP1 and WUTP0 bits determine the Wake-up Timer prescaling when the Wake-up Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in the datasheet.

##### WUTE - Wake-up Timer Enable

`#define WUTE_BIT 3`

`#define WUTE_MASK 8`

When the WUTE is set (one) the Wake-up Timer is enabled, and the WUTE is cleared (zero) the Wake-up Timer function is disabled.

##### WUTR - Wake-up Timer Reset

`#define WUTR_BIT 4`

`#define WUTR_MASK 16`

When WUTR is written to one, the Wake-up Timer is reset, and starts counting from zero. The WUTR bit is automatically cleared to zero after the reset has been performed.

##### WUTCF - Wake-up timer Calibration Flag

`#define WUTCF_BIT 5`

`#define WUTCF_MASK 32`

The WUTCF bit is set after every 256 Slow RC OScillator clocks (2 ms @ 131 kHz)

##### WUTIE - Wake-up Timer Interrupt Enable

`#define WUTIE_BIT 6`

`#define WUTIE_MASK 64`

When the WUTIE bit and the I-bit in the Status Register are set (one), the Wake-up Timer interrupt is enabled. The corresponding interrupt is executed if a Wake-up Timer overflow occurs, i.e., when the WUTIF bit is set .

##### WUTIF - Wake-up Timer Interrupt Flag

`#define WUTIF_BIT 7`

`#define WUTIF_MASK 128`

The bit WUTIF is set (one) when an overflow occurs in the Wake-up Timer. WUTIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, WUTIE (Wake-up Timer Interrupt Enable), and WUTIF are set (one), the Wake-up Timer interrupt is executed.

## BATTERY PROTECTION

### BPPLR - Battery Protection Parameter Lock Register

`sfrb BPPLR = 0xF8;`

##### BPPL - Battery Protection Parameter Lock

`#define BPPL_BIT 0`

`#define BPPL_MASK 1`

##### BPPLE - Battery Protection Parameter Lock Enable

`#define BPPLE_BIT 1`

`#define BPPLE_MASK 2`

### BPCR - Battery Protection Control Register

`sfrb BPCR = 0xF7;`

##### CCD

`#define CCD_BIT 0`

`#define CCD_MASK 1`

##### DCD

`#define DCD_BIT 1`

`#define DCD_MASK 2`

##### SCD

`#define SCD_BIT 2`

`#define SCD_MASK 4`

##### DUVD

`#define DUVD_BIT 3`

`#define DUVD_MASK 8`

### CBPTR - Current Battery Protection Timing Register

`sfrb CBPTR = 0xF6;`

##### OCPT0

`#define OCPT0_BIT 0`

`#define OCPT0_MASK 1`

##### OCPT1

`#define OCPT1_BIT 1`

`#define OCPT1_MASK 2`

##### OCPT2

`#define OCPT2_BIT 2`

`#define OCPT2_MASK 4`

##### OCPT3

`#define OCPT3_BIT 3`

`#define OCPT3_MASK 8`

##### SCPT0

`#define SCPT0_BIT 4`

`#define SCPT0_MASK 16`

##### SCPT1

`#define SCPT1_BIT 5`

`#define SCPT1_MASK 32`

##### SCPT2

`#define SCPT2_BIT 6`

`#define SCPT2_MASK 64`

##### SCPT3

`#define SCPT3_BIT 7`

`#define SCPT3_MASK 128`

### BPOCD - Battery Protection OverCurrent Detection Level Register

`sfrb BPOCD = 0xF5;`

##### CCDL0

`#define CCDL0_BIT 0`

`#define CCDL0_MASK 1`

##### CCDL1

`#define CCDL1_BIT 1`

`#define CCDL1_MASK 2`

##### CCDL2

`#define CCDL2_BIT 2`

`#define CCDL2_MASK 4`

##### CCDL3

`#define CCDL3_BIT 3`

`#define CCDL3_MASK 8`

##### DCDL0

`#define DCDL0_BIT 4`

`#define DCDL0_MASK 16`

##### DCDL1

`#define DCDL1_BIT 5`

`#define DCDL1_MASK 32`

##### DCDL2

`#define DCDL2_BIT 6`

`#define DCDL2_MASK 64`

##### DCDL3

`#define DCDL3_BIT 7`

`#define DCDL3_MASK 128`

### BPSCD - Battery Protection Short-Circuit Detection Level Register

`sfrb BPSCD = 0xF4;`

##### SCDL0

`#define SCDL0_BIT 0`

`#define SCDL0_MASK 1`

##### SCDL1

`#define SCDL1_BIT 1`

`#define SCDL1_MASK 2`

##### SCDL2

`#define SCDL2_BIT 2`

`#define SCDL2_MASK 4`

##### SCDL3

`#define SCDL3_BIT 3`

`#define SCDL3_MASK 8`

### BPDUV - Battery Protection Deep Under Voltage Register

`sfrb BPDUV = 0xF3;`

##### DUDL0

`#define DUDL0_BIT 0`

`#define DUDL0_MASK 1`

##### DUDL1

`#define DUDL1_BIT 1`

`#define DUDL1_MASK 2`

##### DUDL2

`#define DUDL2_BIT 2`

`#define DUDL2_MASK 4`

##### DUDL3

`#define DUDL3_BIT 3`

`#define DUDL3_MASK 8`

##### DUVT0

`#define DUVT0_BIT 4`

`#define DUVT0_MASK 16`

##### DUVT1

`#define DUVT1_BIT 5`

`#define DUVT1_MASK 32`

### BPIR - Battery Protection Interrupt Register

`sfrb BPIR = 0xF2;`

##### SCIE

`#define SCIE_BIT 0`

`#define SCIE_MASK 1`

##### DOCIE

`#define DOCIE_BIT 1`

`#define DOCIE_MASK 2`

##### COCIE

`#define COCIE_BIT 2`

`#define COCIE_MASK 4`

##### DUVIE - Deep Under-voltage Early Warning Interrupt Enable

`#define DUVIE_BIT 3`

`#define DUVIE_MASK 8`

##### SCIF

`#define SCIF_BIT 4`

`#define SCIF_MASK 16`

##### DOCIF

`#define DOCIF_BIT 5`

`#define DOCIF_MASK 32`

##### COCIF - Charge Over-current Protection Activated Interrupt Flag

`#define COCIF_BIT 6`

`#define COCIF_MASK 64`

##### DUVIF - Deep Under-voltage Early Warning Interrupt Flag

`#define DUVIF_BIT 7`

`#define DUVIF_MASK 128`

## FET

### FCSR -

`sfrb FCSR = 0xF0;`

##### PFD - Precharge FET disable

`#define PFD_BIT 0`

`#define PFD_MASK 1`

The PFD bit provides complete control of the Precharge FET. When the PFD bit is cleared (zero), the Precharge FET will be enabled. When the PFD bit is set (one), the Precharge FET will be disabled. This bit will be set when CURRENT_PROTECTION is set (one).

##### CFE - Charge FET Enable

`#define CFE_BIT 1`

`#define CFE_MASK 2`

When the CFE bit is cleared (zero), the Charge FET will be disabled regardless of the state of the Battery Protection circuitry. When this bit is set (one), the Charge FET state is determined by the Battery Protection circuitry. This bit will be cleared when CURRENT_PROTECTION is set (one).

##### DFE - Discharge FET Enable

`#define DFE_BIT 2`

`#define DFE_MASK 4`

When the DFE bit is cleared (zero), the Discharge FET will be disabled regardless of the state of the Battery Protection circuitry. When this bit is set (one), the Discharge FET state is determined by the Battery Protection circuitry. This bit will be cleared when CURRENT_PROTECTION is set (one).

##### CPS - Current Protection Status

`#define CPS_BIT 3`

`#define CPS_MASK 8`

The CPTS bit shows the status of the Current Protection. This bit is set (one) when the Current Protection Timer is activated, and is cleared (zero) when the hold-off time has elapsed.

##### PWMOPC - Pulse Width Modulation Modulation of OPC output

`#define PWMOPC_BIT 4`

`#define PWMOPC_MASK 16`

When the PWMOPC is cleared (zero), the PFD bit and the battery protection circuitry controls the OPC output. When this bit is set (one), the OC output will be controlled by the PWM output from the 8-bit Timer/Counter0 and the battery protection circuitry.

##### PWMOC - Pulse Width Modulation of OC output

`#define PWMOC_BIT 5`

`#define PWMOC_MASK 32`

When the PWMOC is cleared (zero), the CFE bit and the battery protection circuitry controls the OC output. When this bit is set (one), the OC output will be controlled by the PWM output from the 8-bit Timer/Counter0 and the battery protection circuitry.

## COULOMB COUNTER

### CADCSRA - CC-ADC Control and Status Register A

`sfrb CADCSRA = 0xE4;`

##### CADSE - When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.

`#define CADSE_BIT 0`

`#define CADSE_MASK 1`

##### CADSI0 - The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.

`#define CADSI0_BIT 1`

`#define CADSI0_MASK 2`

##### CADSI1 - The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.

`#define CADSI1_BIT 2`

`#define CADSI1_MASK 4`

##### CADAS0 - CC_ADC Accumulate Current Select Bit 0

`#define CADAS0_BIT 3`

`#define CADAS0_MASK 8`

The CADAS bits select the conversion time for the Accumulate Current output. Please refer to table 45 in the manual.

##### CADAS1 - CC_ADC Accumulate Current Select Bit 1

`#define CADAS1_BIT 4`

`#define CADAS1_MASK 16`

The CADAS bits select the conversion time for the Accumulate Current output. Please refer to table 45 in the manual.

##### CADUB - CC_ADC Update Busy

`#define CADUB_BIT 5`

`#define CADUB_MASK 32`

##### CADEN - When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.

`#define CADEN_BIT 7`

`#define CADEN_MASK 128`

### CADCSRB - CC-ADC Control and Status Register B

`sfrb CADCSRB = 0xE5;`

##### CADICIF - CC-ADC Instantaneous Current Interrupt Flag

`#define CADICIF_BIT 0`

`#define CADICIF_MASK 1`

The CADICIF bit is set (one) when a CC-ADC Instantaneous Current conversion is completed. The CC-ADC Instantaneous Current Interrupt is executed if the CADICIE bit and the I-bit in SREG are set (one). CADICIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADICIF is cleared by writing a logic one to the flag.

##### CADRCIF - CC-ADC Accumulate Current Interrupt Flag

`#define CADRCIF_BIT 1`

`#define CADRCIF_MASK 2`

The CADACIF bit is set (one) after the Accumulate Current conversion has completed. The CC-ADC Accumulate Current Interrupt is executed if the CADAIE bit and the I-bit in SREG are set (one). CADACIF is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, CADACIF is cleared by writing a logic one to the flag. he CADRCIF bit is set (one) when the absolute value of the result of the last CC-ADC conversion is greater than, or equal to, the compare values set by the CC-ADC Regular Charge/Discharge Current Level Registers. A positive value is compared to the Regular Charge Current Level, and a negative value is compared to the Regular Discharge Current Level. The CC-ADC Regular Current Interrupt is executed if the CADRCIE bit and the I-bit in SREG are set (one). CADRCIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADRCIF is cleared by writing a logic one to the flag.

##### CADACIF - CC-ADC Accumulate Current Interrupt Flag

`#define CADACIF_BIT 2`

`#define CADACIF_MASK 4`

The CADACIF bit is set (one) after the Accumulate Current conversion has completed. The CC-ADC Accumulate Current Interrupt is executed if the CADAIE bit and the I-bit in SREG are set (one). CADACIF is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, CADACIF is cleared by writing a logic one to the flag. he CADRCIF bit is set (one) when the absolute value of the result of the last CC-ADC conversion is greater than, or equal to, the compare values set by the CC-ADC Regular Charge/Discharge Current Level Registers. A positive value is compared to the Regular Charge Current Level, and a negative value is compared to the Regular Discharge Current Level. The CC-ADC Regular Current Interrupt is executed if the CADRCIE bit and the I-bit in SREG are set (one). CADRCIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADRCIF is cleared by writing a logic one to the flag.

##### CADICIE - CAD Instantenous Current Interrupt Enable

`#define CADICIE_BIT 4`

`#define CADICIE_MASK 16`

The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43.

##### CADRCIE - Regular Current Interrupt Enable

`#define CADRCIE_BIT 5`

`#define CADRCIE_MASK 32`

When the CADACIE bit is set (one), and the I-bit in the Status Register is set (one), the CC-ADC Accumulate Current Interrupt is enabled.

##### CADACIE

`#define CADACIE_BIT 6`

`#define CADACIE_MASK 64`

CC-ADC Accumulate Current Interrupt Enable

### CADICH - CC-ADC Instantaneous Current

`sfrb CADICH = 0xE9;`

##### CADICH0 - When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.

`#define CADICH0_BIT 0`

`#define CADICH0_MASK 1`

##### CADICH1 - The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.

`#define CADICH1_BIT 1`

`#define CADICH1_MASK 2`

##### CADICH2 - The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.

`#define CADICH2_BIT 2`

`#define CADICH2_MASK 4`

##### CADICH3 - The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43.

`#define CADICH3_BIT 3`

`#define CADICH3_MASK 8`

##### CADICH4 - The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43.

`#define CADICH4_BIT 4`

`#define CADICH4_MASK 16`

##### CADICH5

`#define CADICH5_BIT 5`

`#define CADICH5_MASK 32`

##### CADICH6

`#define CADICH6_BIT 6`

`#define CADICH6_MASK 64`

##### CADICH7 - When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.

`#define CADICH7_BIT 7`

`#define CADICH7_MASK 128`

### CADICL - CC-ADC Instantaneous Current

`sfrb CADICL = 0xE8;`

##### CADICL0 - When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.

`#define CADICL0_BIT 0`

`#define CADICL0_MASK 1`

##### CADICL1 - The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.

`#define CADICL1_BIT 1`

`#define CADICL1_MASK 2`

##### CADICL2 - The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.

`#define CADICL2_BIT 2`

`#define CADICL2_MASK 4`

##### CADICL3 - The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43.

`#define CADICL3_BIT 3`

`#define CADICL3_MASK 8`

##### CADICL4 - The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43.

`#define CADICL4_BIT 4`

`#define CADICL4_MASK 16`

##### CADICL5

`#define CADICL5_BIT 5`

`#define CADICL5_MASK 32`

##### CADICL6

`#define CADICL6_BIT 6`

`#define CADICL6_MASK 64`

##### CADICL7 - When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.

`#define CADICL7_BIT 7`

`#define CADICL7_MASK 128`

### CADAC3 - ADC Accumulate Current

`sfrb CADAC3 = 0xE3;`

##### CADAC24

`#define CADAC24_BIT 0`

`#define CADAC24_MASK 1`

##### CADAC25

`#define CADAC25_BIT 1`

`#define CADAC25_MASK 2`

##### CADAC26

`#define CADAC26_BIT 2`

`#define CADAC26_MASK 4`

##### CADAC27

`#define CADAC27_BIT 3`

`#define CADAC27_MASK 8`

##### CADAC28

`#define CADAC28_BIT 4`

`#define CADAC28_MASK 16`

##### CADAC29

`#define CADAC29_BIT 5`

`#define CADAC29_MASK 32`

##### CADAC30

`#define CADAC30_BIT 6`

`#define CADAC30_MASK 64`

##### CADAC31

`#define CADAC31_BIT 7`

`#define CADAC31_MASK 128`

### CADAC2 - ADC Accumulate Current

`sfrb CADAC2 = 0xE2;`

##### CADAC16

`#define CADAC16_BIT 0`

`#define CADAC16_MASK 1`

##### CADAC17

`#define CADAC17_BIT 1`

`#define CADAC17_MASK 2`

##### CADAC18

`#define CADAC18_BIT 2`

`#define CADAC18_MASK 4`

##### CADAC19

`#define CADAC19_BIT 3`

`#define CADAC19_MASK 8`

##### CADAC20

`#define CADAC20_BIT 4`

`#define CADAC20_MASK 16`

##### CADAC21

`#define CADAC21_BIT 5`

`#define CADAC21_MASK 32`

##### CADAC22

`#define CADAC22_BIT 6`

`#define CADAC22_MASK 64`

##### CADAC23

`#define CADAC23_BIT 7`

`#define CADAC23_MASK 128`

### CADAC1 - ADC Accumulate Current

`sfrb CADAC1 = 0xE1;`

##### CADAC08

`#define CADAC08_BIT 0`

`#define CADAC08_MASK 1`

##### CADAC09

`#define CADAC09_BIT 1`

`#define CADAC09_MASK 2`

##### CADAC10

`#define CADAC10_BIT 2`

`#define CADAC10_MASK 4`

##### CADAC11

`#define CADAC11_BIT 3`

`#define CADAC11_MASK 8`

##### CADAC12

`#define CADAC12_BIT 4`

`#define CADAC12_MASK 16`

##### CADAC13

`#define CADAC13_BIT 5`

`#define CADAC13_MASK 32`

##### CADAC14

`#define CADAC14_BIT 6`

`#define CADAC14_MASK 64`

##### CADAC15

`#define CADAC15_BIT 7`

`#define CADAC15_MASK 128`

### CADAC0 - ADC Accumulate Current

`sfrb CADAC0 = 0xE0;`

##### CADAC00

`#define CADAC00_BIT 0`

`#define CADAC00_MASK 1`

##### CADAC01

`#define CADAC01_BIT 1`

`#define CADAC01_MASK 2`

##### CADAC02

`#define CADAC02_BIT 2`

`#define CADAC02_MASK 4`

##### CADAC03

`#define CADAC03_BIT 3`

`#define CADAC03_MASK 8`

##### CADAC04

`#define CADAC04_BIT 4`

`#define CADAC04_MASK 16`

##### CADAC05

`#define CADAC05_BIT 5`

`#define CADAC05_MASK 32`

##### CADAC06

`#define CADAC06_BIT 6`

`#define CADAC06_MASK 64`

##### CADAC07

`#define CADAC07_BIT 7`

`#define CADAC07_MASK 128`

### CADRCC - CC-ADC Regular Charge Current

`sfrb CADRCC = 0xE6;`

##### CADRCC0 - When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.

`#define CADRCC0_BIT 0`

`#define CADRCC0_MASK 1`

##### CADRCC1 - The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.

`#define CADRCC1_BIT 1`

`#define CADRCC1_MASK 2`

##### CADRCC2 - The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.

`#define CADRCC2_BIT 2`

`#define CADRCC2_MASK 4`

##### CADRCC3 - The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43.

`#define CADRCC3_BIT 3`

`#define CADRCC3_MASK 8`

##### CADRCC4 - The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43.

`#define CADRCC4_BIT 4`

`#define CADRCC4_MASK 16`

##### CADRCC5

`#define CADRCC5_BIT 5`

`#define CADRCC5_MASK 32`

##### CADRCC6

`#define CADRCC6_BIT 6`

`#define CADRCC6_MASK 64`

##### CADRCC7 - When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.

`#define CADRCC7_BIT 7`

`#define CADRCC7_MASK 128`

### CADRDC - CC-ADC Regular Discharge Current

`sfrb CADRDC = 0xE7;`

##### CADRDC0 - When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.

`#define CADRDC0_BIT 0`

`#define CADRDC0_MASK 1`

##### CADRDC1 - The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.

`#define CADRDC1_BIT 1`

`#define CADRDC1_MASK 2`

##### CADRDC2 - The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.

`#define CADRDC2_BIT 2`

`#define CADRDC2_MASK 4`

##### CADRDC3 - The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43.

`#define CADRDC3_BIT 3`

`#define CADRDC3_MASK 8`

##### CADRDC4 - The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43.

`#define CADRDC4_BIT 4`

`#define CADRDC4_MASK 16`

##### CADRDC5

`#define CADRDC5_BIT 5`

`#define CADRDC5_MASK 32`

##### CADRDC6

`#define CADRDC6_BIT 6`

`#define CADRDC6_MASK 64`

##### CADRDC7 - When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.

`#define CADRDC7_BIT 7`

`#define CADRDC7_MASK 128`

## CELL BALANCING

### CBCR - Cell Balancing Control Register

`sfrb CBCR = 0xF1;`

##### CBE1 - Battery Protection Parameter Lock

`#define CBE1_BIT 0`

`#define CBE1_MASK 1`

##### CBE2 - Cell Balancing Enable 2

`#define CBE2_BIT 1`

`#define CBE2_MASK 2`

##### CBE3 - Cell Balancing Enable 4

`#define CBE3_BIT 2`

`#define CBE3_MASK 4`

##### CBE4 - Cell Balancing Enable 4

`#define CBE4_BIT 3`

`#define CBE4_MASK 8`

## CPU

### SREG - Status Register

`sfrb SREG = 0x3F;`

### SPH - Stack Pointer High

`sfrb SPH = 0x3E;`

##### SP8 - Stack pointer bit 8

`#define SP8_BIT 0`

`#define SP8_MASK 1`

##### SP9 - Stack pointer bit 9

`#define SP9_BIT 1`

`#define SP9_MASK 2`

##### SP10 - Stack pointer bit 10

`#define SP10_BIT 2`

`#define SP10_MASK 4`

##### SP11 - Stack pointer bit 11

`#define SP11_BIT 3`

`#define SP11_MASK 8`

##### SP12

`#define SP12_BIT 4`

`#define SP12_MASK 16`

##### SP13 - Stack pointer bit 13

`#define SP13_BIT 5`

`#define SP13_MASK 32`

##### SP14 - Stack pointer bit 14

`#define SP14_BIT 6`

`#define SP14_MASK 64`

##### SP15 - Stack pointer bit 15

`#define SP15_BIT 7`

`#define SP15_MASK 128`

### SPL - Stack Pointer Low

`sfrb SPL = 0x3D;`

##### SP0 - Stack pointer bit 0

`#define SP0_BIT 0`

`#define SP0_MASK 1`

##### SP1 - Stack pointer bit 1

`#define SP1_BIT 1`

`#define SP1_MASK 2`

##### SP2 - Stack pointer bit 2

`#define SP2_BIT 2`

`#define SP2_MASK 4`

##### SP3 - Stack pointer bit 3

`#define SP3_BIT 3`

`#define SP3_MASK 8`

##### SP4

`#define SP4_BIT 4`

`#define SP4_MASK 16`

##### SP5 - Stack pointer bit 5

`#define SP5_BIT 5`

`#define SP5_MASK 32`

##### SP6 - Stack pointer bit 6

`#define SP6_BIT 6`

`#define SP6_MASK 64`

##### SP7 - Stack pointer bit 7

`#define SP7_BIT 7`

`#define SP7_MASK 128`

### MCUCR - MCU Control Register

`sfrb MCUCR = 0x35;`

##### IVCE - Interrupt Vector Change Enable

`#define IVCE_BIT 0`

`#define IVCE_MASK 1`

The IVCE bit must be written to logic one to enable change of the IVSEL bit.IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.Setting the IVCE bit will disable interrupts.

##### IVSEL - Interrupt Vector Select

`#define IVSEL_BIT 1`

`#define IVSEL_MASK 2`

When the IVSEL bit is cleared (zero),the interrupt vectors are placed at the start of the Flash memory.When this bit is set (one),the interrupt vectors are moved to the beginning of the Boot Loader section of the flash.The actual address of the start of the boot flash section is determined by the BOOTSZ fuses.

##### PUD - Pull-up disable

`#define PUD_BIT 4`

`#define PUD_MASK 16`

When this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn,PORTxn}=0b01).

##### JTD - JTAG Disable

`#define JTD_BIT 7`

`#define JTD_MASK 128`

### MCUSR - MCU Status Register

`sfrb MCUSR = 0x34;`

##### PORF - Power-on reset flag

`#define PORF_BIT 0`

`#define PORF_MASK 1`

This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.

##### EXTRF - External Reset Flag

`#define EXTRF_BIT 1`

`#define EXTRF_MASK 2`

This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

##### BODRF - Brown-out Reset Flag

`#define BODRF_BIT 2`

`#define BODRF_MASK 4`

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by

##### WDRF - Watchdog Reset Flag

`#define WDRF_BIT 3`

`#define WDRF_MASK 8`

This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

##### JTRF - JTAG Reset Flag

`#define JTRF_BIT 4`

`#define JTRF_MASK 16`

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on reset, or by writing a logic zero to the flag. ? Bit 3 - WDRF: Watchdog Reset Flag

### FOSCCAL - Fast Oscillator Calibration Value

`sfrb FOSCCAL = 0x66;`

##### FCAL0 - Oscillator Calibration Value Bit0

`#define FCAL0_BIT 0`

`#define FCAL0_MASK 1`

##### FCAL1 - Oscillator Calibration Value Bit1

`#define FCAL1_BIT 1`

`#define FCAL1_MASK 2`

##### FCAL2 - Oscillator Calibration Value Bit2

`#define FCAL2_BIT 2`

`#define FCAL2_MASK 4`

##### FCAL3 - Oscillator Calibration Value Bit3

`#define FCAL3_BIT 3`

`#define FCAL3_MASK 8`

##### FCAL4 - Oscillator Calibration Value Bit4

`#define FCAL4_BIT 4`

`#define FCAL4_MASK 16`

##### FCAL5 - Oscillator Calibration Value Bit5

`#define FCAL5_BIT 5`

`#define FCAL5_MASK 32`

##### FCAL6 - Oscillator Calibration Value Bit6

`#define FCAL6_BIT 6`

`#define FCAL6_MASK 64`

##### FCAL7 - Oscillator Calibration Value Bit7

`#define FCAL7_BIT 7`

`#define FCAL7_MASK 128`

### SMCR - Sleep Mode Control Register

`sfrb SMCR = 0x33;`

##### SE - Sleep Enable

`#define SE_BIT 0`

`#define SE_MASK 1`

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.To

##### SM0 - Sleep Mode Select bit 0

`#define SM0_BIT 1`

`#define SM0_MASK 2`

These bits select between the five available sleep modes.

##### SM1 - Sleep Mode Select bit 1

`#define SM1_BIT 2`

`#define SM1_MASK 4`

These bits select between the five available sleep modes.

##### SM2 - Sleep Mode Select bit 2

`#define SM2_BIT 3`

`#define SM2_MASK 8`

These bits select between the five available sleep modes.

### GPIOR2 - General Purpose IO Register 2

`sfrb GPIOR2 = 0x2B;`

##### GPIOR20 - General Purpose IO Register 2 bit 0

`#define GPIOR20_BIT 0`

`#define GPIOR20_MASK 1`

##### GPIOR21 - General Purpose IO Register 2 bit 1

`#define GPIOR21_BIT 1`

`#define GPIOR21_MASK 2`

##### GPIOR22 - General Purpose IO Register 2 bit 2

`#define GPIOR22_BIT 2`

`#define GPIOR22_MASK 4`

##### GPIOR23 - General Purpose IO Register 2 bit 3

`#define GPIOR23_BIT 3`

`#define GPIOR23_MASK 8`

##### GPIOR24 - General Purpose IO Register 2 bit 4

`#define GPIOR24_BIT 4`

`#define GPIOR24_MASK 16`

##### GPIOR25 - General Purpose IO Register 2 bit 5

`#define GPIOR25_BIT 5`

`#define GPIOR25_MASK 32`

##### GPIOR26 - General Purpose IO Register 2 bit 6

`#define GPIOR26_BIT 6`

`#define GPIOR26_MASK 64`

##### GPIOR27 - General Purpose IO Register 2 bit 7

`#define GPIOR27_BIT 7`

`#define GPIOR27_MASK 128`

### GPIOR1 - General Purpose IO Register 1

`sfrb GPIOR1 = 0x2A;`

##### GPIOR10 - General Purpose IO Register 1 bit 0

`#define GPIOR10_BIT 0`

`#define GPIOR10_MASK 1`

##### GPIOR11 - General Purpose IO Register 1 bit 1

`#define GPIOR11_BIT 1`

`#define GPIOR11_MASK 2`

##### GPIOR12 - General Purpose IO Register 1 bit 2

`#define GPIOR12_BIT 2`

`#define GPIOR12_MASK 4`

##### GPIOR13 - General Purpose IO Register 1 bit 3

`#define GPIOR13_BIT 3`

`#define GPIOR13_MASK 8`

##### GPIOR14 - General Purpose IO Register 1 bit 4

`#define GPIOR14_BIT 4`

`#define GPIOR14_MASK 16`

##### GPIOR15 - General Purpose IO Register 1 bit 5

`#define GPIOR15_BIT 5`

`#define GPIOR15_MASK 32`

##### GPIOR16 - General Purpose IO Register 1 bit 6

`#define GPIOR16_BIT 6`

`#define GPIOR16_MASK 64`

##### GPIOR17 - General Purpose IO Register 1 bit 7

`#define GPIOR17_BIT 7`

`#define GPIOR17_MASK 128`

### GPIOR0 - General Purpose IO Register 0

`sfrb GPIOR0 = 0x1E;`

##### GPIOR00 - General Purpose IO Register 0 bit 0

`#define GPIOR00_BIT 0`

`#define GPIOR00_MASK 1`

##### GPIOR01 - General Purpose IO Register 0 bit 1

`#define GPIOR01_BIT 1`

`#define GPIOR01_MASK 2`

##### GPIOR02 - General Purpose IO Register 0 bit 2

`#define GPIOR02_BIT 2`

`#define GPIOR02_MASK 4`

##### GPIOR03 - General Purpose IO Register 0 bit 3

`#define GPIOR03_BIT 3`

`#define GPIOR03_MASK 8`

##### GPIOR04 - General Purpose IO Register 0 bit 4

`#define GPIOR04_BIT 4`

`#define GPIOR04_MASK 16`

##### GPIOR05 - General Purpose IO Register 0 bit 5

`#define GPIOR05_BIT 5`

`#define GPIOR05_MASK 32`

##### GPIOR06 - General Purpose IO Register 0 bit 6

`#define GPIOR06_BIT 6`

`#define GPIOR06_MASK 64`

##### GPIOR07 - General Purpose IO Register 0 bit 7

`#define GPIOR07_BIT 7`

`#define GPIOR07_MASK 128`

### CCSR - Clock Control and Status Register

`sfrb CCSR = 0xC0;`

##### ACS - Asynchronous Clock Select

`#define ACS_BIT 0`

`#define ACS_MASK 1`

The ACS bit is used to selected the source of the asynchronous clock for the Coulomb Counter ADC and Wake-up Timer. The Slow RC Oscillator is selected when this bit is cleared (zero). The 32 kHz Crystal Oscillator is selected when this bit is set (one).

##### XOE - 32 kHz Crystal Oscillator Enable

`#define XOE_BIT 1`

`#define XOE_MASK 2`

The XOE bit is used to enable the 32 kHz Crystal Oscillator before it is selected as clock source. This allows the Oscillator clock to stabilize prior to use. The 32 kHz Crystal Oscillator requires approximately two seconds to stabilize, this must be timed by the user software. This bit must remain set as long as the ACS bit is set, otherwise the 32 kHz clock to CC-ADC and Wake-up timer will be stopped.

### DIDR0 - Digital Input Disable Register

`sfrb DIDR0 = 0x7E;`

##### VADC0D - When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.

`#define VADC0D_BIT 0`

`#define VADC0D_MASK 1`

##### VADC1D - When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.

`#define VADC1D_BIT 1`

`#define VADC1D_MASK 2`

##### VADC2D - When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.

`#define VADC2D_BIT 2`

`#define VADC2D_MASK 4`

##### VADC3D - When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.

`#define VADC3D_BIT 3`

`#define VADC3D_MASK 8`

### PRR0 - Power Reduction Register 0

`sfrb PRR0 = 0x64;`

##### PRVADC - Power Reduction V-ADC

`#define PRVADC_BIT 0`

`#define PRVADC_MASK 1`

Writing a logic one to this bit shuts down the V-ADC. The V-ADC must be disabled before shut down.

##### PRTIM0 - Power Reduction Timer/Counter0

`#define PRTIM0_BIT 1`

`#define PRTIM0_MASK 2`

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown.

##### PRTIM1 - Power Reduction Timer/Counter1

`#define PRTIM1_BIT 2`

`#define PRTIM1_MASK 4`

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the, Timer/Counter1 is enabled, operation will continue like before the shutdown.

##### PRTWI - Power Reduction TWI

`#define PRTWI_BIT 3`

`#define PRTWI_MASK 8`

Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation.

## WATCHDOG

### WDTCSR - Watchdog Timer Control Register

`sfrb WDTCSR = 0x60;`

##### WDP0 - Watch Dog Timer Prescaler bit 0

`#define WDP0_BIT 0`

`#define WDP0_MASK 1`

##### WDP1 - Watch Dog Timer Prescaler bit 1

`#define WDP1_BIT 1`

`#define WDP1_MASK 2`

##### WDP2 - Watch Dog Timer Prescaler bit 2

`#define WDP2_BIT 2`

`#define WDP2_MASK 4`

##### WDE - Watch Dog Enable

`#define WDE_BIT 3`

`#define WDE_MASK 8`

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog

##### WDCE - Watchdog Change Enable

`#define WDCE_BIT 4`

`#define WDCE_MASK 16`

##### WDP3 - Watchdog Timer Prescaler Bit 3

`#define WDP3_BIT 5`

`#define WDP3_MASK 32`

##### WDIE - Watchdog Timeout Interrupt Enable

`#define WDIE_BIT 6`

`#define WDIE_MASK 64`

##### WDIF - Watchdog Timeout Interrupt Flag

`#define WDIF_BIT 7`

`#define WDIF_MASK 128`

## TIMER COUNTER 0

The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in ?Timer/Counter0 Control Register - TCCR0? on page 35. The overflow status flag is found in ?The Timer/Counter Interrupt Flag Register - TIFR? on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in ?The Timer/Counter Interrupt Mask Regis-ter - TIMSK? on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions

### TCCR0A - Timer/Counter0 Control Register

`sfrb TCCR0A = 0x24;`

##### WGM00 - Clock Select0 bit 0

`#define WGM00_BIT 0`

`#define WGM00_MASK 1`

##### WGM01 - Clock Select0 bit 1

`#define WGM01_BIT 1`

`#define WGM01_MASK 2`

##### COM0B0

`#define COM0B0_BIT 4`

`#define COM0B0_MASK 16`

##### COM0B1

`#define COM0B1_BIT 5`

`#define COM0B1_MASK 32`

##### COM0A0 - Waveform Generation Mode

`#define COM0A0_BIT 6`

`#define COM0A0_MASK 64`

##### COM0A1 - Force Output Compare

`#define COM0A1_BIT 7`

`#define COM0A1_MASK 128`

### TCCR0B - Timer/Counter0 Control Register

`sfrb TCCR0B = 0x25;`

##### CS00 - Clock Select0 bit 0

`#define CS00_BIT 0`

`#define CS00_MASK 1`

##### CS01 - Clock Select0 bit 1

`#define CS01_BIT 1`

`#define CS01_MASK 2`

##### CS02 - Clock Select0 bit 2

`#define CS02_BIT 2`

`#define CS02_MASK 4`

##### WGM02

`#define WGM02_BIT 3`

`#define WGM02_MASK 8`

##### FOC0B - Waveform Generation Mode

`#define FOC0B_BIT 6`

`#define FOC0B_MASK 64`

##### FOC0A - Force Output Compare

`#define FOC0A_BIT 7`

`#define FOC0A_MASK 128`

### TCNT0 - Timer Counter 0

`sfrb TCNT0 = 0x26;`

##### TCNT00 - Timer Counter 0 bit 0

`#define TCNT00_BIT 0`

`#define TCNT00_MASK 1`

##### TCNT01 - Timer Counter 0 bit 1

`#define TCNT01_BIT 1`

`#define TCNT01_MASK 2`

##### TCNT02 - Timer Counter 0 bit 2

`#define TCNT02_BIT 2`

`#define TCNT02_MASK 4`

##### TCNT03 - Timer Counter 0 bit 3

`#define TCNT03_BIT 3`

`#define TCNT03_MASK 8`

##### TCNT04 - Timer Counter 0 bit 4

`#define TCNT04_BIT 4`

`#define TCNT04_MASK 16`

##### TCNT05 - Timer Counter 0 bit 5

`#define TCNT05_BIT 5`

`#define TCNT05_MASK 32`

##### TCNT06 - Timer Counter 0 bit 6

`#define TCNT06_BIT 6`

`#define TCNT06_MASK 64`

##### TCNT07 - Timer Counter 0 bit 7

`#define TCNT07_BIT 7`

`#define TCNT07_MASK 128`

### OCR0A - Output compare Register A

`sfrb OCR0A = 0x27;`

##### OCR0A0

`#define OCR0A0_BIT 0`

`#define OCR0A0_MASK 1`

##### OCR0A1

`#define OCR0A1_BIT 1`

`#define OCR0A1_MASK 2`

##### OCR0A2

`#define OCR0A2_BIT 2`

`#define OCR0A2_MASK 4`

##### OCR0A3

`#define OCR0A3_BIT 3`

`#define OCR0A3_MASK 8`

##### OCR0A4

`#define OCR0A4_BIT 4`

`#define OCR0A4_MASK 16`

##### OCR0A5

`#define OCR0A5_BIT 5`

`#define OCR0A5_MASK 32`

##### OCR0A6

`#define OCR0A6_BIT 6`

`#define OCR0A6_MASK 64`

##### OCR0A7

`#define OCR0A7_BIT 7`

`#define OCR0A7_MASK 128`

### OCR0B - Output compare Register B

`sfrb OCR0B = 0x28;`

##### OCR0B0

`#define OCR0B0_BIT 0`

`#define OCR0B0_MASK 1`

##### OCR0B1

`#define OCR0B1_BIT 1`

`#define OCR0B1_MASK 2`

##### OCR0B2

`#define OCR0B2_BIT 2`

`#define OCR0B2_MASK 4`

##### OCR0B3

`#define OCR0B3_BIT 3`

`#define OCR0B3_MASK 8`

##### OCR0B4

`#define OCR0B4_BIT 4`

`#define OCR0B4_MASK 16`

##### OCR0B5

`#define OCR0B5_BIT 5`

`#define OCR0B5_MASK 32`

##### OCR0B6

`#define OCR0B6_BIT 6`

`#define OCR0B6_MASK 64`

##### OCR0B7

`#define OCR0B7_BIT 7`

`#define OCR0B7_MASK 128`

### TIMSK0 - Timer/Counter Interrupt Mask Register

`sfrb TIMSK0 = 0x6E;`

##### TOIE0 - Overflow Interrupt Enable

`#define TOIE0_BIT 0`

`#define TOIE0_MASK 1`

##### OCIE0A - Output Compare Interrupt Enable

`#define OCIE0A_BIT 1`

`#define OCIE0A_MASK 2`

##### OCIE0B - Output Compare Interrupt Enable

`#define OCIE0B_BIT 2`

`#define OCIE0B_MASK 4`

### TIFR0 - Timer/Counter Interrupt Flag register

`sfrb TIFR0 = 0x15;`

##### TOV0 - Overflow Flag

`#define TOV0_BIT 0`

`#define TOV0_MASK 1`

##### OCF0A - Output Compare Flag

`#define OCF0A_BIT 1`

`#define OCF0A_MASK 2`

##### OCF0B - Output Compare Flag

`#define OCF0B_BIT 2`

`#define OCF0B_MASK 4`

## PORTA

### PORTA - Port A Data Register

`sfrb PORTA = 0x02;`

##### PORTA0 - Port A Data Register bit 0

`#define PORTA0_BIT 0`

`#define PORTA0_MASK 1`

##### PORTA1 - Port A Data Register bit 1

`#define PORTA1_BIT 1`

`#define PORTA1_MASK 2`

##### PORTA2 - Port A Data Register bit 2

`#define PORTA2_BIT 2`

`#define PORTA2_MASK 4`

##### PORTA3 - Port A Data Register bit 3

`#define PORTA3_BIT 3`

`#define PORTA3_MASK 8`

##### PORTA4 - Port A Data Register bit 4

`#define PORTA4_BIT 4`

`#define PORTA4_MASK 16`

##### PORTA5 - Port A Data Register bit 5

`#define PORTA5_BIT 5`

`#define PORTA5_MASK 32`

##### PORTA6 - Port A Data Register bit 6

`#define PORTA6_BIT 6`

`#define PORTA6_MASK 64`

##### PORTA7 - Port A Data Register bit 7

`#define PORTA7_BIT 7`

`#define PORTA7_MASK 128`

### DDRA - Port A Data Direction Register

`sfrb DDRA = 0x01;`

##### DDA0 - Data Direction Register, Port A, bit 0

`#define DDA0_BIT 0`

`#define DDA0_MASK 1`

##### DDA1 - Data Direction Register, Port A, bit 1

`#define DDA1_BIT 1`

`#define DDA1_MASK 2`

##### DDA2 - Data Direction Register, Port A, bit 2

`#define DDA2_BIT 2`

`#define DDA2_MASK 4`

##### DDA3 - Data Direction Register, Port A, bit 3

`#define DDA3_BIT 3`

`#define DDA3_MASK 8`

##### DDA4 - Data Direction Register, Port A, bit 4

`#define DDA4_BIT 4`

`#define DDA4_MASK 16`

##### DDA5 - Data Direction Register, Port A, bit 5

`#define DDA5_BIT 5`

`#define DDA5_MASK 32`

##### DDA6 - Data Direction Register, Port A, bit 6

`#define DDA6_BIT 6`

`#define DDA6_MASK 64`

##### DDA7 - Data Direction Register, Port A, bit 7

`#define DDA7_BIT 7`

`#define DDA7_MASK 128`

### PINA - Port A Input Pins

`sfrb PINA = 0x00;`

##### PINA0 - Input Pins, Port A bit 0

`#define PINA0_BIT 0`

`#define PINA0_MASK 1`

##### PINA1 - Input Pins, Port A bit 1

`#define PINA1_BIT 1`

`#define PINA1_MASK 2`

##### PINA2 - Input Pins, Port A bit 2

`#define PINA2_BIT 2`

`#define PINA2_MASK 4`

##### PINA3 - Input Pins, Port A bit 3

`#define PINA3_BIT 3`

`#define PINA3_MASK 8`

##### PINA4 - Input Pins, Port A bit 4

`#define PINA4_BIT 4`

`#define PINA4_MASK 16`

##### PINA5 - Input Pins, Port A bit 5

`#define PINA5_BIT 5`

`#define PINA5_MASK 32`

##### PINA6 - Input Pins, Port A bit 6

`#define PINA6_BIT 6`

`#define PINA6_MASK 64`

##### PINA7 - Input Pins, Port A bit 7

`#define PINA7_BIT 7`

`#define PINA7_MASK 128`

## PORTB

### PORTB - Port B Data Register

`sfrb PORTB = 0x05;`

##### PORTB0 - Port B Data Register bit 0

`#define PORTB0_BIT 0`

`#define PORTB0_MASK 1`

##### PORTB1 - Port B Data Register bit 1

`#define PORTB1_BIT 1`

`#define PORTB1_MASK 2`

##### PORTB2 - Port B Data Register bit 2

`#define PORTB2_BIT 2`

`#define PORTB2_MASK 4`

##### PORTB3 - Port B Data Register bit 3

`#define PORTB3_BIT 3`

`#define PORTB3_MASK 8`

##### PORTB4 - Port B Data Register bit 4

`#define PORTB4_BIT 4`

`#define PORTB4_MASK 16`

##### PORTB5 - Port B Data Register bit 5

`#define PORTB5_BIT 5`

`#define PORTB5_MASK 32`

##### PORTB6 - Port B Data Register bit 6

`#define PORTB6_BIT 6`

`#define PORTB6_MASK 64`

##### PORTB7 - Port B Data Register bit 7

`#define PORTB7_BIT 7`

`#define PORTB7_MASK 128`

### DDRB - Port B Data Direction Register

`sfrb DDRB = 0x04;`

##### DDB0 - Port B Data Direction Register bit 0

`#define DDB0_BIT 0`

`#define DDB0_MASK 1`

##### DDB1 - Port B Data Direction Register bit 1

`#define DDB1_BIT 1`

`#define DDB1_MASK 2`

##### DDB2 - Port B Data Direction Register bit 2

`#define DDB2_BIT 2`

`#define DDB2_MASK 4`

##### DDB3 - Port B Data Direction Register bit 3

`#define DDB3_BIT 3`

`#define DDB3_MASK 8`

##### DDB4 - Port B Data Direction Register bit 4

`#define DDB4_BIT 4`

`#define DDB4_MASK 16`

##### DDB5 - Port B Data Direction Register bit 5

`#define DDB5_BIT 5`

`#define DDB5_MASK 32`

##### DDB6 - Port B Data Direction Register bit 6

`#define DDB6_BIT 6`

`#define DDB6_MASK 64`

##### DDB7 - Port B Data Direction Register bit 7

`#define DDB7_BIT 7`

`#define DDB7_MASK 128`

### PINB - Port B Input Pins

`sfrb PINB = 0x03;`

##### PINB0 - Port B Input Pins bit 0

`#define PINB0_BIT 0`

`#define PINB0_MASK 1`

##### PINB1 - Port B Input Pins bit 1

`#define PINB1_BIT 1`

`#define PINB1_MASK 2`

##### PINB2 - Port B Input Pins bit 2

`#define PINB2_BIT 2`

`#define PINB2_MASK 4`

##### PINB3 - Port B Input Pins bit 3

`#define PINB3_BIT 3`

`#define PINB3_MASK 8`

##### PINB4 - Port B Input Pins bit 4

`#define PINB4_BIT 4`

`#define PINB4_MASK 16`

##### PINB5 - Port B Input Pins bit 5

`#define PINB5_BIT 5`

`#define PINB5_MASK 32`

##### PINB6 - Port B Input Pins bit 6

`#define PINB6_BIT 6`

`#define PINB6_MASK 64`

##### PINB7 - Port B Input Pins bit 7

`#define PINB7_BIT 7`

`#define PINB7_MASK 128`

## PORTC

### PORTC - Port C Data Register

`sfrb PORTC = 0x08;`

##### PORTC0 - Port C Data Register bit 0

`#define PORTC0_BIT 0`

`#define PORTC0_MASK 1`

## PORTD

### PORTD - Data Register, Port D

`sfrb PORTD = 0x0B;`

##### PORTD0

`#define PORTD0_BIT 0`

`#define PORTD0_MASK 1`

##### PORTD1

`#define PORTD1_BIT 1`

`#define PORTD1_MASK 2`

### DDRD -

`sfrb DDRD = 0x0A;`

##### DDD0

`#define DDD0_BIT 0`

`#define DDD0_MASK 1`

##### DDD1

`#define DDD1_BIT 1`

`#define DDD1_MASK 2`

### PIND - Input Pins, Port D

`sfrb PIND = 0x09;`

##### PIND0

`#define PIND0_BIT 0`

`#define PIND0_MASK 1`

##### PIND1

`#define PIND1_BIT 1`

`#define PIND1_MASK 2`

## BOOT LOAD

The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppor

### SPMCSR - Store Program Memory Control Register

`sfrb SPMCSR = 0x37;`

##### SPMEN - Store Program Memory Enable

`#define SPMEN_BIT 0`

`#define SPMEN_MASK 1`

This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than ?10001?, "01001", "00101", "00011" or "00001" in the lower five bits will have no effec

##### PGERS - Page Erase

`#define PGERS_BIT 1`

`#define PGERS_MASK 2`

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.

##### PGWRT - Page Write

`#define PGWRT_BIT 2`

`#define PGWRT_MASK 4`

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.

##### BLBSET - Boot Lock Bit Set

`#define BLBSET_BIT 3`

`#define BLBSET_MASK 8`

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See ?Reading the Fuse and Lock Bits from Software? on page 235 for details

##### RWWSRE - Read While Write section read enable

`#define RWWSRE_BIT 4`

`#define RWWSRE_MASK 16`

When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lo

##### SIGRD - Signature Row Read

`#define SIGRD_BIT 5`

`#define SIGRD_MASK 32`

If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read a byte from the signature row into the destination register. see ?Reading the Signature Row from Software? in the datasheet for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. This operation is reserved for future use and should not be used.

##### RWWSB - Read While Write Section Busy

`#define RWWSB_BIT 6`

`#define RWWSB_MASK 64`

When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated.

##### SPMIE - SPM Interrupt Enable

`#define SPMIE_BIT 7`

`#define SPMIE_MASK 128`

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared.

## TWI

TWI: Simple yet powerful and flexible communications interface, only two bus lines needed. Both master and slave operation supported. Device can operate as transmitter or receiver. 7-bit address space allows up to 128 different slave addresses. Multi-master arbitration support Up to 400 kHz data transfer speed Slew-rate limited output drivers Noise suppression circuitry rejects spikes on bus lines Fully programmable slave address with general call support Address recognition causes wake-up when AVR is in sleep mode The Two-Wire Serial Interface (TWI) is ideally suited to typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bidirectional bus lines, one for clock (SCL) andone for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI

### TWBCSR - TWI Bus Control and Status Register

`sfrb TWBCSR = 0xBE;`

##### TWBCIP - TWI Bus Connect/Disconnect Interrupt Polarity

`#define TWBCIP_BIT 0`

`#define TWBCIP_MASK 1`

##### TWBDT0 - TWI Bus Disconnect Time-out Period

`#define TWBDT0_BIT 1`

`#define TWBDT0_MASK 2`

##### TWBDT1 - TWI Bus Disconnect Time-out Period

`#define TWBDT1_BIT 2`

`#define TWBDT1_MASK 4`

##### TWBCIE - TWI Bus Connect/Disconnect Interrupt Enable

`#define TWBCIE_BIT 6`

`#define TWBCIE_MASK 64`

##### TWBCIF - TWI Bus Connect/Disconnect Interrupt Flag

`#define TWBCIF_BIT 7`

`#define TWBCIF_MASK 128`

### TWAMR - TWI (Slave) Address Mask Register

`sfrb TWAMR = 0xBD;`

##### TWAM0

`#define TWAM0_BIT 1`

`#define TWAM0_MASK 2`

##### TWAM1

`#define TWAM1_BIT 2`

`#define TWAM1_MASK 4`

##### TWAM2

`#define TWAM2_BIT 3`

`#define TWAM2_MASK 8`

##### TWAM3

`#define TWAM3_BIT 4`

`#define TWAM3_MASK 16`

##### TWAM4

`#define TWAM4_BIT 5`

`#define TWAM4_MASK 32`

##### TWAM5

`#define TWAM5_BIT 6`

`#define TWAM5_MASK 64`

##### TWAM6

`#define TWAM6_BIT 7`

`#define TWAM6_MASK 128`

### TWBR - TWI Bit Rate register

`sfrb TWBR = 0xB8;`

##### TWBR0

`#define TWBR0_BIT 0`

`#define TWBR0_MASK 1`

##### TWBR1

`#define TWBR1_BIT 1`

`#define TWBR1_MASK 2`

##### TWBR2

`#define TWBR2_BIT 2`

`#define TWBR2_MASK 4`

##### TWBR3

`#define TWBR3_BIT 3`

`#define TWBR3_MASK 8`

##### TWBR4

`#define TWBR4_BIT 4`

`#define TWBR4_MASK 16`

##### TWBR5

`#define TWBR5_BIT 5`

`#define TWBR5_MASK 32`

##### TWBR6

`#define TWBR6_BIT 6`

`#define TWBR6_MASK 64`

##### TWBR7

`#define TWBR7_BIT 7`

`#define TWBR7_MASK 128`

### TWCR - TWI Control Register

`sfrb TWCR = 0xBC;`

##### TWIE - TWI Interrupt Enable

`#define TWIE_BIT 0`

`#define TWIE_MASK 1`

When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT flag is high.

##### TWEN - TWI Enable Bit

`#define TWEN_BIT 2`

`#define TWEN_MASK 4`

The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation.

##### TWWC - TWI Write Collition Flag

`#define TWWC_BIT 3`

`#define TWWC_MASK 8`

The TWWC bit is set when attempting to write to the TWI Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR register when TWINT is high.

##### TWSTO - TWI Stop Condition Bit

`#define TWSTO_BIT 4`

`#define TWSTO_MASK 16`

Writing the TWSTO bit to one in master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high impedance state.

##### TWSTA - TWI Start Condition Bit

`#define TWSTA_BIT 5`

`#define TWSTA_MASK 32`

The application writes the TWSTA bit to one when it desires to become a master on the 2-wire Serial Bus. The TWI hard-ware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master sta-tus. TWSTA is cleared by the TWI hardware when the START condition has been transmitted.

##### TWEA - TWI Enable Acknowledge Bit

`#define TWEA_BIT 6`

`#define TWEA_MASK 64`

The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is gener-ated on the TWI bus if the following conditions are met: 1. The device?s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in master receiver or slave receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again

##### TWINT - TWI Interrupt Flag

`#define TWINT_BIT 7`

`#define TWINT_MASK 128`

This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag

### TWSR - TWI Status Register

`sfrb TWSR = 0xB9;`

##### TWPS0 - TWI Prescaler

`#define TWPS0_BIT 0`

`#define TWPS0_MASK 1`

Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See ?Bit Rate Generator Unit? on page 165 for calculating bit rates.

##### TWPS1 - TWI Prescaler

`#define TWPS1_BIT 1`

`#define TWPS1_MASK 2`

Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See ?Bit Rate Generator Unit? on page 165 for calculating bit rates.

##### TWS3 - TWI Status

`#define TWS3_BIT 3`

`#define TWS3_MASK 8`

Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co

##### TWS4 - TWI Status

`#define TWS4_BIT 4`

`#define TWS4_MASK 16`

Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co

##### TWS5 - TWI Status

`#define TWS5_BIT 5`

`#define TWS5_MASK 32`

Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c

##### TWS6 - TWI Status

`#define TWS6_BIT 6`

`#define TWS6_MASK 64`

Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co

##### TWS7 - TWI Status

`#define TWS7_BIT 7`

`#define TWS7_MASK 128`

Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c

### TWDR - TWI Data register

`sfrb TWDR = 0xBB;`

##### TWD0 - TWI Data Register Bit 0

`#define TWD0_BIT 0`

`#define TWD0_MASK 1`

##### TWD1 - TWI Data Register Bit 1

`#define TWD1_BIT 1`

`#define TWD1_MASK 2`

##### TWD2 - TWI Data Register Bit 2

`#define TWD2_BIT 2`

`#define TWD2_MASK 4`

##### TWD3 - TWI Data Register Bit 3

`#define TWD3_BIT 3`

`#define TWD3_MASK 8`

##### TWD4 - TWI Data Register Bit 4

`#define TWD4_BIT 4`

`#define TWD4_MASK 16`

##### TWD5 - TWI Data Register Bit 5

`#define TWD5_BIT 5`

`#define TWD5_MASK 32`

##### TWD6 - TWI Data Register Bit 6

`#define TWD6_BIT 6`

`#define TWD6_MASK 64`

##### TWD7 - TWI Data Register Bit 7

`#define TWD7_BIT 7`

`#define TWD7_MASK 128`

### TWAR - TWI (Slave) Address register

`sfrb TWAR = 0xBA;`

##### TWGCE - TWI General Call Recognition Enable Bit

`#define TWGCE_BIT 0`

`#define TWGCE_MASK 1`

##### TWA0 - TWI (Slave) Address register Bit 0

`#define TWA0_BIT 1`

`#define TWA0_MASK 2`

##### TWA1 - TWI (Slave) Address register Bit 1

`#define TWA1_BIT 2`

`#define TWA1_MASK 4`

##### TWA2 - TWI (Slave) Address register Bit 2

`#define TWA2_BIT 3`

`#define TWA2_MASK 8`

##### TWA3 - TWI (Slave) Address register Bit 3

`#define TWA3_BIT 4`

`#define TWA3_MASK 16`

##### TWA4 - TWI (Slave) Address register Bit 4

`#define TWA4_BIT 5`

`#define TWA4_MASK 32`

##### TWA5 - TWI (Slave) Address register Bit 5

`#define TWA5_BIT 6`

`#define TWA5_MASK 64`

##### TWA6 - TWI (Slave) Address register Bit 6

`#define TWA6_BIT 7`

`#define TWA6_MASK 128`

## BANDGAP

### BGCRR - Bandgap Calibration of Resistor Ladder

`sfrb BGCRR = 0xD1;`

##### BGCR0 - Bandgap Calibration of Resistor Ladder Bit 0

`#define BGCR0_BIT 0`

`#define BGCR0_MASK 1`

##### BGCR1 - Bandgap Calibration of Resistor Ladder Bit 1

`#define BGCR1_BIT 1`

`#define BGCR1_MASK 2`

##### BGCR2 - Bandgap Calibration of Resistor Ladder Bit 2

`#define BGCR2_BIT 2`

`#define BGCR2_MASK 4`

##### BGCR3 - Bandgap Calibration of Resistor Ladder Bit 3

`#define BGCR3_BIT 3`

`#define BGCR3_MASK 8`

##### BGCR4 - Bandgap Calibration of Resistor Ladder Bit 4

`#define BGCR4_BIT 4`

`#define BGCR4_MASK 16`

##### BGCR5 - Bandgap Calibration of Resistor Ladder Bit 5

`#define BGCR5_BIT 5`

`#define BGCR5_MASK 32`

##### BGCR6 - Bandgap Calibration of Resistor Ladder Bit 6

`#define BGCR6_BIT 6`

`#define BGCR6_MASK 64`

##### BGCR7 - Bandgap Calibration of Resistor Ladder Bit 7

`#define BGCR7_BIT 7`

`#define BGCR7_MASK 128`

### BGCCR - Bandgap Calibration Register

`sfrb BGCCR = 0xD0;`

##### BGCC0 - BG Calibration of PTAT Current Bit 0

`#define BGCC0_BIT 0`

`#define BGCC0_MASK 1`

These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.

##### BGCC1 - BG Calibration of PTAT Current Bit 1

`#define BGCC1_BIT 1`

`#define BGCC1_MASK 2`

These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.

##### BGCC2 - BG Calibration of PTAT Current Bit 2

`#define BGCC2_BIT 2`

`#define BGCC2_MASK 4`

These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.

##### BGCC3 - BG Calibration of PTAT Current Bit 3

`#define BGCC3_BIT 3`

`#define BGCC3_MASK 8`

These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.

##### BGCC4 - BG Calibration of PTAT Current Bit 4

`#define BGCC4_BIT 4`

`#define BGCC4_MASK 16`

These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.

##### BGCC5 - BG Calibration of PTAT Current Bit 5

`#define BGCC5_BIT 5`

`#define BGCC5_MASK 32`

##### BGD - Setting the BGD bit to one will disable the bandgap voltage reference. This bit must be cleared before enabling CC-ADC or V-ADC, and must remain unset while either ADC is enabled.

`#define BGD_BIT 7`

`#define BGD_MASK 128`

## EEPROM

### EEARH - EEPROM Address Register High Byte

`sfrb EEARH = 0x22;`

##### EEAR8 - EEPROM Read/Write Access Bit 8

`#define EEAR8_BIT 0`

`#define EEAR8_MASK 1`

### EEARL - EEPROM Address Register Low Byte

`sfrb EEARL = 0x21;`

##### EEAR0 - EEPROM Read/Write Access Bit 0

`#define EEAR0_BIT 0`

`#define EEAR0_MASK 1`

##### EEAR1 - EEPROM Read/Write Access Bit 1

`#define EEAR1_BIT 1`

`#define EEAR1_MASK 2`

##### EEAR2 - EEPROM Read/Write Access Bit 2

`#define EEAR2_BIT 2`

`#define EEAR2_MASK 4`

##### EEAR3 - EEPROM Read/Write Access Bit 3

`#define EEAR3_BIT 3`

`#define EEAR3_MASK 8`

##### EEAR4 - EEPROM Read/Write Access Bit 4

`#define EEAR4_BIT 4`

`#define EEAR4_MASK 16`

##### EEAR5 - EEPROM Read/Write Access Bit 5

`#define EEAR5_BIT 5`

`#define EEAR5_MASK 32`

##### EEAR6 - EEPROM Read/Write Access Bit 6

`#define EEAR6_BIT 6`

`#define EEAR6_MASK 64`

##### EEAR7 - EEPROM Read/Write Access Bit 7

`#define EEAR7_BIT 7`

`#define EEAR7_MASK 128`

### EEDR - EEPROM Data Register

`sfrb EEDR = 0x20;`

##### EEDR0 - EEPROM Data Register bit 0

`#define EEDR0_BIT 0`

`#define EEDR0_MASK 1`

##### EEDR1 - EEPROM Data Register bit 1

`#define EEDR1_BIT 1`

`#define EEDR1_MASK 2`

##### EEDR2 - EEPROM Data Register bit 2

`#define EEDR2_BIT 2`

`#define EEDR2_MASK 4`

##### EEDR3 - EEPROM Data Register bit 3

`#define EEDR3_BIT 3`

`#define EEDR3_MASK 8`

##### EEDR4 - EEPROM Data Register bit 4

`#define EEDR4_BIT 4`

`#define EEDR4_MASK 16`

##### EEDR5 - EEPROM Data Register bit 5

`#define EEDR5_BIT 5`

`#define EEDR5_MASK 32`

##### EEDR6 - EEPROM Data Register bit 6

`#define EEDR6_BIT 6`

`#define EEDR6_MASK 64`

##### EEDR7 - EEPROM Data Register bit 7

`#define EEDR7_BIT 7`

`#define EEDR7_MASK 128`

### EECR - EEPROM Control Register

`sfrb EECR = 0x1F;`

##### EERE - EEPROM Read Enable

`#define EERE_BIT 0`

`#define EERE_MASK 1`

##### EEPE - EEPROM Programming Enable

`#define EEPE_BIT 1`

`#define EEPE_MASK 2`

##### EEMPE - EEPROM Master Programming Enable

`#define EEMPE_BIT 2`

`#define EEMPE_MASK 4`

##### EERIE - EEPROM Ready Interrupt Enable

`#define EERIE_BIT 3`

`#define EERIE_MASK 8`

##### EEPM0 - EEPROM Programming Mode Bits

`#define EEPM0_BIT 4`

`#define EEPM0_MASK 16`

##### EEPM1 - EEPROM Programming Mode Bits

`#define EEPM1_BIT 5`

`#define EEPM1_MASK 32`