This documentation was generated automatically from the AVR Studio part description file `AT76C.pdf`.

## TIMER COUNTER 0

### TCCR0 - Timer/Counter0 Control Register

`sfrb TCCR0 = 0x33;`

##### CS00 - Clock Select 1

`#define CS00_BIT 0`

`#define CS00_MASK 1`

The three clock select bits select the clock source to be used by the Timer/Counter,

##### CS01 - Clock Select 1

`#define CS01_BIT 1`

`#define CS01_MASK 2`

The three clock select bits select the clock source to be used by the Timer/Counter,

##### CS02 - Clock Select 2

`#define CS02_BIT 2`

`#define CS02_MASK 4`

The three clock select bits select the clock source to be used by the Timer/Counter,

### TCNT0 - Timer/Counter0

`sfrb TCNT0 = 0x32;`

##### TCNT0_0

`#define TCNT0_0_BIT 0`

`#define TCNT0_0_MASK 1`

##### TCNT0_1

`#define TCNT0_1_BIT 1`

`#define TCNT0_1_MASK 2`

##### TCNT0_2

`#define TCNT0_2_BIT 2`

`#define TCNT0_2_MASK 4`

##### TCNT0_3

`#define TCNT0_3_BIT 3`

`#define TCNT0_3_MASK 8`

##### TCNT0_4

`#define TCNT0_4_BIT 4`

`#define TCNT0_4_MASK 16`

##### TCNT0_5

`#define TCNT0_5_BIT 5`

`#define TCNT0_5_MASK 32`

##### TCNT0_6

`#define TCNT0_6_BIT 6`

`#define TCNT0_6_MASK 64`

##### TCNT0_7

`#define TCNT0_7_BIT 7`

`#define TCNT0_7_MASK 128`

### PRELD0 - Pre-load Register 0

`sfrb PRELD0 = 0x31;`

##### OCR0_0

`#define OCR0_0_BIT 0`

`#define OCR0_0_MASK 1`

##### OCR0_1

`#define OCR0_1_BIT 1`

`#define OCR0_1_MASK 2`

##### BIT2

`#define BIT2_BIT 2`

`#define BIT2_MASK 4`

##### BIT3

`#define BIT3_BIT 3`

`#define BIT3_MASK 8`

##### BIT4

`#define BIT4_BIT 4`

`#define BIT4_MASK 16`

##### BIT5

`#define BIT5_BIT 5`

`#define BIT5_MASK 32`

##### BIT6

`#define BIT6_BIT 6`

`#define BIT6_MASK 64`

##### BIT7

`#define BIT7_BIT 7`

`#define BIT7_MASK 128`

## TIMER COUNTER 1

### TCCR1B - Timer/Counter1 Control Register B

`sfrb TCCR1B = 0x2E;`

##### CS10 - Prescaler source of Timer/Counter 1

`#define CS10_BIT 0`

`#define CS10_MASK 1`

Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.

##### CS11 - Prescaler source of Timer/Counter 1

`#define CS11_BIT 1`

`#define CS11_MASK 2`

Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.

##### CS12 - Prescaler source of Timer/Counter 1

`#define CS12_BIT 2`

`#define CS12_MASK 4`

Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.

##### CTCA1 - Clear Timer/Counter 1 on compare A match

`#define CTCA1_BIT 3`

`#define CTCA1_MASK 8`

When it is one the Timer/Counter1 is resetWhen it is one the Timer/Counter1 is reset to $0000 after compare A match. If it is cleared the Timer/Counter1 continues counting after a compare A match.

##### ICES1 - Input Capture 1 Edge Select

`#define ICES1_BIT 6`

`#define ICES1_MASK 64`

While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.

##### ICNC1 - Input Capture 1 Noise Canceler

`#define ICNC1_BIT 7`

`#define ICNC1_MASK 128`

When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.

### TCNT1H - Timer/Counter1 High Byte

`sfrb TCNT1H = 0x2D;`

##### TCNT1H0 - Timer/Counter1 High Byte bit 0

`#define TCNT1H0_BIT 0`

`#define TCNT1H0_MASK 1`

##### TCNT1H1 - Timer/Counter1 High Byte bit 1

`#define TCNT1H1_BIT 1`

`#define TCNT1H1_MASK 2`

##### TCNT1H2 - Timer/Counter1 High Byte bit 2

`#define TCNT1H2_BIT 2`

`#define TCNT1H2_MASK 4`

##### TCNT1H3 - Timer/Counter1 High Byte bit 3

`#define TCNT1H3_BIT 3`

`#define TCNT1H3_MASK 8`

##### TCNT1H4 - Timer/Counter1 High Byte bit 4

`#define TCNT1H4_BIT 4`

`#define TCNT1H4_MASK 16`

##### TCNT1H5 - Timer/Counter1 High Byte bit 5

`#define TCNT1H5_BIT 5`

`#define TCNT1H5_MASK 32`

##### TCNT1H6 - Timer/Counter1 High Byte bit 6

`#define TCNT1H6_BIT 6`

`#define TCNT1H6_MASK 64`

##### TCNT1H7 - Timer/Counter1 High Byte bit 7

`#define TCNT1H7_BIT 7`

`#define TCNT1H7_MASK 128`

### TCNT1L - Timer/Counter1 Low Byte

`sfrb TCNT1L = 0x2C;`

##### TCNT1L0 - Timer/Counter1 Low Byte bit 0

`#define TCNT1L0_BIT 0`

`#define TCNT1L0_MASK 1`

##### TCNT1L1 - Timer/Counter1 Low Byte bit 1

`#define TCNT1L1_BIT 1`

`#define TCNT1L1_MASK 2`

##### TCNT1L2 - Timer/Counter1 Low Byte bit 2

`#define TCNT1L2_BIT 2`

`#define TCNT1L2_MASK 4`

##### TCNT1L3 - Timer/Counter1 Low Byte bit 3

`#define TCNT1L3_BIT 3`

`#define TCNT1L3_MASK 8`

##### TCNT1L4 - Timer/Counter1 Low Byte bit 4

`#define TCNT1L4_BIT 4`

`#define TCNT1L4_MASK 16`

##### TCNT1L5 - Timer/Counter1 Low Byte bit 5

`#define TCNT1L5_BIT 5`

`#define TCNT1L5_MASK 32`

##### TCNT1L6 - Timer/Counter1 Low Byte bit 6

`#define TCNT1L6_BIT 6`

`#define TCNT1L6_MASK 64`

##### TCNT1L7 - Timer/Counter1 Low Byte bit 7

`#define TCNT1L7_BIT 7`

`#define TCNT1L7_MASK 128`

### OCR1AH - Timer/Counter1 Outbut Compare Register A High Byte

`sfrb OCR1AH = 0x2B;`

##### OCR1AH0 - Timer/Counter1 Outbut Compare Register High Byte bit 0

`#define OCR1AH0_BIT 0`

`#define OCR1AH0_MASK 1`

##### OCR1AH1 - Timer/Counter1 Outbut Compare Register High Byte bit 1

`#define OCR1AH1_BIT 1`

`#define OCR1AH1_MASK 2`

##### OCR1AH2 - Timer/Counter1 Outbut Compare Register High Byte bit 2

`#define OCR1AH2_BIT 2`

`#define OCR1AH2_MASK 4`

##### OCR1AH3 - Timer/Counter1 Outbut Compare Register High Byte bit 3

`#define OCR1AH3_BIT 3`

`#define OCR1AH3_MASK 8`

##### OCR1AH4 - Timer/Counter1 Outbut Compare Register High Byte bit 4

`#define OCR1AH4_BIT 4`

`#define OCR1AH4_MASK 16`

##### OCR1AH5 - Timer/Counter1 Outbut Compare Register High Byte bit 5

`#define OCR1AH5_BIT 5`

`#define OCR1AH5_MASK 32`

##### OCR1AH6 - Timer/Counter1 Outbut Compare Register High Byte bit 6

`#define OCR1AH6_BIT 6`

`#define OCR1AH6_MASK 64`

##### OCR1AH7 - Timer/Counter1 Outbut Compare Register High Byte bit 7

`#define OCR1AH7_BIT 7`

`#define OCR1AH7_MASK 128`

### OCR1AL - Timer/Counter1 Outbut Compare Register A Low Byte

`sfrb OCR1AL = 0x2A;`

##### OCR1AL0 - Timer/Counter1 Outbut Compare Register Low Byte Bit 0

`#define OCR1AL0_BIT 0`

`#define OCR1AL0_MASK 1`

##### OCR1AL1 - Timer/Counter1 Outbut Compare Register Low Byte Bit 1

`#define OCR1AL1_BIT 1`

`#define OCR1AL1_MASK 2`

##### OCR1AL2 - Timer/Counter1 Outbut Compare Register Low Byte Bit 2

`#define OCR1AL2_BIT 2`

`#define OCR1AL2_MASK 4`

##### OCR1AL3 - Timer/Counter1 Outbut Compare Register Low Byte Bit 3

`#define OCR1AL3_BIT 3`

`#define OCR1AL3_MASK 8`

##### OCR1AL4 - Timer/Counter1 Outbut Compare Register Low Byte Bit 4

`#define OCR1AL4_BIT 4`

`#define OCR1AL4_MASK 16`

##### OCR1AL5 - Timer/Counter1 Outbut Compare Register Low Byte Bit 5

`#define OCR1AL5_BIT 5`

`#define OCR1AL5_MASK 32`

##### OCR1AL6 - Timer/Counter1 Outbut Compare Register Low Byte Bit 6

`#define OCR1AL6_BIT 6`

`#define OCR1AL6_MASK 64`

##### OCR1AL7 - Timer/Counter1 Outbut Compare Register Low Byte Bit 7

`#define OCR1AL7_BIT 7`

`#define OCR1AL7_MASK 128`

### OCR1BH - Timer/Counter1 Output Compare Register B High Byte

`sfrb OCR1BH = 0x29;`

##### OCR1BH0 - Timer/Counter1 Output Compare Register High Byte bit 0

`#define OCR1BH0_BIT 0`

`#define OCR1BH0_MASK 1`

##### OCR1BH1 - Timer/Counter1 Output Compare Register High Byte bit 1

`#define OCR1BH1_BIT 1`

`#define OCR1BH1_MASK 2`

##### OCR1BH2 - Timer/Counter1 Output Compare Register High Byte bit 2

`#define OCR1BH2_BIT 2`

`#define OCR1BH2_MASK 4`

##### OCR1BH3 - Timer/Counter1 Output Compare Register High Byte bit 3

`#define OCR1BH3_BIT 3`

`#define OCR1BH3_MASK 8`

##### OCR1BH4 - Timer/Counter1 Output Compare Register High Byte bit 4

`#define OCR1BH4_BIT 4`

`#define OCR1BH4_MASK 16`

##### OCR1BH5 - Timer/Counter1 Output Compare Register High Byte bit 5

`#define OCR1BH5_BIT 5`

`#define OCR1BH5_MASK 32`

##### OCR1BH6 - Timer/Counter1 Output Compare Register High Byte bit 6

`#define OCR1BH6_BIT 6`

`#define OCR1BH6_MASK 64`

##### OCR1BH7 - Timer/Counter1 Output Compare Register High Byte bit 7

`#define OCR1BH7_BIT 7`

`#define OCR1BH7_MASK 128`

### OCR1BL - Timer/Counter1 Output Compare Register B Low Byte

`sfrb OCR1BL = 0x28;`

##### OCR1BL0 - Timer/Counter1 Output Compare Register Low Byte bit 0

`#define OCR1BL0_BIT 0`

`#define OCR1BL0_MASK 1`

##### OCR1BL1 - Timer/Counter1 Output Compare Register Low Byte bit 1

`#define OCR1BL1_BIT 1`

`#define OCR1BL1_MASK 2`

##### OCR1BL2 - Timer/Counter1 Output Compare Register Low Byte bit 2

`#define OCR1BL2_BIT 2`

`#define OCR1BL2_MASK 4`

##### OCR1BL3 - Timer/Counter1 Output Compare Register Low Byte bit 3

`#define OCR1BL3_BIT 3`

`#define OCR1BL3_MASK 8`

##### OCR1BL4 - Timer/Counter1 Output Compare Register Low Byte bit 4

`#define OCR1BL4_BIT 4`

`#define OCR1BL4_MASK 16`

##### OCR1BL5 - Timer/Counter1 Output Compare Register Low Byte bit 5

`#define OCR1BL5_BIT 5`

`#define OCR1BL5_MASK 32`

##### OCR1BL6 - Timer/Counter1 Output Compare Register Low Byte bit 6

`#define OCR1BL6_BIT 6`

`#define OCR1BL6_MASK 64`

##### OCR1BL7 - Timer/Counter1 Output Compare Register Low Byte bit 7

`#define OCR1BL7_BIT 7`

`#define OCR1BL7_MASK 128`

### ICR1H - Timer/Counter1 Input Capture Register High Byte

`sfrb ICR1H = 0x27;`

##### ICR1H0 - Timer/Counter1 Input Capture Register High Byte bit 0

`#define ICR1H0_BIT 0`

`#define ICR1H0_MASK 1`

##### ICR1H1 - Timer/Counter1 Input Capture Register High Byte bit 1

`#define ICR1H1_BIT 1`

`#define ICR1H1_MASK 2`

##### ICR1H2 - Timer/Counter1 Input Capture Register High Byte bit 2

`#define ICR1H2_BIT 2`

`#define ICR1H2_MASK 4`

##### ICR1H3 - Timer/Counter1 Input Capture Register High Byte bit 3

`#define ICR1H3_BIT 3`

`#define ICR1H3_MASK 8`

##### ICR1H4 - Timer/Counter1 Input Capture Register High Byte bit 4

`#define ICR1H4_BIT 4`

`#define ICR1H4_MASK 16`

##### ICR1H5 - Timer/Counter1 Input Capture Register High Byte bit 5

`#define ICR1H5_BIT 5`

`#define ICR1H5_MASK 32`

##### ICR1H6 - Timer/Counter1 Input Capture Register High Byte bit 6

`#define ICR1H6_BIT 6`

`#define ICR1H6_MASK 64`

##### ICR1H7 - Timer/Counter1 Input Capture Register High Byte bit 7

`#define ICR1H7_BIT 7`

`#define ICR1H7_MASK 128`

### ICR1L - Timer/Counter1 Input Capture Register Low Byte

`sfrb ICR1L = 0x26;`

##### ICR1L0 - Timer/Counter1 Input Capture Register Low Byte bit 0

`#define ICR1L0_BIT 0`

`#define ICR1L0_MASK 1`

##### ICR1L1 - Timer/Counter1 Input Capture Register Low Byte bit 1

`#define ICR1L1_BIT 1`

`#define ICR1L1_MASK 2`

##### ICR1L2 - Timer/Counter1 Input Capture Register Low Byte bit 2

`#define ICR1L2_BIT 2`

`#define ICR1L2_MASK 4`

##### ICR1L3 - Timer/Counter1 Input Capture Register Low Byte bit 3

`#define ICR1L3_BIT 3`

`#define ICR1L3_MASK 8`

##### ICR1L4 - Timer/Counter1 Input Capture Register Low Byte bit 4

`#define ICR1L4_BIT 4`

`#define ICR1L4_MASK 16`

##### ICR1L5 - Timer/Counter1 Input Capture Register Low Byte bit 5

`#define ICR1L5_BIT 5`

`#define ICR1L5_MASK 32`

##### ICR1L6 - Timer/Counter1 Input Capture Register Low Byte bit 6

`#define ICR1L6_BIT 6`

`#define ICR1L6_MASK 64`

##### ICR1L7 - Timer/Counter1 Input Capture Register Low Byte bit 7

`#define ICR1L7_BIT 7`

`#define ICR1L7_MASK 128`

### TIMSK - Timer/Counter Interrupt Mask Register

`sfrb TIMSK = 0x39;`

##### TOIE2 - Timer/Counter 2 Overflow Interrupt enable

`#define TOIE2_BIT 2`

`#define TOIE2_MASK 4`

When this bit is set and the I-bit in the Status Register is 1, the Timer/Counter 2 Overflow interrupt is enabled. The corresponding interrupt (at vector $001C) is executed if an overflow in Timer/Counter1 occurs. The Timer/Counter1 Overflow Flag is set in the Timer/Counter Interrupt Flag Register b

##### TICIE1 - Timer/Counter1 Input Capture Interrupt Enable

`#define TICIE1_BIT 3`

`#define TICIE1_MASK 8`

When this bit is set and the I-bit in the Status Register is one, the Input Capture Event interrupt is enabled. The corresponding interrupt (at vector $0016) is executed if a capture event occurs on pin PB3. The Input Capture Flag in Timer/Counter1 is set in the Timer/Counter Interrupt Flag Register b

##### OCIE1B - Timer/Counter1 Output CompareB Match Interrupt Enable

`#define OCIE1B_BIT 5`

`#define OCIE1B_MASK 32`

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

##### OCIE1A - Timer/Counter1 Output CompareA Match Interrupt Enable

`#define OCIE1A_BIT 6`

`#define OCIE1A_MASK 64`

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

##### TOIE1 - Timer/Counter Overflow Interrupt enable

`#define TOIE1_BIT 7`

`#define TOIE1_MASK 128`

When this bit is set and the I-bit in the Status Register is 1, the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $001C) is executed if an overflow in Timer/Counter1 occurs. The Timer/Counter1 Overflow Flag is set in the Timer/Counter1 Interrupt Flag Register b

### TIFR - Timer/Counter Interrupt Flag register

`sfrb TIFR = 0x38;`

##### TOV0 - Timer/Counter0 Overflow Flag

`#define TOV0_BIT 0`

`#define TOV0_MASK 1`

The TOV0 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter0 Overflow Interrupt is executed. This flag is cleared when written a logic one.

##### TOV2 - Timer/Counter2 Overflow Flag

`#define TOV2_BIT 2`

`#define TOV2_MASK 4`

The TOV2 is set (one) when an overflow occurs in Timer/Counter2. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. This flag is cleared when written with a logic one.

##### ICF1 - Input Capture Flag 1

`#define ICF1_BIT 3`

`#define ICF1_MASK 8`

The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.

##### OCFB - Output Compare Flag B

`#define OCFB_BIT 5`

`#define OCFB_MASK 32`

The OCFB bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.

##### OCFA - Output Compare Flag A

`#define OCFA_BIT 6`

`#define OCFA_MASK 64`

The OCFA bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed.

## TIMER COUNTER 2

### TCCR2 - Timer/Counter2 Control Register

`sfrb TCCR2 = 0x25;`

##### CS00 - Clock Select 1

`#define CS00_BIT 0`

`#define CS00_MASK 1`

The three clock select bits select the clock source to be used by the Timer/Counter,

##### CS01 - Clock Select 1

`#define CS01_BIT 1`

`#define CS01_MASK 2`

The three clock select bits select the clock source to be used by the Timer/Counter,

##### CS02 - Clock Select 2

`#define CS02_BIT 2`

`#define CS02_MASK 4`

The three clock select bits select the clock source to be used by the Timer/Counter,

### TCNT2 - Timer/Counter2

`sfrb TCNT2 = 0x32;`

##### TCNT2_0

`#define TCNT2_0_BIT 0`

`#define TCNT2_0_MASK 1`

##### TCNT2_1

`#define TCNT2_1_BIT 1`

`#define TCNT2_1_MASK 2`

##### TCNT2_2

`#define TCNT2_2_BIT 2`

`#define TCNT2_2_MASK 4`

##### TCNT2_3

`#define TCNT2_3_BIT 3`

`#define TCNT2_3_MASK 8`

##### TCNT2_4

`#define TCNT2_4_BIT 4`

`#define TCNT2_4_MASK 16`

##### TCNT2_5

`#define TCNT2_5_BIT 5`

`#define TCNT2_5_MASK 32`

##### TCNT2_6

`#define TCNT2_6_BIT 6`

`#define TCNT2_6_MASK 64`

##### TCNT2_7

`#define TCNT2_7_BIT 7`

`#define TCNT2_7_MASK 128`

### PRELD2 - Pre-load Register 2

`sfrb PRELD2 = 0x23;`

##### OCR0_0

`#define OCR0_0_BIT 0`

`#define OCR0_0_MASK 1`

##### OCR0_1

`#define OCR0_1_BIT 1`

`#define OCR0_1_MASK 2`

##### BIT2

`#define BIT2_BIT 2`

`#define BIT2_MASK 4`

##### BIT3

`#define BIT3_BIT 3`

`#define BIT3_MASK 8`

##### BIT4

`#define BIT4_BIT 4`

`#define BIT4_MASK 16`

##### BIT5

`#define BIT5_BIT 5`

`#define BIT5_MASK 32`

##### BIT6

`#define BIT6_BIT 6`

`#define BIT6_MASK 64`

##### BIT7

`#define BIT7_BIT 7`

`#define BIT7_MASK 128`

## WATCHDOG

### WDTCR - Watchdog Timer Control Register

`sfrb WDTCR = 0x21;`

##### WDP0 - Watch Dog Timer Prescaler bit 0

`#define WDP0_BIT 0`

`#define WDP0_MASK 1`

The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.

##### WDP1 - Watch Dog Timer Prescaler bit 1

`#define WDP1_BIT 1`

`#define WDP1_MASK 2`

The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.

##### WDP2 - Watch Dog Timer Prescaler bit 2

`#define WDP2_BIT 2`

`#define WDP2_MASK 4`

The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.

##### WDE - Watch Dog Enable

`#define WDE_BIT 3`

`#define WDE_MASK 8`

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watch

##### WDTOE - Watchdog Turn Off Enable

`#define WDTOE_BIT 4`

`#define WDTOE_MASK 16`

This bit must be set when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, H/w will clear this bit to zero after four cycles.

## SPI

The Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: b

### SPCR - SPI Control Register

`sfrb SPCR = 0x0D;`

##### SPR0 - SPI Clock Rate Select 0

`#define SPR0_BIT 0`

`#define SPR0_MASK 1`

These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.

##### SPR1 - SPI Clock Rate Select 1

`#define SPR1_BIT 1`

`#define SPR1_MASK 2`

These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.

##### CPHA - Clock Phase

`#define CPHA_BIT 2`

`#define CPHA_MASK 4`

Refer to Figure 36 or Figure 37 for the functionality of this bit.

##### CPOL - Clock polarity

`#define CPOL_BIT 3`

`#define CPOL_MASK 8`

When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.

##### MSTR - Master/Slave Select

`#define MSTR_BIT 4`

`#define MSTR_MASK 16`

This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.

##### DORD - Data Order

`#define DORD_BIT 5`

`#define DORD_MASK 32`

When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.

##### SPE - SPI Enable

`#define SPE_BIT 6`

`#define SPE_MASK 64`

When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.

##### SPIE - SPI Interrupt Enable

`#define SPIE_BIT 7`

`#define SPIE_MASK 128`

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.

### SPSR - SPI Status Register

`sfrb SPSR = 0x0E;`

##### WCOL - Write Collision Flag

`#define WCOL_BIT 6`

`#define WCOL_MASK 64`

The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.

##### SPIF - SPI Interrupt Flag

`#define SPIF_BIT 7`

`#define SPIF_MASK 128`

When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).

### SPDR - SPI Data Register

`sfrb SPDR = 0x0F;`

##### SPDR0 - SPI Data Register bit 0

`#define SPDR0_BIT 0`

`#define SPDR0_MASK 1`

##### SPDR1 - SPI Data Register bit 1

`#define SPDR1_BIT 1`

`#define SPDR1_MASK 2`

##### SPDR2 - SPI Data Register bit 2

`#define SPDR2_BIT 2`

`#define SPDR2_MASK 4`

##### SPDR3 - SPI Data Register bit 3

`#define SPDR3_BIT 3`

`#define SPDR3_MASK 8`

##### SPDR4 - SPI Data Register bit 4

`#define SPDR4_BIT 4`

`#define SPDR4_MASK 16`

##### SPDR5 - SPI Data Register bit 5

`#define SPDR5_BIT 5`

`#define SPDR5_MASK 32`

##### SPDR6 - SPI Data Register bit 6

`#define SPDR6_BIT 6`

`#define SPDR6_MASK 64`

##### SPDR7 - SPI Data Register bit 7

`#define SPDR7_BIT 7`

`#define SPDR7_MASK 128`

## PORTA

### PORTA - Port A Data Register

`sfrb PORTA = 0x1B;`

##### PORTA0 - Port A Data Register bit 0

`#define PORTA0_BIT 0`

`#define PORTA0_MASK 1`

##### PORTA1 - Port A Data Register bit 1

`#define PORTA1_BIT 1`

`#define PORTA1_MASK 2`

##### PORTA2 - Port A Data Register bit 2

`#define PORTA2_BIT 2`

`#define PORTA2_MASK 4`

##### PORTA3 - Port A Data Register bit 3

`#define PORTA3_BIT 3`

`#define PORTA3_MASK 8`

##### PORTA4 - Port A Data Register bit 4

`#define PORTA4_BIT 4`

`#define PORTA4_MASK 16`

##### PORTA5 - Port A Data Register bit 5

`#define PORTA5_BIT 5`

`#define PORTA5_MASK 32`

##### PORTA6 - Port A Data Register bit 6

`#define PORTA6_BIT 6`

`#define PORTA6_MASK 64`

##### PORTA7 - Port A Data Register bit 7

`#define PORTA7_BIT 7`

`#define PORTA7_MASK 128`

### DDRA - Port A Data Direction Register

`sfrb DDRA = 0x1A;`

##### DDRA0 - Data Direction Register, Port A, bit 0

`#define DDRA0_BIT 0`

`#define DDRA0_MASK 1`

##### DDRA1 - Data Direction Register, Port A, bit 1

`#define DDRA1_BIT 1`

`#define DDRA1_MASK 2`

##### DDRA2 - Data Direction Register, Port A, bit 2

`#define DDRA2_BIT 2`

`#define DDRA2_MASK 4`

##### DDRA3 - Data Direction Register, Port A, bit 3

`#define DDRA3_BIT 3`

`#define DDRA3_MASK 8`

##### DDRA4 - Data Direction Register, Port A, bit 4

`#define DDRA4_BIT 4`

`#define DDRA4_MASK 16`

##### DDRA5 - Data Direction Register, Port A, bit 5

`#define DDRA5_BIT 5`

`#define DDRA5_MASK 32`

##### DDRA6 - Data Direction Register, Port A, bit 6

`#define DDRA6_BIT 6`

`#define DDRA6_MASK 64`

##### DDRA7 - Data Direction Register, Port A, bit 7

`#define DDRA7_BIT 7`

`#define DDRA7_MASK 128`

### PINA - Port A Input Pins

`sfrb PINA = 0x19;`

##### PINA0 - Input Pins, Port A bit 0

`#define PINA0_BIT 0`

`#define PINA0_MASK 1`

##### PINA1 - Input Pins, Port A bit 1

`#define PINA1_BIT 1`

`#define PINA1_MASK 2`

##### PINA2 - Input Pins, Port A bit 2

`#define PINA2_BIT 2`

`#define PINA2_MASK 4`

##### PINA3 - Input Pins, Port A bit 3

`#define PINA3_BIT 3`

`#define PINA3_MASK 8`

##### PINA4 - Input Pins, Port A bit 4

`#define PINA4_BIT 4`

`#define PINA4_MASK 16`

##### PINA5 - Input Pins, Port A bit 5

`#define PINA5_BIT 5`

`#define PINA5_MASK 32`

##### PINA6 - Input Pins, Port A bit 6

`#define PINA6_BIT 6`

`#define PINA6_MASK 64`

##### PINA7 - Input Pins, Port A bit 7

`#define PINA7_BIT 7`

`#define PINA7_MASK 128`

## PORTB

### PORTB - Port B Data Register

`sfrb PORTB = 0x18;`

##### PORTB0 - Port B Data Register bit 0

`#define PORTB0_BIT 0`

`#define PORTB0_MASK 1`

##### PORTB1 - Port B Data Register bit 1

`#define PORTB1_BIT 1`

`#define PORTB1_MASK 2`

##### PORTB2 - Port B Data Register bit 2

`#define PORTB2_BIT 2`

`#define PORTB2_MASK 4`

##### PORTB3 - Port B Data Register bit 3

`#define PORTB3_BIT 3`

`#define PORTB3_MASK 8`

##### PORTB4 - Port B Data Register bit 4

`#define PORTB4_BIT 4`

`#define PORTB4_MASK 16`

##### PORTB5 - Port B Data Register bit 5

`#define PORTB5_BIT 5`

`#define PORTB5_MASK 32`

##### PORTB6 - Port B Data Register bit 6

`#define PORTB6_BIT 6`

`#define PORTB6_MASK 64`

##### PORTB7 - Port B Data Register bit 7

`#define PORTB7_BIT 7`

`#define PORTB7_MASK 128`

### DDRB - Port B Data Direction Register

`sfrb DDRB = 0x17;`

##### DDRB0 - Port B Data Direction Register bit 0

`#define DDRB0_BIT 0`

`#define DDRB0_MASK 1`

##### DDRB1 - Port B Data Direction Register bit 1

`#define DDRB1_BIT 1`

`#define DDRB1_MASK 2`

##### DDRB2 - Port B Data Direction Register bit 2

`#define DDRB2_BIT 2`

`#define DDRB2_MASK 4`

##### DDRB3 - Port B Data Direction Register bit 3

`#define DDRB3_BIT 3`

`#define DDRB3_MASK 8`

##### DDRB4 - Port B Data Direction Register bit 4

`#define DDRB4_BIT 4`

`#define DDRB4_MASK 16`

##### DDRB5 - Port B Data Direction Register bit 5

`#define DDRB5_BIT 5`

`#define DDRB5_MASK 32`

##### DDRB6 - Port B Data Direction Register bit 6

`#define DDRB6_BIT 6`

`#define DDRB6_MASK 64`

##### DDRB7 - Port B Data Direction Register bit 7

`#define DDRB7_BIT 7`

`#define DDRB7_MASK 128`

### PINB - Port B Input Pins

`sfrb PINB = 0x16;`

##### PINB0 - Port B Input Pins bit 0

`#define PINB0_BIT 0`

`#define PINB0_MASK 1`

##### PINB1 - Port B Input Pins bit 1

`#define PINB1_BIT 1`

`#define PINB1_MASK 2`

##### PINB2 - Port B Input Pins bit 2

`#define PINB2_BIT 2`

`#define PINB2_MASK 4`

##### PINB3 - Port B Input Pins bit 3

`#define PINB3_BIT 3`

`#define PINB3_MASK 8`

##### PINB4 - Port B Input Pins bit 4

`#define PINB4_BIT 4`

`#define PINB4_MASK 16`

##### PINB5 - Port B Input Pins bit 5

`#define PINB5_BIT 5`

`#define PINB5_MASK 32`

##### PINB6 - Port B Input Pins bit 6

`#define PINB6_BIT 6`

`#define PINB6_MASK 64`

##### PINB7 - Port B Input Pins bit 7

`#define PINB7_BIT 7`

`#define PINB7_MASK 128`

## PORTC

### PORTC - Port C Data Register

`sfrb PORTC = 0x15;`

##### PORTC0 - Port C Data Register bit 0

`#define PORTC0_BIT 0`

`#define PORTC0_MASK 1`

##### PORTC1 - Port C Data Register bit 1

`#define PORTC1_BIT 1`

`#define PORTC1_MASK 2`

##### PORTC2 - Port C Data Register bit 2

`#define PORTC2_BIT 2`

`#define PORTC2_MASK 4`

##### PORTC3 - Port C Data Register bit 3

`#define PORTC3_BIT 3`

`#define PORTC3_MASK 8`

##### PORTC4 - Port C Data Register bit 4

`#define PORTC4_BIT 4`

`#define PORTC4_MASK 16`

##### PORTC5 - Port C Data Register bit 5

`#define PORTC5_BIT 5`

`#define PORTC5_MASK 32`

##### PORTC6 - Port C Data Register bit 6

`#define PORTC6_BIT 6`

`#define PORTC6_MASK 64`

##### PORTC7 - Port C Data Register bit 7

`#define PORTC7_BIT 7`

`#define PORTC7_MASK 128`

### DDRC - Port C Data Direction Register

`sfrb DDRC = 0x14;`

##### DDRC0 - Port C Data Direction Register bit 0

`#define DDRC0_BIT 0`

`#define DDRC0_MASK 1`

##### DDRC1 - Port C Data Direction Register bit 1

`#define DDRC1_BIT 1`

`#define DDRC1_MASK 2`

##### DDRC2 - Port C Data Direction Register bit 2

`#define DDRC2_BIT 2`

`#define DDRC2_MASK 4`

##### DDRC3 - Port C Data Direction Register bit 3

`#define DDRC3_BIT 3`

`#define DDRC3_MASK 8`

##### DDRC4 - Port C Data Direction Register bit 4

`#define DDRC4_BIT 4`

`#define DDRC4_MASK 16`

##### DDRC5 - Port C Data Direction Register bit 5

`#define DDRC5_BIT 5`

`#define DDRC5_MASK 32`

##### DDRC6 - Port C Data Direction Register bit 6

`#define DDRC6_BIT 6`

`#define DDRC6_MASK 64`

##### DDRC7 - Port C Data Direction Register bit 7

`#define DDRC7_BIT 7`

`#define DDRC7_MASK 128`

### PINC - Port C Input Pins

`sfrb PINC = 0x13;`

##### PINC0 - Port C Input Pins bit 0

`#define PINC0_BIT 0`

`#define PINC0_MASK 1`

##### PINC1 - Port C Input Pins bit 1

`#define PINC1_BIT 1`

`#define PINC1_MASK 2`

##### PINC2 - Port C Input Pins bit 2

`#define PINC2_BIT 2`

`#define PINC2_MASK 4`

##### PINC3 - Port C Input Pins bit 3

`#define PINC3_BIT 3`

`#define PINC3_MASK 8`

##### PINC4 - Port C Input Pins bit 4

`#define PINC4_BIT 4`

`#define PINC4_MASK 16`

##### PINC5 - Port C Input Pins bit 5

`#define PINC5_BIT 5`

`#define PINC5_MASK 32`

##### PINC6 - Port C Input Pins bit 6

`#define PINC6_BIT 6`

`#define PINC6_MASK 64`

##### PINC7 - Port C Input Pins bit 7

`#define PINC7_BIT 7`

`#define PINC7_MASK 128`

## PORTD

### PORTD - Port D Data Register

`sfrb PORTD = 0x12;`

##### PORTD0 - Port D Data Register bit 0

`#define PORTD0_BIT 0`

`#define PORTD0_MASK 1`

##### PORTD1 - Port D Data Register bit 1

`#define PORTD1_BIT 1`

`#define PORTD1_MASK 2`

##### PORTD2 - Port D Data Register bit 2

`#define PORTD2_BIT 2`

`#define PORTD2_MASK 4`

##### PORTD3 - Port D Data Register bit 3

`#define PORTD3_BIT 3`

`#define PORTD3_MASK 8`

##### PORTD4 - Port D Data Register bit 4

`#define PORTD4_BIT 4`

`#define PORTD4_MASK 16`

##### PORTD5 - Port D Data Register bit 5

`#define PORTD5_BIT 5`

`#define PORTD5_MASK 32`

##### PORTD6 - Port D Data Register bit 6

`#define PORTD6_BIT 6`

`#define PORTD6_MASK 64`

##### PORTD7 - Port D Data Register bit 7

`#define PORTD7_BIT 7`

`#define PORTD7_MASK 128`

### DDRD - Port D Data Direction Register

`sfrb DDRD = 0x11;`

##### DDRD0 - Port D Data Direction Register bit 0

`#define DDRD0_BIT 0`

`#define DDRD0_MASK 1`

##### DDRD1 - Port D Data Direction Register bit 1

`#define DDRD1_BIT 1`

`#define DDRD1_MASK 2`

##### DDRD2 - Port D Data Direction Register bit 2

`#define DDRD2_BIT 2`

`#define DDRD2_MASK 4`

##### DDRD3 - Port D Data Direction Register bit 3

`#define DDRD3_BIT 3`

`#define DDRD3_MASK 8`

##### DDRD4 - Port D Data Direction Register bit 4

`#define DDRD4_BIT 4`

`#define DDRD4_MASK 16`

##### DDRD5 - Port D Data Direction Register bit 5

`#define DDRD5_BIT 5`

`#define DDRD5_MASK 32`

##### DDRD6 - Port D Data Direction Register bit 6

`#define DDRD6_BIT 6`

`#define DDRD6_MASK 64`

##### DDRD7 - Port D Data Direction Register bit 7

`#define DDRD7_BIT 7`

`#define DDRD7_MASK 128`

### PIND - Port D Input Pins

`sfrb PIND = 0x10;`

##### PIND0 - Port D Input Pins bit 0

`#define PIND0_BIT 0`

`#define PIND0_MASK 1`

##### PIND1 - Port D Input Pins bit 1

`#define PIND1_BIT 1`

`#define PIND1_MASK 2`

##### PIND2 - Port D Input Pins bit 2

`#define PIND2_BIT 2`

`#define PIND2_MASK 4`

##### PIND3 - Port D Input Pins bit 3

`#define PIND3_BIT 3`

`#define PIND3_MASK 8`

##### PIND4 - Port D Input Pins bit 4

`#define PIND4_BIT 4`

`#define PIND4_MASK 16`

##### PIND5 - Port D Input Pins bit 5

`#define PIND5_BIT 5`

`#define PIND5_MASK 32`

##### PIND6 - Port D Input Pins bit 6

`#define PIND6_BIT 6`

`#define PIND6_MASK 64`

##### PIND7 - Port D Input Pins bit 7

`#define PIND7_BIT 7`

`#define PIND7_MASK 128`

## PORTE

### PORTE - Data Register, Port E

`sfrb PORTE = 0x0A;`

##### PORTE0

`#define PORTE0_BIT 0`

`#define PORTE0_MASK 1`

##### PORTE1

`#define PORTE1_BIT 1`

`#define PORTE1_MASK 2`

##### PORTE2

`#define PORTE2_BIT 2`

`#define PORTE2_MASK 4`

##### PORTE3

`#define PORTE3_BIT 3`

`#define PORTE3_MASK 8`

##### PORTE4

`#define PORTE4_BIT 4`

`#define PORTE4_MASK 16`

##### PORTE5

`#define PORTE5_BIT 5`

`#define PORTE5_MASK 32`

##### PORTE6

`#define PORTE6_BIT 6`

`#define PORTE6_MASK 64`

##### PORTE7

`#define PORTE7_BIT 7`

`#define PORTE7_MASK 128`

### DDRE - Data Direction Register, Port E

`sfrb DDRE = 0x09;`

##### DDRE0

`#define DDRE0_BIT 0`

`#define DDRE0_MASK 1`

##### DDRE1

`#define DDRE1_BIT 1`

`#define DDRE1_MASK 2`

##### DDRE2

`#define DDRE2_BIT 2`

`#define DDRE2_MASK 4`

##### DDRE3

`#define DDRE3_BIT 3`

`#define DDRE3_MASK 8`

##### DDRE4

`#define DDRE4_BIT 4`

`#define DDRE4_MASK 16`

##### DDRE5

`#define DDRE5_BIT 5`

`#define DDRE5_MASK 32`

##### DDRE6

`#define DDRE6_BIT 6`

`#define DDRE6_MASK 64`

##### DDRE7

`#define DDRE7_BIT 7`

`#define DDRE7_MASK 128`

### PINE - Input Pins, Port E

`sfrb PINE = 0x08;`

##### PINE0

`#define PINE0_BIT 0`

`#define PINE0_MASK 1`

##### PINE1

`#define PINE1_BIT 1`

`#define PINE1_MASK 2`

##### PINE2

`#define PINE2_BIT 2`

`#define PINE2_MASK 4`

##### PINE3

`#define PINE3_BIT 3`

`#define PINE3_MASK 8`

##### PINE4

`#define PINE4_BIT 4`

`#define PINE4_MASK 16`

##### PINE5

`#define PINE5_BIT 5`

`#define PINE5_MASK 32`

##### PINE6

`#define PINE6_BIT 6`

`#define PINE6_MASK 64`

##### PINE7

`#define PINE7_BIT 7`

`#define PINE7_MASK 128`

## JTAG

JTAG Features: JTAG (IEEE std. 1149.1 compliant) Interface. Boundary-Scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard. Debugger Access to: b

### IDR - I/O Debug Register

`sfrb IDR = 0x3C;`

##### IDR0 - On-Chip Debug Register Bit 0

`#define IDR0_BIT 0`

`#define IDR0_MASK 1`

##### IDR1 - On-Chip Debug Register Bit 1

`#define IDR1_BIT 1`

`#define IDR1_MASK 2`

##### IDR2 - On-Chip Debug Register Bit 2

`#define IDR2_BIT 2`

`#define IDR2_MASK 4`

##### IDR3 - On-Chip Debug Register Bit 3

`#define IDR3_BIT 3`

`#define IDR3_MASK 8`

##### IDR4 - On-Chip Debug Register Bit 4

`#define IDR4_BIT 4`

`#define IDR4_MASK 16`

##### IDR5 - On-Chip Debug Register Bit 5

`#define IDR5_BIT 5`

`#define IDR5_MASK 32`

##### IDR6 - On-Chip Debug Register Bit 6

`#define IDR6_BIT 6`

`#define IDR6_MASK 64`

##### IDRD - IO Debug register dirty.

`#define IDRD_BIT 7`

`#define IDRD_MASK 128`

This bit is set to indicate to the debugger that the register has been written.

## EXTERNAL INTERRUPT

The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in b

### EIMSK - External Interrupt Mask Register

`sfrb EIMSK = 0x37;`

##### INT0 - External Interrupt Request 0 Enable

`#define INT0_BIT 0`

`#define INT0_MASK 1`

If it is set and the 1-bit in the Status Register is set, the external pin interrupt 0 is enabled.

##### INT1 - External Interrupt Request 1 Enable

`#define INT1_BIT 1`

`#define INT1_MASK 2`

If it is set and the 1-bit in the Status Register is set, the external pin interrupt 1 is enabled.

##### INT2 - External Interrupt Request 2 Enable

`#define INT2_BIT 2`

`#define INT2_MASK 4`

If it is set and the 1-bit in the Status Register is set, the external pin interrupt 2 is enabled.

##### INT3 - External Interrupt Request 3 Enable

`#define INT3_BIT 3`

`#define INT3_MASK 8`

If it is set and the 1-bit in the Status Register is set, the external pin interrupt 3 is enabled.

##### POL0 - Polarity of External Interrupt 0

`#define POL0_BIT 4`

`#define POL0_MASK 16`

INT0 is active high when this bit is low.

##### POL1 - Polarity of External Interrupt 1

`#define POL1_BIT 5`

`#define POL1_MASK 32`

INT1 is active high when this bit is low.

##### POL2 - Polarity of External Interrupt 2.

`#define POL2_BIT 6`

`#define POL2_MASK 64`

INT2 is active high when this bit is low.

##### POL3 - Polarity of External Interrupt 3.

`#define POL3_BIT 7`

`#define POL3_MASK 128`

INT3 is active high when this bit is low.

## MEMORY ACCESS

External Memory Interface

### EMICRA - External Memory Interface Control Register A

`sfrb EMICRA = 0x1C;`

##### WM0

`#define WM0_BIT 0`

`#define WM0_MASK 1`

These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.

##### WM1

`#define WM1_BIT 1`

`#define WM1_MASK 2`

These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.

##### WW0

`#define WW0_BIT 2`

`#define WW0_MASK 4`

These bits control the Wait states inserted inthe corresponding (read, write and ALE) signals.

##### WW1

`#define WW1_BIT 3`

`#define WW1_MASK 8`

These bits control the Wait states inserted inthe corresponding (read, write and ALE) signals.

##### RM0

`#define RM0_BIT 4`

`#define RM0_MASK 16`

These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.

##### RM1

`#define RM1_BIT 5`

`#define RM1_MASK 32`

These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.

##### RW0

`#define RW0_BIT 6`

`#define RW0_MASK 64`

These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.

##### RW1

`#define RW1_BIT 7`

`#define RW1_MASK 128`

These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.

### EMICRB - External memory Interface Control Register B

`sfrb EMICRB = 0x1D;`

##### EMD1

`#define EMD1_BIT 0`

`#define EMD1_MASK 1`

These bits select the external memory interface mode

##### EMD0

`#define EMD0_BIT 1`

`#define EMD0_MASK 2`

These bits select the external memory interface mode

##### AM0

`#define AM0_BIT 4`

`#define AM0_MASK 16`

These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.

##### AM1

`#define AM1_BIT 5`

`#define AM1_MASK 32`

These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.

##### AW0

`#define AW0_BIT 6`

`#define AW0_MASK 64`

These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.

##### AW1

`#define AW1_BIT 7`

`#define AW1_MASK 128`

These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.

### MEMMAP - Memory Bank Map Register

`sfrb MEMMAP = 0xF800;`

##### MEMMAP0

`#define MEMMAP0_BIT 0`

`#define MEMMAP0_MASK 1`

##### MEMMAP1

`#define MEMMAP1_BIT 1`

`#define MEMMAP1_MASK 2`

##### MEMMAP2

`#define MEMMAP2_BIT 2`

`#define MEMMAP2_MASK 4`

##### MEMMAP3

`#define MEMMAP3_BIT 3`

`#define MEMMAP3_MASK 8`

##### MEMMAP4

`#define MEMMAP4_BIT 4`

`#define MEMMAP4_MASK 16`

##### MEMMAP5

`#define MEMMAP5_BIT 5`

`#define MEMMAP5_MASK 32`

##### MEMMAP6

`#define MEMMAP6_BIT 6`

`#define MEMMAP6_MASK 64`

##### MEMMAP7

`#define MEMMAP7_BIT 7`

`#define MEMMAP7_MASK 128`

### DMA_EMICRA - DMA External Memory Interface Control Register A

`sfrb DMA_EMICRA = 0xF801;`

##### WM0 - Write Mode Select

`#define WM0_BIT 0`

`#define WM0_MASK 1`

These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.

##### WM1 - Write Mode Select

`#define WM1_BIT 1`

`#define WM1_MASK 2`

These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.

##### WW0 - Write Wait States

`#define WW0_BIT 2`

`#define WW0_MASK 4`

These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.

##### WW1 - Write Wait States

`#define WW1_BIT 3`

`#define WW1_MASK 8`

These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.

##### RM0 - Read Mode Select

`#define RM0_BIT 4`

`#define RM0_MASK 16`

These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.

##### RM1 - Read Mode Select

`#define RM1_BIT 5`

`#define RM1_MASK 32`

These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.

##### RW0 - Read Wait States

`#define RW0_BIT 6`

`#define RW0_MASK 64`

These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.

##### RW1 - Read Wait States

`#define RW1_BIT 7`

`#define RW1_MASK 128`

These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.

### DMA_EMICRB - DMA External Memory Interface Control Register B

`sfrb DMA_EMICRB = 0xF802;`

##### EMD0 - External Memory Device Select

`#define EMD0_BIT 0`

`#define EMD0_MASK 1`

These bits select the external memory interface mode.

##### EMD1 - External Memory Device Select

`#define EMD1_BIT 1`

`#define EMD1_MASK 2`

These bits select the external memory interface mode.

##### AM0 - ALE Mode Select

`#define AM0_BIT 4`

`#define AM0_MASK 16`

These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.

##### AM1 - ALE Mode Select

`#define AM1_BIT 5`

`#define AM1_MASK 32`

These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.

##### AW0 - ALE Wait States

`#define AW0_BIT 6`

`#define AW0_MASK 64`

These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.

##### AW1 - ALE Wait States

`#define AW1_BIT 7`

`#define AW1_MASK 128`

These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.

### REMAP - Remapping Register

`sfrb REMAP = 0xF404;`

##### REMAP - Remap bit

`#define REMAP_BIT 0`

`#define REMAP_MASK 1`

This bit indicates the active memory. If this bit is low (zero) we are in ROM mode, while if it is high ( one) we are in SRAM mode

## IRDA

### IRDACR - IrDA Control Register

`sfrb IRDACR = 0x22;`

##### IRDAEN - Enable IRDA

`#define IRDAEN_BIT 0`

`#define IRDAEN_MASK 1`

When set enables the IrDA codec. When cleared the codec is transparent to UART0/1 SIN/SOUT pins

##### USEL - UART Select

`#define USEL_BIT 1`

`#define USEL_MASK 2`

When cleared the codec uses UART0. When set the codec uses UART1

##### MODE

`#define MODE_BIT 2`

`#define MODE_MASK 4`

When cleared enables the 3/16 Return-to-Zero encoding scheme. When set enables the 4/16 Return-to-Zero encoding scheme

##### RXPOL - Receive Polarity

`#define RXPOL_BIT 3`

`#define RXPOL_MASK 8`

When set, the SIN signal is inverted before entering the IrDA codec

##### TXPOL - Transmit Polarity

`#define TXPOL_BIT 4`

`#define TXPOL_MASK 16`

If set the SOUT signal is inverted.

## CPU

### SREG - Status Register

`sfrb SREG = 0x3F;`

### SPH - Stack Pointer High

`sfrb SPH = 0x3E;`

##### SP8 - Stack pointer bit 8

`#define SP8_BIT 0`

`#define SP8_MASK 1`

##### SP9 - Stack pointer bit 9

`#define SP9_BIT 1`

`#define SP9_MASK 2`

##### SP10 - Stack pointer bit 10

`#define SP10_BIT 2`

`#define SP10_MASK 4`

##### SP11 - Stack pointer bit 11

`#define SP11_BIT 3`

`#define SP11_MASK 8`

##### SP12

`#define SP12_BIT 4`

`#define SP12_MASK 16`

##### SP13 - Stack pointer bit 13

`#define SP13_BIT 5`

`#define SP13_MASK 32`

##### SP14 - Stack pointer bit 14

`#define SP14_BIT 6`

`#define SP14_MASK 64`

##### SP15 - Stack pointer bit 15

`#define SP15_BIT 7`

`#define SP15_MASK 128`

### SPL - Stack Pointer Low

`sfrb SPL = 0x3D;`

##### SP0 - Stack pointer bit 0

`#define SP0_BIT 0`

`#define SP0_MASK 1`

##### SP1 - Stack pointer bit 1

`#define SP1_BIT 1`

`#define SP1_MASK 2`

##### SP2 - Stack pointer bit 2

`#define SP2_BIT 2`

`#define SP2_MASK 4`

##### SP3 - Stack pointer bit 3

`#define SP3_BIT 3`

`#define SP3_MASK 8`

##### SP4

`#define SP4_BIT 4`

`#define SP4_MASK 16`

##### SP5 - Stack pointer bit 5

`#define SP5_BIT 5`

`#define SP5_MASK 32`

##### SP6 - Stack pointer bit 6

`#define SP6_BIT 6`

`#define SP6_MASK 64`

##### SP7 - Stack pointer bit 7

`#define SP7_BIT 7`

`#define SP7_MASK 128`

### MCUCR - MCU Control Register

`sfrb MCUCR = 0x35;`

##### SM - Sleep mode select bit

`#define SM_BIT 5`

`#define SM_MASK 32`

Thsi bit selects between the two available sleep modes

##### SE - Sleep enable

`#define SE_BIT 6`

`#define SE_MASK 64`

When set permits the MCU to enter in sleep mode when the SLEEP instruction is executed.

### MCUSR - MCU Status Register

`sfrb MCUSR = 0x34;`

##### PORF - Power-on reset flag

`#define PORF_BIT 0`

`#define PORF_MASK 1`

This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.

##### EXTRF - External Reset Flag

`#define EXTRF_BIT 1`

`#define EXTRF_MASK 2`

This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

### CLK_CNTR - Clock Control Register

`sfrb CLK_CNTR = 0x0C;`

##### MCSP0 - AVR Core speed select 0

`#define MCSP0_BIT 0`

`#define MCSP0_MASK 1`

These bits control the AVR clock divisor according to table 19 of datasheet

##### MCSP1 - AVR Core speed select 1

`#define MCSP1_BIT 1`

`#define MCSP1_MASK 2`

These bits control the AVR clock divisor according to table 19 of datasheet

##### MUL16 - PLL multiplier select

`#define MUL16_BIT 2`

`#define MUL16_MASK 4`

Selects the multiplier of the PLL. When set the external 12MHz crystal frequency is multiplied by 16 to generate an internal fast clock of 192MHz. When cleared, the external 12MHz crystal frequency is multiplied by 8 generating an internal fast clock of 96MHz.

##### PIVCO1 - PLL IVCO[1]

`#define PIVCO1_BIT 3`

`#define PIVCO1_MASK 8`

Selects the PLL frequency range. Normally, this bit must be eual to the MUL16 bit.

##### UDPLL

`#define UDPLL_BIT 5`

`#define UDPLL_MASK 32`

Select DPLL96 instead of DPLL48 for USB clock recovery.

##### PLCK

`#define PLCK_BIT 6`

`#define PLCK_MASK 64`

If set the PLL Lock signal is used for "PLL Stable indication. If cleared , the "PLL Stable" indication is equal to the "PLL Enable" signal delayed by a significant factor.

##### NPICP - Equal to the reversed PLL ICP bit.

`#define NPICP_BIT 7`

`#define NPICP_MASK 128`

This bit controls the PLL Charge-Pump current

### PERIPHEN - Peripheral Enable Control Register

`sfrb PERIPHEN = 0x0B;`

##### EMIEN - External memory Interface Enable

`#define EMIEN_BIT 0`

`#define EMIEN_MASK 1`

When set, the exetrnal memory interface is enabled and the pin functions of PortA and Port C are set to their alternative pin functions. the EMIEN bit overrides any bit direction settings in the respective data direction registers

##### USBE - USB Enable

`#define USBE_BIT 1`

`#define USBE_MASK 2`

When set enables the function of USB (clock Enable).

##### UATTACH - USB Attach

`#define UATTACH_BIT 2`

`#define UATTACH_MASK 4`

When set deactivates (logic 0) the USB_ATTACH pin.

##### UART0 - UART0 Enable

`#define UART0_BIT 3`

`#define UART0_MASK 8`

When set enables the function of UART0

##### UART1 - UART1 Enable

`#define UART1_BIT 4`

`#define UART1_MASK 16`

When set enables the function of UART1

##### SPI - SPI Enable

`#define SPI_BIT 5`

`#define SPI_MASK 32`

If set enables the SPI Controller

### PMOD - Program Mode Register

`sfrb PMOD = 0x1F;`

##### PMODE0 - The value of the PMODE0 input pin.

`#define PMODE0_BIT 0`

`#define PMODE0_MASK 1`

The value of the PMODE0 input pin.

##### PMODE1 - The value of the PMODE1 input pin.

`#define PMODE1_BIT 1`

`#define PMODE1_MASK 2`

The value of the PMODE1 input pin.

## UART0

The base address for UART0 registers is $F200 and for UART1 registers is $F300. Each read or write access of UART registers consumes at least 2 CPU cycles, since the UART core clock is asynchronous and fixed to 14.769MHz.

### HR - Receive/Transmit Holding Register

`sfrb HR = $F200;`

##### HR0

`#define HR0_BIT 0`

`#define HR0_MASK 1`

##### HR1

`#define HR1_BIT 1`

`#define HR1_MASK 2`

##### HR2

`#define HR2_BIT 2`

`#define HR2_MASK 4`

##### HR3

`#define HR3_BIT 3`

`#define HR3_MASK 8`

##### HR4

`#define HR4_BIT 4`

`#define HR4_MASK 16`

##### HR5

`#define HR5_BIT 5`

`#define HR5_MASK 32`

##### HR6

`#define HR6_BIT 6`

`#define HR6_MASK 64`

##### HR7

`#define HR7_BIT 7`

`#define HR7_MASK 128`

### IER - Interrupt Enable Register

`sfrb IER = $F201;`

##### RDAI - Enable RX Data Available Interrupt

`#define RDAI_BIT 0`

`#define RDAI_MASK 1`

If set enables the Rx data available interrupt. Also enables and the time-out interrupt when time-out counter is enabled (in FIFO mode or if RTO is not zero, see XR1[5] and RTO).

##### TRI - Enable THR Ready Interrupt

`#define TRI_BIT 1`

`#define TRI_MASK 2`

If set enables THR Ready Interrupt

##### RSLI - Enable Receive Line Status Interrupt

`#define RSLI_BIT 2`

`#define RSLI_MASK 4`

If set enables Receive Line Status Interrupt

##### MSI - Enable Modem Status Interrupt

`#define MSI_BIT 3`

`#define MSI_MASK 8`

If set enables the MODEM status interrupt

### IIR - Interrupt Identification Register

`sfrb IIR = $F202;`

##### NIP - Not Interrupt Pending

`#define NIP_BIT 0`

`#define NIP_MASK 1`

If in logic b

##### ID0 - Interrupt ID Bit 0

`#define ID0_BIT 1`

`#define ID0_MASK 2`

Interrupt ID Bit 0

##### ID1 - Interrupt ID Bit 1

`#define ID1_BIT 2`

`#define ID1_MASK 4`

Interrupt ID Bit 1

##### ID2 - Interrupt ID Bit 2

`#define ID2_BIT 3`

`#define ID2_MASK 8`

Interrupt ID Bit 2

##### FIFOEN - FIFO enabled

`#define FIFOEN_BIT 6`

`#define FIFOEN_MASK 64`

These two bits are set when FCR[0] is set.

##### FIFOEN - FIFO enabled

`#define FIFOEN_BIT 7`

`#define FIFOEN_MASK 128`

These two bits are set when FCR[0] is set.

### FCR - FIFO Control Register

`sfrb FCR = $F202;`

##### FEN - FIFO Enable

`#define FEN_BIT 0`

`#define FEN_MASK 1`

When set, enables the 16 byte receive and transmit FIFOs. When cleared FIFOs are disabled and reset.

##### FRS - Rx FIFO reset

`#define FRS_BIT 1`

`#define FRS_MASK 2`

When set, resets the receive FIFO

##### TRS - Tx FIFO Reset

`#define TRS_BIT 2`

`#define TRS_MASK 4`

When set, resets the transmit FIFO.

##### RDMA - DMA Mode Select

`#define RDMA_BIT 3`

`#define RDMA_MASK 8`

When FIFOs are disabled (FCR[0] is low), this bit is forced to b

##### RCVR0 - RCVR Trigger bits

`#define RCVR0_BIT 6`

`#define RCVR0_MASK 64`

These bits indicate the minimum number of bytes required in the receive FIFO to generate a receive ready interrupt. The trigger level is shown from the following table

##### RCVR1 - RCVR Trigger bits

`#define RCVR1_BIT 7`

`#define RCVR1_MASK 128`

These bits indicate the minimum number of bytes required in the receive FIFO to generate a receive ready interrupt. The trigger level is shown from the following table

### LCR - Line Control Register

`sfrb LCR = $F203;`

##### WL1 - Word Length

`#define WL1_BIT 1`

`#define WL1_MASK 2`

These bits determine the word length

##### SB - Number of Stop bits

`#define SB_BIT 2`

`#define SB_MASK 4`

This bit determines the number of stop bits

##### ENPAR - Enable Parity

`#define ENPAR_BIT 3`

`#define ENPAR_MASK 8`

Setting this bit to logic '1' a parity bit is transmitted or checked. Resetting this bit to '0' no parity bit is transmitted or checked.

##### EVPAR - Even Parity

`#define EVPAR_BIT 4`

`#define EVPAR_MASK 16`

When the Enable Parity bit is a '1' and the Stick Parity bit is a '0', then setting to logic '1' the Even parity an even number of logic 1s is transmitted or checked in the data word bits and the Parity bit. When Even Parity bit is reset to logic '0' an odd number of 1s are transmitted or checked.When the Enable Parity bit is a '1' and the Stick Parity bit is a '0', then setting to logic '1' the Even parity an even number of logic 1s is transmitted or checked in the data word bits and the Parity bit. When Even Parity bit is reset to logic '0' an odd number of 1s are transmitted or checked.When the Enable Parity bit is a '1' and the Stick Parity bit is a '0', then setting to logic '1' the Even parity an even number of logic 1s is transmitted or checked in the data word bits and the Parity bit. When Even Parity bit is reset to logic '0' an odd number of 1s are transmitted or checked.When the Enable Parity bit is a '1' and the Stick Parity bit is a '0', then setting to logic '1' the Even parity an even number of logic 1s is transmitted or checked in the data word bits and the Parity bit. When Even Parity bit is reset to logic '0' an odd number of 1s are transmitted or checked

##### SPAR - Stick Parity

`#define SPAR_BIT 5`

`#define SPAR_MASK 32`

When the Parity Enable bit and the Parity Stick bit are set to logic '1' then the Even Parity bit controls the transmitted parity value. Resetting the Even parity bit to logic '0' then the parity bit is transmitted and checked as '1'. Setting the Even parity bit to logic '1' then the parity bit is transmitted and checked as '0'.

##### SBRK - Set Break

`#define SBRK_BIT 6`

`#define SBRK_MASK 64`

If set then it causes a break condition to to be transmitted to the receiving UART. The SOUT pin is forced to the spacing state (logic '0'). Resetting to logic '0' stops the break condition.The break control bit acts only on SOUT pin and has no effect on the transmitter logic. Note that UART waits before starting the break condition command for the complete transmission of the word in the transmit shift register. There is no need for software synchronization.

##### DLAB - Divisor Latch Register

`#define DLAB_BIT 7`

`#define DLAB_MASK 128`

It must be set to logic b

### MCR - Modem Control Register

`sfrb MCR = $F204;`

##### DTR - The compliment value of the bidirectional pin nDTR

`#define DTR_BIT 0`

`#define DTR_MASK 1`

The compliment value of the bidirectional pin nDTR

##### RTS - The compliment value of the bidirectional pin nRTS

`#define RTS_BIT 1`

`#define RTS_MASK 2`

The compliment value of the bidirectional pin nRTS

##### OUT1 - The compliment value of the bidirectional pin nOUT1

`#define OUT1_BIT 2`

`#define OUT1_MASK 4`

The compliment value of the bidirectional pin nOUT1

##### OUT2 - The compliment value of the bidirectional pin nOUT2

`#define OUT2_BIT 3`

`#define OUT2_MASK 8`

The compliment value of the bidirectional pin nOUT2

##### LB - Loop Back

`#define LB_BIT 4`

`#define LB_MASK 16`

f Set enables the loopback mode. you can not set this bit at logic b

### LSR - Line Status Register

`sfrb LSR = $F205;`

##### RDA - Receive Holding Register Ready

`#define RDA_BIT 0`

`#define RDA_MASK 1`

If set indicates that there are data available in the RHR. This bit resets to logic '0' by reading all of the data from the Receive Holding Register or the Rx FIFO.

##### OE - Overrun Error

`#define OE_BIT 1`

`#define OE_MASK 2`

If set indicates an overrun error. Indicates that data in RHR was not read by the core before the next word was transferred into the RHR, thereby destroying the previous word. In FIFO Mode an overrun error will occur only after the Rx FIFO is full and the next word has been completely received in shift register. The word in the shift register is overwritten, but it is not transferred to the Rx FIFO. Overrun error is indicated to the core as soon as it happens. This bit is reset to a logic '0' whenever the core reads the LSR

##### PE - Parity Error

`#define PE_BIT 2`

`#define PE_MASK 4`

If set indicates a parity error. Indicates that the received word in RHR does not have the correct parity bit. In FIFO mode this error is associated with the word at the top of the FIFO which is equivalent to RHR. This bit is reset to a logic '0' whenever the core reads the LSR.

##### FE - Framing Error

`#define FE_BIT 3`

`#define FE_MASK 8`

If set indicates a framing error. Indicates that the received word in RHR does not have the correct stop bit. In FIFO mode this error is associated with the word at the top of the Rx FIFO which is equivalent to RHR. This bit is reset to a logic '0' whenever the core reads the LSR.

##### BI - Receive Break Interrupt

`#define BI_BIT 4`

`#define BI_MASK 16`

If set indicates a Break Interrupt. Indicates that the receive data input is held in the spacing state (logic '0') for longer than a full word transmission time.In FIFO mode this error is associated with the word at the top of the Rx FIFO which is equivalent to RHR. This bit is reset to a logic '0' whenever the core reads the LSR.

##### THRR - Transmit Holding Register ready

`#define THRR_BIT 5`

`#define THRR_MASK 32`

If set indicates that the THR is ready to accept a new word for transmission. This bit is set when a word is transferred from the THR into the Tx shift register. This bit is reset concurrently with the loading of the THR by the core. If Tx FIFO is enabled (FCR[0]=1, XR2[7]=0), the function of this bit is controlled by XR2[4]. If XR2[4] is '0', then this bit is set when the Tx FIFO is empty; it is cleared when at least 1 word is written to the Tx FIFO. If XR2[4] is '1', then this bit is set when the TxFIFO is not full

##### TE - Transmit Empty

`#define TE_BIT 6`

`#define TE_MASK 64`

When set indicates that both the Transmit Shift Register and Transmit Holding Register, or the Tx FIFO if Tx FIFO is enabled, are empty.

##### ERF - Error in RX FIFO

`#define ERF_BIT 7`

`#define ERF_MASK 128`

If the FIFOs are disabled this bit is a '0'. If FIFOs are enabled this bit indicates that at least one word in the Rx FIFO has it's Parity Error or Framing Error or Break Indication bits high.

### MSR - Modem Status Register

`sfrb MSR = $F206;`

##### DCTS - Delta Clear to send indicator

`#define DCTS_BIT 0`

`#define DCTS_MASK 1`

##### DDSR - Delta Data Set Ready indicator

`#define DDSR_BIT 1`

`#define DDSR_MASK 2`

##### TRI - Trailing Edge of ring Indicator

`#define TRI_BIT 2`

`#define TRI_MASK 4`

##### DCD

`#define DCD_BIT 3`

`#define DCD_MASK 8`

##### CTS

`#define CTS_BIT 4`

`#define CTS_MASK 16`

##### DSR

`#define DSR_BIT 5`

`#define DSR_MASK 32`

##### RI

`#define RI_BIT 6`

`#define RI_MASK 64`

##### CD

`#define CD_BIT 7`

`#define CD_MASK 128`

### SCR - Scratch patch register

`sfrb SCR = $F207;`

##### SCR0

`#define SCR0_BIT 0`

`#define SCR0_MASK 1`

##### SCR1

`#define SCR1_BIT 1`

`#define SCR1_MASK 2`

##### SCR2

`#define SCR2_BIT 2`

`#define SCR2_MASK 4`

##### SCR3

`#define SCR3_BIT 3`

`#define SCR3_MASK 8`

##### SCR4

`#define SCR4_BIT 4`

`#define SCR4_MASK 16`

##### SCR5

`#define SCR5_BIT 5`

`#define SCR5_MASK 32`

##### SCR6

`#define SCR6_BIT 6`

`#define SCR6_MASK 64`

##### SCR7

`#define SCR7_BIT 7`

`#define SCR7_MASK 128`

### DLL - Divisor Latch Register Low Byte

`sfrb DLL = $F200;`

##### DLL0

`#define DLL0_BIT 0`

`#define DLL0_MASK 1`

##### DLL1

`#define DLL1_BIT 1`

`#define DLL1_MASK 2`

##### DLL2

`#define DLL2_BIT 2`

`#define DLL2_MASK 4`

##### DLL3

`#define DLL3_BIT 3`

`#define DLL3_MASK 8`

##### DLL4

`#define DLL4_BIT 4`

`#define DLL4_MASK 16`

##### DLL5

`#define DLL5_BIT 5`

`#define DLL5_MASK 32`

##### DLL6

`#define DLL6_BIT 6`

`#define DLL6_MASK 64`

##### DLL7

`#define DLL7_BIT 7`

`#define DLL7_MASK 128`

### DLL - Divisor Latch Register High Byte

`sfrb DLL = $F201;`

##### DLH0

`#define DLH0_BIT 0`

`#define DLH0_MASK 1`

##### DLH1

`#define DLH1_BIT 1`

`#define DLH1_MASK 2`

##### DLH2

`#define DLH2_BIT 2`

`#define DLH2_MASK 4`

##### DLH3

`#define DLH3_BIT 3`

`#define DLH3_MASK 8`

##### DLH4

`#define DLH4_BIT 4`

`#define DLH4_MASK 16`

##### DLH5

`#define DLH5_BIT 5`

`#define DLH5_MASK 32`

##### DLH6

`#define DLH6_BIT 6`

`#define DLH6_MASK 64`

##### DLH7

`#define DLH7_BIT 7`

`#define DLH7_MASK 128`

### XR1 - Extra register 1

`sfrb XR1 = $F208;`

##### RXDIS - Rx Disable

`#define RXDIS_BIT 0`

`#define RXDIS_MASK 1`

##### TXDIS - Tx Disable

`#define TXDIS_BIT 1`

`#define TXDIS_MASK 2`

##### RXR - Rx Reset

`#define RXR_BIT 2`

`#define RXR_MASK 4`

##### TXR - Tx Reset

`#define TXR_BIT 3`

`#define TXR_MASK 8`

##### RTO - Restart Time out

`#define RTO_BIT 4`

`#define RTO_MASK 16`

##### STOC - Start Time out control

`#define STOC_BIT 5`

`#define STOC_MASK 32`

##### SA - Send Address

`#define SA_BIT 6`

`#define SA_MASK 64`

##### OPL - Output Pins in loopback

`#define OPL_BIT 7`

`#define OPL_MASK 128`

### XR2 - Extra register 2

`sfrb XR2 = $F209;`

##### MDM - Multi Drop Mode

`#define MDM_BIT 0`

`#define MDM_MASK 1`

##### THRRC - THR ready bit Control

`#define THRRC_BIT 4`

`#define THRRC_MASK 16`

##### THRR - THR Ready

`#define THRR_BIT 5`

`#define THRR_MASK 32`

##### TE - Transmitter Empty

`#define TE_BIT 6`

`#define TE_MASK 64`

##### TxFD - Tx FIFO disable

`#define TxFD_BIT 7`

`#define TxFD_MASK 128`

### MDR - Modem Direction Register

`sfrb MDR = $F20A;`

##### DTRD - DTRD pin direction

`#define DTRD_BIT 0`

`#define DTRD_MASK 1`

##### RTSD - RTSD pin direction

`#define RTSD_BIT 1`

`#define RTSD_MASK 2`

##### OUT1D - OUT1D pin Direction

`#define OUT1D_BIT 2`

`#define OUT1D_MASK 4`

##### OUT2D - OUT2D pin direction

`#define OUT2D_BIT 3`

`#define OUT2D_MASK 8`

##### CTSD - CTSD pin direction

`#define CTSD_BIT 4`

`#define CTSD_MASK 16`

##### DSRD - DSRD Pin direction

`#define DSRD_BIT 5`

`#define DSRD_MASK 32`

##### RID - RID pin Direction

`#define RID_BIT 6`

`#define RID_MASK 64`

##### CDD - CD pin Direction

`#define CDD_BIT 7`

`#define CDD_MASK 128`

### RTO - Receiver Time-Out Register

`sfrb RTO = $F20B;`

##### RTO0

`#define RTO0_BIT 0`

`#define RTO0_MASK 1`

##### RTO1

`#define RTO1_BIT 1`

`#define RTO1_MASK 2`

##### RTO2

`#define RTO2_BIT 2`

`#define RTO2_MASK 4`

##### RTO3

`#define RTO3_BIT 3`

`#define RTO3_MASK 8`

##### RTO4

`#define RTO4_BIT 4`

`#define RTO4_MASK 16`

##### RTO5

`#define RTO5_BIT 5`

`#define RTO5_MASK 32`

##### RTO6

`#define RTO6_BIT 6`

`#define RTO6_MASK 64`

##### RTO7

`#define RTO7_BIT 7`

`#define RTO7_MASK 128`

### TTG - Transmitter Time Guard register

`sfrb TTG = $F20C;`

##### TTG0

`#define TTG0_BIT 0`

`#define TTG0_MASK 1`

##### TTG1

`#define TTG1_BIT 1`

`#define TTG1_MASK 2`

##### TTG2

`#define TTG2_BIT 2`

`#define TTG2_MASK 4`

##### TTG3

`#define TTG3_BIT 3`

`#define TTG3_MASK 8`

##### TTG4

`#define TTG4_BIT 4`

`#define TTG4_MASK 16`

##### TTG5

`#define TTG5_BIT 5`

`#define TTG5_MASK 32`

##### TTG6

`#define TTG6_BIT 6`

`#define TTG6_MASK 64`

##### TTG7

`#define TTG7_BIT 7`

`#define TTG7_MASK 128`

## UART1

The base address for UART0 registers is $F200 and for UART1 registers is $F300. Each read or write access of UART registers consumes at least 2 CPU cycles, since the UART core clock is asynchronous and fixed to 14.769MHz.

### HR - Receive/Transmit Holding Register

`sfrb HR = $F300;`

##### HR0

`#define HR0_BIT 0`

`#define HR0_MASK 1`

##### HR1

`#define HR1_BIT 1`

`#define HR1_MASK 2`

##### HR2

`#define HR2_BIT 2`

`#define HR2_MASK 4`

##### HR3

`#define HR3_BIT 3`

`#define HR3_MASK 8`

##### HR4

`#define HR4_BIT 4`

`#define HR4_MASK 16`

##### HR5

`#define HR5_BIT 5`

`#define HR5_MASK 32`

##### HR6

`#define HR6_BIT 6`

`#define HR6_MASK 64`

##### HR7

`#define HR7_BIT 7`

`#define HR7_MASK 128`

### IER - Interrupt Enable Register

`sfrb IER = $F301;`

##### RDAI - Enable RX Data Available Interrupt

`#define RDAI_BIT 0`

`#define RDAI_MASK 1`

If set enables the Rx data available interrupt. Also enables and the time-out interrupt when time-out counter is enabled (in FIFO mode or if RTO is not zero, see XR1[5] and RTO).

##### TRI - Enable THR Ready Interrupt

`#define TRI_BIT 1`

`#define TRI_MASK 2`

If set enables THR Ready Interrupt

##### RSLI - Enable Receive Line Status Interrupt

`#define RSLI_BIT 2`

`#define RSLI_MASK 4`

If set enables Receive Line Status Interrupt

##### MSI - Enable Modem Status Interrupt

`#define MSI_BIT 3`

`#define MSI_MASK 8`

If set enables the MODEM status interrupt

### IIR - Interrupt Identification Register

`sfrb IIR = $F302;`

##### NIP - Not Interrupt Pending

`#define NIP_BIT 0`

`#define NIP_MASK 1`

If in logic b

##### ID0 - Interrupt ID Bit 0

`#define ID0_BIT 1`

`#define ID0_MASK 2`

Interrupt ID Bit 0

##### ID1 - Interrupt ID Bit 1

`#define ID1_BIT 2`

`#define ID1_MASK 4`

Interrupt ID Bit 1

##### ID2 - Interrupt ID Bit 2

`#define ID2_BIT 3`

`#define ID2_MASK 8`

Interrupt ID Bit 2

##### FIFOEN - FIFO enabled

`#define FIFOEN_BIT 6`

`#define FIFOEN_MASK 64`

These two bits are set when FCR[0] is set.

##### FIFOEN - FIFO enabled

`#define FIFOEN_BIT 7`

`#define FIFOEN_MASK 128`

These two bits are set when FCR[0] is set.

### FCR - FIFO Control Register

`sfrb FCR = $F302;`

##### FEN - FIFO Enable

`#define FEN_BIT 0`

`#define FEN_MASK 1`

When set, enables the 16 byte receive and transmit FIFOs. When cleared FIFOs are disabled and reset.

##### FRS - Rx FIFO reset

`#define FRS_BIT 1`

`#define FRS_MASK 2`

When set, resets the receive FIFO

##### TRS - Tx FIFO Reset

`#define TRS_BIT 2`

`#define TRS_MASK 4`

When set, resets the transmit FIFO.

##### RDMA - DMA Mode Select

`#define RDMA_BIT 3`

`#define RDMA_MASK 8`

When FIFOs are disabled (FCR[0] is low), this bit is forced to b

##### RCVR0 - RCVR Trigger bits

`#define RCVR0_BIT 6`

`#define RCVR0_MASK 64`

These bits indicate the minimum number of bytes required in the receive FIFO to generate a receive ready interrupt. The trigger level is shown from the following table

##### RCVR1 - RCVR Trigger bits

`#define RCVR1_BIT 7`

`#define RCVR1_MASK 128`

These bits indicate the minimum number of bytes required in the receive FIFO to generate a receive ready interrupt. The trigger level is shown from the following table

### LCR - Line Control Register

`sfrb LCR = $F303;`

##### WL1 - Word Length

`#define WL1_BIT 1`

`#define WL1_MASK 2`

These bits determine the word length

##### SB - Number of Stop bits

`#define SB_BIT 2`

`#define SB_MASK 4`

This bit determines the number of stop bits

##### ENPAR - Enable Parity

`#define ENPAR_BIT 3`

`#define ENPAR_MASK 8`

Setting this bit to logic '1' a parity bit is transmitted or checked. Resetting this bit to '0' no parity bit is transmitted or checked.

##### EVPAR - Even Parity

`#define EVPAR_BIT 4`

`#define EVPAR_MASK 16`

When the Enable Parity bit is a '1' and the Stick Parity bit is a '0', then setting to logic '1' the Even parity an even number of logic 1s is transmitted or checked in the data word bits and the Parity bit. When Even Parity bit is reset to logic '0' an odd number of 1s are transmitted or checked.When the Enable Parity bit is a '1' and the Stick Parity bit is a '0', then setting to logic '1' the Even parity an even number of logic 1s is transmitted or checked in the data word bits and the Parity bit. When Even Parity bit is reset to logic '0' an odd number of 1s are transmitted or checked.When the Enable Parity bit is a '1' and the Stick Parity bit is a '0', then setting to logic '1' the Even parity an even number of logic 1s is transmitted or checked in the data word bits and the Parity bit. When Even Parity bit is reset to logic '0' an odd number of 1s are transmitted or checked.When the Enable Parity bit is a '1' and the Stick Parity bit is a '0', then setting to logic '1' the Even parity an even number of logic 1s is transmitted or checked in the data word bits and the Parity bit. When Even Parity bit is reset to logic '0' an odd number of 1s are transmitted or checked

##### SPAR - Stick Parity

`#define SPAR_BIT 5`

`#define SPAR_MASK 32`

When the Parity Enable bit and the Parity Stick bit are set to logic '1' then the Even Parity bit controls the transmitted parity value. Resetting the Even parity bit to logic '0' then the parity bit is transmitted and checked as '1'. Setting the Even parity bit to logic '1' then the parity bit is transmitted and checked as '0'.

##### SBRK - Set Break

`#define SBRK_BIT 6`

`#define SBRK_MASK 64`

If set then it causes a break condition to to be transmitted to the receiving UART. The SOUT pin is forced to the spacing state (logic '0'). Resetting to logic '0' stops the break condition.The break control bit acts only on SOUT pin and has no effect on the transmitter logic. Note that UART waits before starting the break condition command for the complete transmission of the word in the transmit shift register. There is no need for software synchronization.

##### DLAB - Divisor Latch Register

`#define DLAB_BIT 7`

`#define DLAB_MASK 128`

It must be set to logic b

### MCR - Modem Control Register

`sfrb MCR = $F304;`

##### DTR - The compliment value of the bidirectional pin nDTR

`#define DTR_BIT 0`

`#define DTR_MASK 1`

The compliment value of the bidirectional pin nDTR

##### RTS - The compliment value of the bidirectional pin nRTS

`#define RTS_BIT 1`

`#define RTS_MASK 2`

The compliment value of the bidirectional pin nRTS

##### OUT1 - The compliment value of the bidirectional pin nOUT1

`#define OUT1_BIT 2`

`#define OUT1_MASK 4`

The compliment value of the bidirectional pin nOUT1

##### OUT2 - The compliment value of the bidirectional pin nOUT2

`#define OUT2_BIT 3`

`#define OUT2_MASK 8`

The compliment value of the bidirectional pin nOUT2

##### LB - Loop Back

`#define LB_BIT 4`

`#define LB_MASK 16`

f Set enables the loopback mode. you can not set this bit at logic b

### LSR - Line Status Register

`sfrb LSR = $F305;`

##### RDA - Receive Holding Register Ready

`#define RDA_BIT 0`

`#define RDA_MASK 1`

If set indicates that there are data available in the RHR. This bit resets to logic '0' by reading all of the data from the Receive Holding Register or the Rx FIFO.

##### OE - Overrun Error

`#define OE_BIT 1`

`#define OE_MASK 2`

If set indicates an overrun error. Indicates that data in RHR was not read by the core before the next word was transferred into the RHR, thereby destroying the previous word. In FIFO Mode an overrun error will occur only after the Rx FIFO is full and the next word has been completely received in shift register. The word in the shift register is overwritten, but it is not transferred to the Rx FIFO. Overrun error is indicated to the core as soon as it happens. This bit is reset to a logic '0' whenever the core reads the LSR

##### PE - Parity Error

`#define PE_BIT 2`

`#define PE_MASK 4`

If set indicates a parity error. Indicates that the received word in RHR does not have the correct parity bit. In FIFO mode this error is associated with the word at the top of the FIFO which is equivalent to RHR. This bit is reset to a logic '0' whenever the core reads the LSR.

##### FE - Framing Error

`#define FE_BIT 3`

`#define FE_MASK 8`

If set indicates a framing error. Indicates that the received word in RHR does not have the correct stop bit. In FIFO mode this error is associated with the word at the top of the Rx FIFO which is equivalent to RHR. This bit is reset to a logic '0' whenever the core reads the LSR.

##### BI - Receive Break Interrupt

`#define BI_BIT 4`

`#define BI_MASK 16`

If set indicates a Break Interrupt. Indicates that the receive data input is held in the spacing state (logic '0') for longer than a full word transmission time.In FIFO mode this error is associated with the word at the top of the Rx FIFO which is equivalent to RHR. This bit is reset to a logic '0' whenever the core reads the LSR.

##### THRR - Transmit Holding Register ready

`#define THRR_BIT 5`

`#define THRR_MASK 32`

If set indicates that the THR is ready to accept a new word for transmission. This bit is set when a word is transferred from the THR into the Tx shift register. This bit is reset concurrently with the loading of the THR by the core. If Tx FIFO is enabled (FCR[0]=1, XR2[7]=0), the function of this bit is controlled by XR2[4]. If XR2[4] is '0', then this bit is set when the Tx FIFO is empty; it is cleared when at least 1 word is written to the Tx FIFO. If XR2[4] is '1', then this bit is set when the TxFIFO is not full

##### TE - Transmit Empty

`#define TE_BIT 6`

`#define TE_MASK 64`

When set indicates that both the Transmit Shift Register and Transmit Holding Register, or the Tx FIFO if Tx FIFO is enabled, are empty.

##### ERF - Error in RX FIFO

`#define ERF_BIT 7`

`#define ERF_MASK 128`

If the FIFOs are disabled this bit is a '0'. If FIFOs are enabled this bit indicates that at least one word in the Rx FIFO has it's Parity Error or Framing Error or Break Indication bits high.

### MSR - Modem Status Register

`sfrb MSR = $F306;`

##### DCTS - Delta Clear to send indicator

`#define DCTS_BIT 0`

`#define DCTS_MASK 1`

##### DDSR - Delta Data Set Ready indicator

`#define DDSR_BIT 1`

`#define DDSR_MASK 2`

##### TRI - Trailing Edge of ring Indicator

`#define TRI_BIT 2`

`#define TRI_MASK 4`

##### DCD

`#define DCD_BIT 3`

`#define DCD_MASK 8`

##### CTS

`#define CTS_BIT 4`

`#define CTS_MASK 16`

##### DSR

`#define DSR_BIT 5`

`#define DSR_MASK 32`

##### RI

`#define RI_BIT 6`

`#define RI_MASK 64`

##### CD

`#define CD_BIT 7`

`#define CD_MASK 128`

### SCR - Scratch patch register

`sfrb SCR = $F307;`

##### SCR0

`#define SCR0_BIT 0`

`#define SCR0_MASK 1`

##### SCR1

`#define SCR1_BIT 1`

`#define SCR1_MASK 2`

##### SCR2

`#define SCR2_BIT 2`

`#define SCR2_MASK 4`

##### SCR3

`#define SCR3_BIT 3`

`#define SCR3_MASK 8`

##### SCR4

`#define SCR4_BIT 4`

`#define SCR4_MASK 16`

##### SCR5

`#define SCR5_BIT 5`

`#define SCR5_MASK 32`

##### SCR6

`#define SCR6_BIT 6`

`#define SCR6_MASK 64`

##### SCR7

`#define SCR7_BIT 7`

`#define SCR7_MASK 128`

### DLL - Divisor Latch Register Low Byte

`sfrb DLL = $F300;`

##### DLL0

`#define DLL0_BIT 0`

`#define DLL0_MASK 1`

##### DLL1

`#define DLL1_BIT 1`

`#define DLL1_MASK 2`

##### DLL2

`#define DLL2_BIT 2`

`#define DLL2_MASK 4`

##### DLL3

`#define DLL3_BIT 3`

`#define DLL3_MASK 8`

##### DLL4

`#define DLL4_BIT 4`

`#define DLL4_MASK 16`

##### DLL5

`#define DLL5_BIT 5`

`#define DLL5_MASK 32`

##### DLL6

`#define DLL6_BIT 6`

`#define DLL6_MASK 64`

##### DLL7

`#define DLL7_BIT 7`

`#define DLL7_MASK 128`

### DLL - Divisor Latch Register High Byte

`sfrb DLL = $F301;`

##### DLH0

`#define DLH0_BIT 0`

`#define DLH0_MASK 1`

##### DLH1

`#define DLH1_BIT 1`

`#define DLH1_MASK 2`

##### DLH2

`#define DLH2_BIT 2`

`#define DLH2_MASK 4`

##### DLH3

`#define DLH3_BIT 3`

`#define DLH3_MASK 8`

##### DLH4

`#define DLH4_BIT 4`

`#define DLH4_MASK 16`

##### DLH5

`#define DLH5_BIT 5`

`#define DLH5_MASK 32`

##### DLH6

`#define DLH6_BIT 6`

`#define DLH6_MASK 64`

##### DLH7

`#define DLH7_BIT 7`

`#define DLH7_MASK 128`

### XR1 - Extra register 1

`sfrb XR1 = $F308;`

##### RXDIS - Rx Disable

`#define RXDIS_BIT 0`

`#define RXDIS_MASK 1`

##### TXDIS - Tx Disable

`#define TXDIS_BIT 1`

`#define TXDIS_MASK 2`

##### RXR - Rx Reset

`#define RXR_BIT 2`

`#define RXR_MASK 4`

##### TXR - Tx Reset

`#define TXR_BIT 3`

`#define TXR_MASK 8`

##### RTO - Restart Time out

`#define RTO_BIT 4`

`#define RTO_MASK 16`

##### STOC - Start Time out control

`#define STOC_BIT 5`

`#define STOC_MASK 32`

##### SA - Send Address

`#define SA_BIT 6`

`#define SA_MASK 64`

##### OPL - Output Pins in loopback

`#define OPL_BIT 7`

`#define OPL_MASK 128`

### XR2 - Extra register 2

`sfrb XR2 = $F309;`

##### MDM - Multi Drop Mode

`#define MDM_BIT 0`

`#define MDM_MASK 1`

##### THRRC - THR ready bit Control

`#define THRRC_BIT 4`

`#define THRRC_MASK 16`

##### THRR - THR Ready

`#define THRR_BIT 5`

`#define THRR_MASK 32`

##### TE - Transmitter Empty

`#define TE_BIT 6`

`#define TE_MASK 64`

##### TxFD - Tx FIFO disable

`#define TxFD_BIT 7`

`#define TxFD_MASK 128`

### MDR - Modem Direction Register

`sfrb MDR = $F30A;`

##### DTRD - DTRD pin direction

`#define DTRD_BIT 0`

`#define DTRD_MASK 1`

##### RTSD - RTSD pin direction

`#define RTSD_BIT 1`

`#define RTSD_MASK 2`

##### OUT1D - OUT1D pin Direction

`#define OUT1D_BIT 2`

`#define OUT1D_MASK 4`

##### OUT2D - OUT2D pin direction

`#define OUT2D_BIT 3`

`#define OUT2D_MASK 8`

##### CTSD - CTSD pin direction

`#define CTSD_BIT 4`

`#define CTSD_MASK 16`

##### DSRD - DSRD Pin direction

`#define DSRD_BIT 5`

`#define DSRD_MASK 32`

##### RID - RID pin Direction

`#define RID_BIT 6`

`#define RID_MASK 64`

##### CDD - CD pin Direction

`#define CDD_BIT 7`

`#define CDD_MASK 128`

### RTO - Receiver Time-Out Register

`sfrb RTO = $F30B;`

##### RTO0

`#define RTO0_BIT 0`

`#define RTO0_MASK 1`

##### RTO1

`#define RTO1_BIT 1`

`#define RTO1_MASK 2`

##### RTO2

`#define RTO2_BIT 2`

`#define RTO2_MASK 4`

##### RTO3

`#define RTO3_BIT 3`

`#define RTO3_MASK 8`

##### RTO4

`#define RTO4_BIT 4`

`#define RTO4_MASK 16`

##### RTO5

`#define RTO5_BIT 5`

`#define RTO5_MASK 32`

##### RTO6

`#define RTO6_BIT 6`

`#define RTO6_MASK 64`

##### RTO7

`#define RTO7_BIT 7`

`#define RTO7_MASK 128`

### TTG - Transmitter Time Guard register

`sfrb TTG = $F30C;`

##### TTG0

`#define TTG0_BIT 0`

`#define TTG0_MASK 1`

##### TTG1

`#define TTG1_BIT 1`

`#define TTG1_MASK 2`

##### TTG2

`#define TTG2_BIT 2`

`#define TTG2_MASK 4`

##### TTG3

`#define TTG3_BIT 3`

`#define TTG3_MASK 8`

##### TTG4

`#define TTG4_BIT 4`

`#define TTG4_MASK 16`

##### TTG5

`#define TTG5_BIT 5`

`#define TTG5_MASK 32`

##### TTG6

`#define TTG6_BIT 6`

`#define TTG6_MASK 64`

##### TTG7

`#define TTG7_BIT 7`

`#define TTG7_MASK 128`

## USB

### SLP_MODE - Sleep Mode Control Register

`sfrb SLP_MODE = $F000;`

##### SLP

`#define SLP_BIT 5`

`#define SLP_MASK 32`

If set, puts the USB Controller in sleep Mode

### IRQ_EN - USB Interrupt Mask Register

`sfrb IRQ_EN = $F001;`

##### RSM_INT_EN

`#define RSM_INT_EN_BIT 0`

`#define RSM_INT_EN_MASK 1`

If this bit is high, an interrupt is generated when the USB enters resume mode. A J-to-K state change on the USB port signal resume.

##### SUSP_INT_EN

`#define SUSP_INT_EN_BIT 1`

`#define SUSP_INT_EN_MASK 2`

If this bit is high, an interrupt is generated when the USB enters suspend mode. A USB device enters in suspend mode only when requested by the USB host through bus inactivity for at least 3ms.

##### INT_EN

`#define INT_EN_BIT 6`

`#define INT_EN_MASK 64`

When thsi bit is high, enables the USB protocol handler to cause Interrupt.

### IRQ_STAT - USB Interrupt status register

`sfrb IRQ_STAT = $F002;`

##### RSM

`#define RSM_BIT 0`

`#define RSM_MASK 1`

When this bit is high, the USB has entered the resume state.

##### SUSP

`#define SUSP_BIT 1`

`#define SUSP_MASK 2`

When this bit is high, the USB has entered the suspend mode.

##### INT

`#define INT_BIT 6`

`#define INT_MASK 64`

Interrupt from the USB protocol handler. When this bit is high, then at least one bit of UISR is set.

### RES_STAT - Reset Status

`sfrb RES_STAT = $F003;`

##### USB_RES

`#define USB_RES_BIT 3`

`#define USB_RES_MASK 8`

Set when USB enters reset State

### PAIR_EN - Pair Addressing Enable

`sfrb PAIR_EN = $F004;`

##### UPA1 - By setting any of these bits, a pair of EPs is formed of oneIN and one OUT. For example, if UPA[1] is set, the EP1 should be configured as an OUT EP, while the EP4 as an IN EP

`#define UPA1_BIT 1`

`#define UPA1_MASK 2`

UPA[1]: EP4 has the same USB physical address with EP1

##### UPA2 - By setting any of these bits, a pair of EPs is formed of oneIN and one OUT. For example, if UPA[1] is set, the EP1 should be configured as an OUT EP, while the EP4 as an IN EP

`#define UPA2_BIT 2`

`#define UPA2_MASK 4`

UPA[2]: EP4 has the same USB physical address with EP2

##### UPA3 - By setting any of these bits, a pair of EPs is formed of oneIN and one OUT. For example, if UPA[1] is set, the EP1 should be configured as an OUT EP, while the EP4 as an IN EP

`#define UPA3_BIT 3`

`#define UPA3_MASK 8`

UPA[3]: EP4 has the same USB physical address with EP3

### USB_DMA_ADL - DMA Address Low

`sfrb USB_DMA_ADL = $F005;`

##### UDA0

`#define UDA0_BIT 0`

`#define UDA0_MASK 1`

##### UDA1

`#define UDA1_BIT 1`

`#define UDA1_MASK 2`

##### UDA2

`#define UDA2_BIT 2`

`#define UDA2_MASK 4`

##### UDA3

`#define UDA3_BIT 3`

`#define UDA3_MASK 8`

##### UDA4

`#define UDA4_BIT 4`

`#define UDA4_MASK 16`

##### UDA5

`#define UDA5_BIT 5`

`#define UDA5_MASK 32`

##### UDA6

`#define UDA6_BIT 6`

`#define UDA6_MASK 64`

##### UDA7

`#define UDA7_BIT 7`

`#define UDA7_MASK 128`

### USB_DMA_ADH - DMA Address High

`sfrb USB_DMA_ADH = $F006;`

##### UDA8

`#define UDA8_BIT 1`

`#define UDA8_MASK 2`

##### UDA9

`#define UDA9_BIT 2`

`#define UDA9_MASK 4`

##### UDA10

`#define UDA10_BIT 3`

`#define UDA10_MASK 8`

##### UDA11

`#define UDA11_BIT 4`

`#define UDA11_MASK 16`

##### UDA12

`#define UDA12_BIT 5`

`#define UDA12_MASK 32`

##### UDA13

`#define UDA13_BIT 6`

`#define UDA13_MASK 64`

##### UDA14

`#define UDA14_BIT 7`

`#define UDA14_MASK 128`

### USB_DMA_LEN - DMA Packet length

`sfrb USB_DMA_LEN = $F007;`

##### PLEN0

`#define PLEN0_BIT 0`

`#define PLEN0_MASK 1`

##### PLEN1

`#define PLEN1_BIT 1`

`#define PLEN1_MASK 2`

##### PLEN2

`#define PLEN2_BIT 2`

`#define PLEN2_MASK 4`

##### PLEN3

`#define PLEN3_BIT 3`

`#define PLEN3_MASK 8`

##### PLEN4

`#define PLEN4_BIT 4`

`#define PLEN4_MASK 16`

##### PLEN5

`#define PLEN5_BIT 5`

`#define PLEN5_MASK 32`

##### PLEN6

`#define PLEN6_BIT 6`

`#define PLEN6_MASK 64`

##### PLEN7

`#define PLEN7_BIT 7`

`#define PLEN7_MASK 128`

### USB_DMA_EAD - DMA target endpoint Address

`sfrb USB_DMA_EAD = $F008;`

##### EAD0

`#define EAD0_BIT 0`

`#define EAD0_MASK 1`

##### EAD1

`#define EAD1_BIT 1`

`#define EAD1_MASK 2`

##### EAD2

`#define EAD2_BIT 2`

`#define EAD2_MASK 4`

##### EAD3

`#define EAD3_BIT 3`

`#define EAD3_MASK 8`

##### EAD4

`#define EAD4_BIT 4`

`#define EAD4_MASK 16`

##### EAD5

`#define EAD5_BIT 5`

`#define EAD5_MASK 32`

##### EAD6

`#define EAD6_BIT 6`

`#define EAD6_MASK 64`

##### EAD7

`#define EAD7_BIT 7`

`#define EAD7_MASK 128`

### USB_DMA_PLT - DMA Packet Length transferred durring the last DMA

`sfrb USB_DMA_PLT = $F009;`

##### TPL0

`#define TPL0_BIT 0`

`#define TPL0_MASK 1`

##### TPL1

`#define TPL1_BIT 1`

`#define TPL1_MASK 2`

##### TPL2

`#define TPL2_BIT 2`

`#define TPL2_MASK 4`

##### TPL3

`#define TPL3_BIT 3`

`#define TPL3_MASK 8`

##### TPL4

`#define TPL4_BIT 4`

`#define TPL4_MASK 16`

##### TPL5

`#define TPL5_BIT 5`

`#define TPL5_MASK 32`

##### TPL6

`#define TPL6_BIT 6`

`#define TPL6_MASK 64`

##### TPL7

`#define TPL7_BIT 7`

`#define TPL7_MASK 128`

### USB_DMA_EN - DMA Enable register

`sfrb USB_DMA_EN = $F00A;`

##### USB_TDMA_EN

`#define USB_TDMA_EN_BIT 0`

`#define USB_TDMA_EN_MASK 1`

Enables Transmit DMA (for IN EPs). This bit is automatically cleared after the end of the DMA.

##### USB_RDMA_EN

`#define USB_RDMA_EN_BIT 1`

`#define USB_RDMA_EN_MASK 2`

Enables Receive DMA (for OUT EPs). This bit is automatically cleared after the end of the DMA.

### FBYTE_CNT7_H - FIFO Byte Count 7 Register

`sfrb FBYTE_CNT7_H = $F0A8;`

##### BYTECNT8 - Length of data packet in FIFO (bit 8)

`#define BYTECNT8_BIT 0`

`#define BYTECNT8_MASK 1`

##### BYTECNT9 - Length of data packet in FIFO (bit 9)

`#define BYTECNT9_BIT 1`

`#define BYTECNT9_MASK 2`

##### BYTECNT10 - Length of data packet in FIFO (bit 10)

`#define BYTECNT10_BIT 2`

`#define BYTECNT10_MASK 4`

### FBYTE_CNT6_H - FIFO Byte Count 6 Register

`sfrb FBYTE_CNT6_H = $F0A9;`

##### BYTECNT8 - Length of data packet in FIFO (bit 8)

`#define BYTECNT8_BIT 0`

`#define BYTECNT8_MASK 1`

##### BYTECNT9 - Length of data packet in FIFO (bit 9)

`#define BYTECNT9_BIT 1`

`#define BYTECNT9_MASK 2`

##### BYTECNT10 - Length of data packet in FIFO (bit 10)

`#define BYTECNT10_BIT 2`

`#define BYTECNT10_MASK 4`

### FBYTE_CNT5_H - FIFO Byte Count 5 Register

`sfrb FBYTE_CNT5_H = $F0AA;`

##### BYTECNT8 - Length of data packet in FIFO (bit 8)

`#define BYTECNT8_BIT 0`

`#define BYTECNT8_MASK 1`

##### BYTECNT9 - Length of data packet in FIFO (bit 9)

`#define BYTECNT9_BIT 1`

`#define BYTECNT9_MASK 2`

##### BYTECNT10 - Length of data packet in FIFO (bit 10)

`#define BYTECNT10_BIT 2`

`#define BYTECNT10_MASK 4`

### FBYTE_CNT4_H - FIFO Byte Count 4 Register

`sfrb FBYTE_CNT4_H = $F0AB;`

##### BYTECNT8 - Length of data packet in FIFO (bit 8)

`#define BYTECNT8_BIT 0`

`#define BYTECNT8_MASK 1`

##### BYTECNT9 - Length of data packet in FIFO (bit 9)

`#define BYTECNT9_BIT 1`

`#define BYTECNT9_MASK 2`

##### BYTECNT10 - Length of data packet in FIFO (bit 10)

`#define BYTECNT10_BIT 2`

`#define BYTECNT10_MASK 4`

### FBYTE_CNT3_H - FIFO Byte Count 3 Register

`sfrb FBYTE_CNT3_H = $F0AC;`

##### BYTECNT8 - Length of data packet in FIFO (bit 8)

`#define BYTECNT8_BIT 0`

`#define BYTECNT8_MASK 1`

##### BYTECNT9 - Length of data packet in FIFO (bit 9)

`#define BYTECNT9_BIT 1`

`#define BYTECNT9_MASK 2`

##### BYTECNT10 - Length of data packet in FIFO (bit 10)

`#define BYTECNT10_BIT 2`

`#define BYTECNT10_MASK 4`

### FBYTE_CNT2_H - FIFO Byte Count 2 Register

`sfrb FBYTE_CNT2_H = $F0AD;`

##### BYTECNT8 - Length of data packet in FIFO (bit 8)

`#define BYTECNT8_BIT 0`

`#define BYTECNT8_MASK 1`

##### BYTECNT9 - Length of data packet in FIFO (bit 9)

`#define BYTECNT9_BIT 1`

`#define BYTECNT9_MASK 2`

##### BYTECNT10 - Length of data packet in FIFO (bit 10)

`#define BYTECNT10_BIT 2`

`#define BYTECNT10_MASK 4`

### FBYTE_CNT1_H - FIFO Byte Count 1 Register

`sfrb FBYTE_CNT1_H = $F0AE;`

##### BYTECNT8 - Length of data packet in FIFO (bit 8)

`#define BYTECNT8_BIT 0`

`#define BYTECNT8_MASK 1`

##### BYTECNT9 - Length of data packet in FIFO (bit 9)

`#define BYTECNT9_BIT 1`

`#define BYTECNT9_MASK 2`

##### BYTECNT10 - Length of data packet in FIFO (bit 10)

`#define BYTECNT10_BIT 2`

`#define BYTECNT10_MASK 4`

### FBYTE_CNT0_H - FIFO Byte Count 0 Register

`sfrb FBYTE_CNT0_H = $F0AF;`

##### BYTECNT8 - Length of data packet in FIFO (bit 8)

`#define BYTECNT8_BIT 0`

`#define BYTECNT8_MASK 1`

##### BYTECNT9 - Length of data packet in FIFO (bit 9)

`#define BYTECNT9_BIT 1`

`#define BYTECNT9_MASK 2`

##### BYTECNT10 - Length of data packet in FIFO (bit 10)

`#define BYTECNT10_BIT 2`

`#define BYTECNT10_MASK 4`

### FBYTE_CNT7_L - FIFO Byte Count Low 7 Register

`sfrb FBYTE_CNT7_L = $F0B8;`

##### BYTECNT0 - Length of data packet in FIFO. (bit 0)

`#define BYTECNT0_BIT 0`

`#define BYTECNT0_MASK 1`

##### BYTECNT1 - Length of data packet in FIFO. (bit 1)

`#define BYTECNT1_BIT 1`

`#define BYTECNT1_MASK 2`

##### BYTECNT2 - Length of data packet in FIFO. (bit 2)

`#define BYTECNT2_BIT 2`

`#define BYTECNT2_MASK 4`

##### BYTECNT3 - Length of data packet in FIFO. (bit 3)

`#define BYTECNT3_BIT 3`

`#define BYTECNT3_MASK 8`

##### BYTECNT4 - Length of data packet in FIFO. (bit 4)

`#define BYTECNT4_BIT 4`

`#define BYTECNT4_MASK 16`

##### BYTECNT5 - Length of data packet in FIFO. (bit 5)

`#define BYTECNT5_BIT 5`

`#define BYTECNT5_MASK 32`

##### BYTECNT6 - Length of data packet in FIFO. (bit 6)

`#define BYTECNT6_BIT 6`

`#define BYTECNT6_MASK 64`

##### BYTECNT7 - Length of data packet in FIFO. (bit 7)

`#define BYTECNT7_BIT 7`

`#define BYTECNT7_MASK 128`

### FBYTE_CNT6_L - FIFO Byte Count Low 6 Register

`sfrb FBYTE_CNT6_L = $F0B9;`

##### BYTECNT0 - Length of data packet in FIFO. (bit 0)

`#define BYTECNT0_BIT 0`

`#define BYTECNT0_MASK 1`

##### BYTECNT1 - Length of data packet in FIFO. (bit 1)

`#define BYTECNT1_BIT 1`

`#define BYTECNT1_MASK 2`

##### BYTECNT2 - Length of data packet in FIFO. (bit 2)

`#define BYTECNT2_BIT 2`

`#define BYTECNT2_MASK 4`

##### BYTECNT3 - Length of data packet in FIFO. (bit 3)

`#define BYTECNT3_BIT 3`

`#define BYTECNT3_MASK 8`

##### BYTECNT4 - Length of data packet in FIFO. (bit 4)

`#define BYTECNT4_BIT 4`

`#define BYTECNT4_MASK 16`

##### BYTECNT5 - Length of data packet in FIFO. (bit 5)

`#define BYTECNT5_BIT 5`

`#define BYTECNT5_MASK 32`

##### BYTECNT6 - Length of data packet in FIFO. (bit 6)

`#define BYTECNT6_BIT 6`

`#define BYTECNT6_MASK 64`

##### BYTECNT7 - Length of data packet in FIFO. (bit 7)

`#define BYTECNT7_BIT 7`

`#define BYTECNT7_MASK 128`

### FBYTE_CNT5_L - FIFO Byte Count Low 5 Register

`sfrb FBYTE_CNT5_L = $F0BA;`

##### BYTECNT0 - Length of data packet in FIFO. (bit 0)

`#define BYTECNT0_BIT 0`

`#define BYTECNT0_MASK 1`

##### BYTECNT1 - Length of data packet in FIFO. (bit 1)

`#define BYTECNT1_BIT 1`

`#define BYTECNT1_MASK 2`

##### BYTECNT2 - Length of data packet in FIFO. (bit 2)

`#define BYTECNT2_BIT 2`

`#define BYTECNT2_MASK 4`

##### BYTECNT3 - Length of data packet in FIFO. (bit 3)

`#define BYTECNT3_BIT 3`

`#define BYTECNT3_MASK 8`

##### BYTECNT4 - Length of data packet in FIFO. (bit 4)

`#define BYTECNT4_BIT 4`

`#define BYTECNT4_MASK 16`

##### BYTECNT5 - Length of data packet in FIFO. (bit 5)

`#define BYTECNT5_BIT 5`

`#define BYTECNT5_MASK 32`

##### BYTECNT6 - Length of data packet in FIFO. (bit 6)

`#define BYTECNT6_BIT 6`

`#define BYTECNT6_MASK 64`

##### BYTECNT7 - Length of data packet in FIFO. (bit 7)

`#define BYTECNT7_BIT 7`

`#define BYTECNT7_MASK 128`

### FBYTE_CNT4_L - FIFO Byte Count Low 4 Register

`sfrb FBYTE_CNT4_L = $F0BB;`

##### BYTECNT0 - Length of data packet in FIFO. (bit 0)

`#define BYTECNT0_BIT 0`

`#define BYTECNT0_MASK 1`

##### BYTECNT1 - Length of data packet in FIFO. (bit 1)

`#define BYTECNT1_BIT 1`

`#define BYTECNT1_MASK 2`

##### BYTECNT2 - Length of data packet in FIFO. (bit 2)

`#define BYTECNT2_BIT 2`

`#define BYTECNT2_MASK 4`

##### BYTECNT3 - Length of data packet in FIFO. (bit 3)

`#define BYTECNT3_BIT 3`

`#define BYTECNT3_MASK 8`

##### BYTECNT4 - Length of data packet in FIFO. (bit 4)

`#define BYTECNT4_BIT 4`

`#define BYTECNT4_MASK 16`

##### BYTECNT5 - Length of data packet in FIFO. (bit 5)

`#define BYTECNT5_BIT 5`

`#define BYTECNT5_MASK 32`

##### BYTECNT6 - Length of data packet in FIFO. (bit 6)

`#define BYTECNT6_BIT 6`

`#define BYTECNT6_MASK 64`

##### BYTECNT7 - Length of data packet in FIFO. (bit 7)

`#define BYTECNT7_BIT 7`

`#define BYTECNT7_MASK 128`

### FBYTE_CNT3_L - FIFO Byte Count Low 3 Register

`sfrb FBYTE_CNT3_L = $F0BC;`

##### BYTECNT0 - Length of data packet in FIFO. (bit 0)

`#define BYTECNT0_BIT 0`

`#define BYTECNT0_MASK 1`

##### BYTECNT1 - Length of data packet in FIFO. (bit 1)

`#define BYTECNT1_BIT 1`

`#define BYTECNT1_MASK 2`

##### BYTECNT2 - Length of data packet in FIFO. (bit 2)

`#define BYTECNT2_BIT 2`

`#define BYTECNT2_MASK 4`

##### BYTECNT3 - Length of data packet in FIFO. (bit 3)

`#define BYTECNT3_BIT 3`

`#define BYTECNT3_MASK 8`

##### BYTECNT4 - Length of data packet in FIFO. (bit 4)

`#define BYTECNT4_BIT 4`

`#define BYTECNT4_MASK 16`

##### BYTECNT5 - Length of data packet in FIFO. (bit 5)

`#define BYTECNT5_BIT 5`

`#define BYTECNT5_MASK 32`

##### BYTECNT6 - Length of data packet in FIFO. (bit 6)

`#define BYTECNT6_BIT 6`

`#define BYTECNT6_MASK 64`

##### BYTECNT7 - Length of data packet in FIFO. (bit 7)

`#define BYTECNT7_BIT 7`

`#define BYTECNT7_MASK 128`

### FBYTE_CNT2_L - FIFO Byte Count Low 2 Register

`sfrb FBYTE_CNT2_L = $F0BD;`

##### BYTECNT0 - Length of data packet in FIFO. (bit 0)

`#define BYTECNT0_BIT 0`

`#define BYTECNT0_MASK 1`

##### BYTECNT1 - Length of data packet in FIFO. (bit 1)

`#define BYTECNT1_BIT 1`

`#define BYTECNT1_MASK 2`

##### BYTECNT2 - Length of data packet in FIFO. (bit 2)

`#define BYTECNT2_BIT 2`

`#define BYTECNT2_MASK 4`

##### BYTECNT3 - Length of data packet in FIFO. (bit 3)

`#define BYTECNT3_BIT 3`

`#define BYTECNT3_MASK 8`

##### BYTECNT4 - Length of data packet in FIFO. (bit 4)

`#define BYTECNT4_BIT 4`

`#define BYTECNT4_MASK 16`

##### BYTECNT5 - Length of data packet in FIFO. (bit 5)

`#define BYTECNT5_BIT 5`

`#define BYTECNT5_MASK 32`

##### BYTECNT6 - Length of data packet in FIFO. (bit 6)

`#define BYTECNT6_BIT 6`

`#define BYTECNT6_MASK 64`

##### BYTECNT7 - Length of data packet in FIFO. (bit 7)

`#define BYTECNT7_BIT 7`

`#define BYTECNT7_MASK 128`

### FBYTE_CNT1_L - FIFO Byte Count Low 1 Register

`sfrb FBYTE_CNT1_L = $F0BE;`

##### BYTECNT0 - Length of data packet in FIFO. (bit 0)

`#define BYTECNT0_BIT 0`

`#define BYTECNT0_MASK 1`

##### BYTECNT1 - Length of data packet in FIFO. (bit 1)

`#define BYTECNT1_BIT 1`

`#define BYTECNT1_MASK 2`

##### BYTECNT2 - Length of data packet in FIFO. (bit 2)

`#define BYTECNT2_BIT 2`

`#define BYTECNT2_MASK 4`

##### BYTECNT3 - Length of data packet in FIFO. (bit 3)

`#define BYTECNT3_BIT 3`

`#define BYTECNT3_MASK 8`

##### BYTECNT4 - Length of data packet in FIFO. (bit 4)

`#define BYTECNT4_BIT 4`

`#define BYTECNT4_MASK 16`

##### BYTECNT5 - Length of data packet in FIFO. (bit 5)

`#define BYTECNT5_BIT 5`

`#define BYTECNT5_MASK 32`

##### BYTECNT6 - Length of data packet in FIFO. (bit 6)

`#define BYTECNT6_BIT 6`

`#define BYTECNT6_MASK 64`

##### BYTECNT7 - Length of data packet in FIFO. (bit 7)

`#define BYTECNT7_BIT 7`

`#define BYTECNT7_MASK 128`

### FBYTE_CNT0_L - FIFO Byte Count Low 0 Register

`sfrb FBYTE_CNT0_L = $F0BF;`

##### BYTECNT0 - Length of data packet in FIFO. (bit 0)

`#define BYTECNT0_BIT 0`

`#define BYTECNT0_MASK 1`

##### BYTECNT1 - Length of data packet in FIFO. (bit 1)

`#define BYTECNT1_BIT 1`

`#define BYTECNT1_MASK 2`

##### BYTECNT2 - Length of data packet in FIFO. (bit 2)

`#define BYTECNT2_BIT 2`

`#define BYTECNT2_MASK 4`

##### BYTECNT3 - Length of data packet in FIFO. (bit 3)

`#define BYTECNT3_BIT 3`

`#define BYTECNT3_MASK 8`

##### BYTECNT4 - Length of data packet in FIFO. (bit 4)

`#define BYTECNT4_BIT 4`

`#define BYTECNT4_MASK 16`

##### BYTECNT5 - Length of data packet in FIFO. (bit 5)

`#define BYTECNT5_BIT 5`

`#define BYTECNT5_MASK 32`

##### BYTECNT6 - Length of data packet in FIFO. (bit 6)

`#define BYTECNT6_BIT 6`

`#define BYTECNT6_MASK 64`

##### BYTECNT7 - Length of data packet in FIFO. (bit 7)

`#define BYTECNT7_BIT 7`

`#define BYTECNT7_MASK 128`

### FDR7 - FIFO Data Register 7

`sfrb FDR7 = $F0C8;`

##### FIFODATA0

`#define FIFODATA0_BIT 0`

`#define FIFODATA0_MASK 1`

##### FIFODATA1

`#define FIFODATA1_BIT 1`

`#define FIFODATA1_MASK 2`

##### FIFODATA2

`#define FIFODATA2_BIT 2`

`#define FIFODATA2_MASK 4`

##### FIFODATA3

`#define FIFODATA3_BIT 3`

`#define FIFODATA3_MASK 8`

##### FIFODATA4

`#define FIFODATA4_BIT 4`

`#define FIFODATA4_MASK 16`

##### FIFODATA5

`#define FIFODATA5_BIT 5`

`#define FIFODATA5_MASK 32`

##### FIFODATA6

`#define FIFODATA6_BIT 6`

`#define FIFODATA6_MASK 64`

##### FIFODATA7

`#define FIFODATA7_BIT 7`

`#define FIFODATA7_MASK 128`

### FDR6 - FIFO Data Register 6

`sfrb FDR6 = $F0C9;`

##### FIFODATA0

`#define FIFODATA0_BIT 0`

`#define FIFODATA0_MASK 1`

##### FIFODATA1

`#define FIFODATA1_BIT 1`

`#define FIFODATA1_MASK 2`

##### FIFODATA2

`#define FIFODATA2_BIT 2`

`#define FIFODATA2_MASK 4`

##### FIFODATA3

`#define FIFODATA3_BIT 3`

`#define FIFODATA3_MASK 8`

##### FIFODATA4

`#define FIFODATA4_BIT 4`

`#define FIFODATA4_MASK 16`

##### FIFODATA5

`#define FIFODATA5_BIT 5`

`#define FIFODATA5_MASK 32`

##### FIFODATA6

`#define FIFODATA6_BIT 6`

`#define FIFODATA6_MASK 64`

##### FIFODATA7

`#define FIFODATA7_BIT 7`

`#define FIFODATA7_MASK 128`

### FDR5 - FIFO Data Register 5

`sfrb FDR5 = $F0CA;`

##### FIFODATA0

`#define FIFODATA0_BIT 0`

`#define FIFODATA0_MASK 1`

##### FIFODATA1

`#define FIFODATA1_BIT 1`

`#define FIFODATA1_MASK 2`

##### FIFODATA2

`#define FIFODATA2_BIT 2`

`#define FIFODATA2_MASK 4`

##### FIFODATA3

`#define FIFODATA3_BIT 3`

`#define FIFODATA3_MASK 8`

##### FIFODATA4

`#define FIFODATA4_BIT 4`

`#define FIFODATA4_MASK 16`

##### FIFODATA5

`#define FIFODATA5_BIT 5`

`#define FIFODATA5_MASK 32`

##### FIFODATA6

`#define FIFODATA6_BIT 6`

`#define FIFODATA6_MASK 64`

##### FIFODATA7

`#define FIFODATA7_BIT 7`

`#define FIFODATA7_MASK 128`

### FDR4 - FIFO Data Register 4

`sfrb FDR4 = $F0CB;`

##### FIFODATA0

`#define FIFODATA0_BIT 0`

`#define FIFODATA0_MASK 1`

##### FIFODATA1

`#define FIFODATA1_BIT 1`

`#define FIFODATA1_MASK 2`

##### FIFODATA2

`#define FIFODATA2_BIT 2`

`#define FIFODATA2_MASK 4`

##### FIFODATA3

`#define FIFODATA3_BIT 3`

`#define FIFODATA3_MASK 8`

##### FIFODATA4

`#define FIFODATA4_BIT 4`

`#define FIFODATA4_MASK 16`

##### FIFODATA5

`#define FIFODATA5_BIT 5`

`#define FIFODATA5_MASK 32`

##### FIFODATA6

`#define FIFODATA6_BIT 6`

`#define FIFODATA6_MASK 64`

##### FIFODATA7

`#define FIFODATA7_BIT 7`

`#define FIFODATA7_MASK 128`

### FDR3 - FIFO Data Register 3

`sfrb FDR3 = $F0CC;`

##### FIFODATA0

`#define FIFODATA0_BIT 0`

`#define FIFODATA0_MASK 1`

##### FIFODATA1

`#define FIFODATA1_BIT 1`

`#define FIFODATA1_MASK 2`

##### FIFODATA2

`#define FIFODATA2_BIT 2`

`#define FIFODATA2_MASK 4`

##### FIFODATA3

`#define FIFODATA3_BIT 3`

`#define FIFODATA3_MASK 8`

##### FIFODATA4

`#define FIFODATA4_BIT 4`

`#define FIFODATA4_MASK 16`

##### FIFODATA5

`#define FIFODATA5_BIT 5`

`#define FIFODATA5_MASK 32`

##### FIFODATA6

`#define FIFODATA6_BIT 6`

`#define FIFODATA6_MASK 64`

##### FIFODATA7

`#define FIFODATA7_BIT 7`

`#define FIFODATA7_MASK 128`

### FDR2 - FIFO Data Register 2

`sfrb FDR2 = $F0CD;`

##### FIFODATA0

`#define FIFODATA0_BIT 0`

`#define FIFODATA0_MASK 1`

##### FIFODATA1

`#define FIFODATA1_BIT 1`

`#define FIFODATA1_MASK 2`

##### FIFODATA2

`#define FIFODATA2_BIT 2`

`#define FIFODATA2_MASK 4`

##### FIFODATA3

`#define FIFODATA3_BIT 3`

`#define FIFODATA3_MASK 8`

##### FIFODATA4

`#define FIFODATA4_BIT 4`

`#define FIFODATA4_MASK 16`

##### FIFODATA5

`#define FIFODATA5_BIT 5`

`#define FIFODATA5_MASK 32`

##### FIFODATA6

`#define FIFODATA6_BIT 6`

`#define FIFODATA6_MASK 64`

##### FIFODATA7

`#define FIFODATA7_BIT 7`

`#define FIFODATA7_MASK 128`

### FDR1 - FIFO Data Register 1

`sfrb FDR1 = $F0CE;`

##### FIFODATA0

`#define FIFODATA0_BIT 0`

`#define FIFODATA0_MASK 1`

##### FIFODATA1

`#define FIFODATA1_BIT 1`

`#define FIFODATA1_MASK 2`

##### FIFODATA2

`#define FIFODATA2_BIT 2`

`#define FIFODATA2_MASK 4`

##### FIFODATA3

`#define FIFODATA3_BIT 3`

`#define FIFODATA3_MASK 8`

##### FIFODATA4

`#define FIFODATA4_BIT 4`

`#define FIFODATA4_MASK 16`

##### FIFODATA5

`#define FIFODATA5_BIT 5`

`#define FIFODATA5_MASK 32`

##### FIFODATA6

`#define FIFODATA6_BIT 6`

`#define FIFODATA6_MASK 64`

##### FIFODATA7

`#define FIFODATA7_BIT 7`

`#define FIFODATA7_MASK 128`

### FDR0 - FIFO Data Register 0

`sfrb FDR0 = $F0CF;`

##### FIFODATA0

`#define FIFODATA0_BIT 0`

`#define FIFODATA0_MASK 1`

##### FIFODATA1

`#define FIFODATA1_BIT 1`

`#define FIFODATA1_MASK 2`

##### FIFODATA2

`#define FIFODATA2_BIT 2`

`#define FIFODATA2_MASK 4`

##### FIFODATA3

`#define FIFODATA3_BIT 3`

`#define FIFODATA3_MASK 8`

##### FIFODATA4

`#define FIFODATA4_BIT 4`

`#define FIFODATA4_MASK 16`

##### FIFODATA5

`#define FIFODATA5_BIT 5`

`#define FIFODATA5_MASK 32`

##### FIFODATA6

`#define FIFODATA6_BIT 6`

`#define FIFODATA6_MASK 64`

##### FIFODATA7

`#define FIFODATA7_BIT 7`

`#define FIFODATA7_MASK 128`

### ECSR7 - Endpoint Control and Status Register 7

`sfrb ECSR7 = $F0D8;`

##### TXComplete

`#define TXComplete_BIT 0`

`#define TXComplete_MASK 1`

##### RXOUT

`#define RXOUT_BIT 1`

`#define RXOUT_MASK 2`

##### RXSETUP

`#define RXSETUP_BIT 2`

`#define RXSETUP_MASK 4`

##### StallSnd

`#define StallSnd_BIT 3`

`#define StallSnd_MASK 8`

##### TxPacketReady

`#define TxPacketReady_BIT 4`

`#define TxPacketReady_MASK 16`

##### ForceStall

`#define ForceStall_BIT 5`

`#define ForceStall_MASK 32`

##### DataEnd

`#define DataEnd_BIT 6`

`#define DataEnd_MASK 64`

##### ControlDirection

`#define ControlDirection_BIT 7`

`#define ControlDirection_MASK 128`

### ECSR6 - Endpoint Control and Status Register 6

`sfrb ECSR6 = $F0D9;`

##### TXComplete

`#define TXComplete_BIT 0`

`#define TXComplete_MASK 1`

##### RXOUT

`#define RXOUT_BIT 1`

`#define RXOUT_MASK 2`

##### RXSETUP

`#define RXSETUP_BIT 2`

`#define RXSETUP_MASK 4`

##### StallSnd

`#define StallSnd_BIT 3`

`#define StallSnd_MASK 8`

##### TxPacketReady

`#define TxPacketReady_BIT 4`

`#define TxPacketReady_MASK 16`

##### ForceStall

`#define ForceStall_BIT 5`

`#define ForceStall_MASK 32`

##### DataEnd

`#define DataEnd_BIT 6`

`#define DataEnd_MASK 64`

##### ControlDirection

`#define ControlDirection_BIT 7`

`#define ControlDirection_MASK 128`

### ECSR5 - Endpoint Control and Status Register 5

`sfrb ECSR5 = $F0DA;`

##### TXComplete

`#define TXComplete_BIT 0`

`#define TXComplete_MASK 1`

##### RXOUT

`#define RXOUT_BIT 1`

`#define RXOUT_MASK 2`

##### RXSETUP

`#define RXSETUP_BIT 2`

`#define RXSETUP_MASK 4`

##### StallSnd

`#define StallSnd_BIT 3`

`#define StallSnd_MASK 8`

##### TxPacketReady

`#define TxPacketReady_BIT 4`

`#define TxPacketReady_MASK 16`

##### ForceStall

`#define ForceStall_BIT 5`

`#define ForceStall_MASK 32`

##### DataEnd

`#define DataEnd_BIT 6`

`#define DataEnd_MASK 64`

##### ControlDirection

`#define ControlDirection_BIT 7`

`#define ControlDirection_MASK 128`

### ECSR4 - Endpoint Control and Status Register 4

`sfrb ECSR4 = $F0DB;`

##### TXComplete

`#define TXComplete_BIT 0`

`#define TXComplete_MASK 1`

##### RXOUT

`#define RXOUT_BIT 1`

`#define RXOUT_MASK 2`

##### RXSETUP

`#define RXSETUP_BIT 2`

`#define RXSETUP_MASK 4`

##### StallSnd

`#define StallSnd_BIT 3`

`#define StallSnd_MASK 8`

##### TxPacketReady

`#define TxPacketReady_BIT 4`

`#define TxPacketReady_MASK 16`

##### ForceStall

`#define ForceStall_BIT 5`

`#define ForceStall_MASK 32`

##### DataEnd

`#define DataEnd_BIT 6`

`#define DataEnd_MASK 64`

##### ControlDirection

`#define ControlDirection_BIT 7`

`#define ControlDirection_MASK 128`

### ECSR3 - Endpoint Control and Status Register 3

`sfrb ECSR3 = $F0DC;`

##### TXComplete

`#define TXComplete_BIT 0`

`#define TXComplete_MASK 1`

##### RXOUT

`#define RXOUT_BIT 1`

`#define RXOUT_MASK 2`

##### RXSETUP

`#define RXSETUP_BIT 2`

`#define RXSETUP_MASK 4`

##### StallSnd

`#define StallSnd_BIT 3`

`#define StallSnd_MASK 8`

##### TxPacketReady

`#define TxPacketReady_BIT 4`

`#define TxPacketReady_MASK 16`

##### ForceStall

`#define ForceStall_BIT 5`

`#define ForceStall_MASK 32`

##### DataEnd

`#define DataEnd_BIT 6`

`#define DataEnd_MASK 64`

##### ControlDirection

`#define ControlDirection_BIT 7`

`#define ControlDirection_MASK 128`

### ECSR2 - Endpoint Control and Status Register 2

`sfrb ECSR2 = $F0DD;`

##### TXComplete

`#define TXComplete_BIT 0`

`#define TXComplete_MASK 1`

##### RXOUT

`#define RXOUT_BIT 1`

`#define RXOUT_MASK 2`

##### RXSETUP

`#define RXSETUP_BIT 2`

`#define RXSETUP_MASK 4`

##### StallSnd

`#define StallSnd_BIT 3`

`#define StallSnd_MASK 8`

##### TxPacketReady

`#define TxPacketReady_BIT 4`

`#define TxPacketReady_MASK 16`

##### ForceStall

`#define ForceStall_BIT 5`

`#define ForceStall_MASK 32`

##### DataEnd

`#define DataEnd_BIT 6`

`#define DataEnd_MASK 64`

##### ControlDirection

`#define ControlDirection_BIT 7`

`#define ControlDirection_MASK 128`

### ECSR1 - Endpoint Control and Status Register 1

`sfrb ECSR1 = $F0DE;`

##### TXComplete

`#define TXComplete_BIT 0`

`#define TXComplete_MASK 1`

##### RXOUT

`#define RXOUT_BIT 1`

`#define RXOUT_MASK 2`

##### RXSETUP

`#define RXSETUP_BIT 2`

`#define RXSETUP_MASK 4`

##### StallSnd

`#define StallSnd_BIT 3`

`#define StallSnd_MASK 8`

##### TxPacketReady

`#define TxPacketReady_BIT 4`

`#define TxPacketReady_MASK 16`

##### ForceStall

`#define ForceStall_BIT 5`

`#define ForceStall_MASK 32`

##### DataEnd

`#define DataEnd_BIT 6`

`#define DataEnd_MASK 64`

##### ControlDirection

`#define ControlDirection_BIT 7`

`#define ControlDirection_MASK 128`

### ECSR0 - Endpoint Control and Status Register 0

`sfrb ECSR0 = $F0DF;`

##### TXComplete

`#define TXComplete_BIT 0`

`#define TXComplete_MASK 1`

##### RXOUT

`#define RXOUT_BIT 1`

`#define RXOUT_MASK 2`

##### RXSETUP

`#define RXSETUP_BIT 2`

`#define RXSETUP_MASK 4`

##### StallSnd

`#define StallSnd_BIT 3`

`#define StallSnd_MASK 8`

##### TxPacketReady

`#define TxPacketReady_BIT 4`

`#define TxPacketReady_MASK 16`

##### ForceStall

`#define ForceStall_BIT 5`

`#define ForceStall_MASK 32`

##### DataEnd

`#define DataEnd_BIT 6`

`#define DataEnd_MASK 64`

##### ControlDirection

`#define ControlDirection_BIT 7`

`#define ControlDirection_MASK 128`

### ECR7 - Endpoint Control Register 7

`sfrb ECR7 = $F0E8;`

##### EPTYPE0 - Endpoint Type

`#define EPTYPE0_BIT 0`

`#define EPTYPE0_MASK 1`

These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.

##### EPTYPE1 - Endpoint Type

`#define EPTYPE1_BIT 1`

`#define EPTYPE1_MASK 2`

These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.

##### EPDIR - Endpoint Direction

`#define EPDIR_BIT 2`

`#define EPDIR_MASK 4`

Only applicable for non-Control Endpoints (0 =Out, 1 =In).

##### DTGLE - Data Toggle

`#define DTGLE_BIT 3`

`#define DTGLE_MASK 8`

Identifies DATA0 or DATA1 packets

##### EPEDS - Endpoint Enable/Disable

`#define EPEDS_BIT 7`

`#define EPEDS_MASK 128`

(0 = Disable Endpoint, 1 = Enable Endpoint)

### ECR6 - Endpoint Control Register 6

`sfrb ECR6 = $F0E9;`

##### EPTYPE0 - Endpoint Type

`#define EPTYPE0_BIT 0`

`#define EPTYPE0_MASK 1`

These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.

##### EPTYPE1 - Endpoint Type

`#define EPTYPE1_BIT 1`

`#define EPTYPE1_MASK 2`

These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.

##### EPDIR - Endpoint Direction

`#define EPDIR_BIT 2`

`#define EPDIR_MASK 4`

Only applicable for non-Control Endpoints (0 =Out, 1 =In).

##### DTGLE - Data Toggle

`#define DTGLE_BIT 3`

`#define DTGLE_MASK 8`

Identifies DATA0 or DATA1 packets

##### EPEDS - Endpoint Enable/Disable

`#define EPEDS_BIT 7`

`#define EPEDS_MASK 128`

(0 = Disable Endpoint, 1 = Enable Endpoint)

### ECR6 - Endpoint Control Register 6

`sfrb ECR6 = $F0EA;`

##### EPTYPE0 - Endpoint Type

`#define EPTYPE0_BIT 0`

`#define EPTYPE0_MASK 1`

These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.

##### EPTYPE1 - Endpoint Type

`#define EPTYPE1_BIT 1`

`#define EPTYPE1_MASK 2`

These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.

##### EPDIR - Endpoint Direction

`#define EPDIR_BIT 2`

`#define EPDIR_MASK 4`

Only applicable for non-Control Endpoints (0 =Out, 1 =In).

##### DTGLE - Data Toggle

`#define DTGLE_BIT 3`

`#define DTGLE_MASK 8`

Identifies DATA0 or DATA1 packets

##### EPEDS - Endpoint Enable/Disable

`#define EPEDS_BIT 7`

`#define EPEDS_MASK 128`

(0 = Disable Endpoint, 1 = Enable Endpoint)

### ECR4 - Endpoint Control Register 4

`sfrb ECR4 = $F0EB;`

##### EPTYPE0 - Endpoint Type

`#define EPTYPE0_BIT 0`

`#define EPTYPE0_MASK 1`

These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.

##### EPTYPE1 - Endpoint Type

`#define EPTYPE1_BIT 1`

`#define EPTYPE1_MASK 2`

These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.

##### EPDIR - Endpoint Direction

`#define EPDIR_BIT 2`

`#define EPDIR_MASK 4`

Only applicable for non-Control Endpoints (0 =Out, 1 =In).

##### DTGLE - Data Toggle

`#define DTGLE_BIT 3`

`#define DTGLE_MASK 8`

Identifies DATA0 or DATA1 packets

##### EPEDS - Endpoint Enable/Disable

`#define EPEDS_BIT 7`

`#define EPEDS_MASK 128`

(0 = Disable Endpoint, 1 = Enable Endpoint)

### ECR3 - Endpoint Control Register 3

`sfrb ECR3 = $F0EC;`

##### EPTYPE0 - Endpoint Type

`#define EPTYPE0_BIT 0`

`#define EPTYPE0_MASK 1`

These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.

##### EPTYPE1 - Endpoint Type

`#define EPTYPE1_BIT 1`

`#define EPTYPE1_MASK 2`

These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.

##### EPDIR - Endpoint Direction

`#define EPDIR_BIT 2`

`#define EPDIR_MASK 4`

Only applicable for non-Control Endpoints (0 =Out, 1 =In).

##### DTGLE - Data Toggle

`#define DTGLE_BIT 3`

`#define DTGLE_MASK 8`

Identifies DATA0 or DATA1 packets

##### EPEDS - Endpoint Enable/Disable

`#define EPEDS_BIT 7`

`#define EPEDS_MASK 128`

(0 = Disable Endpoint, 1 = Enable Endpoint)

### ECR2 - Endpoint Control Register 2

`sfrb ECR2 = $F0EC;`

##### EPTYPE0 - Endpoint Type

`#define EPTYPE0_BIT 0`

`#define EPTYPE0_MASK 1`

These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.

##### EPTYPE1 - Endpoint Type

`#define EPTYPE1_BIT 1`

`#define EPTYPE1_MASK 2`

These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.

##### EPDIR - Endpoint Direction

`#define EPDIR_BIT 2`

`#define EPDIR_MASK 4`

Only applicable for non-Control Endpoints (0 =Out, 1 =In).

##### DTGLE - Data Toggle

`#define DTGLE_BIT 3`

`#define DTGLE_MASK 8`

Identifies DATA0 or DATA1 packets

##### EPEDS - Endpoint Enable/Disable

`#define EPEDS_BIT 7`

`#define EPEDS_MASK 128`

(0 = Disable Endpoint, 1 = Enable Endpoint)

### ECR1 - Endpoint Control Register 1

`sfrb ECR1 = $F0ED;`

##### EPTYPE0 - Endpoint Type

`#define EPTYPE0_BIT 0`

`#define EPTYPE0_MASK 1`

These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.

##### EPTYPE1 - Endpoint Type

`#define EPTYPE1_BIT 1`

`#define EPTYPE1_MASK 2`

These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.

##### EPDIR - Endpoint Direction

`#define EPDIR_BIT 2`

`#define EPDIR_MASK 4`

Only applicable for non-Control Endpoints (0 =Out, 1 =In).

##### DTGLE - Data Toggle

`#define DTGLE_BIT 3`

`#define DTGLE_MASK 8`

Identifies DATA0 or DATA1 packets

##### EPEDS - Endpoint Enable/Disable

`#define EPEDS_BIT 7`

`#define EPEDS_MASK 128`

(0 = Disable Endpoint, 1 = Enable Endpoint)

### ECR0 - Endpoint Control Register 0

`sfrb ECR0 = $F0EF;`

##### EPTYPE0 - Endpoint Type

`#define EPTYPE0_BIT 0`

`#define EPTYPE0_MASK 1`

These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.

##### EPTYPE1 - Endpoint Type

`#define EPTYPE1_BIT 1`

`#define EPTYPE1_MASK 2`

These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.

##### EPDIR - Endpoint Direction

`#define EPDIR_BIT 2`

`#define EPDIR_MASK 4`

Only applicable for non-Control Endpoints (0 =Out, 1 =In).

##### DTGLE - Data Toggle

`#define DTGLE_BIT 3`

`#define DTGLE_MASK 8`

Identifies DATA0 or DATA1 packets

##### EPEDS - Endpoint Enable/Disable

`#define EPEDS_BIT 7`

`#define EPEDS_MASK 128`

(0 = Disable Endpoint, 1 = Enable Endpoint)

### ENDPPGPG - Function Endpoint Ping Pong Register

`sfrb ENDPPGPG = $F0F1;`

##### PGPG0EN - Enable EndPoint 0 Ping-Pong

`#define PGPG0EN_BIT 0`

`#define PGPG0EN_MASK 1`

##### PGPG1EN - Enable EndPoint 1 Ping-Pong

`#define PGPG1EN_BIT 1`

`#define PGPG1EN_MASK 2`

##### PGPG2EN - Enable EndPoint 2 Ping-Pong

`#define PGPG2EN_BIT 2`

`#define PGPG2EN_MASK 4`

##### PGPG3EN - Enable EndPoint 3 Ping-Pong

`#define PGPG3EN_BIT 3`

`#define PGPG3EN_MASK 8`

##### PGPG4EN - Enable EndPoint 4 Ping-Pong

`#define PGPG4EN_BIT 4`

`#define PGPG4EN_MASK 16`

##### PGPG5EN - Enable EndPoint 5 Ping-Pong

`#define PGPG5EN_BIT 5`

`#define PGPG5EN_MASK 32`

##### PGPG6EN - Enable EndPoint 6 Ping-Pong

`#define PGPG6EN_BIT 6`

`#define PGPG6EN_MASK 64`

### FADDR - Function Address Register

`sfrb FADDR = $F0F2;`

##### FADD0 - Function address (bit 0)

`#define FADD0_BIT 0`

`#define FADD0_MASK 1`

##### FADD1 - Function address (bit 1)

`#define FADD1_BIT 1`

`#define FADD1_MASK 2`

##### FADD2 - Function address (bit 2)

`#define FADD2_BIT 2`

`#define FADD2_MASK 4`

##### FADD3 - Function address (bit 3)

`#define FADD3_BIT 3`

`#define FADD3_MASK 8`

##### FADD4 - Function address (bit 4)

`#define FADD4_BIT 4`

`#define FADD4_MASK 16`

##### FADD5 - Function address (bit 5)

`#define FADD5_BIT 5`

`#define FADD5_MASK 32`

##### FADD6 - Function address (bit 6)

`#define FADD6_BIT 6`

`#define FADD6_MASK 64`

##### FEN - Function Enable

`#define FEN_BIT 7`

`#define FEN_MASK 128`

### UIER - USB Interrupt Enable Register

`sfrb UIER = $F0F3;`

##### EP0IE - Enable Endpoint 0 Interrupt

`#define EP0IE_BIT 0`

`#define EP0IE_MASK 1`

##### EP1IE - Enable Endpoint 1 Interrupt

`#define EP1IE_BIT 1`

`#define EP1IE_MASK 2`

##### EP2IE - Enable Endpoint 2 Interrupt

`#define EP2IE_BIT 2`

`#define EP2IE_MASK 4`

##### EP3IE - Enable Endpoint 3 Interrupt

`#define EP3IE_BIT 3`

`#define EP3IE_MASK 8`

##### EP5IE - Enable Endpoint 4 Interrupt

`#define EP5IE_BIT 4`

`#define EP5IE_MASK 16`

##### EP5IE - Enable Endpoint 5 Interrupt

`#define EP5IE_BIT 5`

`#define EP5IE_MASK 32`

##### EP6IE - Enable Endpoint 6 Interrupt

`#define EP6IE_BIT 6`

`#define EP6IE_MASK 64`

##### SOF IE - Enable SOF Interrupt

`#define SOF IE_BIT 7`

`#define SOF IE_MASK 128`

### UIAR - USB Interrupt Acknowledge Register

`sfrb UIAR = $F0F5;`

##### EP0INTA - Endpoint 0 Interrupt Acknowledge

`#define EP0INTA_BIT 0`

`#define EP0INTA_MASK 1`

##### EP1INTA - Endpoint 1 Interrupt Acknowledge

`#define EP1INTA_BIT 1`

`#define EP1INTA_MASK 2`

##### EP2INTA - Endpoint 2 Interrupt Acknowledge

`#define EP2INTA_BIT 2`

`#define EP2INTA_MASK 4`

##### EP3INTA - Endpoint 3 Interrupt Acknowledge

`#define EP3INTA_BIT 3`

`#define EP3INTA_MASK 8`

##### EP4INTA - Endpoint 4 Interrupt Acknowledge

`#define EP4INTA_BIT 4`

`#define EP4INTA_MASK 16`

##### EP5INTA - Endpoint 5 Interrupt Acknowledge

`#define EP5INTA_BIT 5`

`#define EP5INTA_MASK 32`

##### EP6INTA - Endpoint 6 Interrupt Acknowledge

`#define EP6INTA_BIT 6`

`#define EP6INTA_MASK 64`

### UISR - USB Interrupt Status Register

`sfrb UISR = $F0F7;`

##### EP0INT - Endpoint 0 Interrupt

`#define EP0INT_BIT 0`

`#define EP0INT_MASK 1`

##### EP1INT - Endpoint 1 Interrupt

`#define EP1INT_BIT 1`

`#define EP1INT_MASK 2`

##### EP2INT - Endpoint 2 Interrupt

`#define EP2INT_BIT 2`

`#define EP2INT_MASK 4`

##### EP3INT - Endpoint 3 Interrupt

`#define EP3INT_BIT 3`

`#define EP3INT_MASK 8`

##### EP4INT - Endpoint 4 Interrupt

`#define EP4INT_BIT 4`

`#define EP4INT_MASK 16`

##### EP5INT - Endpoint 5 Interrupt

`#define EP5INT_BIT 5`

`#define EP5INT_MASK 32`

##### EP6INT - Endpoint 6 Interrupt

`#define EP6INT_BIT 6`

`#define EP6INT_MASK 64`

### SPRSIE - Suspend/Resume Interrupt Enable Register

`sfrb SPRSIE = $F0F9;`

##### SUSPIE - Enable Suspend Signaling Interrupt 1 = enable 0 = disable

`#define SUSPIE_BIT 0`

`#define SUSPIE_MASK 1`

##### RCVDRSNIE - Enable BUS Resume Signaling Interrupt 1 = enable 0 = disable

`#define RCVDRSNIE_BIT 1`

`#define RCVDRSNIE_MASK 2`

##### EXTRSMIE - Enable External Resume Signaling Interrupt 1 = enable 0 = disable

`#define EXTRSMIE_BIT 2`

`#define EXTRSMIE_MASK 4`

##### SOF IE - Enable SOF Interrupt

`#define SOF IE_BIT 3`

`#define SOF IE_MASK 8`

### SPRSR - Suspend/Resume Register

`sfrb SPRSR = $F0FA;`

##### SUSP - Suspend

`#define SUSP_BIT 0`

`#define SUSP_MASK 1`

##### RCVDRSM - Received Resume

`#define RCVDRSM_BIT 1`

`#define RCVDRSM_MASK 2`

##### EXTRSM - Received External Resume

`#define EXTRSM_BIT 2`

`#define EXTRSM_MASK 4`

##### SOF INT - SOF Interrupt

`#define SOF INT_BIT 3`

`#define SOF INT_MASK 8`

### GLB_STATE - Global State Register

`sfrb GLB_STATE = $F0FB;`

##### FADD - Function Address Enable

`#define FADD_BIT 0`

`#define FADD_MASK 1`

##### CONFG - Configured

`#define CONFG_BIT 1`

`#define CONFG_MASK 2`

##### RMWUPE - Remote Wake-up Enable

`#define RMWUPE_BIT 2`

`#define RMWUPE_MASK 4`

##### RSMINPR

`#define RSMINPR_BIT 3`

`#define RSMINPR_MASK 8`

### FRM_NUM_L - Frame Number Low Register

`sfrb FRM_NUM_L = $F0FC;`

##### FCL0

`#define FCL0_BIT 0`

`#define FCL0_MASK 1`

##### FCL1

`#define FCL1_BIT 1`

`#define FCL1_MASK 2`

##### FCL2

`#define FCL2_BIT 2`

`#define FCL2_MASK 4`

##### FCL3

`#define FCL3_BIT 3`

`#define FCL3_MASK 8`

##### FCL4

`#define FCL4_BIT 4`

`#define FCL4_MASK 16`

##### FCL5

`#define FCL5_BIT 5`

`#define FCL5_MASK 32`

##### FCL6

`#define FCL6_BIT 6`

`#define FCL6_MASK 64`

##### FCL7

`#define FCL7_BIT 7`

`#define FCL7_MASK 128`

### FRM_NUM_H - Frame Number High Register

`sfrb FRM_NUM_H = $F0FD;`

##### FCH8

`#define FCH8_BIT 0`

`#define FCH8_MASK 1`

##### FCH9

`#define FCH9_BIT 1`

`#define FCH9_MASK 2`

##### FCH10

`#define FCH10_BIT 2`

`#define FCH10_MASK 4`