This documentation was generated automatically from the AVR Studio part description file `ATtiny2313.pdf`.

## PORTB

### PORTB - Port B Data Register

`sfrb PORTB = $18;`

##### PORTB0 - Port B Data Register bit 0

`#define PORTB0_BIT 0`

`#define PORTB0_MASK 1`

##### PORTB1 - Port B Data Register bit 1

`#define PORTB1_BIT 1`

`#define PORTB1_MASK 2`

##### PORTB2 - Port B Data Register bit 2

`#define PORTB2_BIT 2`

`#define PORTB2_MASK 4`

##### PORTB3 - Port B Data Register bit 3

`#define PORTB3_BIT 3`

`#define PORTB3_MASK 8`

##### PORTB4 - Port B Data Register bit 4

`#define PORTB4_BIT 4`

`#define PORTB4_MASK 16`

##### PORTB5 - Port B Data Register bit 5

`#define PORTB5_BIT 5`

`#define PORTB5_MASK 32`

##### PORTB6 - Port B Data Register bit 6

`#define PORTB6_BIT 6`

`#define PORTB6_MASK 64`

##### PORTB7 - Port B Data Register bit 7

`#define PORTB7_BIT 7`

`#define PORTB7_MASK 128`

### DDRB - Port B Data Direction Register

`sfrb DDRB = $17;`

##### DDB0 - Port B Data Direction Register bit 0

`#define DDB0_BIT 0`

`#define DDB0_MASK 1`

##### DDB1 - Port B Data Direction Register bit 1

`#define DDB1_BIT 1`

`#define DDB1_MASK 2`

##### DDB2 - Port B Data Direction Register bit 2

`#define DDB2_BIT 2`

`#define DDB2_MASK 4`

##### DDB3 - Port B Data Direction Register bit 3

`#define DDB3_BIT 3`

`#define DDB3_MASK 8`

##### DDB4 - Port B Data Direction Register bit 4

`#define DDB4_BIT 4`

`#define DDB4_MASK 16`

##### DDB5 - Port B Data Direction Register bit 5

`#define DDB5_BIT 5`

`#define DDB5_MASK 32`

##### DDB6 - Port B Data Direction Register bit 6

`#define DDB6_BIT 6`

`#define DDB6_MASK 64`

##### DDB7 - Port B Data Direction Register bit 7

`#define DDB7_BIT 7`

`#define DDB7_MASK 128`

### PINB - Port B Input Pins

`sfrb PINB = $16;`

##### PINB0 - Port B Input Pins bit 0

`#define PINB0_BIT 0`

`#define PINB0_MASK 1`

##### PINB1 - Port B Input Pins bit 1

`#define PINB1_BIT 1`

`#define PINB1_MASK 2`

##### PINB2 - Port B Input Pins bit 2

`#define PINB2_BIT 2`

`#define PINB2_MASK 4`

##### PINB3 - Port B Input Pins bit 3

`#define PINB3_BIT 3`

`#define PINB3_MASK 8`

##### PINB4 - Port B Input Pins bit 4

`#define PINB4_BIT 4`

`#define PINB4_MASK 16`

##### PINB5 - Port B Input Pins bit 5

`#define PINB5_BIT 5`

`#define PINB5_MASK 32`

##### PINB6 - Port B Input Pins bit 6

`#define PINB6_BIT 6`

`#define PINB6_MASK 64`

##### PINB7 - Port B Input Pins bit 7

`#define PINB7_BIT 7`

`#define PINB7_MASK 128`

## TIMER COUNTER 0

### TIMSK - Timer/Counter Interrupt Mask Register

`sfrb TIMSK = $39;`

##### OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable

`#define OCIE0A_BIT 0`

`#define OCIE0A_MASK 1`

##### TOIE0 - Timer/Counter0 Overflow Interrupt Enable

`#define TOIE0_BIT 1`

`#define TOIE0_MASK 2`

##### OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable

`#define OCIE0B_BIT 2`

`#define OCIE0B_MASK 4`

### TIFR - Timer/Counter Interrupt Flag register

`sfrb TIFR = $38;`

##### OCF0A - Timer/Counter0 Output Compare Flag 0A

`#define OCF0A_BIT 0`

`#define OCF0A_MASK 1`

##### TOV0 - Timer/Counter0 Overflow Flag

`#define TOV0_BIT 1`

`#define TOV0_MASK 2`

##### OCF0B - Timer/Counter0 Output Compare Flag 0B

`#define OCF0B_BIT 2`

`#define OCF0B_MASK 4`

### OCR0B - Timer/Counter0 Output Compare Register

`sfrb OCR0B = $3C;`

##### OCR0_0

`#define OCR0_0_BIT 0`

`#define OCR0_0_MASK 1`

##### OCR0_1

`#define OCR0_1_BIT 1`

`#define OCR0_1_MASK 2`

##### OCR0_2

`#define OCR0_2_BIT 2`

`#define OCR0_2_MASK 4`

##### OCR0_3

`#define OCR0_3_BIT 3`

`#define OCR0_3_MASK 8`

##### OCR0_4

`#define OCR0_4_BIT 4`

`#define OCR0_4_MASK 16`

##### OCR0_5

`#define OCR0_5_BIT 5`

`#define OCR0_5_MASK 32`

##### OCR0_6

`#define OCR0_6_BIT 6`

`#define OCR0_6_MASK 64`

##### OCR0_7

`#define OCR0_7_BIT 7`

`#define OCR0_7_MASK 128`

### OCR0A - Timer/Counter0 Output Compare Register

`sfrb OCR0A = $36;`

##### OCR0_0

`#define OCR0_0_BIT 0`

`#define OCR0_0_MASK 1`

##### OCR0_1

`#define OCR0_1_BIT 1`

`#define OCR0_1_MASK 2`

##### OCR0_2

`#define OCR0_2_BIT 2`

`#define OCR0_2_MASK 4`

##### OCR0_3

`#define OCR0_3_BIT 3`

`#define OCR0_3_MASK 8`

##### OCR0_4

`#define OCR0_4_BIT 4`

`#define OCR0_4_MASK 16`

##### OCR0_5

`#define OCR0_5_BIT 5`

`#define OCR0_5_MASK 32`

##### OCR0_6

`#define OCR0_6_BIT 6`

`#define OCR0_6_MASK 64`

##### OCR0_7

`#define OCR0_7_BIT 7`

`#define OCR0_7_MASK 128`

### TCCR0A - Timer/Counter Control Register A

`sfrb TCCR0A = $30;`

##### WGM00 - Waveform Generation Mode

`#define WGM00_BIT 0`

`#define WGM00_MASK 1`

Controls the Waveform Generation Mode, please refer to datasheet for further details.

##### WGM01 - Waveform Generation Mode

`#define WGM01_BIT 1`

`#define WGM01_MASK 2`

Controls the Waveform Generation Mode, please refer to datasheet for further details.

##### COM0B0 - Compare Match Output B Mode

`#define COM0B0_BIT 4`

`#define COM0B0_MASK 16`

Controls Output Compare Pin B behaviour. Please refer to datasheet.

##### COM0B1 - Compare Match Output B Mode

`#define COM0B1_BIT 5`

`#define COM0B1_MASK 32`

Controls Output Compare Pin B behaviour. Please refer to datasheet.

##### COM0A0 - Compare Match Output A Mode

`#define COM0A0_BIT 6`

`#define COM0A0_MASK 64`

Controls Output Compare Pin A behaviour. Please refer to datasheet.

##### COM0A1 - Compare Match Output A Mode

`#define COM0A1_BIT 7`

`#define COM0A1_MASK 128`

Controls Output Compare Pin A behaviour. Please refer to datasheet.

### TCNT0 - Timer/Counter0

`sfrb TCNT0 = $32;`

##### TCNT0_0

`#define TCNT0_0_BIT 0`

`#define TCNT0_0_MASK 1`

##### TCNT0_1

`#define TCNT0_1_BIT 1`

`#define TCNT0_1_MASK 2`

##### TCNT0_2

`#define TCNT0_2_BIT 2`

`#define TCNT0_2_MASK 4`

##### TCNT0_3

`#define TCNT0_3_BIT 3`

`#define TCNT0_3_MASK 8`

##### TCNT0_4

`#define TCNT0_4_BIT 4`

`#define TCNT0_4_MASK 16`

##### TCNT0_5

`#define TCNT0_5_BIT 5`

`#define TCNT0_5_MASK 32`

##### TCNT0_6

`#define TCNT0_6_BIT 6`

`#define TCNT0_6_MASK 64`

##### TCNT0_7

`#define TCNT0_7_BIT 7`

`#define TCNT0_7_MASK 128`

### TCCR0B - Timer/Counter Control Register B

`sfrb TCCR0B = $33;`

##### CS00 - Clock Select

`#define CS00_BIT 0`

`#define CS00_MASK 1`

##### CS01 - Clock Select

`#define CS01_BIT 1`

`#define CS01_MASK 2`

##### CS02 - Clock Select

`#define CS02_BIT 2`

`#define CS02_MASK 4`

##### WGM02

`#define WGM02_BIT 3`

`#define WGM02_MASK 8`

##### FOC0B - Force Output Compare B

`#define FOC0B_BIT 6`

`#define FOC0B_MASK 64`

##### FOC0A - Force Output Compare B

`#define FOC0A_BIT 7`

`#define FOC0A_MASK 128`

## TIMER COUNTER 1

### TIMSK - Timer/Counter Interrupt Mask Register

`sfrb TIMSK = $39;`

##### ICIE1 - Timer/Counter1 Input Capture Interrupt Enable

`#define ICIE1_BIT 3`

`#define ICIE1_MASK 8`

When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

##### OCIE1B - Timer/Counter1 Output CompareB Match Interrupt Enable

`#define OCIE1B_BIT 5`

`#define OCIE1B_MASK 32`

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

##### OCIE1A - Timer/Counter1 Output CompareA Match Interrupt Enable

`#define OCIE1A_BIT 6`

`#define OCIE1A_MASK 64`

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

##### TOIE1 - Timer/Counter1 Overflow Interrupt Enable

`#define TOIE1_BIT 7`

`#define TOIE1_MASK 128`

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

### TIFR - Timer/Counter Interrupt Flag register

`sfrb TIFR = $38;`

##### ICF1 - Input Capture Flag 1

`#define ICF1_BIT 3`

`#define ICF1_MASK 8`

The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.

##### OCF1B - Output Compare Flag 1B

`#define OCF1B_BIT 5`

`#define OCF1B_MASK 32`

The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.

##### OCF1A - Output Compare Flag 1A

`#define OCF1A_BIT 6`

`#define OCF1A_MASK 64`

The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed.

##### TOV1 - Timer/Counter1 Overflow Flag

`#define TOV1_BIT 7`

`#define TOV1_MASK 128`

The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.

### TCCR1A - Timer/Counter1 Control Register A

`sfrb TCCR1A = $2F;`

##### WGM10 - Pulse Width Modulator Select Bit 0

`#define WGM10_BIT 0`

`#define WGM10_MASK 1`

##### WGM11 - Pulse Width Modulator Select Bit 1

`#define WGM11_BIT 1`

`#define WGM11_MASK 2`

##### COM1B0 - Comparet Ouput Mode 1B, bit 0

`#define COM1B0_BIT 4`

`#define COM1B0_MASK 16`

##### COM1B1 - Compare Output Mode 1B, bit 1

`#define COM1B1_BIT 5`

`#define COM1B1_MASK 32`

##### COM1A0 - Comparet Ouput Mode 1A, bit 0

`#define COM1A0_BIT 6`

`#define COM1A0_MASK 64`

The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in the databook.

##### COM1A1 - Compare Output Mode 1A, bit 1

`#define COM1A1_BIT 7`

`#define COM1A1_MASK 128`

The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in the databook.

### TCCR1B - Timer/Counter1 Control Register B

`sfrb TCCR1B = $2E;`

##### CS10 - Clock Select bit 0

`#define CS10_BIT 0`

`#define CS10_MASK 1`

##### CS11 - Clock Select 1 bit 1

`#define CS11_BIT 1`

`#define CS11_MASK 2`

##### CS12 - Clock Select1 bit 2

`#define CS12_BIT 2`

`#define CS12_MASK 4`

##### WGM12 - Waveform Generation Mode Bit 2

`#define WGM12_BIT 3`

`#define WGM12_MASK 8`

##### WGM13 - Waveform Generation Mode Bit 3

`#define WGM13_BIT 4`

`#define WGM13_MASK 16`

##### ICES1 - Input Capture 1 Edge Select

`#define ICES1_BIT 6`

`#define ICES1_MASK 64`

While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.

##### ICNC1 - Input Capture 1 Noise Canceler

`#define ICNC1_BIT 7`

`#define ICNC1_MASK 128`

When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.

### TCCR1C - Timer/Counter1 Control Register C

`sfrb TCCR1C = $22;`

##### FOC1B - Force Output Compare for Channel B

`#define FOC1B_BIT 6`

`#define FOC1B_MASK 64`

The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero

##### FOC1A - Force Output Compare for Channel A

`#define FOC1A_BIT 7`

`#define FOC1A_MASK 128`

The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero

### TCNT1H - Timer/Counter1 High Byte

`sfrb TCNT1H = $2D;`

##### TCNT1H0 - Timer/Counter1 High Byte bit 0

`#define TCNT1H0_BIT 0`

`#define TCNT1H0_MASK 1`

##### TCNT1H1 - Timer/Counter1 High Byte bit 1

`#define TCNT1H1_BIT 1`

`#define TCNT1H1_MASK 2`

##### TCNT1H2 - Timer/Counter1 High Byte bit 2

`#define TCNT1H2_BIT 2`

`#define TCNT1H2_MASK 4`

##### TCNT1H3 - Timer/Counter1 High Byte bit 3

`#define TCNT1H3_BIT 3`

`#define TCNT1H3_MASK 8`

##### TCNT1H4 - Timer/Counter1 High Byte bit 4

`#define TCNT1H4_BIT 4`

`#define TCNT1H4_MASK 16`

##### TCNT1H5 - Timer/Counter1 High Byte bit 5

`#define TCNT1H5_BIT 5`

`#define TCNT1H5_MASK 32`

##### TCNT1H6 - Timer/Counter1 High Byte bit 6

`#define TCNT1H6_BIT 6`

`#define TCNT1H6_MASK 64`

##### TCNT1H7 - Timer/Counter1 High Byte bit 7

`#define TCNT1H7_BIT 7`

`#define TCNT1H7_MASK 128`

### TCNT1L - Timer/Counter1 Low Byte

`sfrb TCNT1L = $2C;`

##### TCNT1L0 - Timer/Counter1 Low Byte bit 0

`#define TCNT1L0_BIT 0`

`#define TCNT1L0_MASK 1`

##### TCNT1L1 - Timer/Counter1 Low Byte bit 1

`#define TCNT1L1_BIT 1`

`#define TCNT1L1_MASK 2`

##### TCNT1L2 - Timer/Counter1 Low Byte bit 2

`#define TCNT1L2_BIT 2`

`#define TCNT1L2_MASK 4`

##### TCNT1L3 - Timer/Counter1 Low Byte bit 3

`#define TCNT1L3_BIT 3`

`#define TCNT1L3_MASK 8`

##### TCNT1L4 - Timer/Counter1 Low Byte bit 4

`#define TCNT1L4_BIT 4`

`#define TCNT1L4_MASK 16`

##### TCNT1L5 - Timer/Counter1 Low Byte bit 5

`#define TCNT1L5_BIT 5`

`#define TCNT1L5_MASK 32`

##### TCNT1L6 - Timer/Counter1 Low Byte bit 6

`#define TCNT1L6_BIT 6`

`#define TCNT1L6_MASK 64`

##### TCNT1L7 - Timer/Counter1 Low Byte bit 7

`#define TCNT1L7_BIT 7`

`#define TCNT1L7_MASK 128`

### OCR1AH - Timer/Counter1 Outbut Compare Register High Byte

`sfrb OCR1AH = $2B;`

##### OCR1AH0 - Timer/Counter1 Outbut Compare Register High Byte bit 0

`#define OCR1AH0_BIT 0`

`#define OCR1AH0_MASK 1`

##### OCR1AH1 - Timer/Counter1 Outbut Compare Register High Byte bit 1

`#define OCR1AH1_BIT 1`

`#define OCR1AH1_MASK 2`

##### OCR1AH2 - Timer/Counter1 Outbut Compare Register High Byte bit 2

`#define OCR1AH2_BIT 2`

`#define OCR1AH2_MASK 4`

##### OCR1AH3 - Timer/Counter1 Outbut Compare Register High Byte bit 3

`#define OCR1AH3_BIT 3`

`#define OCR1AH3_MASK 8`

##### OCR1AH4 - Timer/Counter1 Outbut Compare Register High Byte bit 4

`#define OCR1AH4_BIT 4`

`#define OCR1AH4_MASK 16`

##### OCR1AH5 - Timer/Counter1 Outbut Compare Register High Byte bit 5

`#define OCR1AH5_BIT 5`

`#define OCR1AH5_MASK 32`

##### OCR1AH6 - Timer/Counter1 Outbut Compare Register High Byte bit 6

`#define OCR1AH6_BIT 6`

`#define OCR1AH6_MASK 64`

##### OCR1AH7 - Timer/Counter1 Outbut Compare Register High Byte bit 7

`#define OCR1AH7_BIT 7`

`#define OCR1AH7_MASK 128`

### OCR1AL - Timer/Counter1 Outbut Compare Register Low Byte

`sfrb OCR1AL = $2A;`

##### OCR1AL0 - Timer/Counter1 Outbut Compare Register Low Byte Bit 0

`#define OCR1AL0_BIT 0`

`#define OCR1AL0_MASK 1`

##### OCR1AL1 - Timer/Counter1 Outbut Compare Register Low Byte Bit 1

`#define OCR1AL1_BIT 1`

`#define OCR1AL1_MASK 2`

##### OCR1AL2 - Timer/Counter1 Outbut Compare Register Low Byte Bit 2

`#define OCR1AL2_BIT 2`

`#define OCR1AL2_MASK 4`

##### OCR1AL3 - Timer/Counter1 Outbut Compare Register Low Byte Bit 3

`#define OCR1AL3_BIT 3`

`#define OCR1AL3_MASK 8`

##### OCR1AL4 - Timer/Counter1 Outbut Compare Register Low Byte Bit 4

`#define OCR1AL4_BIT 4`

`#define OCR1AL4_MASK 16`

##### OCR1AL5 - Timer/Counter1 Outbut Compare Register Low Byte Bit 5

`#define OCR1AL5_BIT 5`

`#define OCR1AL5_MASK 32`

##### OCR1AL6 - Timer/Counter1 Outbut Compare Register Low Byte Bit 6

`#define OCR1AL6_BIT 6`

`#define OCR1AL6_MASK 64`

##### OCR1AL7 - Timer/Counter1 Outbut Compare Register Low Byte Bit 7

`#define OCR1AL7_BIT 7`

`#define OCR1AL7_MASK 128`

### OCR1BH - Timer/Counter1 Outbut Compare Register High Byte

`sfrb OCR1BH = $29;`

##### OCR1AH0 - Timer/Counter1 Outbut Compare Register High Byte bit 0

`#define OCR1AH0_BIT 0`

`#define OCR1AH0_MASK 1`

##### OCR1AH1 - Timer/Counter1 Outbut Compare Register High Byte bit 1

`#define OCR1AH1_BIT 1`

`#define OCR1AH1_MASK 2`

##### OCR1AH2 - Timer/Counter1 Outbut Compare Register High Byte bit 2

`#define OCR1AH2_BIT 2`

`#define OCR1AH2_MASK 4`

##### OCR1AH3 - Timer/Counter1 Outbut Compare Register High Byte bit 3

`#define OCR1AH3_BIT 3`

`#define OCR1AH3_MASK 8`

##### OCR1AH4 - Timer/Counter1 Outbut Compare Register High Byte bit 4

`#define OCR1AH4_BIT 4`

`#define OCR1AH4_MASK 16`

##### OCR1AH5 - Timer/Counter1 Outbut Compare Register High Byte bit 5

`#define OCR1AH5_BIT 5`

`#define OCR1AH5_MASK 32`

##### OCR1AH6 - Timer/Counter1 Outbut Compare Register High Byte bit 6

`#define OCR1AH6_BIT 6`

`#define OCR1AH6_MASK 64`

##### OCR1AH7 - Timer/Counter1 Outbut Compare Register High Byte bit 7

`#define OCR1AH7_BIT 7`

`#define OCR1AH7_MASK 128`

### OCR1BL - Timer/Counter1 Output Compare Register Low Byte

`sfrb OCR1BL = $28;`

##### OCR1AL0 - Timer/Counter1 Outbut Compare Register Low Byte Bit 0

`#define OCR1AL0_BIT 0`

`#define OCR1AL0_MASK 1`

##### OCR1AL1 - Timer/Counter1 Outbut Compare Register Low Byte Bit 1

`#define OCR1AL1_BIT 1`

`#define OCR1AL1_MASK 2`

##### OCR1AL2 - Timer/Counter1 Outbut Compare Register Low Byte Bit 2

`#define OCR1AL2_BIT 2`

`#define OCR1AL2_MASK 4`

##### OCR1AL3 - Timer/Counter1 Outbut Compare Register Low Byte Bit 3

`#define OCR1AL3_BIT 3`

`#define OCR1AL3_MASK 8`

##### OCR1AL4 - Timer/Counter1 Outbut Compare Register Low Byte Bit 4

`#define OCR1AL4_BIT 4`

`#define OCR1AL4_MASK 16`

##### OCR1AL5 - Timer/Counter1 Outbut Compare Register Low Byte Bit 5

`#define OCR1AL5_BIT 5`

`#define OCR1AL5_MASK 32`

##### OCR1AL6 - Timer/Counter1 Outbut Compare Register Low Byte Bit 6

`#define OCR1AL6_BIT 6`

`#define OCR1AL6_MASK 64`

##### OCR1AL7 - Timer/Counter1 Outbut Compare Register Low Byte Bit 7

`#define OCR1AL7_BIT 7`

`#define OCR1AL7_MASK 128`

### ICR1H - Timer/Counter1 Input Capture Register High Byte

`sfrb ICR1H = $25;`

##### ICR1H0 - Timer/Counter1 Input Capture Register High Byte bit 0

`#define ICR1H0_BIT 0`

`#define ICR1H0_MASK 1`

##### ICR1H1 - Timer/Counter1 Input Capture Register High Byte bit 1

`#define ICR1H1_BIT 1`

`#define ICR1H1_MASK 2`

##### ICR1H2 - Timer/Counter1 Input Capture Register High Byte bit 2

`#define ICR1H2_BIT 2`

`#define ICR1H2_MASK 4`

##### ICR1H3 - Timer/Counter1 Input Capture Register High Byte bit 3

`#define ICR1H3_BIT 3`

`#define ICR1H3_MASK 8`

##### ICR1H4 - Timer/Counter1 Input Capture Register High Byte bit 4

`#define ICR1H4_BIT 4`

`#define ICR1H4_MASK 16`

##### ICR1H5 - Timer/Counter1 Input Capture Register High Byte bit 5

`#define ICR1H5_BIT 5`

`#define ICR1H5_MASK 32`

##### ICR1H6 - Timer/Counter1 Input Capture Register High Byte bit 6

`#define ICR1H6_BIT 6`

`#define ICR1H6_MASK 64`

##### ICR1H7 - Timer/Counter1 Input Capture Register High Byte bit 7

`#define ICR1H7_BIT 7`

`#define ICR1H7_MASK 128`

### ICR1L - Timer/Counter1 Input Capture Register Low Byte

`sfrb ICR1L = $24;`

##### ICR1L0 - Timer/Counter1 Input Capture Register Low Byte bit 0

`#define ICR1L0_BIT 0`

`#define ICR1L0_MASK 1`

##### ICR1L1 - Timer/Counter1 Input Capture Register Low Byte bit 1

`#define ICR1L1_BIT 1`

`#define ICR1L1_MASK 2`

##### ICR1L2 - Timer/Counter1 Input Capture Register Low Byte bit 2

`#define ICR1L2_BIT 2`

`#define ICR1L2_MASK 4`

##### ICR1L3 - Timer/Counter1 Input Capture Register Low Byte bit 3

`#define ICR1L3_BIT 3`

`#define ICR1L3_MASK 8`

##### ICR1L4 - Timer/Counter1 Input Capture Register Low Byte bit 4

`#define ICR1L4_BIT 4`

`#define ICR1L4_MASK 16`

##### ICR1L5 - Timer/Counter1 Input Capture Register Low Byte bit 5

`#define ICR1L5_BIT 5`

`#define ICR1L5_MASK 32`

##### ICR1L6 - Timer/Counter1 Input Capture Register Low Byte bit 6

`#define ICR1L6_BIT 6`

`#define ICR1L6_MASK 64`

##### ICR1L7 - Timer/Counter1 Input Capture Register Low Byte bit 7

`#define ICR1L7_BIT 7`

`#define ICR1L7_MASK 128`

## WATCHDOG

### WDTCR - Watchdog Timer Control Register

`sfrb WDTCR = $21;`

##### WDP0 - Watch Dog Timer Prescaler bit 0

`#define WDP0_BIT 0`

`#define WDP0_MASK 1`

##### WDP1 - Watch Dog Timer Prescaler bit 1

`#define WDP1_BIT 1`

`#define WDP1_MASK 2`

##### WDP2 - Watch Dog Timer Prescaler bit 2

`#define WDP2_BIT 2`

`#define WDP2_MASK 4`

##### WDE - Watch Dog Enable

`#define WDE_BIT 3`

`#define WDE_MASK 8`

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog

##### WDCE - Watchdog Change Enable

`#define WDCE_BIT 4`

`#define WDCE_MASK 16`

##### WDP3 - Watchdog Timer Prescaler Bit 3

`#define WDP3_BIT 5`

`#define WDP3_MASK 32`

##### WDIE - Watchdog Timeout Interrupt Enable

`#define WDIE_BIT 6`

`#define WDIE_MASK 64`

##### WDIF - Watchdog Timeout Interrupt Flag

`#define WDIF_BIT 7`

`#define WDIF_MASK 128`

## EXTERNAL INTERRUPT

### GIMSK - General Interrupt Mask Register

`sfrb GIMSK = $3B;`

##### PCIE

`#define PCIE_BIT 5`

`#define PCIE_MASK 32`

##### INT0 - External Interrupt Request 0 Enable

`#define INT0_BIT 6`

`#define INT0_MASK 64`

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also ?External Interrupts.? ? Bits 5..0 - Res: Reserved bits

##### INT1 - External Interrupt Request 1 Enable

`#define INT1_BIT 7`

`#define INT1_MASK 128`

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory address $002. See also ?External Interrupts?.

### EIFR - Extended Interrupt Flag Register

`sfrb EIFR = $3A;`

##### PCIF

`#define PCIF_BIT 5`

`#define PCIF_MASK 32`

##### INTF0 - External Interrupt Flag 0

`#define INTF0_BIT 6`

`#define INTF0_MASK 64`

When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

##### INTF1 - External Interrupt Flag 1

`#define INTF1_BIT 7`

`#define INTF1_MASK 128`

When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $002. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

## USART

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: ? Full Duplex Operation (Independent Serial Receive and Transmit Registers) ? Asynchronous or Synchronous Operation ? Master or Slave Clocked Synchronous Operation ? High Resolution Baud Rate Generator ? Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits ? Odd or Even Parity Generation and Parity Check Supported by Hardware ? Data OverRun Detection ? Framing Error Detection ? Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter ? Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete ? Multi-processor Communication Mode ? Double Speed Asynchronous Comm

### UDR - USART I/O Data Register

`sfrb UDR = $0C;`

##### UDR0 - USART I/O Data Register bit 0

`#define UDR0_BIT 0`

`#define UDR0_MASK 1`

##### UDR1 - USART I/O Data Register bit 1

`#define UDR1_BIT 1`

`#define UDR1_MASK 2`

##### UDR2 - USART I/O Data Register bit 2

`#define UDR2_BIT 2`

`#define UDR2_MASK 4`

##### UDR3 - USART I/O Data Register bit 3

`#define UDR3_BIT 3`

`#define UDR3_MASK 8`

##### UDR4 - USART I/O Data Register bit 4

`#define UDR4_BIT 4`

`#define UDR4_MASK 16`

##### UDR5 - USART I/O Data Register bit 5

`#define UDR5_BIT 5`

`#define UDR5_MASK 32`

##### UDR6 - USART I/O Data Register bit 6

`#define UDR6_BIT 6`

`#define UDR6_MASK 64`

##### UDR7 - USART I/O Data Register bit 7

`#define UDR7_BIT 7`

`#define UDR7_MASK 128`

### UCSRA - USART Control and Status Register A

`sfrb UCSRA = $0B;`

##### MPCM - Multi-processor Communication Mode

`#define MPCM_BIT 0`

`#define MPCM_MASK 1`

##### U2X - Double the USART Transmission Speed

`#define U2X_BIT 1`

`#define U2X_MASK 2`

##### UPE - USART Parity Error

`#define UPE_BIT 2`

`#define UPE_MASK 4`

##### DOR - Data overRun

`#define DOR_BIT 3`

`#define DOR_MASK 8`

This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0.

##### FE - Framing Error

`#define FE_BIT 4`

`#define FE_MASK 16`

This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.

##### UDRE - USART Data Register Empty

`#define UDRE_BIT 5`

`#define UDRE_MASK 32`

This bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is rea

##### TXC - USART Transmitt Complete

`#define TXC_BIT 6`

`#define TXC_MASK 64`

This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bi

##### RXC - USART Receive Complete

`#define RXC_BIT 7`

`#define RXC_MASK 128`

This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.

### UCSRB - USART Control and Status Register B

`sfrb UCSRB = $0A;`

##### TXB8 - Transmit Data Bit 8

`#define TXB8_BIT 0`

`#define TXB8_MASK 1`

TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.

##### RXB8 - Receive Data Bit 8

`#define RXB8_BIT 1`

`#define RXB8_MASK 2`

RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.

##### UCSZ2 - Character Size

`#define UCSZ2_BIT 2`

`#define UCSZ2_MASK 4`

##### TXEN - Transmitter Enable

`#define TXEN_BIT 3`

`#define TXEN_MASK 8`

Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.

##### RXEN - Receiver Enable

`#define RXEN_BIT 4`

`#define RXEN_MASK 16`

Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.

##### UDRIE - USART Data register Empty Interrupt Enable

`#define UDRIE_BIT 5`

`#define UDRIE_MASK 32`

Writing this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.

##### TXCIE - TX Complete Interrupt Enable

`#define TXCIE_BIT 6`

`#define TXCIE_MASK 64`

Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.

##### RXCIE - RX Complete Interrupt Enable

`#define RXCIE_BIT 7`

`#define RXCIE_MASK 128`

Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.

### UCSRC - USART Control and Status Register C

`sfrb UCSRC = $03;`

##### UCPOL - Clock Polarity

`#define UCPOL_BIT 0`

`#define UCPOL_MASK 1`

##### UCSZ0 - Character Size Bit 0

`#define UCSZ0_BIT 1`

`#define UCSZ0_MASK 2`

##### UCSZ1 - Character Size Bit 1

`#define UCSZ1_BIT 2`

`#define UCSZ1_MASK 4`

##### USBS - Stop Bit Select

`#define USBS_BIT 3`

`#define USBS_MASK 8`

##### UPM0 - Parity Mode Bit 0

`#define UPM0_BIT 4`

`#define UPM0_MASK 16`

##### UPM1 - Parity Mode Bit 1

`#define UPM1_BIT 5`

`#define UPM1_MASK 32`

##### UMSEL - USART Mode Select

`#define UMSEL_BIT 6`

`#define UMSEL_MASK 64`

### UBRRH - USART Baud Rate Register High Byte

`sfrb UBRRH = $02;`

##### UBRR8 - USART Baud Rate Register bit 8

`#define UBRR8_BIT 0`

`#define UBRR8_MASK 1`

##### UBRR9 - USART Baud Rate Register bit 9

`#define UBRR9_BIT 1`

`#define UBRR9_MASK 2`

##### UBRR10 - USART Baud Rate Register bit 10

`#define UBRR10_BIT 2`

`#define UBRR10_MASK 4`

##### UBRR11 - USART Baud Rate Register bit 11

`#define UBRR11_BIT 3`

`#define UBRR11_MASK 8`

### UBRRL - USART Baud Rate Register Low Byte

`sfrb UBRRL = $09;`

##### UBRR0 - USART Baud Rate Register bit 0

`#define UBRR0_BIT 0`

`#define UBRR0_MASK 1`

##### UBRR1 - USART Baud Rate Register bit 1

`#define UBRR1_BIT 1`

`#define UBRR1_MASK 2`

##### UBRR2 - USART Baud Rate Register bit 2

`#define UBRR2_BIT 2`

`#define UBRR2_MASK 4`

##### UBRR3 - USART Baud Rate Register bit 3

`#define UBRR3_BIT 3`

`#define UBRR3_MASK 8`

##### UBRR4 - USART Baud Rate Register bit 4

`#define UBRR4_BIT 4`

`#define UBRR4_MASK 16`

##### UBRR5 - USART Baud Rate Register bit 5

`#define UBRR5_BIT 5`

`#define UBRR5_MASK 32`

##### UBRR6 - USART Baud Rate Register bit 6

`#define UBRR6_BIT 6`

`#define UBRR6_MASK 64`

##### UBRR7 - USART Baud Rate Register bit 7

`#define UBRR7_BIT 7`

`#define UBRR7_MASK 128`

## ANALOG COMPARATOR

### ACSR - Analog Comparator Control And Status Register

`sfrb ACSR = $08;`

##### ACIS0 - Analog Comparator Interrupt Mode Select bit 0

`#define ACIS0_BIT 0`

`#define ACIS0_MASK 1`

These bits determine which comparator events that trigger the Analog Comparator interrupt.

##### ACIS1 - Analog Comparator Interrupt Mode Select bit 1

`#define ACIS1_BIT 1`

`#define ACIS1_MASK 2`

These bits determine which comparator events that trigger the Analog Comparator interrupt.

##### ACIC

`#define ACIC_BIT 2`

`#define ACIC_MASK 4`

##### ACIE - Analog Comparator Interrupt Enable

`#define ACIE_BIT 3`

`#define ACIE_MASK 8`

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.

##### ACI - Analog Comparator Interrupt Flag

`#define ACI_BIT 4`

`#define ACI_MASK 16`

This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

##### ACO - Analog Compare Output

`#define ACO_BIT 5`

`#define ACO_MASK 32`

The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.

##### ACBG - Analog Comparator Bandgap Select

`#define ACBG_BIT 6`

`#define ACBG_MASK 64`

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See ?Internal Voltage Reference? on page 42.

##### ACD - Analog Comparator Disable

`#define ACD_BIT 7`

`#define ACD_MASK 128`

When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

### DIDR - Digital Input Disable Register 1

`sfrb DIDR = $01;`

##### AIN0D - AIN0 Digital Input Disable

`#define AIN0D_BIT 0`

`#define AIN0D_MASK 1`

##### AIN1D - AIN1 Digital Input Disable

`#define AIN1D_BIT 1`

`#define AIN1D_MASK 2`

## PORTD

### PORTD - Data Register, Port D

`sfrb PORTD = $12;`

##### PORTD0

`#define PORTD0_BIT 0`

`#define PORTD0_MASK 1`

##### PORTD1

`#define PORTD1_BIT 1`

`#define PORTD1_MASK 2`

##### PORTD2

`#define PORTD2_BIT 2`

`#define PORTD2_MASK 4`

##### PORTD3

`#define PORTD3_BIT 3`

`#define PORTD3_MASK 8`

##### PORTD4

`#define PORTD4_BIT 4`

`#define PORTD4_MASK 16`

##### PORTD5

`#define PORTD5_BIT 5`

`#define PORTD5_MASK 32`

##### PORTD6

`#define PORTD6_BIT 6`

`#define PORTD6_MASK 64`

### DDRD -

`sfrb DDRD = $11;`

##### DDD0

`#define DDD0_BIT 0`

`#define DDD0_MASK 1`

##### DDD1

`#define DDD1_BIT 1`

`#define DDD1_MASK 2`

##### DDD2

`#define DDD2_BIT 2`

`#define DDD2_MASK 4`

##### DDD3

`#define DDD3_BIT 3`

`#define DDD3_MASK 8`

##### DDD4

`#define DDD4_BIT 4`

`#define DDD4_MASK 16`

##### DDD5

`#define DDD5_BIT 5`

`#define DDD5_MASK 32`

##### DDD6

`#define DDD6_BIT 6`

`#define DDD6_MASK 64`

### PIND - Input Pins, Port D

`sfrb PIND = $10;`

##### PIND0

`#define PIND0_BIT 0`

`#define PIND0_MASK 1`

##### PIND1

`#define PIND1_BIT 1`

`#define PIND1_MASK 2`

##### PIND2

`#define PIND2_BIT 2`

`#define PIND2_MASK 4`

##### PIND3

`#define PIND3_BIT 3`

`#define PIND3_MASK 8`

##### PIND4

`#define PIND4_BIT 4`

`#define PIND4_MASK 16`

##### PIND5

`#define PIND5_BIT 5`

`#define PIND5_MASK 32`

##### PIND6

`#define PIND6_BIT 6`

`#define PIND6_MASK 64`

## EEPROM

### EEAR - EEPROM Read/Write Access

`sfrb EEAR = $1E;`

##### EEAR0 - EEPROM Read/Write Access bit 0

`#define EEAR0_BIT 0`

`#define EEAR0_MASK 1`

##### EEAR1 - EEPROM Read/Write Access bit 1

`#define EEAR1_BIT 1`

`#define EEAR1_MASK 2`

##### EEAR2 - EEPROM Read/Write Access bit 2

`#define EEAR2_BIT 2`

`#define EEAR2_MASK 4`

##### EEAR3 - EEPROM Read/Write Access bit 3

`#define EEAR3_BIT 3`

`#define EEAR3_MASK 8`

##### EEAR4 - EEPROM Read/Write Access bit 4

`#define EEAR4_BIT 4`

`#define EEAR4_MASK 16`

##### EEAR5 - EEPROM Read/Write Access bit 5

`#define EEAR5_BIT 5`

`#define EEAR5_MASK 32`

##### EEAR6 - EEPROM Read/Write Access bit 6

`#define EEAR6_BIT 6`

`#define EEAR6_MASK 64`

### EEDR - EEPROM Data Register

`sfrb EEDR = $1D;`

##### EEDR0 - EEPROM Data Register bit 0

`#define EEDR0_BIT 0`

`#define EEDR0_MASK 1`

##### EEDR1 - EEPROM Data Register bit 1

`#define EEDR1_BIT 1`

`#define EEDR1_MASK 2`

##### EEDR2 - EEPROM Data Register bit 2

`#define EEDR2_BIT 2`

`#define EEDR2_MASK 4`

##### EEDR3 - EEPROM Data Register bit 3

`#define EEDR3_BIT 3`

`#define EEDR3_MASK 8`

##### EEDR4 - EEPROM Data Register bit 4

`#define EEDR4_BIT 4`

`#define EEDR4_MASK 16`

##### EEDR5 - EEPROM Data Register bit 5

`#define EEDR5_BIT 5`

`#define EEDR5_MASK 32`

##### EEDR6 - EEPROM Data Register bit 6

`#define EEDR6_BIT 6`

`#define EEDR6_MASK 64`

##### EEDR7 - EEPROM Data Register bit 7

`#define EEDR7_BIT 7`

`#define EEDR7_MASK 128`

### EECR - EEPROM Control Register

`sfrb EECR = $1C;`

##### EERE - EEPROM Read Enable

`#define EERE_BIT 0`

`#define EERE_MASK 1`

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined.

##### EEPE - EEPROM Write Enable

`#define EEPE_BIT 1`

`#define EEPE_MASK 2`

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one to the EEMWE bit, the EEWE bit mustbewritten to zero in thesamecycle). 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at V CC =5Vor 4msatV CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted or two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems.

##### EEMPE - EEPROM Master Write Enable

`#define EEMPE_BIT 2`

`#define EEMPE_MASK 4`

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure.

##### EERIE - EEProm Ready Interrupt Enable

`#define EERIE_BIT 3`

`#define EERIE_MASK 8`

When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero).

##### EEPM0

`#define EEPM0_BIT 4`

`#define EEPM0_MASK 16`

##### EEPM1

`#define EEPM1_BIT 5`

`#define EEPM1_MASK 32`

## PORTA

### PORTA - Port A Data Register

`sfrb PORTA = $1B;`

##### PORTA0 - Port A Data Register bit 0

`#define PORTA0_BIT 0`

`#define PORTA0_MASK 1`

##### PORTA1 - Port A Data Register bit 1

`#define PORTA1_BIT 1`

`#define PORTA1_MASK 2`

##### PORTA2 - Port A Data Register bit 2

`#define PORTA2_BIT 2`

`#define PORTA2_MASK 4`

### DDRA - Port A Data Direction Register

`sfrb DDRA = $1A;`

##### DDA0 - Data Direction Register, Port A, bit 0

`#define DDA0_BIT 0`

`#define DDA0_MASK 1`

##### DDA1 - Data Direction Register, Port A, bit 1

`#define DDA1_BIT 1`

`#define DDA1_MASK 2`

##### DDA2 - Data Direction Register, Port A, bit 2

`#define DDA2_BIT 2`

`#define DDA2_MASK 4`

### PINA - Port A Input Pins

`sfrb PINA = $19;`

##### PINA0 - Input Pins, Port A bit 0

`#define PINA0_BIT 0`

`#define PINA0_MASK 1`

##### PINA1 - Input Pins, Port A bit 1

`#define PINA1_BIT 1`

`#define PINA1_MASK 2`

##### PINA2 - Input Pins, Port A bit 2

`#define PINA2_BIT 2`

`#define PINA2_MASK 4`

## CPU

### SREG - Status Register

`sfrb SREG = $3F;`

### SPL - Stack Pointer Low Byte

`sfrb SPL = $3D;`

##### SP0 - Stack Pointer Bit 0

`#define SP0_BIT 0`

`#define SP0_MASK 1`

##### SP1 - Stack Pointer Bit 1

`#define SP1_BIT 1`

`#define SP1_MASK 2`

##### SP2 - Stack Pointer Bit 2

`#define SP2_BIT 2`

`#define SP2_MASK 4`

##### SP3 - Stack Pointer Bit 3

`#define SP3_BIT 3`

`#define SP3_MASK 8`

##### SP4

`#define SP4_BIT 4`

`#define SP4_MASK 16`

##### SP5 - Stack Pointer Bit 5

`#define SP5_BIT 5`

`#define SP5_MASK 32`

##### SP6 - Stack Pointer Bit 6

`#define SP6_BIT 6`

`#define SP6_MASK 64`

##### SP7 - Stack Pointer Bit 7

`#define SP7_BIT 7`

`#define SP7_MASK 128`

### SPMCSR - Store Program Memory Control and Status register

`sfrb SPMCSR = $37;`

##### SPMEN - Store Program Memory Enable

`#define SPMEN_BIT 0`

`#define SPMEN_MASK 1`

This bit enables the SPM instruction for the next four clock cycles. If written to one together with either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. Writing any other combination than ?10001?, ?01001?, ?00101?, ?00011? or ?00001? in the lower five bits will have no effe

##### PGERS - Page Erase

`#define PGERS_BIT 1`

`#define PGERS_MASK 2`

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation.

##### PGWRT - Page Write

`#define PGWRT_BIT 2`

`#define PGWRT_MASK 4`

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation.

##### RFLB - Read Fuse and Lock Bits

`#define RFLB_BIT 3`

`#define RFLB_MASK 8`

An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Zpointer) into the destination register.

##### CTPB

`#define CTPB_BIT 4`

`#define CTPB_MASK 16`

If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost.

### MCUCR - MCU Control Register

`sfrb MCUCR = $35;`

##### ISC00 - Interrupt Sense Control 0 bit 0

`#define ISC00_BIT 0`

`#define ISC00_MASK 1`

##### ISC01 - Interrupt Sense Control 0 bit 1

`#define ISC01_BIT 1`

`#define ISC01_MASK 2`

##### ISC10 - Interrupt Sense Control 1 bit 0

`#define ISC10_BIT 2`

`#define ISC10_MASK 4`

##### ISC11 - Interrupt Sense Control 1 bit 1

`#define ISC11_BIT 3`

`#define ISC11_MASK 8`

##### SM0 - Sleep Mode Select Bit 0

`#define SM0_BIT 4`

`#define SM0_MASK 16`

##### SE - Sleep Enable

`#define SE_BIT 5`

`#define SE_MASK 32`

The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.

##### SM1 - Sleep Mode Select Bit 1

`#define SM1_BIT 6`

`#define SM1_MASK 64`

##### PUD - Pull-up Disable

`#define PUD_BIT 7`

`#define PUD_MASK 128`

### MCUSR - MCU Status register

`sfrb MCUSR = $34;`

##### PORF - Power-On Reset Flag

`#define PORF_BIT 0`

`#define PORF_MASK 1`

This bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchanged

##### EXTRF - External Reset Flag

`#define EXTRF_BIT 1`

`#define EXTRF_MASK 2`

After a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged.

##### BORF - Brown-out Reset Flag

`#define BORF_BIT 2`

`#define BORF_MASK 4`

##### WDRF - Watchdog Reset Flag

`#define WDRF_BIT 3`

`#define WDRF_MASK 8`

### OSCCAL - Oscillator Calibration Register

`sfrb OSCCAL = $31;`

##### CAL0 - Oscillatro Calibration Value Bit 0

`#define CAL0_BIT 0`

`#define CAL0_MASK 1`

##### CAL1 - Oscillatro Calibration Value Bit 1

`#define CAL1_BIT 1`

`#define CAL1_MASK 2`

##### CAL2 - Oscillatro Calibration Value Bit 2

`#define CAL2_BIT 2`

`#define CAL2_MASK 4`

##### CAL3 - Oscillatro Calibration Value Bit 3

`#define CAL3_BIT 3`

`#define CAL3_MASK 8`

##### CAL4 - Oscillatro Calibration Value Bit 4

`#define CAL4_BIT 4`

`#define CAL4_MASK 16`

##### CAL5 - Oscillatro Calibration Value Bit 5

`#define CAL5_BIT 5`

`#define CAL5_MASK 32`

##### CAL6 - Oscillatro Calibration Value Bit 6

`#define CAL6_BIT 6`

`#define CAL6_MASK 64`

### CLKPR - Clock Prescale Register

`sfrb CLKPR = $26;`

##### CLKPS0 - Clock Prescaler Select Bit 0

`#define CLKPS0_BIT 0`

`#define CLKPS0_MASK 1`

##### CLKPS1 - Clock Prescaler Select Bit 1

`#define CLKPS1_BIT 1`

`#define CLKPS1_MASK 2`

##### CLKPS2 - Clock Prescaler Select Bit 2

`#define CLKPS2_BIT 2`

`#define CLKPS2_MASK 4`

##### CLKPS3 - Clock Prescaler Select Bit 3

`#define CLKPS3_BIT 3`

`#define CLKPS3_MASK 8`

##### CLKPCE - Clock Prescaler Change Enable

`#define CLKPCE_BIT 7`

`#define CLKPCE_MASK 128`

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.

### GTCCR - General Timer Counter Control Register

`sfrb GTCCR = $23;`

##### PSR10

`#define PSR10_BIT 0`

`#define PSR10_MASK 1`

### PCMSK - Pin-Change Mask register

`sfrb PCMSK = $20;`

##### PCINT0 - Pin-Change Interrupt 0

`#define PCINT0_BIT 0`

`#define PCINT0_MASK 1`

##### PCINT1 - Pin-Change Interrupt 1

`#define PCINT1_BIT 1`

`#define PCINT1_MASK 2`

##### PCINT2 - Pin-Change Interrupt 2

`#define PCINT2_BIT 2`

`#define PCINT2_MASK 4`

##### PCINT3 - Pin-Change Interrupt 3

`#define PCINT3_BIT 3`

`#define PCINT3_MASK 8`

##### PCINT4 - Pin-Change Interrupt 4

`#define PCINT4_BIT 4`

`#define PCINT4_MASK 16`

##### PCINT5 - Pin-Change Interrupt 5

`#define PCINT5_BIT 5`

`#define PCINT5_MASK 32`

##### PCINT6 - Pin-Change Interrupt 6

`#define PCINT6_BIT 6`

`#define PCINT6_MASK 64`

##### PCINT7 - Pin-Change Interrupt 7

`#define PCINT7_BIT 7`

`#define PCINT7_MASK 128`

### GPIOR2 - General Purpose I/O Register 2

`sfrb GPIOR2 = $15;`

##### GPIOR20 - General Purpose I/O Register 2 bit 0

`#define GPIOR20_BIT 0`

`#define GPIOR20_MASK 1`

##### GPIOR21 - General Purpose I/O Register 2 bit 1

`#define GPIOR21_BIT 1`

`#define GPIOR21_MASK 2`

##### GPIOR22 - General Purpose I/O Register 2 bit 2

`#define GPIOR22_BIT 2`

`#define GPIOR22_MASK 4`

##### GPIOR23 - General Purpose I/O Register 2 bit 3

`#define GPIOR23_BIT 3`

`#define GPIOR23_MASK 8`

##### GPIOR24 - General Purpose I/O Register 2 bit 4

`#define GPIOR24_BIT 4`

`#define GPIOR24_MASK 16`

##### GPIOR25 - General Purpose I/O Register 2 bit 5

`#define GPIOR25_BIT 5`

`#define GPIOR25_MASK 32`

##### GPIOR26 - General Purpose I/O Register 2 bit 6

`#define GPIOR26_BIT 6`

`#define GPIOR26_MASK 64`

##### GPIOR27 - General Purpose I/O Register 2 bit 7

`#define GPIOR27_BIT 7`

`#define GPIOR27_MASK 128`

### GPIOR1 - General Purpose I/O Register 1

`sfrb GPIOR1 = $14;`

##### GPIOR10 - General Purpose I/O Register 1 bit 0

`#define GPIOR10_BIT 0`

`#define GPIOR10_MASK 1`

##### GPIOR11 - General Purpose I/O Register 1 bit 1

`#define GPIOR11_BIT 1`

`#define GPIOR11_MASK 2`

##### GPIOR12 - General Purpose I/O Register 1 bit 2

`#define GPIOR12_BIT 2`

`#define GPIOR12_MASK 4`

##### GPIOR13 - General Purpose I/O Register 1 bit 3

`#define GPIOR13_BIT 3`

`#define GPIOR13_MASK 8`

##### GPIOR14 - General Purpose I/O Register 1 bit 4

`#define GPIOR14_BIT 4`

`#define GPIOR14_MASK 16`

##### GPIOR15 - General Purpose I/O Register 1 bit 5

`#define GPIOR15_BIT 5`

`#define GPIOR15_MASK 32`

##### GPIOR16 - General Purpose I/O Register 1 bit 6

`#define GPIOR16_BIT 6`

`#define GPIOR16_MASK 64`

##### GPIOR17 - General Purpose I/O Register 1 bit 7

`#define GPIOR17_BIT 7`

`#define GPIOR17_MASK 128`

### GPIOR0 - General Purpose I/O Register 0

`sfrb GPIOR0 = $13;`

##### GPIOR00 - General Purpose I/O Register 0 bit 0

`#define GPIOR00_BIT 0`

`#define GPIOR00_MASK 1`

##### GPIOR01 - General Purpose I/O Register 0 bit 1

`#define GPIOR01_BIT 1`

`#define GPIOR01_MASK 2`

##### GPIOR02 - General Purpose I/O Register 0 bit 2

`#define GPIOR02_BIT 2`

`#define GPIOR02_MASK 4`

##### GPIOR03 - General Purpose I/O Register 0 bit 3

`#define GPIOR03_BIT 3`

`#define GPIOR03_MASK 8`

##### GPIOR04 - General Purpose I/O Register 0 bit 4

`#define GPIOR04_BIT 4`

`#define GPIOR04_MASK 16`

##### GPIOR05 - General Purpose I/O Register 0 bit 5

`#define GPIOR05_BIT 5`

`#define GPIOR05_MASK 32`

##### GPIOR06 - General Purpose I/O Register 0 bit 6

`#define GPIOR06_BIT 6`

`#define GPIOR06_MASK 64`

##### GPIOR07 - General Purpose I/O Register 0 bit 7

`#define GPIOR07_BIT 7`

`#define GPIOR07_MASK 128`

## USI

Universal Serial Interface

### USIDR - USI Data Register

`sfrb USIDR = $0F;`

##### USIDR0 - USI Data Register bit 0

`#define USIDR0_BIT 0`

`#define USIDR0_MASK 1`

##### USIDR1 - USI Data Register bit 1

`#define USIDR1_BIT 1`

`#define USIDR1_MASK 2`

##### USIDR2 - USI Data Register bit 2

`#define USIDR2_BIT 2`

`#define USIDR2_MASK 4`

##### USIDR3 - USI Data Register bit 3

`#define USIDR3_BIT 3`

`#define USIDR3_MASK 8`

##### USIDR4 - USI Data Register bit 4

`#define USIDR4_BIT 4`

`#define USIDR4_MASK 16`

##### USIDR5 - USI Data Register bit 5

`#define USIDR5_BIT 5`

`#define USIDR5_MASK 32`

##### USIDR6 - USI Data Register bit 6

`#define USIDR6_BIT 6`

`#define USIDR6_MASK 64`

##### USIDR7 - USI Data Register bit 7

`#define USIDR7_BIT 7`

`#define USIDR7_MASK 128`

### USISR - USI Status Register

`sfrb USISR = $0E;`

##### USICNT0 - USI Counter Value Bit 0

`#define USICNT0_BIT 0`

`#define USICNT0_MASK 1`

##### USICNT1 - USI Counter Value Bit 1

`#define USICNT1_BIT 1`

`#define USICNT1_MASK 2`

##### USICNT2 - USI Counter Value Bit 2

`#define USICNT2_BIT 2`

`#define USICNT2_MASK 4`

##### USICNT3 - USI Counter Value Bit 3

`#define USICNT3_BIT 3`

`#define USICNT3_MASK 8`

##### USIDC - Data Output Collision

`#define USIDC_BIT 4`

`#define USIDC_MASK 16`

##### USIPF - Stop Condition Flag

`#define USIPF_BIT 5`

`#define USIPF_MASK 32`

##### USIOIF - Counter Overflow Interrupt Flag

`#define USIOIF_BIT 6`

`#define USIOIF_MASK 64`

##### USISIF - Start Condition Interrupt Flag

`#define USISIF_BIT 7`

`#define USISIF_MASK 128`

### USICR - USI Control Register

`sfrb USICR = $0D;`

##### USITC - Toggle Clock Port Pin

`#define USITC_BIT 0`

`#define USITC_MASK 1`

##### USICLK - Clock Strobe

`#define USICLK_BIT 1`

`#define USICLK_MASK 2`

##### USICS0 - USI Clock Source Select Bit 0

`#define USICS0_BIT 2`

`#define USICS0_MASK 4`

##### USICS1 - USI Clock Source Select Bit 1

`#define USICS1_BIT 3`

`#define USICS1_MASK 8`

##### USIWM0 - USI Wire Mode Bit 0

`#define USIWM0_BIT 4`

`#define USIWM0_MASK 16`

##### USIWM1 - USI Wire Mode Bit 1

`#define USIWM1_BIT 5`

`#define USIWM1_MASK 32`

##### USIOIE - Counter Overflow Interrupt Enable

`#define USIOIE_BIT 6`

`#define USIOIE_MASK 64`

##### USISIE - Start Condition Interrupt Enable

`#define USISIE_BIT 7`

`#define USISIE_MASK 128`