    #ifndef __ATmega32_h
    #define __ATmega32_h

    // Interrupt vectors

    #define RESET_vect 0x0000
    #define INT0_vect 0x0004
    #define INT1_vect 0x0008
    #define INT2_vect 0x000c
    #define TIMER2_COMP_vect 0x0010
    #define TIMER2_OVF_vect 0x0014
    #define TIMER1_CAPT_vect 0x0018
    #define TIMER1_COMPA_vect 0x001c
    #define TIMER1_COMPB_vect 0x0020
    #define TIMER1_OVF_vect 0x0024
    #define TIMER0_COMP_vect 0x0028
    #define TIMER0_OVF_vect 0x002c
    #define SPI_STC_vect 0x0030
    #define USART_RXC_vect 0x0034
    #define USART_UDRE_vect 0x0038
    #define USART_TXC_vect 0x003c
    #define ADC_vect 0x0040
    #define EE_RDY_vect 0x0044
    #define ANA_COMP_vect 0x0048
    #define TWI_vect 0x004c
    #define SPM_RDY_vect 0x0050

    // I/O addresses

    sfrb SREG = 0x5f;

    sfrb SPH = 0x5e;
    #define SP8 0
    #define SP8_BIT 0
    #define SP8_MASK 1
    #define SP9 1
    #define SP9_BIT 1
    #define SP9_MASK 2
    #define SP10 2
    #define SP10_BIT 2
    #define SP10_MASK 4
    #define SP11 3
    #define SP11_BIT 3
    #define SP11_MASK 8

    sfrb SPL = 0x5d;
    #define SP0 0
    #define SP0_BIT 0
    #define SP0_MASK 1
    #define SP1 1
    #define SP1_BIT 1
    #define SP1_MASK 2
    #define SP2 2
    #define SP2_BIT 2
    #define SP2_MASK 4
    #define SP3 3
    #define SP3_BIT 3
    #define SP3_MASK 8
    #define SP4 4
    #define SP4_BIT 4
    #define SP4_MASK 16
    #define SP5 5
    #define SP5_BIT 5
    #define SP5_MASK 32
    #define SP6 6
    #define SP6_BIT 6
    #define SP6_MASK 64
    #define SP7 7
    #define SP7_BIT 7
    #define SP7_MASK 128

    sfrw SPW = 0x5d;

    sfrb OCR0 = 0x5c;
    #define OCR0_0 0
    #define OCR0_0_BIT 0
    #define OCR0_0_MASK 1
    #define OCR0_1 1
    #define OCR0_1_BIT 1
    #define OCR0_1_MASK 2
    #define OCR0_2 2
    #define OCR0_2_BIT 2
    #define OCR0_2_MASK 4
    #define OCR0_3 3
    #define OCR0_3_BIT 3
    #define OCR0_3_MASK 8
    #define OCR0_4 4
    #define OCR0_4_BIT 4
    #define OCR0_4_MASK 16
    #define OCR0_5 5
    #define OCR0_5_BIT 5
    #define OCR0_5_MASK 32
    #define OCR0_6 6
    #define OCR0_6_BIT 6
    #define OCR0_6_MASK 64
    #define OCR0_7 7
    #define OCR0_7_BIT 7
    #define OCR0_7_MASK 128

    sfrb GICR = 0x5b;
    #define IVCE 0
    #define IVCE_BIT 0
    #define IVCE_MASK 1
    #define IVSEL 1
    #define IVSEL_BIT 1
    #define IVSEL_MASK 2
    #define INT2 5
    #define INT2_BIT 5
    #define INT2_MASK 32
    #define INT0 6
    #define INT0_BIT 6
    #define INT0_MASK 64
    #define INT1 7
    #define INT1_BIT 7
    #define INT1_MASK 128

    sfrb GIFR = 0x5a;
    #define INTF2 5
    #define INTF2_BIT 5
    #define INTF2_MASK 32
    #define INTF0 6
    #define INTF0_BIT 6
    #define INTF0_MASK 64
    #define INTF1 7
    #define INTF1_BIT 7
    #define INTF1_MASK 128

    sfrb TIMSK = 0x59;
    #define TOIE0 0
    #define TOIE0_BIT 0
    #define TOIE0_MASK 1
    #define OCIE0 1
    #define OCIE0_BIT 1
    #define OCIE0_MASK 2
    #define TOIE1 2
    #define TOIE1_BIT 2
    #define TOIE1_MASK 4
    #define OCIE1B 3
    #define OCIE1B_BIT 3
    #define OCIE1B_MASK 8
    #define OCIE1A 4
    #define OCIE1A_BIT 4
    #define OCIE1A_MASK 16
    #define TICIE1 5
    #define TICIE1_BIT 5
    #define TICIE1_MASK 32
    #define TOIE2 6
    #define TOIE2_BIT 6
    #define TOIE2_MASK 64
    #define OCIE2 7
    #define OCIE2_BIT 7
    #define OCIE2_MASK 128

    sfrb TIFR = 0x58;
    #define TOV0 0
    #define TOV0_BIT 0
    #define TOV0_MASK 1
    #define OCF0 1
    #define OCF0_BIT 1
    #define OCF0_MASK 2
    #define TOV1 2
    #define TOV1_BIT 2
    #define TOV1_MASK 4
    #define OCF1B 3
    #define OCF1B_BIT 3
    #define OCF1B_MASK 8
    #define OCF1A 4
    #define OCF1A_BIT 4
    #define OCF1A_MASK 16
    #define ICF1 5
    #define ICF1_BIT 5
    #define ICF1_MASK 32
    #define TOV2 6
    #define TOV2_BIT 6
    #define TOV2_MASK 64
    #define OCF2 7
    #define OCF2_BIT 7
    #define OCF2_MASK 128

    sfrb SPMCR = 0x57;
    #define SPMEN 0
    #define SPMEN_BIT 0
    #define SPMEN_MASK 1
    #define PGERS 1
    #define PGERS_BIT 1
    #define PGERS_MASK 2
    #define PGWRT 2
    #define PGWRT_BIT 2
    #define PGWRT_MASK 4
    #define BLBSET 3
    #define BLBSET_BIT 3
    #define BLBSET_MASK 8
    #define RWWSRE 4
    #define RWWSRE_BIT 4
    #define RWWSRE_MASK 16
    #define RWWSB 6
    #define RWWSB_BIT 6
    #define RWWSB_MASK 64
    #define SPMIE 7
    #define SPMIE_BIT 7
    #define SPMIE_MASK 128

    sfrb TWCR = 0x56;
    #define TWIE 0
    #define TWIE_BIT 0
    #define TWIE_MASK 1
    #define TWEN 2
    #define TWEN_BIT 2
    #define TWEN_MASK 4
    #define TWWC 3
    #define TWWC_BIT 3
    #define TWWC_MASK 8
    #define TWSTO 4
    #define TWSTO_BIT 4
    #define TWSTO_MASK 16
    #define TWSTA 5
    #define TWSTA_BIT 5
    #define TWSTA_MASK 32
    #define TWEA 6
    #define TWEA_BIT 6
    #define TWEA_MASK 64
    #define TWINT 7
    #define TWINT_BIT 7
    #define TWINT_MASK 128

    sfrb MCUCR = 0x55;
    #define ISC00 0
    #define ISC00_BIT 0
    #define ISC00_MASK 1
    #define ISC01 1
    #define ISC01_BIT 1
    #define ISC01_MASK 2
    #define ISC10 2
    #define ISC10_BIT 2
    #define ISC10_MASK 4
    #define ISC11 3
    #define ISC11_BIT 3
    #define ISC11_MASK 8
    #define SM0 4
    #define SM0_BIT 4
    #define SM0_MASK 16
    #define SM1 5
    #define SM1_BIT 5
    #define SM1_MASK 32
    #define SM2 6
    #define SM2_BIT 6
    #define SM2_MASK 64
    #define SE 7
    #define SE_BIT 7
    #define SE_MASK 128

    sfrb MCUCSR = 0x54;
    #define PORF 0
    #define PORF_BIT 0
    #define PORF_MASK 1
    #define EXTRF 1
    #define EXTRF_BIT 1
    #define EXTRF_MASK 2
    #define BORF 2
    #define BORF_BIT 2
    #define BORF_MASK 4
    #define WDRF 3
    #define WDRF_BIT 3
    #define WDRF_MASK 8
    #define JTRF 4
    #define JTRF_BIT 4
    #define JTRF_MASK 16
    #define ISC2 6
    #define ISC2_BIT 6
    #define ISC2_MASK 64
    #define JTD 7
    #define JTD_BIT 7
    #define JTD_MASK 128

    sfrb TCCR0 = 0x53;
    #define CS00 0
    #define CS00_BIT 0
    #define CS00_MASK 1
    #define CS01 1
    #define CS01_BIT 1
    #define CS01_MASK 2
    #define CS02 2
    #define CS02_BIT 2
    #define CS02_MASK 4
    #define WGM01 3
    #define WGM01_BIT 3
    #define WGM01_MASK 8
    #define COM00 4
    #define COM00_BIT 4
    #define COM00_MASK 16
    #define COM01 5
    #define COM01_BIT 5
    #define COM01_MASK 32
    #define WGM00 6
    #define WGM00_BIT 6
    #define WGM00_MASK 64
    #define FOC0 7
    #define FOC0_BIT 7
    #define FOC0_MASK 128

    sfrb TCNT0 = 0x52;
    #define TCNT0_0 0
    #define TCNT0_0_BIT 0
    #define TCNT0_0_MASK 1
    #define TCNT0_1 1
    #define TCNT0_1_BIT 1
    #define TCNT0_1_MASK 2
    #define TCNT0_2 2
    #define TCNT0_2_BIT 2
    #define TCNT0_2_MASK 4
    #define TCNT0_3 3
    #define TCNT0_3_BIT 3
    #define TCNT0_3_MASK 8
    #define TCNT0_4 4
    #define TCNT0_4_BIT 4
    #define TCNT0_4_MASK 16
    #define TCNT0_5 5
    #define TCNT0_5_BIT 5
    #define TCNT0_5_MASK 32
    #define TCNT0_6 6
    #define TCNT0_6_BIT 6
    #define TCNT0_6_MASK 64
    #define TCNT0_7 7
    #define TCNT0_7_BIT 7
    #define TCNT0_7_MASK 128

    sfrb OSCCAL = 0x51;
    #define CAL0 0
    #define CAL0_BIT 0
    #define CAL0_MASK 1
    #define CAL1 1
    #define CAL1_BIT 1
    #define CAL1_MASK 2
    #define CAL2 2
    #define CAL2_BIT 2
    #define CAL2_MASK 4
    #define CAL3 3
    #define CAL3_BIT 3
    #define CAL3_MASK 8
    #define CAL4 4
    #define CAL4_BIT 4
    #define CAL4_MASK 16
    #define CAL5 5
    #define CAL5_BIT 5
    #define CAL5_MASK 32
    #define CAL6 6
    #define CAL6_BIT 6
    #define CAL6_MASK 64
    #define CAL7 7
    #define CAL7_BIT 7
    #define CAL7_MASK 128

    sfrb OCDR = 0x51;

    sfrb SFIOR = 0x50;
    #define PSR10 0
    #define PSR10_BIT 0
    #define PSR10_MASK 1
    #define PSR2 1
    #define PSR2_BIT 1
    #define PSR2_MASK 2
    #define PUD 2
    #define PUD_BIT 2
    #define PUD_MASK 4
    #define ACME 3
    #define ACME_BIT 3
    #define ACME_MASK 8
    #define ADTS0 5
    #define ADTS0_BIT 5
    #define ADTS0_MASK 32
    #define ADTS1 6
    #define ADTS1_BIT 6
    #define ADTS1_MASK 64
    #define ADTS2 7
    #define ADTS2_BIT 7
    #define ADTS2_MASK 128

    sfrb TCCR1A = 0x4f;
    #define WGM10 0
    #define WGM10_BIT 0
    #define WGM10_MASK 1
    #define WGM11 1
    #define WGM11_BIT 1
    #define WGM11_MASK 2
    #define FOC1B 2
    #define FOC1B_BIT 2
    #define FOC1B_MASK 4
    #define FOC1A 3
    #define FOC1A_BIT 3
    #define FOC1A_MASK 8
    #define COM1B0 4
    #define COM1B0_BIT 4
    #define COM1B0_MASK 16
    #define COM1B1 5
    #define COM1B1_BIT 5
    #define COM1B1_MASK 32
    #define COM1A0 6
    #define COM1A0_BIT 6
    #define COM1A0_MASK 64
    #define COM1A1 7
    #define COM1A1_BIT 7
    #define COM1A1_MASK 128

    sfrb TCCR1B = 0x4e;
    #define CS10 0
    #define CS10_BIT 0
    #define CS10_MASK 1
    #define CS11 1
    #define CS11_BIT 1
    #define CS11_MASK 2
    #define CS12 2
    #define CS12_BIT 2
    #define CS12_MASK 4
    #define WGM12 3
    #define WGM12_BIT 3
    #define WGM12_MASK 8
    #define WGM13 4
    #define WGM13_BIT 4
    #define WGM13_MASK 16
    #define ICES1 6
    #define ICES1_BIT 6
    #define ICES1_MASK 64
    #define ICNC1 7
    #define ICNC1_BIT 7
    #define ICNC1_MASK 128

    sfrb TCNT1H = 0x4d;
    #define TCNT1H0 0
    #define TCNT1H0_BIT 0
    #define TCNT1H0_MASK 1
    #define TCNT1H1 1
    #define TCNT1H1_BIT 1
    #define TCNT1H1_MASK 2
    #define TCNT1H2 2
    #define TCNT1H2_BIT 2
    #define TCNT1H2_MASK 4
    #define TCNT1H3 3
    #define TCNT1H3_BIT 3
    #define TCNT1H3_MASK 8
    #define TCNT1H4 4
    #define TCNT1H4_BIT 4
    #define TCNT1H4_MASK 16
    #define TCNT1H5 5
    #define TCNT1H5_BIT 5
    #define TCNT1H5_MASK 32
    #define TCNT1H6 6
    #define TCNT1H6_BIT 6
    #define TCNT1H6_MASK 64
    #define TCNT1H7 7
    #define TCNT1H7_BIT 7
    #define TCNT1H7_MASK 128

    sfrb TCNT1L = 0x4c;
    #define TCNT1L0 0
    #define TCNT1L0_BIT 0
    #define TCNT1L0_MASK 1
    #define TCNT1L1 1
    #define TCNT1L1_BIT 1
    #define TCNT1L1_MASK 2
    #define TCNT1L2 2
    #define TCNT1L2_BIT 2
    #define TCNT1L2_MASK 4
    #define TCNT1L3 3
    #define TCNT1L3_BIT 3
    #define TCNT1L3_MASK 8
    #define TCNT1L4 4
    #define TCNT1L4_BIT 4
    #define TCNT1L4_MASK 16
    #define TCNT1L5 5
    #define TCNT1L5_BIT 5
    #define TCNT1L5_MASK 32
    #define TCNT1L6 6
    #define TCNT1L6_BIT 6
    #define TCNT1L6_MASK 64
    #define TCNT1L7 7
    #define TCNT1L7_BIT 7
    #define TCNT1L7_MASK 128

    sfrw TCNT1W = 0x4c;

    sfrb OCR1AH = 0x4b;
    #define OCR1AH0 0
    #define OCR1AH0_BIT 0
    #define OCR1AH0_MASK 1
    #define OCR1AH1 1
    #define OCR1AH1_BIT 1
    #define OCR1AH1_MASK 2
    #define OCR1AH2 2
    #define OCR1AH2_BIT 2
    #define OCR1AH2_MASK 4
    #define OCR1AH3 3
    #define OCR1AH3_BIT 3
    #define OCR1AH3_MASK 8
    #define OCR1AH4 4
    #define OCR1AH4_BIT 4
    #define OCR1AH4_MASK 16
    #define OCR1AH5 5
    #define OCR1AH5_BIT 5
    #define OCR1AH5_MASK 32
    #define OCR1AH6 6
    #define OCR1AH6_BIT 6
    #define OCR1AH6_MASK 64
    #define OCR1AH7 7
    #define OCR1AH7_BIT 7
    #define OCR1AH7_MASK 128

    sfrb OCR1AL = 0x4a;
    #define OCR1AL0 0
    #define OCR1AL0_BIT 0
    #define OCR1AL0_MASK 1
    #define OCR1AL1 1
    #define OCR1AL1_BIT 1
    #define OCR1AL1_MASK 2
    #define OCR1AL2 2
    #define OCR1AL2_BIT 2
    #define OCR1AL2_MASK 4
    #define OCR1AL3 3
    #define OCR1AL3_BIT 3
    #define OCR1AL3_MASK 8
    #define OCR1AL4 4
    #define OCR1AL4_BIT 4
    #define OCR1AL4_MASK 16
    #define OCR1AL5 5
    #define OCR1AL5_BIT 5
    #define OCR1AL5_MASK 32
    #define OCR1AL6 6
    #define OCR1AL6_BIT 6
    #define OCR1AL6_MASK 64
    #define OCR1AL7 7
    #define OCR1AL7_BIT 7
    #define OCR1AL7_MASK 128

    sfrw OCR1AW = 0x4a;

    sfrb OCR1BH = 0x49;
    #define OCR1BH0 0
    #define OCR1BH0_BIT 0
    #define OCR1BH0_MASK 1
    #define OCR1BH1 1
    #define OCR1BH1_BIT 1
    #define OCR1BH1_MASK 2
    #define OCR1BH2 2
    #define OCR1BH2_BIT 2
    #define OCR1BH2_MASK 4
    #define OCR1BH3 3
    #define OCR1BH3_BIT 3
    #define OCR1BH3_MASK 8
    #define OCR1BH4 4
    #define OCR1BH4_BIT 4
    #define OCR1BH4_MASK 16
    #define OCR1BH5 5
    #define OCR1BH5_BIT 5
    #define OCR1BH5_MASK 32
    #define OCR1BH6 6
    #define OCR1BH6_BIT 6
    #define OCR1BH6_MASK 64
    #define OCR1BH7 7
    #define OCR1BH7_BIT 7
    #define OCR1BH7_MASK 128

    sfrb OCR1BL = 0x48;
    #define OCR1BL0 0
    #define OCR1BL0_BIT 0
    #define OCR1BL0_MASK 1
    #define OCR1BL1 1
    #define OCR1BL1_BIT 1
    #define OCR1BL1_MASK 2
    #define OCR1BL2 2
    #define OCR1BL2_BIT 2
    #define OCR1BL2_MASK 4
    #define OCR1BL3 3
    #define OCR1BL3_BIT 3
    #define OCR1BL3_MASK 8
    #define OCR1BL4 4
    #define OCR1BL4_BIT 4
    #define OCR1BL4_MASK 16
    #define OCR1BL5 5
    #define OCR1BL5_BIT 5
    #define OCR1BL5_MASK 32
    #define OCR1BL6 6
    #define OCR1BL6_BIT 6
    #define OCR1BL6_MASK 64
    #define OCR1BL7 7
    #define OCR1BL7_BIT 7
    #define OCR1BL7_MASK 128

    sfrw OCR1BW = 0x48;

    sfrb ICR1H = 0x47;
    #define ICR1H0 0
    #define ICR1H0_BIT 0
    #define ICR1H0_MASK 1
    #define ICR1H1 1
    #define ICR1H1_BIT 1
    #define ICR1H1_MASK 2
    #define ICR1H2 2
    #define ICR1H2_BIT 2
    #define ICR1H2_MASK 4
    #define ICR1H3 3
    #define ICR1H3_BIT 3
    #define ICR1H3_MASK 8
    #define ICR1H4 4
    #define ICR1H4_BIT 4
    #define ICR1H4_MASK 16
    #define ICR1H5 5
    #define ICR1H5_BIT 5
    #define ICR1H5_MASK 32
    #define ICR1H6 6
    #define ICR1H6_BIT 6
    #define ICR1H6_MASK 64
    #define ICR1H7 7
    #define ICR1H7_BIT 7
    #define ICR1H7_MASK 128

    sfrb ICR1L = 0x46;
    #define ICR1L0 0
    #define ICR1L0_BIT 0
    #define ICR1L0_MASK 1
    #define ICR1L1 1
    #define ICR1L1_BIT 1
    #define ICR1L1_MASK 2
    #define ICR1L2 2
    #define ICR1L2_BIT 2
    #define ICR1L2_MASK 4
    #define ICR1L3 3
    #define ICR1L3_BIT 3
    #define ICR1L3_MASK 8
    #define ICR1L4 4
    #define ICR1L4_BIT 4
    #define ICR1L4_MASK 16
    #define ICR1L5 5
    #define ICR1L5_BIT 5
    #define ICR1L5_MASK 32
    #define ICR1L6 6
    #define ICR1L6_BIT 6
    #define ICR1L6_MASK 64
    #define ICR1L7 7
    #define ICR1L7_BIT 7
    #define ICR1L7_MASK 128

    sfrw ICR1W = 0x46;

    sfrb TCCR2 = 0x45;
    #define CS20 0
    #define CS20_BIT 0
    #define CS20_MASK 1
    #define CS21 1
    #define CS21_BIT 1
    #define CS21_MASK 2
    #define CS22 2
    #define CS22_BIT 2
    #define CS22_MASK 4
    #define WGM21 3
    #define WGM21_BIT 3
    #define WGM21_MASK 8
    #define COM20 4
    #define COM20_BIT 4
    #define COM20_MASK 16
    #define COM21 5
    #define COM21_BIT 5
    #define COM21_MASK 32
    #define WGM20 6
    #define WGM20_BIT 6
    #define WGM20_MASK 64
    #define FOC2 7
    #define FOC2_BIT 7
    #define FOC2_MASK 128

    sfrb TCNT2 = 0x44;
    #define TCNT2_0 0
    #define TCNT2_0_BIT 0
    #define TCNT2_0_MASK 1
    #define TCNT2_1 1
    #define TCNT2_1_BIT 1
    #define TCNT2_1_MASK 2
    #define TCNT2_2 2
    #define TCNT2_2_BIT 2
    #define TCNT2_2_MASK 4
    #define TCNT2_3 3
    #define TCNT2_3_BIT 3
    #define TCNT2_3_MASK 8
    #define TCNT2_4 4
    #define TCNT2_4_BIT 4
    #define TCNT2_4_MASK 16
    #define TCNT2_5 5
    #define TCNT2_5_BIT 5
    #define TCNT2_5_MASK 32
    #define TCNT2_6 6
    #define TCNT2_6_BIT 6
    #define TCNT2_6_MASK 64
    #define TCNT2_7 7
    #define TCNT2_7_BIT 7
    #define TCNT2_7_MASK 128

    sfrb OCR2 = 0x43;
    #define OCR2_0 0
    #define OCR2_0_BIT 0
    #define OCR2_0_MASK 1
    #define OCR2_1 1
    #define OCR2_1_BIT 1
    #define OCR2_1_MASK 2
    #define OCR2_2 2
    #define OCR2_2_BIT 2
    #define OCR2_2_MASK 4
    #define OCR2_3 3
    #define OCR2_3_BIT 3
    #define OCR2_3_MASK 8
    #define OCR2_4 4
    #define OCR2_4_BIT 4
    #define OCR2_4_MASK 16
    #define OCR2_5 5
    #define OCR2_5_BIT 5
    #define OCR2_5_MASK 32
    #define OCR2_6 6
    #define OCR2_6_BIT 6
    #define OCR2_6_MASK 64
    #define OCR2_7 7
    #define OCR2_7_BIT 7
    #define OCR2_7_MASK 128

    sfrb ASSR = 0x42;
    #define TCR2UB 0
    #define TCR2UB_BIT 0
    #define TCR2UB_MASK 1
    #define OCR2UB 1
    #define OCR2UB_BIT 1
    #define OCR2UB_MASK 2
    #define TCN2UB 2
    #define TCN2UB_BIT 2
    #define TCN2UB_MASK 4
    #define AS2 3
    #define AS2_BIT 3
    #define AS2_MASK 8

    sfrb WDTCR = 0x41;
    #define WDP0 0
    #define WDP0_BIT 0
    #define WDP0_MASK 1
    #define WDP1 1
    #define WDP1_BIT 1
    #define WDP1_MASK 2
    #define WDP2 2
    #define WDP2_BIT 2
    #define WDP2_MASK 4
    #define WDE 3
    #define WDE_BIT 3
    #define WDE_MASK 8
    #define WDTOE 4
    #define WDTOE_BIT 4
    #define WDTOE_MASK 16

    sfrb UBRRH = 0x40;
    #define UBRR8 0
    #define UBRR8_BIT 0
    #define UBRR8_MASK 1
    #define UBRR9 1
    #define UBRR9_BIT 1
    #define UBRR9_MASK 2
    #define UBRR10 2
    #define UBRR10_BIT 2
    #define UBRR10_MASK 4
    #define UBRR11 3
    #define UBRR11_BIT 3
    #define UBRR11_MASK 8

    sfrb UCSRC = 0x40;
    #define UCPOL 0
    #define UCPOL_BIT 0
    #define UCPOL_MASK 1
    #define UCSZ0 1
    #define UCSZ0_BIT 1
    #define UCSZ0_MASK 2
    #define UCSZ1 2
    #define UCSZ1_BIT 2
    #define UCSZ1_MASK 4
    #define USBS 3
    #define USBS_BIT 3
    #define USBS_MASK 8
    #define UPM0 4
    #define UPM0_BIT 4
    #define UPM0_MASK 16
    #define UPM1 5
    #define UPM1_BIT 5
    #define UPM1_MASK 32
    #define UMSEL 6
    #define UMSEL_BIT 6
    #define UMSEL_MASK 64
    #define URSEL 7
    #define URSEL_BIT 7
    #define URSEL_MASK 128

    sfrb EEARH = 0x3f;
    #define EEAR8 0
    #define EEAR8_BIT 0
    #define EEAR8_MASK 1
    #define EEAR9 1
    #define EEAR9_BIT 1
    #define EEAR9_MASK 2

    sfrb EEARL = 0x3e;
    #define EEAR00 0
    #define EEAR00_BIT 0
    #define EEAR00_MASK 1
    #define EEAR1 1
    #define EEAR1_BIT 1
    #define EEAR1_MASK 2
    #define EEAR2 2
    #define EEAR2_BIT 2
    #define EEAR2_MASK 4
    #define EEAR3 3
    #define EEAR3_BIT 3
    #define EEAR3_MASK 8
    #define EEAR4 4
    #define EEAR4_BIT 4
    #define EEAR4_MASK 16
    #define EEAR5 5
    #define EEAR5_BIT 5
    #define EEAR5_MASK 32
    #define EEAR6 6
    #define EEAR6_BIT 6
    #define EEAR6_MASK 64
    #define EEAR7 7
    #define EEAR7_BIT 7
    #define EEAR7_MASK 128

    sfrw EEARW = 0x3e;

    sfrb EEDR = 0x3d;
    #define EEDR0 0
    #define EEDR0_BIT 0
    #define EEDR0_MASK 1
    #define EEDR1 1
    #define EEDR1_BIT 1
    #define EEDR1_MASK 2
    #define EEDR2 2
    #define EEDR2_BIT 2
    #define EEDR2_MASK 4
    #define EEDR3 3
    #define EEDR3_BIT 3
    #define EEDR3_MASK 8
    #define EEDR4 4
    #define EEDR4_BIT 4
    #define EEDR4_MASK 16
    #define EEDR5 5
    #define EEDR5_BIT 5
    #define EEDR5_MASK 32
    #define EEDR6 6
    #define EEDR6_BIT 6
    #define EEDR6_MASK 64
    #define EEDR7 7
    #define EEDR7_BIT 7
    #define EEDR7_MASK 128

    sfrb EECR = 0x3c;
    #define EERE 0
    #define EERE_BIT 0
    #define EERE_MASK 1
    #define EEWE 1
    #define EEWE_BIT 1
    #define EEWE_MASK 2
    #define EEMWE 2
    #define EEMWE_BIT 2
    #define EEMWE_MASK 4
    #define EERIE 3
    #define EERIE_BIT 3
    #define EERIE_MASK 8

    sfrb PORTA = 0x3b;
    #define PORTA0 0
    #define PORTA0_BIT 0
    #define PORTA0_MASK 1
    #define PORTA1 1
    #define PORTA1_BIT 1
    #define PORTA1_MASK 2
    #define PORTA2 2
    #define PORTA2_BIT 2
    #define PORTA2_MASK 4
    #define PORTA3 3
    #define PORTA3_BIT 3
    #define PORTA3_MASK 8
    #define PORTA4 4
    #define PORTA4_BIT 4
    #define PORTA4_MASK 16
    #define PORTA5 5
    #define PORTA5_BIT 5
    #define PORTA5_MASK 32
    #define PORTA6 6
    #define PORTA6_BIT 6
    #define PORTA6_MASK 64
    #define PORTA7 7
    #define PORTA7_BIT 7
    #define PORTA7_MASK 128

    sfrb DDRA = 0x3a;
    #define DDA0 0
    #define DDA0_BIT 0
    #define DDA0_MASK 1
    #define DDA1 1
    #define DDA1_BIT 1
    #define DDA1_MASK 2
    #define DDA2 2
    #define DDA2_BIT 2
    #define DDA2_MASK 4
    #define DDA3 3
    #define DDA3_BIT 3
    #define DDA3_MASK 8
    #define DDA4 4
    #define DDA4_BIT 4
    #define DDA4_MASK 16
    #define DDA5 5
    #define DDA5_BIT 5
    #define DDA5_MASK 32
    #define DDA6 6
    #define DDA6_BIT 6
    #define DDA6_MASK 64
    #define DDA7 7
    #define DDA7_BIT 7
    #define DDA7_MASK 128

    sfrb PINA = 0x39;
    #define PINA0 0
    #define PINA0_BIT 0
    #define PINA0_MASK 1
    #define PINA1 1
    #define PINA1_BIT 1
    #define PINA1_MASK 2
    #define PINA2 2
    #define PINA2_BIT 2
    #define PINA2_MASK 4
    #define PINA3 3
    #define PINA3_BIT 3
    #define PINA3_MASK 8
    #define PINA4 4
    #define PINA4_BIT 4
    #define PINA4_MASK 16
    #define PINA5 5
    #define PINA5_BIT 5
    #define PINA5_MASK 32
    #define PINA6 6
    #define PINA6_BIT 6
    #define PINA6_MASK 64
    #define PINA7 7
    #define PINA7_BIT 7
    #define PINA7_MASK 128

    sfrb PORTB = 0x38;
    #define PORTB0 0
    #define PORTB0_BIT 0
    #define PORTB0_MASK 1
    #define PORTB1 1
    #define PORTB1_BIT 1
    #define PORTB1_MASK 2
    #define PORTB2 2
    #define PORTB2_BIT 2
    #define PORTB2_MASK 4
    #define PORTB3 3
    #define PORTB3_BIT 3
    #define PORTB3_MASK 8
    #define PORTB4 4
    #define PORTB4_BIT 4
    #define PORTB4_MASK 16
    #define PORTB5 5
    #define PORTB5_BIT 5
    #define PORTB5_MASK 32
    #define PORTB6 6
    #define PORTB6_BIT 6
    #define PORTB6_MASK 64
    #define PORTB7 7
    #define PORTB7_BIT 7
    #define PORTB7_MASK 128

    sfrb DDRB = 0x37;
    #define DDB0 0
    #define DDB0_BIT 0
    #define DDB0_MASK 1
    #define DDB1 1
    #define DDB1_BIT 1
    #define DDB1_MASK 2
    #define DDB2 2
    #define DDB2_BIT 2
    #define DDB2_MASK 4
    #define DDB3 3
    #define DDB3_BIT 3
    #define DDB3_MASK 8
    #define DDB4 4
    #define DDB4_BIT 4
    #define DDB4_MASK 16
    #define DDB5 5
    #define DDB5_BIT 5
    #define DDB5_MASK 32
    #define DDB6 6
    #define DDB6_BIT 6
    #define DDB6_MASK 64
    #define DDB7 7
    #define DDB7_BIT 7
    #define DDB7_MASK 128

    sfrb PINB = 0x36;
    #define PINB0 0
    #define PINB0_BIT 0
    #define PINB0_MASK 1
    #define PINB1 1
    #define PINB1_BIT 1
    #define PINB1_MASK 2
    #define PINB2 2
    #define PINB2_BIT 2
    #define PINB2_MASK 4
    #define PINB3 3
    #define PINB3_BIT 3
    #define PINB3_MASK 8
    #define PINB4 4
    #define PINB4_BIT 4
    #define PINB4_MASK 16
    #define PINB5 5
    #define PINB5_BIT 5
    #define PINB5_MASK 32
    #define PINB6 6
    #define PINB6_BIT 6
    #define PINB6_MASK 64
    #define PINB7 7
    #define PINB7_BIT 7
    #define PINB7_MASK 128

    sfrb PORTC = 0x35;
    #define PORTC0 0
    #define PORTC0_BIT 0
    #define PORTC0_MASK 1
    #define PORTC1 1
    #define PORTC1_BIT 1
    #define PORTC1_MASK 2
    #define PORTC2 2
    #define PORTC2_BIT 2
    #define PORTC2_MASK 4
    #define PORTC3 3
    #define PORTC3_BIT 3
    #define PORTC3_MASK 8
    #define PORTC4 4
    #define PORTC4_BIT 4
    #define PORTC4_MASK 16
    #define PORTC5 5
    #define PORTC5_BIT 5
    #define PORTC5_MASK 32
    #define PORTC6 6
    #define PORTC6_BIT 6
    #define PORTC6_MASK 64
    #define PORTC7 7
    #define PORTC7_BIT 7
    #define PORTC7_MASK 128

    sfrb DDRC = 0x34;
    #define DDC0 0
    #define DDC0_BIT 0
    #define DDC0_MASK 1
    #define DDC1 1
    #define DDC1_BIT 1
    #define DDC1_MASK 2
    #define DDC2 2
    #define DDC2_BIT 2
    #define DDC2_MASK 4
    #define DDC3 3
    #define DDC3_BIT 3
    #define DDC3_MASK 8
    #define DDC4 4
    #define DDC4_BIT 4
    #define DDC4_MASK 16
    #define DDC5 5
    #define DDC5_BIT 5
    #define DDC5_MASK 32
    #define DDC6 6
    #define DDC6_BIT 6
    #define DDC6_MASK 64
    #define DDC7 7
    #define DDC7_BIT 7
    #define DDC7_MASK 128

    sfrb PINC = 0x33;
    #define PINC0 0
    #define PINC0_BIT 0
    #define PINC0_MASK 1
    #define PINC1 1
    #define PINC1_BIT 1
    #define PINC1_MASK 2
    #define PINC2 2
    #define PINC2_BIT 2
    #define PINC2_MASK 4
    #define PINC3 3
    #define PINC3_BIT 3
    #define PINC3_MASK 8
    #define PINC4 4
    #define PINC4_BIT 4
    #define PINC4_MASK 16
    #define PINC5 5
    #define PINC5_BIT 5
    #define PINC5_MASK 32
    #define PINC6 6
    #define PINC6_BIT 6
    #define PINC6_MASK 64
    #define PINC7 7
    #define PINC7_BIT 7
    #define PINC7_MASK 128

    sfrb PORTD = 0x32;
    #define PORTD0 0
    #define PORTD0_BIT 0
    #define PORTD0_MASK 1
    #define PORTD1 1
    #define PORTD1_BIT 1
    #define PORTD1_MASK 2
    #define PORTD2 2
    #define PORTD2_BIT 2
    #define PORTD2_MASK 4
    #define PORTD3 3
    #define PORTD3_BIT 3
    #define PORTD3_MASK 8
    #define PORTD4 4
    #define PORTD4_BIT 4
    #define PORTD4_MASK 16
    #define PORTD5 5
    #define PORTD5_BIT 5
    #define PORTD5_MASK 32
    #define PORTD6 6
    #define PORTD6_BIT 6
    #define PORTD6_MASK 64
    #define PORTD7 7
    #define PORTD7_BIT 7
    #define PORTD7_MASK 128

    sfrb DDRD = 0x31;
    #define DDD0 0
    #define DDD0_BIT 0
    #define DDD0_MASK 1
    #define DDD1 1
    #define DDD1_BIT 1
    #define DDD1_MASK 2
    #define DDD2 2
    #define DDD2_BIT 2
    #define DDD2_MASK 4
    #define DDD3 3
    #define DDD3_BIT 3
    #define DDD3_MASK 8
    #define DDD4 4
    #define DDD4_BIT 4
    #define DDD4_MASK 16
    #define DDD5 5
    #define DDD5_BIT 5
    #define DDD5_MASK 32
    #define DDD6 6
    #define DDD6_BIT 6
    #define DDD6_MASK 64
    #define DDD7 7
    #define DDD7_BIT 7
    #define DDD7_MASK 128

    sfrb PIND = 0x30;
    #define PIND0 0
    #define PIND0_BIT 0
    #define PIND0_MASK 1
    #define PIND1 1
    #define PIND1_BIT 1
    #define PIND1_MASK 2
    #define PIND2 2
    #define PIND2_BIT 2
    #define PIND2_MASK 4
    #define PIND3 3
    #define PIND3_BIT 3
    #define PIND3_MASK 8
    #define PIND4 4
    #define PIND4_BIT 4
    #define PIND4_MASK 16
    #define PIND5 5
    #define PIND5_BIT 5
    #define PIND5_MASK 32
    #define PIND6 6
    #define PIND6_BIT 6
    #define PIND6_MASK 64
    #define PIND7 7
    #define PIND7_BIT 7
    #define PIND7_MASK 128

    sfrb SPDR = 0x2f;
    #define SPDR0 0
    #define SPDR0_BIT 0
    #define SPDR0_MASK 1
    #define SPDR1 1
    #define SPDR1_BIT 1
    #define SPDR1_MASK 2
    #define SPDR2 2
    #define SPDR2_BIT 2
    #define SPDR2_MASK 4
    #define SPDR3 3
    #define SPDR3_BIT 3
    #define SPDR3_MASK 8
    #define SPDR4 4
    #define SPDR4_BIT 4
    #define SPDR4_MASK 16
    #define SPDR5 5
    #define SPDR5_BIT 5
    #define SPDR5_MASK 32
    #define SPDR6 6
    #define SPDR6_BIT 6
    #define SPDR6_MASK 64
    #define SPDR7 7
    #define SPDR7_BIT 7
    #define SPDR7_MASK 128

    sfrb SPSR = 0x2e;
    #define SPI2X 0
    #define SPI2X_BIT 0
    #define SPI2X_MASK 1
    #define WCOL 6
    #define WCOL_BIT 6
    #define WCOL_MASK 64
    #define SPIF 7
    #define SPIF_BIT 7
    #define SPIF_MASK 128

    sfrb SPCR = 0x2d;
    #define SPR0 0
    #define SPR0_BIT 0
    #define SPR0_MASK 1
    #define SPR1 1
    #define SPR1_BIT 1
    #define SPR1_MASK 2
    #define CPHA 2
    #define CPHA_BIT 2
    #define CPHA_MASK 4
    #define CPOL 3
    #define CPOL_BIT 3
    #define CPOL_MASK 8
    #define MSTR 4
    #define MSTR_BIT 4
    #define MSTR_MASK 16
    #define DORD 5
    #define DORD_BIT 5
    #define DORD_MASK 32
    #define SPE 6
    #define SPE_BIT 6
    #define SPE_MASK 64
    #define SPIE 7
    #define SPIE_BIT 7
    #define SPIE_MASK 128

    sfrb UDR = 0x2c;
    #define UDR0 0
    #define UDR0_BIT 0
    #define UDR0_MASK 1
    #define UDR1 1
    #define UDR1_BIT 1
    #define UDR1_MASK 2
    #define UDR2 2
    #define UDR2_BIT 2
    #define UDR2_MASK 4
    #define UDR3 3
    #define UDR3_BIT 3
    #define UDR3_MASK 8
    #define UDR4 4
    #define UDR4_BIT 4
    #define UDR4_MASK 16
    #define UDR5 5
    #define UDR5_BIT 5
    #define UDR5_MASK 32
    #define UDR6 6
    #define UDR6_BIT 6
    #define UDR6_MASK 64
    #define UDR7 7
    #define UDR7_BIT 7
    #define UDR7_MASK 128

    sfrb UCSRA = 0x2b;
    #define MPCM 0
    #define MPCM_BIT 0
    #define MPCM_MASK 1
    #define U2X 1
    #define U2X_BIT 1
    #define U2X_MASK 2
    #define UPE 2
    #define UPE_BIT 2
    #define UPE_MASK 4
    #define DOR 3
    #define DOR_BIT 3
    #define DOR_MASK 8
    #define FE 4
    #define FE_BIT 4
    #define FE_MASK 16
    #define UDRE 5
    #define UDRE_BIT 5
    #define UDRE_MASK 32
    #define TXC 6
    #define TXC_BIT 6
    #define TXC_MASK 64
    #define RXC 7
    #define RXC_BIT 7
    #define RXC_MASK 128

    sfrb UCSRB = 0x2a;
    #define TXB8 0
    #define TXB8_BIT 0
    #define TXB8_MASK 1
    #define RXB8 1
    #define RXB8_BIT 1
    #define RXB8_MASK 2
    #define UCSZ2 2
    #define UCSZ2_BIT 2
    #define UCSZ2_MASK 4
    #define TXEN 3
    #define TXEN_BIT 3
    #define TXEN_MASK 8
    #define RXEN 4
    #define RXEN_BIT 4
    #define RXEN_MASK 16
    #define UDRIE 5
    #define UDRIE_BIT 5
    #define UDRIE_MASK 32
    #define TXCIE 6
    #define TXCIE_BIT 6
    #define TXCIE_MASK 64
    #define RXCIE 7
    #define RXCIE_BIT 7
    #define RXCIE_MASK 128

    sfrb UBRRL = 0x29;
    #define UBRR0 0
    #define UBRR0_BIT 0
    #define UBRR0_MASK 1
    #define UBRR1 1
    #define UBRR1_BIT 1
    #define UBRR1_MASK 2
    #define UBRR2 2
    #define UBRR2_BIT 2
    #define UBRR2_MASK 4
    #define UBRR3 3
    #define UBRR3_BIT 3
    #define UBRR3_MASK 8
    #define UBRR4 4
    #define UBRR4_BIT 4
    #define UBRR4_MASK 16
    #define UBRR5 5
    #define UBRR5_BIT 5
    #define UBRR5_MASK 32
    #define UBRR6 6
    #define UBRR6_BIT 6
    #define UBRR6_MASK 64
    #define UBRR7 7
    #define UBRR7_BIT 7
    #define UBRR7_MASK 128

    sfrb ACSR = 0x28;
    #define ACIS0 0
    #define ACIS0_BIT 0
    #define ACIS0_MASK 1
    #define ACIS1 1
    #define ACIS1_BIT 1
    #define ACIS1_MASK 2
    #define ACIC 2
    #define ACIC_BIT 2
    #define ACIC_MASK 4
    #define ACIE 3
    #define ACIE_BIT 3
    #define ACIE_MASK 8
    #define ACI 4
    #define ACI_BIT 4
    #define ACI_MASK 16
    #define ACO 5
    #define ACO_BIT 5
    #define ACO_MASK 32
    #define ACBG 6
    #define ACBG_BIT 6
    #define ACBG_MASK 64
    #define ACD 7
    #define ACD_BIT 7
    #define ACD_MASK 128

    sfrb ADMUX = 0x27;
    #define MUX0 0
    #define MUX0_BIT 0
    #define MUX0_MASK 1
    #define MUX1 1
    #define MUX1_BIT 1
    #define MUX1_MASK 2
    #define MUX2 2
    #define MUX2_BIT 2
    #define MUX2_MASK 4
    #define MUX3 3
    #define MUX3_BIT 3
    #define MUX3_MASK 8
    #define MUX4 4
    #define MUX4_BIT 4
    #define MUX4_MASK 16
    #define ADLAR 5
    #define ADLAR_BIT 5
    #define ADLAR_MASK 32
    #define REFS0 6
    #define REFS0_BIT 6
    #define REFS0_MASK 64
    #define REFS1 7
    #define REFS1_BIT 7
    #define REFS1_MASK 128

    sfrb ADCSRA = 0x26;
    #define ADPS0 0
    #define ADPS0_BIT 0
    #define ADPS0_MASK 1
    #define ADPS1 1
    #define ADPS1_BIT 1
    #define ADPS1_MASK 2
    #define ADPS2 2
    #define ADPS2_BIT 2
    #define ADPS2_MASK 4
    #define ADIE 3
    #define ADIE_BIT 3
    #define ADIE_MASK 8
    #define ADIF 4
    #define ADIF_BIT 4
    #define ADIF_MASK 16
    #define ADATE 5
    #define ADATE_BIT 5
    #define ADATE_MASK 32
    #define ADSC 6
    #define ADSC_BIT 6
    #define ADSC_MASK 64
    #define ADEN 7
    #define ADEN_BIT 7
    #define ADEN_MASK 128

    sfrb ADCH = 0x25;
    #define ADCH0 0
    #define ADCH0_BIT 0
    #define ADCH0_MASK 1
    #define ADCH1 1
    #define ADCH1_BIT 1
    #define ADCH1_MASK 2
    #define ADCH2 2
    #define ADCH2_BIT 2
    #define ADCH2_MASK 4
    #define ADCH3 3
    #define ADCH3_BIT 3
    #define ADCH3_MASK 8
    #define ADCH4 4
    #define ADCH4_BIT 4
    #define ADCH4_MASK 16
    #define ADCH5 5
    #define ADCH5_BIT 5
    #define ADCH5_MASK 32
    #define ADCH6 6
    #define ADCH6_BIT 6
    #define ADCH6_MASK 64
    #define ADCH7 7
    #define ADCH7_BIT 7
    #define ADCH7_MASK 128

    sfrb ADCL = 0x24;
    #define ADCL0 0
    #define ADCL0_BIT 0
    #define ADCL0_MASK 1
    #define ADCL1 1
    #define ADCL1_BIT 1
    #define ADCL1_MASK 2
    #define ADCL2 2
    #define ADCL2_BIT 2
    #define ADCL2_MASK 4
    #define ADCL3 3
    #define ADCL3_BIT 3
    #define ADCL3_MASK 8
    #define ADCL4 4
    #define ADCL4_BIT 4
    #define ADCL4_MASK 16
    #define ADCL5 5
    #define ADCL5_BIT 5
    #define ADCL5_MASK 32
    #define ADCL6 6
    #define ADCL6_BIT 6
    #define ADCL6_MASK 64
    #define ADCL7 7
    #define ADCL7_BIT 7
    #define ADCL7_MASK 128

    sfrw ADCW = 0x24;

    sfrb TWDR = 0x23;
    #define TWD0 0
    #define TWD0_BIT 0
    #define TWD0_MASK 1
    #define TWD1 1
    #define TWD1_BIT 1
    #define TWD1_MASK 2
    #define TWD2 2
    #define TWD2_BIT 2
    #define TWD2_MASK 4
    #define TWD3 3
    #define TWD3_BIT 3
    #define TWD3_MASK 8
    #define TWD4 4
    #define TWD4_BIT 4
    #define TWD4_MASK 16
    #define TWD5 5
    #define TWD5_BIT 5
    #define TWD5_MASK 32
    #define TWD6 6
    #define TWD6_BIT 6
    #define TWD6_MASK 64
    #define TWD7 7
    #define TWD7_BIT 7
    #define TWD7_MASK 128

    sfrb TWAR = 0x22;
    #define TWGCE 0
    #define TWGCE_BIT 0
    #define TWGCE_MASK 1
    #define TWA0 1
    #define TWA0_BIT 1
    #define TWA0_MASK 2
    #define TWA1 2
    #define TWA1_BIT 2
    #define TWA1_MASK 4
    #define TWA2 3
    #define TWA2_BIT 3
    #define TWA2_MASK 8
    #define TWA3 4
    #define TWA3_BIT 4
    #define TWA3_MASK 16
    #define TWA4 5
    #define TWA4_BIT 5
    #define TWA4_MASK 32
    #define TWA5 6
    #define TWA5_BIT 6
    #define TWA5_MASK 64
    #define TWA6 7
    #define TWA6_BIT 7
    #define TWA6_MASK 128

    sfrb TWSR = 0x21;
    #define TWPS0 0
    #define TWPS0_BIT 0
    #define TWPS0_MASK 1
    #define TWPS1 1
    #define TWPS1_BIT 1
    #define TWPS1_MASK 2
    #define TWS3 3
    #define TWS3_BIT 3
    #define TWS3_MASK 8
    #define TWS4 4
    #define TWS4_BIT 4
    #define TWS4_MASK 16
    #define TWS5 5
    #define TWS5_BIT 5
    #define TWS5_MASK 32
    #define TWS6 6
    #define TWS6_BIT 6
    #define TWS6_MASK 64
    #define TWS7 7
    #define TWS7_BIT 7
    #define TWS7_MASK 128

    sfrb TWBR = 0x20;
    #define TWBR0 0
    #define TWBR0_BIT 0
    #define TWBR0_MASK 1
    #define TWBR1 1
    #define TWBR1_BIT 1
    #define TWBR1_MASK 2
    #define TWBR2 2
    #define TWBR2_BIT 2
    #define TWBR2_MASK 4
    #define TWBR3 3
    #define TWBR3_BIT 3
    #define TWBR3_MASK 8
    #define TWBR4 4
    #define TWBR4_BIT 4
    #define TWBR4_MASK 16
    #define TWBR5 5
    #define TWBR5_BIT 5
    #define TWBR5_MASK 32
    #define TWBR6 6
    #define TWBR6_BIT 6
    #define TWBR6_MASK 64
    #define TWBR7 7
    #define TWBR7_BIT 7
    #define TWBR7_MASK 128

    #endif