This documentation was generated automatically from the AVR Studio part description file `AT90PWM3B.pdf`.

## PORTB

### PORTB - Port B Data Register

`sfrb PORTB = $05;`

##### PORTB0 - Port B Data Register bit 0

`#define PORTB0_BIT 0`

`#define PORTB0_MASK 1`

##### PORTB1 - Port B Data Register bit 1

`#define PORTB1_BIT 1`

`#define PORTB1_MASK 2`

##### PORTB2 - Port B Data Register bit 2

`#define PORTB2_BIT 2`

`#define PORTB2_MASK 4`

##### PORTB3 - Port B Data Register bit 3

`#define PORTB3_BIT 3`

`#define PORTB3_MASK 8`

##### PORTB4 - Port B Data Register bit 4

`#define PORTB4_BIT 4`

`#define PORTB4_MASK 16`

##### PORTB5 - Port B Data Register bit 5

`#define PORTB5_BIT 5`

`#define PORTB5_MASK 32`

##### PORTB6 - Port B Data Register bit 6

`#define PORTB6_BIT 6`

`#define PORTB6_MASK 64`

##### PORTB7 - Port B Data Register bit 7

`#define PORTB7_BIT 7`

`#define PORTB7_MASK 128`

### DDRB - Port B Data Direction Register

`sfrb DDRB = $04;`

##### DDB0 - Port B Data Direction Register bit 0

`#define DDB0_BIT 0`

`#define DDB0_MASK 1`

##### DDB1 - Port B Data Direction Register bit 1

`#define DDB1_BIT 1`

`#define DDB1_MASK 2`

##### DDB2 - Port B Data Direction Register bit 2

`#define DDB2_BIT 2`

`#define DDB2_MASK 4`

##### DDB3 - Port B Data Direction Register bit 3

`#define DDB3_BIT 3`

`#define DDB3_MASK 8`

##### DDB4 - Port B Data Direction Register bit 4

`#define DDB4_BIT 4`

`#define DDB4_MASK 16`

##### DDB5 - Port B Data Direction Register bit 5

`#define DDB5_BIT 5`

`#define DDB5_MASK 32`

##### DDB6 - Port B Data Direction Register bit 6

`#define DDB6_BIT 6`

`#define DDB6_MASK 64`

##### DDB7 - Port B Data Direction Register bit 7

`#define DDB7_BIT 7`

`#define DDB7_MASK 128`

### PINB - Port B Input Pins

`sfrb PINB = $03;`

##### PINB0 - Port B Input Pins bit 0

`#define PINB0_BIT 0`

`#define PINB0_MASK 1`

##### PINB1 - Port B Input Pins bit 1

`#define PINB1_BIT 1`

`#define PINB1_MASK 2`

##### PINB2 - Port B Input Pins bit 2

`#define PINB2_BIT 2`

`#define PINB2_MASK 4`

##### PINB3 - Port B Input Pins bit 3

`#define PINB3_BIT 3`

`#define PINB3_MASK 8`

##### PINB4 - Port B Input Pins bit 4

`#define PINB4_BIT 4`

`#define PINB4_MASK 16`

##### PINB5 - Port B Input Pins bit 5

`#define PINB5_BIT 5`

`#define PINB5_MASK 32`

##### PINB6 - Port B Input Pins bit 6

`#define PINB6_BIT 6`

`#define PINB6_MASK 64`

##### PINB7 - Port B Input Pins bit 7

`#define PINB7_BIT 7`

`#define PINB7_MASK 128`

## PORTC

### PORTC - Port C Data Register

`sfrb PORTC = $08;`

##### PORTC0 - Port C Data Register bit 0

`#define PORTC0_BIT 0`

`#define PORTC0_MASK 1`

##### PORTC1 - Port C Data Register bit 1

`#define PORTC1_BIT 1`

`#define PORTC1_MASK 2`

##### PORTC2 - Port C Data Register bit 2

`#define PORTC2_BIT 2`

`#define PORTC2_MASK 4`

##### PORTC3 - Port C Data Register bit 3

`#define PORTC3_BIT 3`

`#define PORTC3_MASK 8`

##### PORTC4 - Port C Data Register bit 4

`#define PORTC4_BIT 4`

`#define PORTC4_MASK 16`

##### PORTC5 - Port C Data Register bit 5

`#define PORTC5_BIT 5`

`#define PORTC5_MASK 32`

##### PORTC6 - Port C Data Register bit 6

`#define PORTC6_BIT 6`

`#define PORTC6_MASK 64`

##### PORTC7 - Port C Data Register bit 7

`#define PORTC7_BIT 7`

`#define PORTC7_MASK 128`

### DDRC - Port C Data Direction Register

`sfrb DDRC = $07;`

##### DDC0 - Port C Data Direction Register bit 0

`#define DDC0_BIT 0`

`#define DDC0_MASK 1`

##### DDC1 - Port C Data Direction Register bit 1

`#define DDC1_BIT 1`

`#define DDC1_MASK 2`

##### DDC2 - Port C Data Direction Register bit 2

`#define DDC2_BIT 2`

`#define DDC2_MASK 4`

##### DDC3 - Port C Data Direction Register bit 3

`#define DDC3_BIT 3`

`#define DDC3_MASK 8`

##### DDC4 - Port C Data Direction Register bit 4

`#define DDC4_BIT 4`

`#define DDC4_MASK 16`

##### DDC5 - Port C Data Direction Register bit 5

`#define DDC5_BIT 5`

`#define DDC5_MASK 32`

##### DDC6 - Port C Data Direction Register bit 6

`#define DDC6_BIT 6`

`#define DDC6_MASK 64`

##### DDC7 - Port C Data Direction Register bit 7

`#define DDC7_BIT 7`

`#define DDC7_MASK 128`

### PINC - Port C Input Pins

`sfrb PINC = $06;`

##### PINC0 - Port C Input Pins bit 0

`#define PINC0_BIT 0`

`#define PINC0_MASK 1`

##### PINC1 - Port C Input Pins bit 1

`#define PINC1_BIT 1`

`#define PINC1_MASK 2`

##### PINC2 - Port C Input Pins bit 2

`#define PINC2_BIT 2`

`#define PINC2_MASK 4`

##### PINC3 - Port C Input Pins bit 3

`#define PINC3_BIT 3`

`#define PINC3_MASK 8`

##### PINC4 - Port C Input Pins bit 4

`#define PINC4_BIT 4`

`#define PINC4_MASK 16`

##### PINC5 - Port C Input Pins bit 5

`#define PINC5_BIT 5`

`#define PINC5_MASK 32`

##### PINC6 - Port C Input Pins bit 6

`#define PINC6_BIT 6`

`#define PINC6_MASK 64`

##### PINC7 - Port C Input Pins bit 7

`#define PINC7_BIT 7`

`#define PINC7_MASK 128`

## PORTD

### PORTD - Port D Data Register

`sfrb PORTD = $0B;`

##### PORTD0 - Port D Data Register bit 0

`#define PORTD0_BIT 0`

`#define PORTD0_MASK 1`

##### PORTD1 - Port D Data Register bit 1

`#define PORTD1_BIT 1`

`#define PORTD1_MASK 2`

##### PORTD2 - Port D Data Register bit 2

`#define PORTD2_BIT 2`

`#define PORTD2_MASK 4`

##### PORTD3 - Port D Data Register bit 3

`#define PORTD3_BIT 3`

`#define PORTD3_MASK 8`

##### PORTD4 - Port D Data Register bit 4

`#define PORTD4_BIT 4`

`#define PORTD4_MASK 16`

##### PORTD5 - Port D Data Register bit 5

`#define PORTD5_BIT 5`

`#define PORTD5_MASK 32`

##### PORTD6 - Port D Data Register bit 6

`#define PORTD6_BIT 6`

`#define PORTD6_MASK 64`

##### PORTD7 - Port D Data Register bit 7

`#define PORTD7_BIT 7`

`#define PORTD7_MASK 128`

### DDRD - Port D Data Direction Register

`sfrb DDRD = $0A;`

##### DDD0 - Port D Data Direction Register bit 0

`#define DDD0_BIT 0`

`#define DDD0_MASK 1`

##### DDD1 - Port D Data Direction Register bit 1

`#define DDD1_BIT 1`

`#define DDD1_MASK 2`

##### DDD2 - Port D Data Direction Register bit 2

`#define DDD2_BIT 2`

`#define DDD2_MASK 4`

##### DDD3 - Port D Data Direction Register bit 3

`#define DDD3_BIT 3`

`#define DDD3_MASK 8`

##### DDD4 - Port D Data Direction Register bit 4

`#define DDD4_BIT 4`

`#define DDD4_MASK 16`

##### DDD5 - Port D Data Direction Register bit 5

`#define DDD5_BIT 5`

`#define DDD5_MASK 32`

##### DDD6 - Port D Data Direction Register bit 6

`#define DDD6_BIT 6`

`#define DDD6_MASK 64`

##### DDD7 - Port D Data Direction Register bit 7

`#define DDD7_BIT 7`

`#define DDD7_MASK 128`

### PIND - Port D Input Pins

`sfrb PIND = $09;`

##### PIND0 - Port D Input Pins bit 0

`#define PIND0_BIT 0`

`#define PIND0_MASK 1`

##### PIND1 - Port D Input Pins bit 1

`#define PIND1_BIT 1`

`#define PIND1_MASK 2`

##### PIND2 - Port D Input Pins bit 2

`#define PIND2_BIT 2`

`#define PIND2_MASK 4`

##### PIND3 - Port D Input Pins bit 3

`#define PIND3_BIT 3`

`#define PIND3_MASK 8`

##### PIND4 - Port D Input Pins bit 4

`#define PIND4_BIT 4`

`#define PIND4_MASK 16`

##### PIND5 - Port D Input Pins bit 5

`#define PIND5_BIT 5`

`#define PIND5_MASK 32`

##### PIND6 - Port D Input Pins bit 6

`#define PIND6_BIT 6`

`#define PIND6_MASK 64`

##### PIND7 - Port D Input Pins bit 7

`#define PIND7_BIT 7`

`#define PIND7_MASK 128`

## BOOT LOAD

The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppor

### SPMCSR - Store Program Memory Control Register

`sfrb SPMCSR = $37;`

##### SPMEN - Store Program Memory Enable

`#define SPMEN_BIT 0`

`#define SPMEN_MASK 1`

This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than ?10001?, "01001", "00101", "00011" or "00001" in the lower five bits will have no effec

##### PGERS - Page Erase

`#define PGERS_BIT 1`

`#define PGERS_MASK 2`

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.

##### PGWRT - Page Write

`#define PGWRT_BIT 2`

`#define PGWRT_MASK 4`

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.

##### BLBSET - Boot Lock Bit Set

`#define BLBSET_BIT 3`

`#define BLBSET_MASK 8`

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See ?Reading the Fuse and Lock Bits from Software? on page 235 for details

##### RWWSRE - Read While Write section read enable

`#define RWWSRE_BIT 4`

`#define RWWSRE_MASK 16`

When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lo

##### RWWSB - Read While Write Section Busy

`#define RWWSB_BIT 6`

`#define RWWSB_MASK 64`

When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated.

##### SPMIE - SPM Interrupt Enable

`#define SPMIE_BIT 7`

`#define SPMIE_MASK 128`

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared.

## EUSART

### EUDR - EUSART I/O Data Register

`sfrb EUDR = 0xCE;`

##### EUDR0 - EUSART I/O Data Register bit 0

`#define EUDR0_BIT 0`

`#define EUDR0_MASK 1`

##### EUDR1 - EUSART I/O Data Register bit 1

`#define EUDR1_BIT 1`

`#define EUDR1_MASK 2`

##### EUDR2 - EUSART I/O Data Register bit 2

`#define EUDR2_BIT 2`

`#define EUDR2_MASK 4`

##### EUDR3 - EUSART I/O Data Register bit 3

`#define EUDR3_BIT 3`

`#define EUDR3_MASK 8`

##### EUDR4 - EUSART I/O Data Register bit 4

`#define EUDR4_BIT 4`

`#define EUDR4_MASK 16`

##### EUDR5 - EUSART I/O Data Register bit 5

`#define EUDR5_BIT 5`

`#define EUDR5_MASK 32`

##### EUDR6 - EUSART I/O Data Register bit 6

`#define EUDR6_BIT 6`

`#define EUDR6_MASK 64`

##### EUDR7 - EUSART I/O Data Register bit 7

`#define EUDR7_BIT 7`

`#define EUDR7_MASK 128`

### EUCSRA - EUSART Control and Status Register A

`sfrb EUCSRA = 0xC8;`

##### URxS0 - EUSART Control and Status Register A Bit 0

`#define URxS0_BIT 0`

`#define URxS0_MASK 1`

##### URxS1 - EUSART Control and Status Register A Bit 1

`#define URxS1_BIT 1`

`#define URxS1_MASK 2`

##### URxS2 - EUSART Control and Status Register A Bit 2

`#define URxS2_BIT 2`

`#define URxS2_MASK 4`

##### URxS3 - EUSART Control and Status Register A Bit 3

`#define URxS3_BIT 3`

`#define URxS3_MASK 8`

##### UTxS0 - EUSART Control and Status Register A Bit 4

`#define UTxS0_BIT 4`

`#define UTxS0_MASK 16`

##### UTxS1 - EUSART Control and Status Register A Bit 5

`#define UTxS1_BIT 5`

`#define UTxS1_MASK 32`

##### UTxS2 - EUSART Control and Status Register A Bit 6

`#define UTxS2_BIT 6`

`#define UTxS2_MASK 64`

##### UTxS3 - EUSART Control and Status Register A Bit 7

`#define UTxS3_BIT 7`

`#define UTxS3_MASK 128`

.

### EUCSRB - EUSART Control Register B

`sfrb EUCSRB = 0xC9;`

##### BODR - Order Bit

`#define BODR_BIT 0`

`#define BODR_MASK 1`

##### EMCH - Manchester Mode Bit

`#define EMCH_BIT 1`

`#define EMCH_MASK 2`

##### EUSBS - EUSBS Enable Bit

`#define EUSBS_BIT 3`

`#define EUSBS_MASK 8`

##### EUSART - EUSART Enable Bit

`#define EUSART_BIT 4`

`#define EUSART_MASK 16`

### EUCSRC - EUSART Status Register C

`sfrb EUCSRC = 0xCA;`

##### STP0 - Stop Bit 0

`#define STP0_BIT 0`

`#define STP0_MASK 1`

##### STP1 - Stop Bit 1

`#define STP1_BIT 1`

`#define STP1_MASK 2`

##### F1617 - F1617 Bit

`#define F1617_BIT 2`

`#define F1617_MASK 4`

##### FEM - Frame Error Manchester Bit

`#define FEM_BIT 3`

`#define FEM_MASK 8`

### MUBRRH - Manchester Receiver Baud Rate Register High Byte

`sfrb MUBRRH = 0xCD;`

##### MUBRR8 - Manchester Receiver Baud Rate Register Bit 8

`#define MUBRR8_BIT 0`

`#define MUBRR8_MASK 1`

##### MUBRR9 - Manchester Receiver Baud Rate Register Bit 9

`#define MUBRR9_BIT 1`

`#define MUBRR9_MASK 2`

##### MUBRR10 - Manchester Receiver Baud Rate Register Bit 10

`#define MUBRR10_BIT 2`

`#define MUBRR10_MASK 4`

##### MUBRR11 - Manchester Receiver Baud Rate Register Bit 11

`#define MUBRR11_BIT 3`

`#define MUBRR11_MASK 8`

##### MUBRR12 - Manchester Receiver Baud Rate Register Bit 12

`#define MUBRR12_BIT 4`

`#define MUBRR12_MASK 16`

##### MUBRR13 - Manchester Receiver Baud Rate Register Bit 13

`#define MUBRR13_BIT 5`

`#define MUBRR13_MASK 32`

##### MUBRR14 - Manchester Receiver Baud Rate Register Bit 14

`#define MUBRR14_BIT 6`

`#define MUBRR14_MASK 64`

##### MUBRR15 - Manchester Receiver Baud Rate Register Bit 15

`#define MUBRR15_BIT 7`

`#define MUBRR15_MASK 128`

### MUBRRL - Manchester Receiver Baud Rate Register Low Byte

`sfrb MUBRRL = 0xCC;`

##### MUBRR0 - Manchester Receiver Baud Rate Register Bit 0

`#define MUBRR0_BIT 0`

`#define MUBRR0_MASK 1`

##### MUBRR1 - Manchester Receiver Baud Rate Register Bit 1

`#define MUBRR1_BIT 1`

`#define MUBRR1_MASK 2`

##### MUBRR2 - Manchester Receiver Baud Rate Register Bit 2

`#define MUBRR2_BIT 2`

`#define MUBRR2_MASK 4`

##### MUBRR3 - Manchester Receiver Baud Rate Register Bit 3

`#define MUBRR3_BIT 3`

`#define MUBRR3_MASK 8`

##### MUBRR4 - Manchester Receiver Baud Rate Register Bit 4

`#define MUBRR4_BIT 4`

`#define MUBRR4_MASK 16`

##### MUBRR5 - Manchester Receiver Baud Rate Register Bit 5

`#define MUBRR5_BIT 5`

`#define MUBRR5_MASK 32`

##### MUBRR6 - Manchester Receiver Baud Rate Register Bit 6

`#define MUBRR6_BIT 6`

`#define MUBRR6_MASK 64`

##### MUBRR7 - Manchester Receiver Baud Rate Register Bit 7

`#define MUBRR7_BIT 7`

`#define MUBRR7_MASK 128`

## ANALOG COMPARATOR

### AC0CON - Analog Comparator 0 Control Register

`sfrb AC0CON = $AD;`

##### AC0M0 - Analog Comparator 0 Multiplexer Register

`#define AC0M0_BIT 0`

`#define AC0M0_MASK 1`

##### AC0M1 - Analog Comparator 0 Multiplexer Regsiter

`#define AC0M1_BIT 1`

`#define AC0M1_MASK 2`

##### AC0M2 - Analog Comparator 0 Multiplexer Register

`#define AC0M2_BIT 2`

`#define AC0M2_MASK 4`

##### AC0IS0 - Analog Comparator 0 Interrupt Select Bit

`#define AC0IS0_BIT 4`

`#define AC0IS0_MASK 16`

##### AC0IS1 - Analog Comparator 0 Interrupt Select Bit

`#define AC0IS1_BIT 5`

`#define AC0IS1_MASK 32`

##### AC0IE - Analog Comparator 0 Interrupt Enable Bit

`#define AC0IE_BIT 6`

`#define AC0IE_MASK 64`

##### AC0EN - Analog Comparator 0 Enable Bit

`#define AC0EN_BIT 7`

`#define AC0EN_MASK 128`

### AC1CON - Analog Comparator 1 Control Register

`sfrb AC1CON = $AE;`

##### AC1M0 - Analog Comparator 1 Multiplexer Register

`#define AC1M0_BIT 0`

`#define AC1M0_MASK 1`

##### AC1M1 - Analog Comparator 1 Multiplexer Regsiter

`#define AC1M1_BIT 1`

`#define AC1M1_MASK 2`

##### AC1M2 - Analog Comparator 1 Multiplexer Register

`#define AC1M2_BIT 2`

`#define AC1M2_MASK 4`

##### AC1ICE - Analog Comparator 1 Interrupt Capture Enable Bit

`#define AC1ICE_BIT 3`

`#define AC1ICE_MASK 8`

##### AC1IS0 - Analog Comparator 1 Interrupt Select Bit

`#define AC1IS0_BIT 4`

`#define AC1IS0_MASK 16`

##### AC1IS1 - Analog Comparator 1 Interrupt Select Bit

`#define AC1IS1_BIT 5`

`#define AC1IS1_MASK 32`

##### AC1IE - Analog Comparator 1 Interrupt Enable Bit

`#define AC1IE_BIT 6`

`#define AC1IE_MASK 64`

##### AC1EN - Analog Comparator 1 Enable Bit

`#define AC1EN_BIT 7`

`#define AC1EN_MASK 128`

### AC2CON - Analog Comparator 2 Control Register

`sfrb AC2CON = $AF;`

##### AC2M0 - Analog Comparator 2 Multiplexer Register

`#define AC2M0_BIT 0`

`#define AC2M0_MASK 1`

##### AC2M1 - Analog Comparator 2 Multiplexer Regsiter

`#define AC2M1_BIT 1`

`#define AC2M1_MASK 2`

##### AC2M2 - Analog Comparator 2 Multiplexer Register

`#define AC2M2_BIT 2`

`#define AC2M2_MASK 4`

##### AC2IS0 - Analog Comparator 2 Interrupt Select Bit

`#define AC2IS0_BIT 4`

`#define AC2IS0_MASK 16`

##### AC2IS1 - Analog Comparator 2 Interrupt Select Bit

`#define AC2IS1_BIT 5`

`#define AC2IS1_MASK 32`

##### AC2IE - Analog Comparator 2 Interrupt Enable Bit

`#define AC2IE_BIT 6`

`#define AC2IE_MASK 64`

##### AC2EN - Analog Comparator 2 Enable Bit

`#define AC2EN_BIT 7`

`#define AC2EN_MASK 128`

### ACSR - Analog Comparator Status Register

`sfrb ACSR = ;`

##### AC0O - Analog Comparator 0 Output Bit

`#define AC0O_BIT 0`

`#define AC0O_MASK 1`

##### AC1O - Analog Comparator 1 Output Bit

`#define AC1O_BIT 1`

`#define AC1O_MASK 2`

##### AC2O - Analog Comparator 2 Output Bit

`#define AC2O_BIT 2`

`#define AC2O_MASK 4`

##### AC0IF - Analog Comparator 0 Interrupt Flag Bit

`#define AC0IF_BIT 4`

`#define AC0IF_MASK 16`

##### AC1IF - Analog Comparator 1 Interrupt Flag Bit

`#define AC1IF_BIT 5`

`#define AC1IF_MASK 32`

##### AC2IF - Analog Comparator 2 Interrupt Flag Bit

`#define AC2IF_BIT 6`

`#define AC2IF_MASK 64`

##### ACCKDIV - Analog Comparator Clock Divider

`#define ACCKDIV_BIT 7`

`#define ACCKDIV_MASK 128`

## DA CONVERTER

Digital to Analog Converter

### DACH - DAC Data Register High Byte

`sfrb DACH = $AC;`

##### DACH0 - DAC Data Register High Byte Bit 0

`#define DACH0_BIT 0`

`#define DACH0_MASK 1`

##### DACH1 - DAC Data Register High Byte Bit 1

`#define DACH1_BIT 1`

`#define DACH1_MASK 2`

##### DACH2 - DAC Data Register High Byte Bit 2

`#define DACH2_BIT 2`

`#define DACH2_MASK 4`

##### DACH3 - DAC Data Register High Byte Bit 3

`#define DACH3_BIT 3`

`#define DACH3_MASK 8`

##### DACH4 - DAC Data Register High Byte Bit 4

`#define DACH4_BIT 4`

`#define DACH4_MASK 16`

##### DACH5 - DAC Data Register High Byte Bit 5

`#define DACH5_BIT 5`

`#define DACH5_MASK 32`

##### DACH6 - DAC Data Register High Byte Bit 6

`#define DACH6_BIT 6`

`#define DACH6_MASK 64`

##### DACH7 - DAC Data Register High Byte Bit 7

`#define DACH7_BIT 7`

`#define DACH7_MASK 128`

### DACL - DAC Data Register Low Byte

`sfrb DACL = $AB;`

##### DACL0 - DAC Data Register Low Byte Bit 0

`#define DACL0_BIT 0`

`#define DACL0_MASK 1`

##### DACL1 - DAC Data Register Low Byte Bit 1

`#define DACL1_BIT 1`

`#define DACL1_MASK 2`

##### DACL2 - DAC Data Register Low Byte Bit 2

`#define DACL2_BIT 2`

`#define DACL2_MASK 4`

##### DACL3 - DAC Data Register Low Byte Bit 3

`#define DACL3_BIT 3`

`#define DACL3_MASK 8`

##### DACL4 - DAC Data Register Low Byte Bit 4

`#define DACL4_BIT 4`

`#define DACL4_MASK 16`

##### DACL5 - DAC Data Register Low Byte Bit 5

`#define DACL5_BIT 5`

`#define DACL5_MASK 32`

##### DACL6 - DAC Data Register Low Byte Bit 6

`#define DACL6_BIT 6`

`#define DACL6_MASK 64`

##### DACL7 - DAC Data Register Low Byte Bit 7

`#define DACL7_BIT 7`

`#define DACL7_MASK 128`

### DACON - DAC Control Register

`sfrb DACON = $AA;`

##### DAEN - DAC Enable Bit

`#define DAEN_BIT 0`

`#define DAEN_MASK 1`

##### DAOE - DAC Output Enable Bit

`#define DAOE_BIT 1`

`#define DAOE_MASK 2`

##### DALA - DAC Left Adjust

`#define DALA_BIT 2`

`#define DALA_MASK 4`

##### DATS0 - DAC Trigger Selection Bit 0

`#define DATS0_BIT 4`

`#define DATS0_MASK 16`

##### DATS1 - DAC Trigger Selection Bit 1

`#define DATS1_BIT 5`

`#define DATS1_MASK 32`

##### DATS2 - DAC Trigger Selection Bit 2

`#define DATS2_BIT 6`

`#define DATS2_MASK 64`

##### DAATE - DAC Auto Trigger Enable Bit

`#define DAATE_BIT 7`

`#define DAATE_MASK 128`

## CPU

### SREG - Status Register

`sfrb SREG = $3F;`

### SPH - Stack Pointer High

`sfrb SPH = $3E;`

##### SP8 - Stack pointer bit 8

`#define SP8_BIT 0`

`#define SP8_MASK 1`

##### SP9 - Stack pointer bit 9

`#define SP9_BIT 1`

`#define SP9_MASK 2`

##### SP10 - Stack pointer bit 10

`#define SP10_BIT 2`

`#define SP10_MASK 4`

##### SP11 - Stack pointer bit 11

`#define SP11_BIT 3`

`#define SP11_MASK 8`

##### SP12

`#define SP12_BIT 4`

`#define SP12_MASK 16`

##### SP13 - Stack pointer bit 13

`#define SP13_BIT 5`

`#define SP13_MASK 32`

##### SP14 - Stack pointer bit 14

`#define SP14_BIT 6`

`#define SP14_MASK 64`

##### SP15 - Stack pointer bit 15

`#define SP15_BIT 7`

`#define SP15_MASK 128`

### SPL - Stack Pointer Low

`sfrb SPL = $3D;`

##### SP0 - Stack pointer bit 0

`#define SP0_BIT 0`

`#define SP0_MASK 1`

##### SP1 - Stack pointer bit 1

`#define SP1_BIT 1`

`#define SP1_MASK 2`

##### SP2 - Stack pointer bit 2

`#define SP2_BIT 2`

`#define SP2_MASK 4`

##### SP3 - Stack pointer bit 3

`#define SP3_BIT 3`

`#define SP3_MASK 8`

##### SP4

`#define SP4_BIT 4`

`#define SP4_MASK 16`

##### SP5 - Stack pointer bit 5

`#define SP5_BIT 5`

`#define SP5_MASK 32`

##### SP6 - Stack pointer bit 6

`#define SP6_BIT 6`

`#define SP6_MASK 64`

##### SP7 - Stack pointer bit 7

`#define SP7_BIT 7`

`#define SP7_MASK 128`

### MCUCR - MCU Control Register

`sfrb MCUCR = $35;`

##### IVCE - Interrupt Vector Change Enable

`#define IVCE_BIT 0`

`#define IVCE_MASK 1`

The IVCE bit must be written to logic one to enable change of the IVSEL bit.IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.Setting the IVCE bit will disable interrupts.

##### IVSEL - Interrupt Vector Select

`#define IVSEL_BIT 1`

`#define IVSEL_MASK 2`

When the IVSEL bit is cleared (zero),the interrupt vectors are placed at the start of the Flash memory.When this bit is set (one),the interrupt vectors are moved to the beginning of the Boot Loader section of the flash.The actual address of the start of the boot flash section is determined by the BOOTSZ fuses.

##### PUD - Pull-up disable

`#define PUD_BIT 4`

`#define PUD_MASK 16`

When this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn,PORTxn}=0b01).

##### SPIPS - SPI Pin Select

`#define SPIPS_BIT 7`

`#define SPIPS_MASK 128`

### MCUSR - MCU Status Register

`sfrb MCUSR = $34;`

##### PORF - Power-on reset flag

`#define PORF_BIT 0`

`#define PORF_MASK 1`

This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.

##### EXTRF - External Reset Flag

`#define EXTRF_BIT 1`

`#define EXTRF_MASK 2`

This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

##### BORF - Brown-out Reset Flag

`#define BORF_BIT 2`

`#define BORF_MASK 4`

This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

##### WDRF - Watchdog Reset Flag

`#define WDRF_BIT 3`

`#define WDRF_MASK 8`

This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

### OSCCAL - Oscillator Calibration Value

`sfrb OSCCAL = $66;`

##### CAL0 - Oscillator Calibration Value Bit0

`#define CAL0_BIT 0`

`#define CAL0_MASK 1`

##### CAL1 - Oscillator Calibration Value Bit1

`#define CAL1_BIT 1`

`#define CAL1_MASK 2`

##### CAL2 - Oscillator Calibration Value Bit2

`#define CAL2_BIT 2`

`#define CAL2_MASK 4`

##### CAL3 - Oscillator Calibration Value Bit3

`#define CAL3_BIT 3`

`#define CAL3_MASK 8`

##### CAL4 - Oscillator Calibration Value Bit4

`#define CAL4_BIT 4`

`#define CAL4_MASK 16`

##### CAL5 - Oscillator Calibration Value Bit5

`#define CAL5_BIT 5`

`#define CAL5_MASK 32`

##### CAL6 - Oscillator Calibration Value Bit6

`#define CAL6_BIT 6`

`#define CAL6_MASK 64`

### CLKPR -

`sfrb CLKPR = $61;`

##### CLKPS0

`#define CLKPS0_BIT 0`

`#define CLKPS0_MASK 1`

##### CLKPS1

`#define CLKPS1_BIT 1`

`#define CLKPS1_MASK 2`

##### CLKPS2

`#define CLKPS2_BIT 2`

`#define CLKPS2_MASK 4`

##### CLKPS3

`#define CLKPS3_BIT 3`

`#define CLKPS3_MASK 8`

##### CLKPCE

`#define CLKPCE_BIT 7`

`#define CLKPCE_MASK 128`

### SMCR - Sleep Mode Control Register

`sfrb SMCR = $33;`

##### SE - Sleep Enable

`#define SE_BIT 0`

`#define SE_MASK 1`

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.To

##### SM0 - Sleep Mode Select bit 0

`#define SM0_BIT 1`

`#define SM0_MASK 2`

These bits select between the five available sleep modes.

##### SM1 - Sleep Mode Select bit 1

`#define SM1_BIT 2`

`#define SM1_MASK 4`

These bits select between the five available sleep modes.

##### SM2 - Sleep Mode Select bit 2

`#define SM2_BIT 3`

`#define SM2_MASK 8`

These bits select between the five available sleep modes.

### GPIOR3 - General Purpose IO Register 3

`sfrb GPIOR3 = $1B;`

##### GPIOR30 - General Purpose IO Register 3 bit 0

`#define GPIOR30_BIT 0`

`#define GPIOR30_MASK 1`

##### GPIOR31 - General Purpose IO Register 3 bit 1

`#define GPIOR31_BIT 1`

`#define GPIOR31_MASK 2`

##### GPIOR32 - General Purpose IO Register 3 bit 2

`#define GPIOR32_BIT 2`

`#define GPIOR32_MASK 4`

##### GPIOR33 - General Purpose IO Register 3 bit 3

`#define GPIOR33_BIT 3`

`#define GPIOR33_MASK 8`

##### GPIOR34 - General Purpose IO Register 3 bit 4

`#define GPIOR34_BIT 4`

`#define GPIOR34_MASK 16`

##### GPIOR35 - General Purpose IO Register 3 bit 5

`#define GPIOR35_BIT 5`

`#define GPIOR35_MASK 32`

##### GPIOR36 - General Purpose IO Register 3 bit 6

`#define GPIOR36_BIT 6`

`#define GPIOR36_MASK 64`

##### GPIOR37 - General Purpose IO Register 3 bit 7

`#define GPIOR37_BIT 7`

`#define GPIOR37_MASK 128`

### GPIOR2 - General Purpose IO Register 2

`sfrb GPIOR2 = $1A;`

##### GPIOR20 - General Purpose IO Register 2 bit 0

`#define GPIOR20_BIT 0`

`#define GPIOR20_MASK 1`

##### GPIOR21 - General Purpose IO Register 2 bit 1

`#define GPIOR21_BIT 1`

`#define GPIOR21_MASK 2`

##### GPIOR22 - General Purpose IO Register 2 bit 2

`#define GPIOR22_BIT 2`

`#define GPIOR22_MASK 4`

##### GPIOR23 - General Purpose IO Register 2 bit 3

`#define GPIOR23_BIT 3`

`#define GPIOR23_MASK 8`

##### GPIOR24 - General Purpose IO Register 2 bit 4

`#define GPIOR24_BIT 4`

`#define GPIOR24_MASK 16`

##### GPIOR25 - General Purpose IO Register 2 bit 5

`#define GPIOR25_BIT 5`

`#define GPIOR25_MASK 32`

##### GPIOR26 - General Purpose IO Register 2 bit 6

`#define GPIOR26_BIT 6`

`#define GPIOR26_MASK 64`

##### GPIOR27 - General Purpose IO Register 2 bit 7

`#define GPIOR27_BIT 7`

`#define GPIOR27_MASK 128`

### GPIOR1 - General Purpose IO Register 1

`sfrb GPIOR1 = $19;`

##### GPIOR10 - General Purpose IO Register 1 bit 0

`#define GPIOR10_BIT 0`

`#define GPIOR10_MASK 1`

##### GPIOR11 - General Purpose IO Register 1 bit 1

`#define GPIOR11_BIT 1`

`#define GPIOR11_MASK 2`

##### GPIOR12 - General Purpose IO Register 1 bit 2

`#define GPIOR12_BIT 2`

`#define GPIOR12_MASK 4`

##### GPIOR13 - General Purpose IO Register 1 bit 3

`#define GPIOR13_BIT 3`

`#define GPIOR13_MASK 8`

##### GPIOR14 - General Purpose IO Register 1 bit 4

`#define GPIOR14_BIT 4`

`#define GPIOR14_MASK 16`

##### GPIOR15 - General Purpose IO Register 1 bit 5

`#define GPIOR15_BIT 5`

`#define GPIOR15_MASK 32`

##### GPIOR16 - General Purpose IO Register 1 bit 6

`#define GPIOR16_BIT 6`

`#define GPIOR16_MASK 64`

##### GPIOR17 - General Purpose IO Register 1 bit 7

`#define GPIOR17_BIT 7`

`#define GPIOR17_MASK 128`

### GPIOR0 - General Purpose IO Register 0

`sfrb GPIOR0 = $1E;`

##### GPIOR00 - General Purpose IO Register 0 bit 0

`#define GPIOR00_BIT 0`

`#define GPIOR00_MASK 1`

##### GPIOR01 - General Purpose IO Register 0 bit 1

`#define GPIOR01_BIT 1`

`#define GPIOR01_MASK 2`

##### GPIOR02 - General Purpose IO Register 0 bit 2

`#define GPIOR02_BIT 2`

`#define GPIOR02_MASK 4`

##### GPIOR03 - General Purpose IO Register 0 bit 3

`#define GPIOR03_BIT 3`

`#define GPIOR03_MASK 8`

##### GPIOR04 - General Purpose IO Register 0 bit 4

`#define GPIOR04_BIT 4`

`#define GPIOR04_MASK 16`

##### GPIOR05 - General Purpose IO Register 0 bit 5

`#define GPIOR05_BIT 5`

`#define GPIOR05_MASK 32`

##### GPIOR06 - General Purpose IO Register 0 bit 6

`#define GPIOR06_BIT 6`

`#define GPIOR06_MASK 64`

##### GPIOR07 - General Purpose IO Register 0 bit 7

`#define GPIOR07_BIT 7`

`#define GPIOR07_MASK 128`

### PLLCSR - PLL Control And Status Register

`sfrb PLLCSR = $29;`

##### PLOCK - PLL Lock Detector

`#define PLOCK_BIT 0`

`#define PLOCK_MASK 1`

##### PLLE - PLL Enable

`#define PLLE_BIT 1`

`#define PLLE_MASK 2`

##### PLLF - PLL Factor

`#define PLLF_BIT 2`

`#define PLLF_MASK 4`

The PLLF bit is used to select the division factor of the PLL.

## PORTE

### PORTE - Port E Data Register

`sfrb PORTE = $0E;`

##### PORTE0

`#define PORTE0_BIT 0`

`#define PORTE0_MASK 1`

##### PORTE1

`#define PORTE1_BIT 1`

`#define PORTE1_MASK 2`

##### PORTE2

`#define PORTE2_BIT 2`

`#define PORTE2_MASK 4`

### DDRE - Port E Data Direction Register

`sfrb DDRE = $0D;`

##### DDE0

`#define DDE0_BIT 0`

`#define DDE0_MASK 1`

##### DDE1

`#define DDE1_BIT 1`

`#define DDE1_MASK 2`

##### DDE2

`#define DDE2_BIT 2`

`#define DDE2_MASK 4`

### PINE - Port E Input Pins

`sfrb PINE = $0C;`

##### PINE0

`#define PINE0_BIT 0`

`#define PINE0_MASK 1`

##### PINE1

`#define PINE1_BIT 1`

`#define PINE1_MASK 2`

##### PINE2

`#define PINE2_BIT 2`

`#define PINE2_MASK 4`

## TIMER COUNTER 0

### TIMSK0 - Timer/Counter0 Interrupt Mask Register

`sfrb TIMSK0 = $6E;`

##### TOIE0 - Timer/Counter0 Overflow Interrupt Enable

`#define TOIE0_BIT 0`

`#define TOIE0_MASK 1`

##### OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable

`#define OCIE0A_BIT 1`

`#define OCIE0A_MASK 2`

##### OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable

`#define OCIE0B_BIT 2`

`#define OCIE0B_MASK 4`

### TIFR0 - Timer/Counter0 Interrupt Flag register

`sfrb TIFR0 = $15;`

##### TOV0 - Timer/Counter0 Overflow Flag

`#define TOV0_BIT 0`

`#define TOV0_MASK 1`

##### OCF0A - Timer/Counter0 Output Compare Flag 0A

`#define OCF0A_BIT 1`

`#define OCF0A_MASK 2`

##### OCF0B - Timer/Counter0 Output Compare Flag 0B

`#define OCF0B_BIT 2`

`#define OCF0B_MASK 4`

### TCCR0A - Timer/Counter Control Register A

`sfrb TCCR0A = $24;`

##### WGM00 - Waveform Generation Mode

`#define WGM00_BIT 0`

`#define WGM00_MASK 1`

##### WGM01 - Waveform Generation Mode

`#define WGM01_BIT 1`

`#define WGM01_MASK 2`

##### COM0B0 - Compare Output Mode, Fast PWm

`#define COM0B0_BIT 4`

`#define COM0B0_MASK 16`

##### COM0B1 - Compare Output Mode, Fast PWm

`#define COM0B1_BIT 5`

`#define COM0B1_MASK 32`

##### COM0A0 - Compare Output Mode, Phase Correct PWM Mode

`#define COM0A0_BIT 6`

`#define COM0A0_MASK 64`

##### COM0A1 - Compare Output Mode, Phase Correct PWM Mode

`#define COM0A1_BIT 7`

`#define COM0A1_MASK 128`

### TCCR0B - Timer/Counter Control Register B

`sfrb TCCR0B = $25;`

##### CS00 - Clock Select

`#define CS00_BIT 0`

`#define CS00_MASK 1`

##### CS01 - Clock Select

`#define CS01_BIT 1`

`#define CS01_MASK 2`

##### CS02 - Clock Select

`#define CS02_BIT 2`

`#define CS02_MASK 4`

##### WGM02

`#define WGM02_BIT 3`

`#define WGM02_MASK 8`

##### FOC0B - Force Output Compare B

`#define FOC0B_BIT 6`

`#define FOC0B_MASK 64`

##### FOC0A - Force Output Compare A

`#define FOC0A_BIT 7`

`#define FOC0A_MASK 128`

### TCNT0 - Timer/Counter0

`sfrb TCNT0 = $26;`

##### TCNT0_0

`#define TCNT0_0_BIT 0`

`#define TCNT0_0_MASK 1`

##### TCNT0_1

`#define TCNT0_1_BIT 1`

`#define TCNT0_1_MASK 2`

##### TCNT0_2

`#define TCNT0_2_BIT 2`

`#define TCNT0_2_MASK 4`

##### TCNT0_3

`#define TCNT0_3_BIT 3`

`#define TCNT0_3_MASK 8`

##### TCNT0_4

`#define TCNT0_4_BIT 4`

`#define TCNT0_4_MASK 16`

##### TCNT0_5

`#define TCNT0_5_BIT 5`

`#define TCNT0_5_MASK 32`

##### TCNT0_6

`#define TCNT0_6_BIT 6`

`#define TCNT0_6_MASK 64`

##### TCNT0_7

`#define TCNT0_7_BIT 7`

`#define TCNT0_7_MASK 128`

### OCR0A - Timer/Counter0 Output Compare Register

`sfrb OCR0A = $27;`

##### OCR0_0

`#define OCR0_0_BIT 0`

`#define OCR0_0_MASK 1`

##### OCR0_1

`#define OCR0_1_BIT 1`

`#define OCR0_1_MASK 2`

##### OCR0_2

`#define OCR0_2_BIT 2`

`#define OCR0_2_MASK 4`

##### OCR0_3

`#define OCR0_3_BIT 3`

`#define OCR0_3_MASK 8`

##### OCR0_4

`#define OCR0_4_BIT 4`

`#define OCR0_4_MASK 16`

##### OCR0_5

`#define OCR0_5_BIT 5`

`#define OCR0_5_MASK 32`

##### OCR0_6

`#define OCR0_6_BIT 6`

`#define OCR0_6_MASK 64`

##### OCR0_7

`#define OCR0_7_BIT 7`

`#define OCR0_7_MASK 128`

### OCR0B - Timer/Counter0 Output Compare Register

`sfrb OCR0B = $28;`

##### OCR0_0

`#define OCR0_0_BIT 0`

`#define OCR0_0_MASK 1`

##### OCR0_1

`#define OCR0_1_BIT 1`

`#define OCR0_1_MASK 2`

##### OCR0_2

`#define OCR0_2_BIT 2`

`#define OCR0_2_MASK 4`

##### OCR0_3

`#define OCR0_3_BIT 3`

`#define OCR0_3_MASK 8`

##### OCR0_4

`#define OCR0_4_BIT 4`

`#define OCR0_4_MASK 16`

##### OCR0_5

`#define OCR0_5_BIT 5`

`#define OCR0_5_MASK 32`

##### OCR0_6

`#define OCR0_6_BIT 6`

`#define OCR0_6_MASK 64`

##### OCR0_7

`#define OCR0_7_BIT 7`

`#define OCR0_7_MASK 128`

### GTCCR - General Timer/Counter Control Register

`sfrb GTCCR = $23;`

##### PSR10 - Prescaler Reset Timer/Counter1 and Timer/Counter0

`#define PSR10_BIT 0`

`#define PSR10_MASK 1`

When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.

##### ICPSEL1 - Timer1 Input Capture Selection Bit

`#define ICPSEL1_BIT 6`

`#define ICPSEL1_MASK 64`

##### TSM - Timer/Counter Synchronization Mode

`#define TSM_BIT 7`

`#define TSM_MASK 128`

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneousl

## TIMER COUNTER 1

### TIMSK1 - Timer/Counter Interrupt Mask Register

`sfrb TIMSK1 = $6F;`

##### TOIE1 - Timer/Counter1 Overflow Interrupt Enable

`#define TOIE1_BIT 0`

`#define TOIE1_MASK 1`

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

##### OCIE1A - Timer/Counter1 Output CompareA Match Interrupt Enable

`#define OCIE1A_BIT 1`

`#define OCIE1A_MASK 2`

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

##### OCIE1B - Timer/Counter1 Output CompareB Match Interrupt Enable

`#define OCIE1B_BIT 2`

`#define OCIE1B_MASK 4`

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

##### ICIE1 - Timer/Counter1 Input Capture Interrupt Enable

`#define ICIE1_BIT 5`

`#define ICIE1_MASK 32`

When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

### TIFR1 - Timer/Counter Interrupt Flag register

`sfrb TIFR1 = $16;`

##### TOV1 - Timer/Counter1 Overflow Flag

`#define TOV1_BIT 0`

`#define TOV1_MASK 1`

The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.

##### OCF1A - Output Compare Flag 1A

`#define OCF1A_BIT 1`

`#define OCF1A_MASK 2`

The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed.

##### OCF1B - Output Compare Flag 1B

`#define OCF1B_BIT 2`

`#define OCF1B_MASK 4`

The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.

##### ICF1 - Input Capture Flag 1

`#define ICF1_BIT 5`

`#define ICF1_MASK 32`

The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.

### TCCR1A - Timer/Counter1 Control Register A

`sfrb TCCR1A = $80;`

##### WGM10 - Waveform Generation Mode

`#define WGM10_BIT 0`

`#define WGM10_MASK 1`

Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.

##### WGM11 - Waveform Generation Mode

`#define WGM11_BIT 1`

`#define WGM11_MASK 2`

Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.

##### COM1B0 - Compare Output Mode 1B, bit 0

`#define COM1B0_BIT 4`

`#define COM1B0_MASK 16`

The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.

##### COM1B1 - Compare Output Mode 1B, bit 1

`#define COM1B1_BIT 5`

`#define COM1B1_MASK 32`

The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.

##### COM1A0 - Comparet Ouput Mode 1A, bit 0

`#define COM1A0_BIT 6`

`#define COM1A0_MASK 64`

The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.

##### COM1A1 - Compare Output Mode 1A, bit 1

`#define COM1A1_BIT 7`

`#define COM1A1_MASK 128`

The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.

### TCCR1B - Timer/Counter1 Control Register B

`sfrb TCCR1B = $81;`

##### CS10 - Prescaler source of Timer/Counter 1

`#define CS10_BIT 0`

`#define CS10_MASK 1`

Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.

##### CS11 - Prescaler source of Timer/Counter 1

`#define CS11_BIT 1`

`#define CS11_MASK 2`

Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.

##### CS12 - Prescaler source of Timer/Counter 1

`#define CS12_BIT 2`

`#define CS12_MASK 4`

Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.

##### WGM12 - Waveform Generation Mode

`#define WGM12_BIT 3`

`#define WGM12_MASK 8`

Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.

##### WGM13 - Waveform Generation Mode

`#define WGM13_BIT 4`

`#define WGM13_MASK 16`

Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.

##### ICES1 - Input Capture 1 Edge Select

`#define ICES1_BIT 6`

`#define ICES1_MASK 64`

While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.

##### ICNC1 - Input Capture 1 Noise Canceler

`#define ICNC1_BIT 7`

`#define ICNC1_MASK 128`

When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.

### TCCR1C - Timer/Counter1 Control Register C

`sfrb TCCR1C = $82;`

##### FOC1B

`#define FOC1B_BIT 6`

`#define FOC1B_MASK 64`

##### FOC1A

`#define FOC1A_BIT 7`

`#define FOC1A_MASK 128`

### TCNT1H - Timer/Counter1 High Byte

`sfrb TCNT1H = $85;`

##### TCNT1H0 - Timer/Counter1 High Byte bit 0

`#define TCNT1H0_BIT 0`

`#define TCNT1H0_MASK 1`

##### TCNT1H1 - Timer/Counter1 High Byte bit 1

`#define TCNT1H1_BIT 1`

`#define TCNT1H1_MASK 2`

##### TCNT1H2 - Timer/Counter1 High Byte bit 2

`#define TCNT1H2_BIT 2`

`#define TCNT1H2_MASK 4`

##### TCNT1H3 - Timer/Counter1 High Byte bit 3

`#define TCNT1H3_BIT 3`

`#define TCNT1H3_MASK 8`

##### TCNT1H4 - Timer/Counter1 High Byte bit 4

`#define TCNT1H4_BIT 4`

`#define TCNT1H4_MASK 16`

##### TCNT1H5 - Timer/Counter1 High Byte bit 5

`#define TCNT1H5_BIT 5`

`#define TCNT1H5_MASK 32`

##### TCNT1H6 - Timer/Counter1 High Byte bit 6

`#define TCNT1H6_BIT 6`

`#define TCNT1H6_MASK 64`

##### TCNT1H7 - Timer/Counter1 High Byte bit 7

`#define TCNT1H7_BIT 7`

`#define TCNT1H7_MASK 128`

### TCNT1L - Timer/Counter1 Low Byte

`sfrb TCNT1L = $84;`

##### TCNT1L0 - Timer/Counter1 Low Byte bit 0

`#define TCNT1L0_BIT 0`

`#define TCNT1L0_MASK 1`

##### TCNT1L1 - Timer/Counter1 Low Byte bit 1

`#define TCNT1L1_BIT 1`

`#define TCNT1L1_MASK 2`

##### TCNT1L2 - Timer/Counter1 Low Byte bit 2

`#define TCNT1L2_BIT 2`

`#define TCNT1L2_MASK 4`

##### TCNT1L3 - Timer/Counter1 Low Byte bit 3

`#define TCNT1L3_BIT 3`

`#define TCNT1L3_MASK 8`

##### TCNT1L4 - Timer/Counter1 Low Byte bit 4

`#define TCNT1L4_BIT 4`

`#define TCNT1L4_MASK 16`

##### TCNT1L5 - Timer/Counter1 Low Byte bit 5

`#define TCNT1L5_BIT 5`

`#define TCNT1L5_MASK 32`

##### TCNT1L6 - Timer/Counter1 Low Byte bit 6

`#define TCNT1L6_BIT 6`

`#define TCNT1L6_MASK 64`

##### TCNT1L7 - Timer/Counter1 Low Byte bit 7

`#define TCNT1L7_BIT 7`

`#define TCNT1L7_MASK 128`

### OCR1AH - Timer/Counter1 Outbut Compare Register High Byte

`sfrb OCR1AH = $89;`

##### OCR1AH0 - Timer/Counter1 Outbut Compare Register High Byte bit 0

`#define OCR1AH0_BIT 0`

`#define OCR1AH0_MASK 1`

##### OCR1AH1 - Timer/Counter1 Outbut Compare Register High Byte bit 1

`#define OCR1AH1_BIT 1`

`#define OCR1AH1_MASK 2`

##### OCR1AH2 - Timer/Counter1 Outbut Compare Register High Byte bit 2

`#define OCR1AH2_BIT 2`

`#define OCR1AH2_MASK 4`

##### OCR1AH3 - Timer/Counter1 Outbut Compare Register High Byte bit 3

`#define OCR1AH3_BIT 3`

`#define OCR1AH3_MASK 8`

##### OCR1AH4 - Timer/Counter1 Outbut Compare Register High Byte bit 4

`#define OCR1AH4_BIT 4`

`#define OCR1AH4_MASK 16`

##### OCR1AH5 - Timer/Counter1 Outbut Compare Register High Byte bit 5

`#define OCR1AH5_BIT 5`

`#define OCR1AH5_MASK 32`

##### OCR1AH6 - Timer/Counter1 Outbut Compare Register High Byte bit 6

`#define OCR1AH6_BIT 6`

`#define OCR1AH6_MASK 64`

##### OCR1AH7 - Timer/Counter1 Outbut Compare Register High Byte bit 7

`#define OCR1AH7_BIT 7`

`#define OCR1AH7_MASK 128`

### OCR1AL - Timer/Counter1 Outbut Compare Register Low Byte

`sfrb OCR1AL = $88;`

##### OCR1AL0 - Timer/Counter1 Outbut Compare Register Low Byte Bit 0

`#define OCR1AL0_BIT 0`

`#define OCR1AL0_MASK 1`

##### OCR1AL1 - Timer/Counter1 Outbut Compare Register Low Byte Bit 1

`#define OCR1AL1_BIT 1`

`#define OCR1AL1_MASK 2`

##### OCR1AL2 - Timer/Counter1 Outbut Compare Register Low Byte Bit 2

`#define OCR1AL2_BIT 2`

`#define OCR1AL2_MASK 4`

##### OCR1AL3 - Timer/Counter1 Outbut Compare Register Low Byte Bit 3

`#define OCR1AL3_BIT 3`

`#define OCR1AL3_MASK 8`

##### OCR1AL4 - Timer/Counter1 Outbut Compare Register Low Byte Bit 4

`#define OCR1AL4_BIT 4`

`#define OCR1AL4_MASK 16`

##### OCR1AL5 - Timer/Counter1 Outbut Compare Register Low Byte Bit 5

`#define OCR1AL5_BIT 5`

`#define OCR1AL5_MASK 32`

##### OCR1AL6 - Timer/Counter1 Outbut Compare Register Low Byte Bit 6

`#define OCR1AL6_BIT 6`

`#define OCR1AL6_MASK 64`

##### OCR1AL7 - Timer/Counter1 Outbut Compare Register Low Byte Bit 7

`#define OCR1AL7_BIT 7`

`#define OCR1AL7_MASK 128`

### OCR1BH - Timer/Counter1 Output Compare Register High Byte

`sfrb OCR1BH = $8B;`

##### OCR1BH0 - Timer/Counter1 Output Compare Register High Byte bit 0

`#define OCR1BH0_BIT 0`

`#define OCR1BH0_MASK 1`

##### OCR1BH1 - Timer/Counter1 Output Compare Register High Byte bit 1

`#define OCR1BH1_BIT 1`

`#define OCR1BH1_MASK 2`

##### OCR1BH2 - Timer/Counter1 Output Compare Register High Byte bit 2

`#define OCR1BH2_BIT 2`

`#define OCR1BH2_MASK 4`

##### OCR1BH3 - Timer/Counter1 Output Compare Register High Byte bit 3

`#define OCR1BH3_BIT 3`

`#define OCR1BH3_MASK 8`

##### OCR1BH4 - Timer/Counter1 Output Compare Register High Byte bit 4

`#define OCR1BH4_BIT 4`

`#define OCR1BH4_MASK 16`

##### OCR1BH5 - Timer/Counter1 Output Compare Register High Byte bit 5

`#define OCR1BH5_BIT 5`

`#define OCR1BH5_MASK 32`

##### OCR1BH6 - Timer/Counter1 Output Compare Register High Byte bit 6

`#define OCR1BH6_BIT 6`

`#define OCR1BH6_MASK 64`

##### OCR1BH7 - Timer/Counter1 Output Compare Register High Byte bit 7

`#define OCR1BH7_BIT 7`

`#define OCR1BH7_MASK 128`

### OCR1BL - Timer/Counter1 Output Compare Register Low Byte

`sfrb OCR1BL = $8A;`

##### OCR1BL0 - Timer/Counter1 Output Compare Register Low Byte bit 0

`#define OCR1BL0_BIT 0`

`#define OCR1BL0_MASK 1`

##### OCR1BL1 - Timer/Counter1 Output Compare Register Low Byte bit 1

`#define OCR1BL1_BIT 1`

`#define OCR1BL1_MASK 2`

##### OCR1BL2 - Timer/Counter1 Output Compare Register Low Byte bit 2

`#define OCR1BL2_BIT 2`

`#define OCR1BL2_MASK 4`

##### OCR1BL3 - Timer/Counter1 Output Compare Register Low Byte bit 3

`#define OCR1BL3_BIT 3`

`#define OCR1BL3_MASK 8`

##### OCR1BL4 - Timer/Counter1 Output Compare Register Low Byte bit 4

`#define OCR1BL4_BIT 4`

`#define OCR1BL4_MASK 16`

##### OCR1BL5 - Timer/Counter1 Output Compare Register Low Byte bit 5

`#define OCR1BL5_BIT 5`

`#define OCR1BL5_MASK 32`

##### OCR1BL6 - Timer/Counter1 Output Compare Register Low Byte bit 6

`#define OCR1BL6_BIT 6`

`#define OCR1BL6_MASK 64`

##### OCR1BL7 - Timer/Counter1 Output Compare Register Low Byte bit 7

`#define OCR1BL7_BIT 7`

`#define OCR1BL7_MASK 128`

### ICR1H - Timer/Counter1 Input Capture Register High Byte

`sfrb ICR1H = $87;`

##### ICR1H0 - Timer/Counter1 Input Capture Register High Byte bit 0

`#define ICR1H0_BIT 0`

`#define ICR1H0_MASK 1`

##### ICR1H1 - Timer/Counter1 Input Capture Register High Byte bit 1

`#define ICR1H1_BIT 1`

`#define ICR1H1_MASK 2`

##### ICR1H2 - Timer/Counter1 Input Capture Register High Byte bit 2

`#define ICR1H2_BIT 2`

`#define ICR1H2_MASK 4`

##### ICR1H3 - Timer/Counter1 Input Capture Register High Byte bit 3

`#define ICR1H3_BIT 3`

`#define ICR1H3_MASK 8`

##### ICR1H4 - Timer/Counter1 Input Capture Register High Byte bit 4

`#define ICR1H4_BIT 4`

`#define ICR1H4_MASK 16`

##### ICR1H5 - Timer/Counter1 Input Capture Register High Byte bit 5

`#define ICR1H5_BIT 5`

`#define ICR1H5_MASK 32`

##### ICR1H6 - Timer/Counter1 Input Capture Register High Byte bit 6

`#define ICR1H6_BIT 6`

`#define ICR1H6_MASK 64`

##### ICR1H7 - Timer/Counter1 Input Capture Register High Byte bit 7

`#define ICR1H7_BIT 7`

`#define ICR1H7_MASK 128`

### ICR1L - Timer/Counter1 Input Capture Register Low Byte

`sfrb ICR1L = $86;`

##### ICR1L0 - Timer/Counter1 Input Capture Register Low Byte bit 0

`#define ICR1L0_BIT 0`

`#define ICR1L0_MASK 1`

##### ICR1L1 - Timer/Counter1 Input Capture Register Low Byte bit 1

`#define ICR1L1_BIT 1`

`#define ICR1L1_MASK 2`

##### ICR1L2 - Timer/Counter1 Input Capture Register Low Byte bit 2

`#define ICR1L2_BIT 2`

`#define ICR1L2_MASK 4`

##### ICR1L3 - Timer/Counter1 Input Capture Register Low Byte bit 3

`#define ICR1L3_BIT 3`

`#define ICR1L3_MASK 8`

##### ICR1L4 - Timer/Counter1 Input Capture Register Low Byte bit 4

`#define ICR1L4_BIT 4`

`#define ICR1L4_MASK 16`

##### ICR1L5 - Timer/Counter1 Input Capture Register Low Byte bit 5

`#define ICR1L5_BIT 5`

`#define ICR1L5_MASK 32`

##### ICR1L6 - Timer/Counter1 Input Capture Register Low Byte bit 6

`#define ICR1L6_BIT 6`

`#define ICR1L6_MASK 64`

##### ICR1L7 - Timer/Counter1 Input Capture Register Low Byte bit 7

`#define ICR1L7_BIT 7`

`#define ICR1L7_MASK 128`

### GTCCR - General Timer/Counter Control Register

`sfrb GTCCR = $23;`

##### PSRSYNC - Prescaler Reset Timer/Counter1 and Timer/Counter0

`#define PSRSYNC_BIT 0`

`#define PSRSYNC_MASK 1`

When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.

##### TSM - Timer/Counter Synchronization Mode

`#define TSM_BIT 7`

`#define TSM_MASK 128`

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneous

## AD CONVERTER

AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode Noi

### ADMUX - The ADC multiplexer Selection Register

`sfrb ADMUX = $7C;`

##### MUX0 - Analog Channel and Gain Selection Bits

`#define MUX0_BIT 0`

`#define MUX0_MASK 1`

The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).

##### MUX1 - Analog Channel and Gain Selection Bits

`#define MUX1_BIT 1`

`#define MUX1_MASK 2`

The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).

##### MUX2 - Analog Channel and Gain Selection Bits

`#define MUX2_BIT 2`

`#define MUX2_MASK 4`

The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).

##### MUX3 - Analog Channel and Gain Selection Bits

`#define MUX3_BIT 3`

`#define MUX3_MASK 8`

The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).

##### ADLAR - Left Adjust Result

`#define ADLAR_BIT 5`

`#define ADLAR_MASK 32`

The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see ?The ADC Data Register -ADCL and ADCH? on page 198.

##### REFS0 - Reference Selection Bit 0

`#define REFS0_BIT 6`

`#define REFS0_MASK 64`

These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.

##### REFS1 - Reference Selection Bit 1

`#define REFS1_BIT 7`

`#define REFS1_MASK 128`

These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.

### ADCSRA - The ADC Control and Status register

`sfrb ADCSRA = $7A;`

##### ADPS0 - ADC Prescaler Select Bits

`#define ADPS0_BIT 0`

`#define ADPS0_MASK 1`

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

##### ADPS1 - ADC Prescaler Select Bits

`#define ADPS1_BIT 1`

`#define ADPS1_MASK 2`

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

##### ADPS2 - ADC Prescaler Select Bits

`#define ADPS2_BIT 2`

`#define ADPS2_MASK 4`

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

##### ADIE - ADC Interrupt Enable

`#define ADIE_BIT 3`

`#define ADIE_MASK 8`

When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.

##### ADIF - ADC Interrupt Flag

`#define ADIF_BIT 4`

`#define ADIF_MASK 16`

This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.

##### ADATE - ADC Auto Trigger Enable

`#define ADATE_BIT 5`

`#define ADATE_MASK 32`

When this bit is written to one,Auto Triggering of the ADC is enabled.The ADC will start a conversion on a positive edge of the selected trigger signal.The trigger source is selected by setting the ADC Trigger Select bits,ADTS in ADCSRB.

##### ADSC - ADC Start Conversion

`#define ADSC_BIT 6`

`#define ADSC_MASK 64`

In Single Conversion Mode, a logical ?1? must be written to this bit to start each conversion. In Free Running Mode, a logical ?1? must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect

##### ADEN - ADC Enable

`#define ADEN_BIT 7`

`#define ADEN_MASK 128`

Writing a logical ?1? to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.

### ADCH - ADC Data Register High Byte

`sfrb ADCH = $79;`

##### ADCH0 - ADC Data Register High Byte Bit 0

`#define ADCH0_BIT 0`

`#define ADCH0_MASK 1`

##### ADCH1 - ADC Data Register High Byte Bit 1

`#define ADCH1_BIT 1`

`#define ADCH1_MASK 2`

##### ADCH2 - ADC Data Register High Byte Bit 2

`#define ADCH2_BIT 2`

`#define ADCH2_MASK 4`

##### ADCH3 - ADC Data Register High Byte Bit 3

`#define ADCH3_BIT 3`

`#define ADCH3_MASK 8`

##### ADCH4 - ADC Data Register High Byte Bit 4

`#define ADCH4_BIT 4`

`#define ADCH4_MASK 16`

##### ADCH5 - ADC Data Register High Byte Bit 5

`#define ADCH5_BIT 5`

`#define ADCH5_MASK 32`

##### ADCH6 - ADC Data Register High Byte Bit 6

`#define ADCH6_BIT 6`

`#define ADCH6_MASK 64`

##### ADCH7 - ADC Data Register High Byte Bit 7

`#define ADCH7_BIT 7`

`#define ADCH7_MASK 128`

### ADCL - ADC Data Register Low Byte

`sfrb ADCL = $78;`

##### ADCL0 - ADC Data Register Low Byte Bit 0

`#define ADCL0_BIT 0`

`#define ADCL0_MASK 1`

##### ADCL1 - ADC Data Register Low Byte Bit 1

`#define ADCL1_BIT 1`

`#define ADCL1_MASK 2`

##### ADCL2 - ADC Data Register Low Byte Bit 2

`#define ADCL2_BIT 2`

`#define ADCL2_MASK 4`

##### ADCL3 - ADC Data Register Low Byte Bit 3

`#define ADCL3_BIT 3`

`#define ADCL3_MASK 8`

##### ADCL4 - ADC Data Register Low Byte Bit 4

`#define ADCL4_BIT 4`

`#define ADCL4_MASK 16`

##### ADCL5 - ADC Data Register Low Byte Bit 5

`#define ADCL5_BIT 5`

`#define ADCL5_MASK 32`

##### ADCL6 - ADC Data Register Low Byte Bit 6

`#define ADCL6_BIT 6`

`#define ADCL6_MASK 64`

##### ADCL7 - ADC Data Register Low Byte Bit 7

`#define ADCL7_BIT 7`

`#define ADCL7_MASK 128`

### ADCSRB - ADC Control and Status Register B

`sfrb ADCSRB = $7B;`

##### ADTS0 - ADC Auto Trigger Source 0

`#define ADTS0_BIT 0`

`#define ADTS0_MASK 1`

##### ADTS1 - ADC Auto Trigger Source 1

`#define ADTS1_BIT 1`

`#define ADTS1_MASK 2`

##### ADTS2 - ADC Auto Trigger Source 2

`#define ADTS2_BIT 2`

`#define ADTS2_MASK 4`

##### ADTS3 - ADC Auto Trigger Source 3

`#define ADTS3_BIT 3`

`#define ADTS3_MASK 8`

##### ADASCR - ADC on Amplified Channel Start Conversion Request Bit

`#define ADASCR_BIT 4`

`#define ADASCR_MASK 16`

##### ADHSM - ADC High Speed Mode

`#define ADHSM_BIT 7`

`#define ADHSM_MASK 128`

### DIDR0 - Digital Input Disable Register 0

`sfrb DIDR0 = $7E;`

##### ADC0D - ADC0 Digital input Disable

`#define ADC0D_BIT 0`

`#define ADC0D_MASK 1`

When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

##### ADC1D - ADC1 Digital input Disable

`#define ADC1D_BIT 1`

`#define ADC1D_MASK 2`

When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

##### ADC2D - ADC2 Digital input Disable

`#define ADC2D_BIT 2`

`#define ADC2D_MASK 4`

When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

##### ADC3D - ADC3 Digital input Disable

`#define ADC3D_BIT 3`

`#define ADC3D_MASK 8`

When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

##### ADC4D - ADC4 Digital input Disable

`#define ADC4D_BIT 4`

`#define ADC4D_MASK 16`

When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

##### ADC5D - ADC5 Digital input Disable

`#define ADC5D_BIT 5`

`#define ADC5D_MASK 32`

When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

##### ADC6D - ADC6 Digital input Disable

`#define ADC6D_BIT 6`

`#define ADC6D_MASK 64`

When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

##### ADC7D - ADC7 Digital input Disable

`#define ADC7D_BIT 7`

`#define ADC7D_MASK 128`

When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

## USART

### UDR - USART I/O Data Register

`sfrb UDR = 0xC6;`

##### UDR0 - USART I/O Data Register bit 0

`#define UDR0_BIT 0`

`#define UDR0_MASK 1`

##### UDR1 - USART I/O Data Register bit 1

`#define UDR1_BIT 1`

`#define UDR1_MASK 2`

##### UDR2 - USART I/O Data Register bit 2

`#define UDR2_BIT 2`

`#define UDR2_MASK 4`

##### UDR3 - USART I/O Data Register bit 3

`#define UDR3_BIT 3`

`#define UDR3_MASK 8`

##### UDR4 - USART I/O Data Register bit 4

`#define UDR4_BIT 4`

`#define UDR4_MASK 16`

##### UDR5 - USART I/O Data Register bit 5

`#define UDR5_BIT 5`

`#define UDR5_MASK 32`

##### UDR6 - USART I/O Data Register bit 6

`#define UDR6_BIT 6`

`#define UDR6_MASK 64`

##### UDR7 - USART I/O Data Register bit 7

`#define UDR7_BIT 7`

`#define UDR7_MASK 128`

### UCSRA - USART Control and Status register A

`sfrb UCSRA = 0xC0;`

##### MPCM - Multi-processor Communication Mode

`#define MPCM_BIT 0`

`#define MPCM_MASK 1`

##### U2X - Double USART Transmission Bit

`#define U2X_BIT 1`

`#define U2X_MASK 2`

##### UPE - USART Parity Error

`#define UPE_BIT 2`

`#define UPE_MASK 4`

##### DOR - Data Overrun

`#define DOR_BIT 3`

`#define DOR_MASK 8`

##### FE - Framing Error

`#define FE_BIT 4`

`#define FE_MASK 16`

##### UDRE - USART Data Register Empty

`#define UDRE_BIT 5`

`#define UDRE_MASK 32`

##### TXC - USART Transmitt Complete

`#define TXC_BIT 6`

`#define TXC_MASK 64`

##### RXC - USART Receive Complete

`#define RXC_BIT 7`

`#define RXC_MASK 128`

### UCSRB - USART Control an Status register B

`sfrb UCSRB = 0xC1;`

##### TXB8 - Transmit Data Bit 8

`#define TXB8_BIT 0`

`#define TXB8_MASK 1`

##### RXB8 - Receive Data Bit 8

`#define RXB8_BIT 1`

`#define RXB8_MASK 2`

##### UCSZ2 - Character Size

`#define UCSZ2_BIT 2`

`#define UCSZ2_MASK 4`

##### TXEN - Transmitter Enable

`#define TXEN_BIT 3`

`#define TXEN_MASK 8`

##### RXEN - Receiver Enable

`#define RXEN_BIT 4`

`#define RXEN_MASK 16`

##### UDRIE - USART Data Register Empty Interrupt Enable

`#define UDRIE_BIT 5`

`#define UDRIE_MASK 32`

##### TXCIE - TX Complete Interrupt Enable

`#define TXCIE_BIT 6`

`#define TXCIE_MASK 64`

##### RXCIE - RX Complete Interrupt Enable

`#define RXCIE_BIT 7`

`#define RXCIE_MASK 128`

### UCSRC - USART Control an Status register C

`sfrb UCSRC = 0xC2;`

##### UCPOL - Clock Polarity

`#define UCPOL_BIT 0`

`#define UCPOL_MASK 1`

##### UCSZ0 - Character Size Bit 0

`#define UCSZ0_BIT 1`

`#define UCSZ0_MASK 2`

##### UCSZ1 - Character Size Bit 1

`#define UCSZ1_BIT 2`

`#define UCSZ1_MASK 4`

##### USBS - Stop Bit Select

`#define USBS_BIT 3`

`#define USBS_MASK 8`

##### UPM0 - Parity Mode Bit 0

`#define UPM0_BIT 4`

`#define UPM0_MASK 16`

##### UPM1 - Parity Mode Bit 1

`#define UPM1_BIT 5`

`#define UPM1_MASK 32`

##### UMSEL0 - USART Mode Select

`#define UMSEL0_BIT 6`

`#define UMSEL0_MASK 64`

### UBRRH - USART Baud Rate Register High Byte

`sfrb UBRRH = 0xC5;`

##### UBRR8 - USART Baud Rate Register Bit 8

`#define UBRR8_BIT 0`

`#define UBRR8_MASK 1`

##### UBRR9 - USART Baud Rate Register Bit 9

`#define UBRR9_BIT 1`

`#define UBRR9_MASK 2`

##### UBRR10 - USART Baud Rate Register Bit 10

`#define UBRR10_BIT 2`

`#define UBRR10_MASK 4`

##### UBRR11 - USART Baud Rate Register Bit 11

`#define UBRR11_BIT 3`

`#define UBRR11_MASK 8`

### UBRRL - USART Baud Rate Register Low Byte

`sfrb UBRRL = 0xC4;`

##### UBRR0 - USART Baud Rate Register bit 0

`#define UBRR0_BIT 0`

`#define UBRR0_MASK 1`

##### UBRR1 - USART Baud Rate Register bit 1

`#define UBRR1_BIT 1`

`#define UBRR1_MASK 2`

##### UBRR2 - USART Baud Rate Register bit 2

`#define UBRR2_BIT 2`

`#define UBRR2_MASK 4`

##### UBRR3 - USART Baud Rate Register bit 3

`#define UBRR3_BIT 3`

`#define UBRR3_MASK 8`

##### UBRR4 - USART Baud Rate Register bit 4

`#define UBRR4_BIT 4`

`#define UBRR4_MASK 16`

##### UBRR5 - USART Baud Rate Register bit 5

`#define UBRR5_BIT 5`

`#define UBRR5_MASK 32`

##### UBRR6 - USART Baud Rate Register bit 6

`#define UBRR6_BIT 6`

`#define UBRR6_MASK 64`

##### UBRR7 - USART Baud Rate Register bit 7

`#define UBRR7_BIT 7`

`#define UBRR7_MASK 128`

## SPI

The Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: ? Full-duplex, 3-wire Synchronous Data Transfer ? Master or Slave Operation ? LSB First or MSB First Data Transfer ? Four Programmable Bit Rates ? End of Transmission Interrupt Flag ? Write Collision Flag Protection ? Wakeup from Idle Mode (Slave Mode Only)

### SPCR - SPI Control Register

`sfrb SPCR = $2C;`

##### SPR0 - SPI Clock Rate Select 0

`#define SPR0_BIT 0`

`#define SPR0_MASK 1`

These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.

##### SPR1 - SPI Clock Rate Select 1

`#define SPR1_BIT 1`

`#define SPR1_MASK 2`

These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.

##### CPHA - Clock Phase

`#define CPHA_BIT 2`

`#define CPHA_MASK 4`

Refer to Figure 36 or Figure 37 for the functionality of this bit.

##### CPOL - Clock polarity

`#define CPOL_BIT 3`

`#define CPOL_MASK 8`

When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.

##### MSTR - Master/Slave Select

`#define MSTR_BIT 4`

`#define MSTR_MASK 16`

This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.

##### DORD - Data Order

`#define DORD_BIT 5`

`#define DORD_MASK 32`

When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.

##### SPE - SPI Enable

`#define SPE_BIT 6`

`#define SPE_MASK 64`

When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.

##### SPIE - SPI Interrupt Enable

`#define SPIE_BIT 7`

`#define SPIE_MASK 128`

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.

### SPSR - SPI Status Register

`sfrb SPSR = $2D;`

##### SPI2X - Double SPI Speed Bit

`#define SPI2X_BIT 0`

`#define SPI2X_MASK 1`

When this bit is written logic one the SPI speed (SCK Frequency)will be doubled when the SPI is in master mode .This means that the minimum SCK period will be 2 CPU clock periods.When the SPI is configured as Slave,the SPI is only guaranteed to work at f osc /4orlower. The SPI interface on the ATmega162 is also used for program memory and EEPROM downloading or uploading.

##### WCOL - Write Collision Flag

`#define WCOL_BIT 6`

`#define WCOL_MASK 64`

The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.

##### SPIF - SPI Interrupt Flag

`#define SPIF_BIT 7`

`#define SPIF_MASK 128`

When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).

### SPDR - SPI Data Register

`sfrb SPDR = $2E;`

##### SPDR0 - SPI Data Register bit 0

`#define SPDR0_BIT 0`

`#define SPDR0_MASK 1`

##### SPDR1 - SPI Data Register bit 1

`#define SPDR1_BIT 1`

`#define SPDR1_MASK 2`

##### SPDR2 - SPI Data Register bit 2

`#define SPDR2_BIT 2`

`#define SPDR2_MASK 4`

##### SPDR3 - SPI Data Register bit 3

`#define SPDR3_BIT 3`

`#define SPDR3_MASK 8`

##### SPDR4 - SPI Data Register bit 4

`#define SPDR4_BIT 4`

`#define SPDR4_MASK 16`

##### SPDR5 - SPI Data Register bit 5

`#define SPDR5_BIT 5`

`#define SPDR5_MASK 32`

##### SPDR6 - SPI Data Register bit 6

`#define SPDR6_BIT 6`

`#define SPDR6_MASK 64`

##### SPDR7 - SPI Data Register bit 7

`#define SPDR7_BIT 7`

`#define SPDR7_MASK 128`

## WATCHDOG

### WDTCSR - Watchdog Timer Control Register

`sfrb WDTCSR = $60;`

##### WDP0 - Watch Dog Timer Prescaler bit 0

`#define WDP0_BIT 0`

`#define WDP0_MASK 1`

##### WDP1 - Watch Dog Timer Prescaler bit 1

`#define WDP1_BIT 1`

`#define WDP1_MASK 2`

##### WDP2 - Watch Dog Timer Prescaler bit 2

`#define WDP2_BIT 2`

`#define WDP2_MASK 4`

##### WDE - Watch Dog Enable

`#define WDE_BIT 3`

`#define WDE_MASK 8`

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog

##### WDCE - Watchdog Change Enable

`#define WDCE_BIT 4`

`#define WDCE_MASK 16`

##### WDP3 - Watchdog Timer Prescaler Bit 3

`#define WDP3_BIT 5`

`#define WDP3_MASK 32`

##### WDIE - Watchdog Timeout Interrupt Enable

`#define WDIE_BIT 6`

`#define WDIE_MASK 64`

##### WDIF - Watchdog Timeout Interrupt Flag

`#define WDIF_BIT 7`

`#define WDIF_MASK 128`

## EXTERNAL INTERRUPT

The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in ?Clock Systems and their Distribution? on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in ?Clock Systems and their Distribution? on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt

### EICRA - External Interrupt Control Register A

`sfrb EICRA = $69;`

##### ISC00 - External Interrupt Sense Control Bit

`#define ISC00_BIT 0`

`#define ISC00_MASK 1`

##### ISC01 - External Interrupt Sense Control Bit

`#define ISC01_BIT 1`

`#define ISC01_MASK 2`

##### ISC10 - External Interrupt Sense Control Bit

`#define ISC10_BIT 2`

`#define ISC10_MASK 4`

##### ISC11 - External Interrupt Sense Control Bit

`#define ISC11_BIT 3`

`#define ISC11_MASK 8`

##### ISC20 - External Interrupt Sense Control Bit

`#define ISC20_BIT 4`

`#define ISC20_MASK 16`

##### ISC21 - External Interrupt Sense Control Bit

`#define ISC21_BIT 5`

`#define ISC21_MASK 32`

##### ISC30 - External Interrupt Sense Control Bit

`#define ISC30_BIT 6`

`#define ISC30_MASK 64`

##### ISC31 - External Interrupt Sense Control Bit

`#define ISC31_BIT 7`

`#define ISC31_MASK 128`

### EIMSK - External Interrupt Mask Register

`sfrb EIMSK = $1D;`

##### INT0 - External Interrupt Request 0 Enable

`#define INT0_BIT 0`

`#define INT0_MASK 1`

##### INT1 - External Interrupt Request 1 Enable

`#define INT1_BIT 1`

`#define INT1_MASK 2`

##### INT2 - External Interrupt Request 2 Enable

`#define INT2_BIT 2`

`#define INT2_MASK 4`

##### INT3 - External Interrupt Request 3 Enable

`#define INT3_BIT 3`

`#define INT3_MASK 8`

### EIFR - External Interrupt Flag Register

`sfrb EIFR = $1C;`

##### INTF0 - External Interrupt Flag 0

`#define INTF0_BIT 0`

`#define INTF0_MASK 1`

##### INTF1 - External Interrupt Flag 1

`#define INTF1_BIT 1`

`#define INTF1_MASK 2`

##### INTF2 - External Interrupt Flag 2

`#define INTF2_BIT 2`

`#define INTF2_MASK 4`

##### INTF3 - External Interrupt Flag 3

`#define INTF3_BIT 3`

`#define INTF3_MASK 8`

## EEPROM

EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See ?Preventing EEPROM Corruption? on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execute

### EEARH - EEPROM Read/Write Access High Byte

`sfrb EEARH = $22;`

##### EEAR8 - EEPROM Read/Write Access Bit 8

`#define EEAR8_BIT 0`

`#define EEAR8_MASK 1`

##### EEAR9 - EEPROM Read/Write Access Bit 9

`#define EEAR9_BIT 1`

`#define EEAR9_MASK 2`

##### EEAR10 - EEPROM Read/Write Access Bit 10

`#define EEAR10_BIT 2`

`#define EEAR10_MASK 4`

##### EEAR11 - EEPROM Read/Write Access Bit 11

`#define EEAR11_BIT 3`

`#define EEAR11_MASK 8`

### EEARL - EEPROM Read/Write Access Low Byte

`sfrb EEARL = $21;`

##### EEARL0 - EEPROM Read/Write Access Bit 0

`#define EEARL0_BIT 0`

`#define EEARL0_MASK 1`

##### EEARL1 - EEPROM Read/Write Access Bit 1

`#define EEARL1_BIT 1`

`#define EEARL1_MASK 2`

##### EEARL2 - EEPROM Read/Write Access Bit 2

`#define EEARL2_BIT 2`

`#define EEARL2_MASK 4`

##### EEARL3 - EEPROM Read/Write Access Bit 3

`#define EEARL3_BIT 3`

`#define EEARL3_MASK 8`

##### EEARL4 - EEPROM Read/Write Access Bit 4

`#define EEARL4_BIT 4`

`#define EEARL4_MASK 16`

##### EEARL5 - EEPROM Read/Write Access Bit 5

`#define EEARL5_BIT 5`

`#define EEARL5_MASK 32`

##### EEARL6 - EEPROM Read/Write Access Bit 6

`#define EEARL6_BIT 6`

`#define EEARL6_MASK 64`

##### EEARL7 - EEPROM Read/Write Access Bit 7

`#define EEARL7_BIT 7`

`#define EEARL7_MASK 128`

### EEDR - EEPROM Data Register

`sfrb EEDR = $20;`

##### EEDR0 - EEPROM Data Register bit 0

`#define EEDR0_BIT 0`

`#define EEDR0_MASK 1`

##### EEDR1 - EEPROM Data Register bit 1

`#define EEDR1_BIT 1`

`#define EEDR1_MASK 2`

##### EEDR2 - EEPROM Data Register bit 2

`#define EEDR2_BIT 2`

`#define EEDR2_MASK 4`

##### EEDR3 - EEPROM Data Register bit 3

`#define EEDR3_BIT 3`

`#define EEDR3_MASK 8`

##### EEDR4 - EEPROM Data Register bit 4

`#define EEDR4_BIT 4`

`#define EEDR4_MASK 16`

##### EEDR5 - EEPROM Data Register bit 5

`#define EEDR5_BIT 5`

`#define EEDR5_MASK 32`

##### EEDR6 - EEPROM Data Register bit 6

`#define EEDR6_BIT 6`

`#define EEDR6_MASK 64`

##### EEDR7 - EEPROM Data Register bit 7

`#define EEDR7_BIT 7`

`#define EEDR7_MASK 128`

### EECR - EEPROM Control Register

`sfrb EECR = $1F;`

##### EERE - EEPROM Read Enable

`#define EERE_BIT 0`

`#define EERE_MASK 1`

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU

##### EEWE - EEPROM Write Enable

`#define EEWE_BIT 1`

`#define EEWE_MASK 2`

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See ?Boot Loader Support - Read While Write self-programming? on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed

##### EEMWE - EEPROM Master Write Enable

`#define EEMWE_BIT 2`

`#define EEMWE_MASK 4`

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

##### EERIE - EEPROM Ready Interrupt Enable

`#define EERIE_BIT 3`

`#define EERIE_MASK 8`

EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.

##### EEPM0 - EEPROM Programming Mode Bit 0

`#define EEPM0_BIT 4`

`#define EEPM0_MASK 16`

The EEPROM Programming mode bit setting defines which programming action will be triggered when writing EEWE.

##### EEPM1 - EEPROM Programming Mode Bit 1

`#define EEPM1_BIT 5`

`#define EEPM1_MASK 32`

The EEPROM Programming mode bit setting defines which programming action will be triggered when writing EEWE.

## PSC0

Power Stage Controller

### PICR0H - PSC 0 Input Capture Register High

`sfrb PICR0H = 0xDF;`

##### PICR0_8

`#define PICR0_8_BIT 0`

`#define PICR0_8_MASK 1`

##### PICR0_9

`#define PICR0_9_BIT 1`

`#define PICR0_9_MASK 2`

##### PICR0_10

`#define PICR0_10_BIT 2`

`#define PICR0_10_MASK 4`

##### PICR0_11

`#define PICR0_11_BIT 3`

`#define PICR0_11_MASK 8`

##### PCST0 - PSC 0 Capture Software Trigger Bit

`#define PCST0_BIT 7`

`#define PCST0_MASK 128`

### PICR0L - PSC 0 Input Capture Register Low

`sfrb PICR0L = 0xDE;`

##### PICR0_0

`#define PICR0_0_BIT 0`

`#define PICR0_0_MASK 1`

##### PICR0_1

`#define PICR0_1_BIT 1`

`#define PICR0_1_MASK 2`

##### PICR0_2

`#define PICR0_2_BIT 2`

`#define PICR0_2_MASK 4`

##### PICR0_3

`#define PICR0_3_BIT 3`

`#define PICR0_3_MASK 8`

##### PICR0_4

`#define PICR0_4_BIT 4`

`#define PICR0_4_MASK 16`

##### PICR0_5

`#define PICR0_5_BIT 5`

`#define PICR0_5_MASK 32`

##### PICR0_6

`#define PICR0_6_BIT 6`

`#define PICR0_6_MASK 64`

##### PICR0_7

`#define PICR0_7_BIT 7`

`#define PICR0_7_MASK 128`

### PFRC0B - PSC 0 Input B Control

`sfrb PFRC0B = 0xDD;`

##### PRFM0B0 - PSC 0 Retrigger and Fault Mode for Part B

`#define PRFM0B0_BIT 0`

`#define PRFM0B0_MASK 1`

##### PRFM0B1 - PSC 0 Retrigger and Fault Mode for Part B

`#define PRFM0B1_BIT 1`

`#define PRFM0B1_MASK 2`

##### PRFM0B2 - PSC 0 Retrigger and Fault Mode for Part B

`#define PRFM0B2_BIT 2`

`#define PRFM0B2_MASK 4`

##### PRFM0B3 - PSC 0 Retrigger and Fault Mode for Part B

`#define PRFM0B3_BIT 3`

`#define PRFM0B3_MASK 8`

##### PFLTE0B - PSC 0 Filter Enable on Input Part B

`#define PFLTE0B_BIT 4`

`#define PFLTE0B_MASK 16`

##### PELEV0B - PSC 0 Edge Level Selector on Input Part B

`#define PELEV0B_BIT 5`

`#define PELEV0B_MASK 32`

##### PISEL0B - PSC 0 Input Select for Part B

`#define PISEL0B_BIT 6`

`#define PISEL0B_MASK 64`

##### PCAE0B - PSC 0 Capture Enable Input Part B

`#define PCAE0B_BIT 7`

`#define PCAE0B_MASK 128`

### PFRC0A - PSC 0 Input A Control

`sfrb PFRC0A = 0xDC;`

##### PRFM0A0 - PSC 0 Retrigger and Fault Mode for Part A

`#define PRFM0A0_BIT 0`

`#define PRFM0A0_MASK 1`

##### PRFM0A1 - PSC 0 Retrigger and Fault Mode for Part A

`#define PRFM0A1_BIT 1`

`#define PRFM0A1_MASK 2`

##### PRFM0A2 - PSC 0 Retrigger and Fault Mode for Part A

`#define PRFM0A2_BIT 2`

`#define PRFM0A2_MASK 4`

##### PRFM0A3 - PSC 0 Retrigger and Fault Mode for Part A

`#define PRFM0A3_BIT 3`

`#define PRFM0A3_MASK 8`

##### PFLTE0A - PSC 0 Filter Enable on Input Part A

`#define PFLTE0A_BIT 4`

`#define PFLTE0A_MASK 16`

##### PELEV0A - PSC 0 Edge Level Selector on Input Part A

`#define PELEV0A_BIT 5`

`#define PELEV0A_MASK 32`

##### PISEL0A - PSC 0 Input Select for Part A

`#define PISEL0A_BIT 6`

`#define PISEL0A_MASK 64`

##### PCAE0A - PSC 0 Capture Enable Input Part A

`#define PCAE0A_BIT 7`

`#define PCAE0A_MASK 128`

### PCTL0 - PSC 0 Control Register

`sfrb PCTL0 = 0xDB;`

##### PRUN0 - PSC 0 Run

`#define PRUN0_BIT 0`

`#define PRUN0_MASK 1`

##### PCCYC0 - PSC0 Complete Cycle

`#define PCCYC0_BIT 1`

`#define PCCYC0_MASK 2`

##### PARUN0 - PSC0 Auto Run

`#define PARUN0_BIT 2`

`#define PARUN0_MASK 4`

##### PAOC0A - PSC 0 Asynchronous Output Control A

`#define PAOC0A_BIT 3`

`#define PAOC0A_MASK 8`

##### PAOC0B - PSC 0 Asynchronous Output Control B

`#define PAOC0B_BIT 4`

`#define PAOC0B_MASK 16`

##### PBFM0 - PSC 0 Balance Flank Width Modulation

`#define PBFM0_BIT 5`

`#define PBFM0_MASK 32`

##### PPRE00 - PSC 0 Prescaler Select 0

`#define PPRE00_BIT 6`

`#define PPRE00_MASK 64`

##### PPRE01 - PSC 0 Prescaler Select 1

`#define PPRE01_BIT 7`

`#define PPRE01_MASK 128`

### PCNF0 - PSC 0 Configuration Register

`sfrb PCNF0 = 0xDA;`

##### PCLKSEL0 - PSC 0 Input Clock Select

`#define PCLKSEL0_BIT 1`

`#define PCLKSEL0_MASK 2`

##### POP0 - PSC 0 Output Polarity

`#define POP0_BIT 2`

`#define POP0_MASK 4`

##### PMODE00 - PSC 0 Mode

`#define PMODE00_BIT 3`

`#define PMODE00_MASK 8`

##### PMODE01 - PSC 0 Mode

`#define PMODE01_BIT 4`

`#define PMODE01_MASK 16`

##### PLOCK0 - PSC 0 Lock

`#define PLOCK0_BIT 5`

`#define PLOCK0_MASK 32`

##### PALOCK0 - PSC 0 Autolock

`#define PALOCK0_BIT 6`

`#define PALOCK0_MASK 64`

##### PFIFTY0 - PSC 0 Fifty

`#define PFIFTY0_BIT 7`

`#define PFIFTY0_MASK 128`

### OCR0RBH - Output Compare RB Register High

`sfrb OCR0RBH = 0xD9;`

##### OCR0RB_8

`#define OCR0RB_8_BIT 0`

`#define OCR0RB_8_MASK 1`

##### OCR0RB_9

`#define OCR0RB_9_BIT 1`

`#define OCR0RB_9_MASK 2`

##### OCR0RB_00

`#define OCR0RB_00_BIT 2`

`#define OCR0RB_00_MASK 4`

##### OCR0RB_01

`#define OCR0RB_01_BIT 3`

`#define OCR0RB_01_MASK 8`

##### OCR0RB_02

`#define OCR0RB_02_BIT 4`

`#define OCR0RB_02_MASK 16`

##### OCR0RB_03

`#define OCR0RB_03_BIT 5`

`#define OCR0RB_03_MASK 32`

##### OCR0RB_04

`#define OCR0RB_04_BIT 6`

`#define OCR0RB_04_MASK 64`

##### OCR0RB_05

`#define OCR0RB_05_BIT 7`

`#define OCR0RB_05_MASK 128`

### OCR0RBL - Output Compare RB Register Low

`sfrb OCR0RBL = 0xD8;`

##### OCR0RB_0

`#define OCR0RB_0_BIT 0`

`#define OCR0RB_0_MASK 1`

##### OCR0RB_1

`#define OCR0RB_1_BIT 1`

`#define OCR0RB_1_MASK 2`

##### OCR0RB_2

`#define OCR0RB_2_BIT 2`

`#define OCR0RB_2_MASK 4`

##### OCR0RB_3

`#define OCR0RB_3_BIT 3`

`#define OCR0RB_3_MASK 8`

##### OCR0RB_4

`#define OCR0RB_4_BIT 4`

`#define OCR0RB_4_MASK 16`

##### OCR0RB_5

`#define OCR0RB_5_BIT 5`

`#define OCR0RB_5_MASK 32`

##### OCR0RB_6

`#define OCR0RB_6_BIT 6`

`#define OCR0RB_6_MASK 64`

##### OCR0RB_7

`#define OCR0RB_7_BIT 7`

`#define OCR0RB_7_MASK 128`

### OCR0SBH - Output Compare SB Register High

`sfrb OCR0SBH = 0xD7;`

##### OCR0SB_8

`#define OCR0SB_8_BIT 0`

`#define OCR0SB_8_MASK 1`

##### OCR0SB_9

`#define OCR0SB_9_BIT 1`

`#define OCR0SB_9_MASK 2`

##### OCR0SB_00

`#define OCR0SB_00_BIT 2`

`#define OCR0SB_00_MASK 4`

##### OCR0SB_01

`#define OCR0SB_01_BIT 3`

`#define OCR0SB_01_MASK 8`

### OCR0SBL - Output Compare SB Register Low

`sfrb OCR0SBL = 0xD6;`

##### OCR0SB_0

`#define OCR0SB_0_BIT 0`

`#define OCR0SB_0_MASK 1`

##### OCR0SB_1

`#define OCR0SB_1_BIT 1`

`#define OCR0SB_1_MASK 2`

##### OCR0SB_2

`#define OCR0SB_2_BIT 2`

`#define OCR0SB_2_MASK 4`

##### OCR0SB_3

`#define OCR0SB_3_BIT 3`

`#define OCR0SB_3_MASK 8`

##### OCR0SB_4

`#define OCR0SB_4_BIT 4`

`#define OCR0SB_4_MASK 16`

##### OCR0SB_5

`#define OCR0SB_5_BIT 5`

`#define OCR0SB_5_MASK 32`

##### OCR0SB_6

`#define OCR0SB_6_BIT 6`

`#define OCR0SB_6_MASK 64`

##### OCR0SB_7

`#define OCR0SB_7_BIT 7`

`#define OCR0SB_7_MASK 128`

### OCR0RAH - Output Compare RA Register High

`sfrb OCR0RAH = 0xD5;`

##### OCR0RA_8

`#define OCR0RA_8_BIT 0`

`#define OCR0RA_8_MASK 1`

##### OCR0RA_9

`#define OCR0RA_9_BIT 1`

`#define OCR0RA_9_MASK 2`

##### OCR0RA_00

`#define OCR0RA_00_BIT 2`

`#define OCR0RA_00_MASK 4`

##### OCR0RA_01

`#define OCR0RA_01_BIT 3`

`#define OCR0RA_01_MASK 8`

### OCR0RAL - Output Compare RA Register Low

`sfrb OCR0RAL = 0xD4;`

##### OCR0RA_0

`#define OCR0RA_0_BIT 0`

`#define OCR0RA_0_MASK 1`

##### OCR0RA_1

`#define OCR0RA_1_BIT 1`

`#define OCR0RA_1_MASK 2`

##### OCR0RA_2

`#define OCR0RA_2_BIT 2`

`#define OCR0RA_2_MASK 4`

##### OCR0RA_3

`#define OCR0RA_3_BIT 3`

`#define OCR0RA_3_MASK 8`

##### OCR0RA_4

`#define OCR0RA_4_BIT 4`

`#define OCR0RA_4_MASK 16`

##### OCR0RA_5

`#define OCR0RA_5_BIT 5`

`#define OCR0RA_5_MASK 32`

##### OCR0RA_6

`#define OCR0RA_6_BIT 6`

`#define OCR0RA_6_MASK 64`

##### OCR0RA_7

`#define OCR0RA_7_BIT 7`

`#define OCR0RA_7_MASK 128`

### OCR0SAH - Output Compare SA Register High

`sfrb OCR0SAH = 0xD3;`

##### OCR0SA_8

`#define OCR0SA_8_BIT 0`

`#define OCR0SA_8_MASK 1`

##### OCR0SA_9

`#define OCR0SA_9_BIT 1`

`#define OCR0SA_9_MASK 2`

##### OCR0SA_00

`#define OCR0SA_00_BIT 2`

`#define OCR0SA_00_MASK 4`

##### OCR0SA_01

`#define OCR0SA_01_BIT 3`

`#define OCR0SA_01_MASK 8`

### OCR0SAL - Output Compare SA Register Low

`sfrb OCR0SAL = 0xD2;`

##### OCR0SA_0

`#define OCR0SA_0_BIT 0`

`#define OCR0SA_0_MASK 1`

##### OCR0SA_1

`#define OCR0SA_1_BIT 1`

`#define OCR0SA_1_MASK 2`

##### OCR0SA_2

`#define OCR0SA_2_BIT 2`

`#define OCR0SA_2_MASK 4`

##### OCR0SA_3

`#define OCR0SA_3_BIT 3`

`#define OCR0SA_3_MASK 8`

##### OCR0SA_4

`#define OCR0SA_4_BIT 4`

`#define OCR0SA_4_MASK 16`

##### OCR0SA_5

`#define OCR0SA_5_BIT 5`

`#define OCR0SA_5_MASK 32`

##### OCR0SA_6

`#define OCR0SA_6_BIT 6`

`#define OCR0SA_6_MASK 64`

##### OCR0SA_7

`#define OCR0SA_7_BIT 7`

`#define OCR0SA_7_MASK 128`

### PSOC0 - PSC0 Synchro and Output Configuration

`sfrb PSOC0 = 0xD0;`

##### POEN0A - PSCOUT00 Output Enable

`#define POEN0A_BIT 0`

`#define POEN0A_MASK 1`

##### POEN0B - PSCOUT01 Output Enable

`#define POEN0B_BIT 2`

`#define POEN0B_MASK 4`

##### PSYNC00 - Synchronization Out for ADC Selection

`#define PSYNC00_BIT 4`

`#define PSYNC00_MASK 16`

##### PSYNC01 - Synchronization Out for ADC Selection

`#define PSYNC01_BIT 5`

`#define PSYNC01_MASK 32`

### PIM0 - PSC0 Interrupt Mask Register

`sfrb PIM0 = $A1;`

##### PEOPE0 - End of Cycle Interrupt Enable

`#define PEOPE0_BIT 0`

`#define PEOPE0_MASK 1`

##### PEVE0A - External Event A Interrupt Enable

`#define PEVE0A_BIT 3`

`#define PEVE0A_MASK 8`

##### PEVE0B - External Event B Interrupt Enable

`#define PEVE0B_BIT 4`

`#define PEVE0B_MASK 16`

##### PSEIE0 - PSC 0 Synchro Error Interrupt Enable

`#define PSEIE0_BIT 5`

`#define PSEIE0_MASK 32`

### PIFR0 - PSC0 Interrupt Flag Register

`sfrb PIFR0 = $A0;`

##### PEOP0 - End of PSC0 Interrupt

`#define PEOP0_BIT 0`

`#define PEOP0_MASK 1`

##### PRN00 - Ramp Number

`#define PRN00_BIT 1`

`#define PRN00_MASK 2`

##### PRN01 - Ramp Number

`#define PRN01_BIT 2`

`#define PRN01_MASK 4`

##### PEV0A - External Event A Interrupt

`#define PEV0A_BIT 3`

`#define PEV0A_MASK 8`

##### PEV0B - External Event B Interrupt

`#define PEV0B_BIT 4`

`#define PEV0B_MASK 16`

##### PSEI0 - PSC 0 Synchro Error Interrupt

`#define PSEI0_BIT 5`

`#define PSEI0_MASK 32`

##### POAC0A - PSC 0 Output A Activity

`#define POAC0A_BIT 6`

`#define POAC0A_MASK 64`

##### POAC0B - PSC 0 Output A Activity

`#define POAC0B_BIT 7`

`#define POAC0B_MASK 128`

## PSC1

Power Stage Controller

### PICR1H - PSC 1 Input Capture Register High

`sfrb PICR1H = 0xEF;`

##### PICR1_8

`#define PICR1_8_BIT 0`

`#define PICR1_8_MASK 1`

##### PICR1_9

`#define PICR1_9_BIT 1`

`#define PICR1_9_MASK 2`

##### PICR1_10

`#define PICR1_10_BIT 2`

`#define PICR1_10_MASK 4`

##### PICR1_11

`#define PICR1_11_BIT 3`

`#define PICR1_11_MASK 8`

##### PCST1 - PSC 1 Capture Software Trigger Bit

`#define PCST1_BIT 7`

`#define PCST1_MASK 128`

### PICR1L - PSC 1 Input Capture Register Low

`sfrb PICR1L = 0xEE;`

##### PICR1_0

`#define PICR1_0_BIT 0`

`#define PICR1_0_MASK 1`

##### PICR1_1

`#define PICR1_1_BIT 1`

`#define PICR1_1_MASK 2`

##### PICR1_2

`#define PICR1_2_BIT 2`

`#define PICR1_2_MASK 4`

##### PICR1_3

`#define PICR1_3_BIT 3`

`#define PICR1_3_MASK 8`

##### PICR1_4

`#define PICR1_4_BIT 4`

`#define PICR1_4_MASK 16`

##### PICR1_5

`#define PICR1_5_BIT 5`

`#define PICR1_5_MASK 32`

##### PICR1_6

`#define PICR1_6_BIT 6`

`#define PICR1_6_MASK 64`

##### PICR1_7

`#define PICR1_7_BIT 7`

`#define PICR1_7_MASK 128`

### PFRC1B - PSC 1 Input B Control

`sfrb PFRC1B = 0xED;`

##### PRFM1B0 - PSC 1 Retrigger and Fault Mode for Part B

`#define PRFM1B0_BIT 0`

`#define PRFM1B0_MASK 1`

##### PRFM1B1 - PSC 1 Retrigger and Fault Mode for Part B

`#define PRFM1B1_BIT 1`

`#define PRFM1B1_MASK 2`

##### PRFM1B2 - PSC 1 Retrigger and Fault Mode for Part B

`#define PRFM1B2_BIT 2`

`#define PRFM1B2_MASK 4`

##### PRFM1B3 - PSC 1 Retrigger and Fault Mode for Part B

`#define PRFM1B3_BIT 3`

`#define PRFM1B3_MASK 8`

##### PFLTE1B - PSC 1 Filter Enable on Input Part B

`#define PFLTE1B_BIT 4`

`#define PFLTE1B_MASK 16`

##### PELEV1B - PSC 1 Edge Level Selector on Input Part B

`#define PELEV1B_BIT 5`

`#define PELEV1B_MASK 32`

##### PISEL1B - PSC 1 Input Select for Part B

`#define PISEL1B_BIT 6`

`#define PISEL1B_MASK 64`

##### PCAE1B - PSC 1 Capture Enable Input Part B

`#define PCAE1B_BIT 7`

`#define PCAE1B_MASK 128`

### PFRC1A - PSC 1 Input B Control

`sfrb PFRC1A = 0xEC;`

##### PRFM1A0 - PSC 1 Retrigger and Fault Mode for Part A

`#define PRFM1A0_BIT 0`

`#define PRFM1A0_MASK 1`

##### PRFM1A1 - PSC 1 Retrigger and Fault Mode for Part A

`#define PRFM1A1_BIT 1`

`#define PRFM1A1_MASK 2`

##### PRFM1A2 - PSC 1 Retrigger and Fault Mode for Part A

`#define PRFM1A2_BIT 2`

`#define PRFM1A2_MASK 4`

##### PRFM1A3 - PSC 1 Retrigger and Fault Mode for Part A

`#define PRFM1A3_BIT 3`

`#define PRFM1A3_MASK 8`

##### PFLTE1A - PSC 1 Filter Enable on Input Part A

`#define PFLTE1A_BIT 4`

`#define PFLTE1A_MASK 16`

##### PELEV1A - PSC 1 Edge Level Selector on Input Part A

`#define PELEV1A_BIT 5`

`#define PELEV1A_MASK 32`

##### PISEL1A - PSC 1 Input Select for Part A

`#define PISEL1A_BIT 6`

`#define PISEL1A_MASK 64`

##### PCAE1A - PSC 1 Capture Enable Input Part A

`#define PCAE1A_BIT 7`

`#define PCAE1A_MASK 128`

### PCTL1 - PSC 1 Control Register

`sfrb PCTL1 = 0xEB;`

##### PRUN1 - PSC 1 Run

`#define PRUN1_BIT 0`

`#define PRUN1_MASK 1`

##### PCCYC1 - PSC1 Complete Cycle

`#define PCCYC1_BIT 1`

`#define PCCYC1_MASK 2`

##### PARUN1 - PSC1 Auto Run

`#define PARUN1_BIT 2`

`#define PARUN1_MASK 4`

##### PAOC1A - PSC 1 Asynchronous Output Control A

`#define PAOC1A_BIT 3`

`#define PAOC1A_MASK 8`

##### PAOC1B - PSC 1 Asynchronous Output Control B

`#define PAOC1B_BIT 4`

`#define PAOC1B_MASK 16`

##### PBFM1 - Balance Flank Width Modulation

`#define PBFM1_BIT 5`

`#define PBFM1_MASK 32`

##### PPRE10 - PSC 1 Prescaler Select 0

`#define PPRE10_BIT 6`

`#define PPRE10_MASK 64`

##### PPRE11 - PSC 1 Prescaler Select 1

`#define PPRE11_BIT 7`

`#define PPRE11_MASK 128`

### PCNF1 - PSC 1 Configuration Register

`sfrb PCNF1 = 0xEA;`

##### PCLKSEL1 - PSC 1 Input Clock Select

`#define PCLKSEL1_BIT 1`

`#define PCLKSEL1_MASK 2`

##### POP1 - PSC 1 Output Polarity

`#define POP1_BIT 2`

`#define POP1_MASK 4`

##### PMODE10 - PSC 1 Mode

`#define PMODE10_BIT 3`

`#define PMODE10_MASK 8`

##### PMODE11 - PSC 1 Mode

`#define PMODE11_BIT 4`

`#define PMODE11_MASK 16`

##### PLOCK1 - PSC 1 Lock

`#define PLOCK1_BIT 5`

`#define PLOCK1_MASK 32`

##### PALOCK1 - PSC 1 Autolock

`#define PALOCK1_BIT 6`

`#define PALOCK1_MASK 64`

##### PFIFTY1 - PSC 1 Fifty

`#define PFIFTY1_BIT 7`

`#define PFIFTY1_MASK 128`

### OCR1RBH - Output Compare RB Register High

`sfrb OCR1RBH = 0xE9;`

##### OCR1RB_8

`#define OCR1RB_8_BIT 0`

`#define OCR1RB_8_MASK 1`

##### OCR1RB_9

`#define OCR1RB_9_BIT 1`

`#define OCR1RB_9_MASK 2`

##### OCR1RB_10

`#define OCR1RB_10_BIT 2`

`#define OCR1RB_10_MASK 4`

##### OCR1RB_11

`#define OCR1RB_11_BIT 3`

`#define OCR1RB_11_MASK 8`

##### OCR1RB_12

`#define OCR1RB_12_BIT 4`

`#define OCR1RB_12_MASK 16`

##### OCR1RB_13

`#define OCR1RB_13_BIT 5`

`#define OCR1RB_13_MASK 32`

##### OCR1RB_14

`#define OCR1RB_14_BIT 6`

`#define OCR1RB_14_MASK 64`

##### OCR1RB_15

`#define OCR1RB_15_BIT 7`

`#define OCR1RB_15_MASK 128`

### OCR1RBL - Output Compare RB Register Low

`sfrb OCR1RBL = 0xE8;`

##### OCR1RB_0

`#define OCR1RB_0_BIT 0`

`#define OCR1RB_0_MASK 1`

##### OCR1RB_1

`#define OCR1RB_1_BIT 1`

`#define OCR1RB_1_MASK 2`

##### OCR1RB_2

`#define OCR1RB_2_BIT 2`

`#define OCR1RB_2_MASK 4`

##### OCR1RB_3

`#define OCR1RB_3_BIT 3`

`#define OCR1RB_3_MASK 8`

##### OCR1RB_4

`#define OCR1RB_4_BIT 4`

`#define OCR1RB_4_MASK 16`

##### OCR1RB_5

`#define OCR1RB_5_BIT 5`

`#define OCR1RB_5_MASK 32`

##### OCR1RB_6

`#define OCR1RB_6_BIT 6`

`#define OCR1RB_6_MASK 64`

##### OCR1RB_7

`#define OCR1RB_7_BIT 7`

`#define OCR1RB_7_MASK 128`

### OCR1SBH - Output Compare SB Register High

`sfrb OCR1SBH = 0xE7;`

##### OCR1SB_8

`#define OCR1SB_8_BIT 0`

`#define OCR1SB_8_MASK 1`

##### OCR1SB_9

`#define OCR1SB_9_BIT 1`

`#define OCR1SB_9_MASK 2`

##### OCR1SB_10

`#define OCR1SB_10_BIT 2`

`#define OCR1SB_10_MASK 4`

##### OCR1SB_11

`#define OCR1SB_11_BIT 3`

`#define OCR1SB_11_MASK 8`

### OCR1SBL - Output Compare SB Register Low

`sfrb OCR1SBL = 0xE6;`

##### OCR1SB_0

`#define OCR1SB_0_BIT 0`

`#define OCR1SB_0_MASK 1`

##### OCR1SB_1

`#define OCR1SB_1_BIT 1`

`#define OCR1SB_1_MASK 2`

##### OCR1SB_2

`#define OCR1SB_2_BIT 2`

`#define OCR1SB_2_MASK 4`

##### OCR1SB_3

`#define OCR1SB_3_BIT 3`

`#define OCR1SB_3_MASK 8`

##### OCR1SB_4

`#define OCR1SB_4_BIT 4`

`#define OCR1SB_4_MASK 16`

##### OCR1SB_5

`#define OCR1SB_5_BIT 5`

`#define OCR1SB_5_MASK 32`

##### OCR1SB_6

`#define OCR1SB_6_BIT 6`

`#define OCR1SB_6_MASK 64`

##### OCR1SB_7

`#define OCR1SB_7_BIT 7`

`#define OCR1SB_7_MASK 128`

### OCR1RAH - Output Compare RA Register High

`sfrb OCR1RAH = 0xE5;`

##### OCR1RA_8

`#define OCR1RA_8_BIT 0`

`#define OCR1RA_8_MASK 1`

##### OCR1RA_9

`#define OCR1RA_9_BIT 1`

`#define OCR1RA_9_MASK 2`

##### OCR1RA_10

`#define OCR1RA_10_BIT 2`

`#define OCR1RA_10_MASK 4`

##### OCR1RA_11

`#define OCR1RA_11_BIT 3`

`#define OCR1RA_11_MASK 8`

### OCR1RAL - Output Compare RA Register Low

`sfrb OCR1RAL = 0xE4;`

##### OCR1RA_0

`#define OCR1RA_0_BIT 0`

`#define OCR1RA_0_MASK 1`

##### OCR1RA_1

`#define OCR1RA_1_BIT 1`

`#define OCR1RA_1_MASK 2`

##### OCR1RA_2

`#define OCR1RA_2_BIT 2`

`#define OCR1RA_2_MASK 4`

##### OCR1RA_3

`#define OCR1RA_3_BIT 3`

`#define OCR1RA_3_MASK 8`

##### OCR1RA_4

`#define OCR1RA_4_BIT 4`

`#define OCR1RA_4_MASK 16`

##### OCR1RA_5

`#define OCR1RA_5_BIT 5`

`#define OCR1RA_5_MASK 32`

##### OCR1RA_6

`#define OCR1RA_6_BIT 6`

`#define OCR1RA_6_MASK 64`

##### OCR1RA_7

`#define OCR1RA_7_BIT 7`

`#define OCR1RA_7_MASK 128`

### OCR1SAH - Output Compare SA Register High

`sfrb OCR1SAH = 0xE3;`

##### OCR1SA_8

`#define OCR1SA_8_BIT 0`

`#define OCR1SA_8_MASK 1`

##### OCR1SA_9

`#define OCR1SA_9_BIT 1`

`#define OCR1SA_9_MASK 2`

##### OCR1SA_10

`#define OCR1SA_10_BIT 2`

`#define OCR1SA_10_MASK 4`

##### OCR1SA_11

`#define OCR1SA_11_BIT 3`

`#define OCR1SA_11_MASK 8`

### OCR1SAL - Output Compare SA Register Low

`sfrb OCR1SAL = 0xE2;`

##### OCR1SA_0

`#define OCR1SA_0_BIT 0`

`#define OCR1SA_0_MASK 1`

##### OCR1SA_1

`#define OCR1SA_1_BIT 1`

`#define OCR1SA_1_MASK 2`

##### OCR1SA_2

`#define OCR1SA_2_BIT 2`

`#define OCR1SA_2_MASK 4`

##### OCR1SA_3

`#define OCR1SA_3_BIT 3`

`#define OCR1SA_3_MASK 8`

##### OCR1SA_4

`#define OCR1SA_4_BIT 4`

`#define OCR1SA_4_MASK 16`

##### OCR1SA_5

`#define OCR1SA_5_BIT 5`

`#define OCR1SA_5_MASK 32`

##### OCR1SA_6

`#define OCR1SA_6_BIT 6`

`#define OCR1SA_6_MASK 64`

##### OCR1SA_7

`#define OCR1SA_7_BIT 7`

`#define OCR1SA_7_MASK 128`

### PSOC1 - PSC1 Synchro and Output Configuration

`sfrb PSOC1 = 0xE0;`

##### POEN1A - PSCOUT10 Output Enable

`#define POEN1A_BIT 0`

`#define POEN1A_MASK 1`

##### POEN1B - PSCOUT11 Output Enable

`#define POEN1B_BIT 2`

`#define POEN1B_MASK 4`

##### PSYNC1_0 - Synchronization Out for ADC Selection

`#define PSYNC1_0_BIT 4`

`#define PSYNC1_0_MASK 16`

##### PSYNC1_1 - Synchronization Out for ADC Selection

`#define PSYNC1_1_BIT 5`

`#define PSYNC1_1_MASK 32`

### PIM1 - PSC1 Interrupt Mask Register

`sfrb PIM1 = $A3;`

##### PEOPE1 - End of Cycle Interrupt Enable

`#define PEOPE1_BIT 0`

`#define PEOPE1_MASK 1`

##### PEVE1A - External Event A Interrupt Enable

`#define PEVE1A_BIT 3`

`#define PEVE1A_MASK 8`

##### PEVE1B - External Event B Interrupt Enable

`#define PEVE1B_BIT 4`

`#define PEVE1B_MASK 16`

##### PSEIE1 - PSC 1 Synchro Error Interrupt Enable

`#define PSEIE1_BIT 5`

`#define PSEIE1_MASK 32`

### PIFR1 - PSC1 Interrupt Flag Register

`sfrb PIFR1 = $A2;`

##### PEOP1 - End of PSC1 Interrupt

`#define PEOP1_BIT 0`

`#define PEOP1_MASK 1`

##### PRN10 - Ramp Number

`#define PRN10_BIT 1`

`#define PRN10_MASK 2`

##### PRN11 - Ramp Number

`#define PRN11_BIT 2`

`#define PRN11_MASK 4`

##### PEV1A - External Event A Interrupt

`#define PEV1A_BIT 3`

`#define PEV1A_MASK 8`

##### PEV1B - External Event B Interrupt

`#define PEV1B_BIT 4`

`#define PEV1B_MASK 16`

##### PSEI1 - PSC 1 Synchro Error Interrupt

`#define PSEI1_BIT 5`

`#define PSEI1_MASK 32`

##### POAC1A - PSC 1 Output A Activity

`#define POAC1A_BIT 6`

`#define POAC1A_MASK 64`

##### POAC1B - PSC 1 Output B Activity

`#define POAC1B_BIT 7`

`#define POAC1B_MASK 128`

## PSC2

Power Stage Controller

### PICR2H - PSC 2 Input Capture Register High

`sfrb PICR2H = 0xFF;`

##### PICR2_8

`#define PICR2_8_BIT 0`

`#define PICR2_8_MASK 1`

##### PICR2_9

`#define PICR2_9_BIT 1`

`#define PICR2_9_MASK 2`

##### PICR2_10

`#define PICR2_10_BIT 2`

`#define PICR2_10_MASK 4`

##### PICR2_11

`#define PICR2_11_BIT 3`

`#define PICR2_11_MASK 8`

##### PCST2 - PSC 2 Capture Software Trigger Bit

`#define PCST2_BIT 7`

`#define PCST2_MASK 128`

### PICR2L - PSC 2 Input Capture Register Low

`sfrb PICR2L = 0xFE;`

##### PICR2_0

`#define PICR2_0_BIT 0`

`#define PICR2_0_MASK 1`

##### PICR2_1

`#define PICR2_1_BIT 1`

`#define PICR2_1_MASK 2`

##### PICR2_2

`#define PICR2_2_BIT 2`

`#define PICR2_2_MASK 4`

##### PICR2_3

`#define PICR2_3_BIT 3`

`#define PICR2_3_MASK 8`

##### PICR2_4

`#define PICR2_4_BIT 4`

`#define PICR2_4_MASK 16`

##### PICR2_5

`#define PICR2_5_BIT 5`

`#define PICR2_5_MASK 32`

##### PICR2_6

`#define PICR2_6_BIT 6`

`#define PICR2_6_MASK 64`

##### PICR2_7

`#define PICR2_7_BIT 7`

`#define PICR2_7_MASK 128`

### PFRC2B - PSC 2 Input B Control

`sfrb PFRC2B = 0xFD;`

##### PRFM2B0 - PSC 2 Retrigger and Fault Mode for Part B

`#define PRFM2B0_BIT 0`

`#define PRFM2B0_MASK 1`

##### PRFM2B1 - PSC 2 Retrigger and Fault Mode for Part B

`#define PRFM2B1_BIT 1`

`#define PRFM2B1_MASK 2`

##### PRFM2B2 - PSC 2 Retrigger and Fault Mode for Part B

`#define PRFM2B2_BIT 2`

`#define PRFM2B2_MASK 4`

##### PRFM2B3 - PSC 2 Retrigger and Fault Mode for Part B

`#define PRFM2B3_BIT 3`

`#define PRFM2B3_MASK 8`

##### PFLTE2B - PSC 2 Filter Enable on Input Part B

`#define PFLTE2B_BIT 4`

`#define PFLTE2B_MASK 16`

##### PELEV2B - PSC 2 Edge Level Selector on Input Part B

`#define PELEV2B_BIT 5`

`#define PELEV2B_MASK 32`

##### PISEL2B - PSC 2 Input Select for Part B

`#define PISEL2B_BIT 6`

`#define PISEL2B_MASK 64`

##### PCAE2B - PSC 2 Capture Enable Input Part B

`#define PCAE2B_BIT 7`

`#define PCAE2B_MASK 128`

### PFRC2A - PSC 2 Input B Control

`sfrb PFRC2A = 0xFC;`

##### PRFM2A0 - PSC 2 Retrigger and Fault Mode for Part A

`#define PRFM2A0_BIT 0`

`#define PRFM2A0_MASK 1`

##### PRFM2A1 - PSC 2 Retrigger and Fault Mode for Part A

`#define PRFM2A1_BIT 1`

`#define PRFM2A1_MASK 2`

##### PRFM2A2 - PSC 2 Retrigger and Fault Mode for Part A

`#define PRFM2A2_BIT 2`

`#define PRFM2A2_MASK 4`

##### PRFM2A3 - PSC 2 Retrigger and Fault Mode for Part A

`#define PRFM2A3_BIT 3`

`#define PRFM2A3_MASK 8`

##### PFLTE2A - PSC 2 Filter Enable on Input Part A

`#define PFLTE2A_BIT 4`

`#define PFLTE2A_MASK 16`

##### PELEV2A - PSC 2 Edge Level Selector on Input Part A

`#define PELEV2A_BIT 5`

`#define PELEV2A_MASK 32`

##### PISEL2A - PSC 2 Input Select for Part A

`#define PISEL2A_BIT 6`

`#define PISEL2A_MASK 64`

##### PCAE2A - PSC 2 Capture Enable Input Part A

`#define PCAE2A_BIT 7`

`#define PCAE2A_MASK 128`

### PCTL2 - PSC 2 Control Register

`sfrb PCTL2 = 0xFB;`

##### PRUN2 - PSC 2 Run

`#define PRUN2_BIT 0`

`#define PRUN2_MASK 1`

##### PCCYC2 - PSC2 Complete Cycle

`#define PCCYC2_BIT 1`

`#define PCCYC2_MASK 2`

##### PARUN2 - PSC2 Auto Run

`#define PARUN2_BIT 2`

`#define PARUN2_MASK 4`

##### PAOC2A - PSC 2 Asynchronous Output Control A

`#define PAOC2A_BIT 3`

`#define PAOC2A_MASK 8`

##### PAOC2B - PSC 2 Asynchronous Output Control B

`#define PAOC2B_BIT 4`

`#define PAOC2B_MASK 16`

##### PBFM2 - Balance Flank Width Modulation

`#define PBFM2_BIT 5`

`#define PBFM2_MASK 32`

##### PPRE20 - PSC 2 Prescaler Select 0

`#define PPRE20_BIT 6`

`#define PPRE20_MASK 64`

##### PPRE21 - PSC 2 Prescaler Select 1

`#define PPRE21_BIT 7`

`#define PPRE21_MASK 128`

### PCNF2 - PSC 2 Configuration Register

`sfrb PCNF2 = 0xFA;`

##### POME2 - PSC 2 Output Matrix Enable

`#define POME2_BIT 0`

`#define POME2_MASK 1`

##### PCLKSEL2 - PSC 2 Input Clock Select

`#define PCLKSEL2_BIT 1`

`#define PCLKSEL2_MASK 2`

##### POP2 - PSC 2 Output Polarity

`#define POP2_BIT 2`

`#define POP2_MASK 4`

##### PMODE20 - PSC 2 Mode

`#define PMODE20_BIT 3`

`#define PMODE20_MASK 8`

##### PMODE21 - PSC 2 Mode

`#define PMODE21_BIT 4`

`#define PMODE21_MASK 16`

##### PLOCK2 - PSC 2 Lock

`#define PLOCK2_BIT 5`

`#define PLOCK2_MASK 32`

##### PALOCK2 - PSC 2 Autolock

`#define PALOCK2_BIT 6`

`#define PALOCK2_MASK 64`

##### PFIFTY2 - PSC 2 Fifty

`#define PFIFTY2_BIT 7`

`#define PFIFTY2_MASK 128`

### OCR2RBH - Output Compare RB Register High

`sfrb OCR2RBH = 0xF9;`

##### OCR2RB_8

`#define OCR2RB_8_BIT 0`

`#define OCR2RB_8_MASK 1`

##### OCR2RB_9

`#define OCR2RB_9_BIT 1`

`#define OCR2RB_9_MASK 2`

##### OCR2RB_10

`#define OCR2RB_10_BIT 2`

`#define OCR2RB_10_MASK 4`

##### OCR2RB_11

`#define OCR2RB_11_BIT 3`

`#define OCR2RB_11_MASK 8`

##### OCR2RB_12

`#define OCR2RB_12_BIT 4`

`#define OCR2RB_12_MASK 16`

##### OCR2RB_13

`#define OCR2RB_13_BIT 5`

`#define OCR2RB_13_MASK 32`

##### OCR2RB_14

`#define OCR2RB_14_BIT 6`

`#define OCR2RB_14_MASK 64`

##### OCR2RB_15

`#define OCR2RB_15_BIT 7`

`#define OCR2RB_15_MASK 128`

### OCR2RBL - Output Compare RB Register Low

`sfrb OCR2RBL = 0xF8;`

##### OCR2RB_0

`#define OCR2RB_0_BIT 0`

`#define OCR2RB_0_MASK 1`

##### OCR2RB_1

`#define OCR2RB_1_BIT 1`

`#define OCR2RB_1_MASK 2`

##### OCR2RB_2

`#define OCR2RB_2_BIT 2`

`#define OCR2RB_2_MASK 4`

##### OCR2RB_3

`#define OCR2RB_3_BIT 3`

`#define OCR2RB_3_MASK 8`

##### OCR2RB_4

`#define OCR2RB_4_BIT 4`

`#define OCR2RB_4_MASK 16`

##### OCR2RB_5

`#define OCR2RB_5_BIT 5`

`#define OCR2RB_5_MASK 32`

##### OCR2RB_6

`#define OCR2RB_6_BIT 6`

`#define OCR2RB_6_MASK 64`

##### OCR2RB_7

`#define OCR2RB_7_BIT 7`

`#define OCR2RB_7_MASK 128`

### OCR2SBH - Output Compare SB Register High

`sfrb OCR2SBH = 0xF7;`

##### OCR2SB_8

`#define OCR2SB_8_BIT 0`

`#define OCR2SB_8_MASK 1`

##### OCR2SB_9

`#define OCR2SB_9_BIT 1`

`#define OCR2SB_9_MASK 2`

##### OCR2SB_10

`#define OCR2SB_10_BIT 2`

`#define OCR2SB_10_MASK 4`

##### OCR2SB_11

`#define OCR2SB_11_BIT 3`

`#define OCR2SB_11_MASK 8`

### OCR2SBL - Output Compare SB Register Low

`sfrb OCR2SBL = 0xF6;`

##### OCR2SB_0

`#define OCR2SB_0_BIT 0`

`#define OCR2SB_0_MASK 1`

##### OCR2SB_1

`#define OCR2SB_1_BIT 1`

`#define OCR2SB_1_MASK 2`

##### OCR2SB_2

`#define OCR2SB_2_BIT 2`

`#define OCR2SB_2_MASK 4`

##### OCR2SB_3

`#define OCR2SB_3_BIT 3`

`#define OCR2SB_3_MASK 8`

##### OCR2SB_4

`#define OCR2SB_4_BIT 4`

`#define OCR2SB_4_MASK 16`

##### OCR2SB_5

`#define OCR2SB_5_BIT 5`

`#define OCR2SB_5_MASK 32`

##### OCR2SB_6

`#define OCR2SB_6_BIT 6`

`#define OCR2SB_6_MASK 64`

##### OCR2SB_7

`#define OCR2SB_7_BIT 7`

`#define OCR2SB_7_MASK 128`

### OCR2RAH - Output Compare RA Register High

`sfrb OCR2RAH = 0xF5;`

##### OCR2RA_8

`#define OCR2RA_8_BIT 0`

`#define OCR2RA_8_MASK 1`

##### OCR2RA_9

`#define OCR2RA_9_BIT 1`

`#define OCR2RA_9_MASK 2`

##### OCR2RA_10

`#define OCR2RA_10_BIT 2`

`#define OCR2RA_10_MASK 4`

##### OCR2RA_11

`#define OCR2RA_11_BIT 3`

`#define OCR2RA_11_MASK 8`

### OCR2RAL - Output Compare RA Register Low

`sfrb OCR2RAL = 0xF4;`

##### OCR2RA_0

`#define OCR2RA_0_BIT 0`

`#define OCR2RA_0_MASK 1`

##### OCR2RA_1

`#define OCR2RA_1_BIT 1`

`#define OCR2RA_1_MASK 2`

##### OCR2RA_2

`#define OCR2RA_2_BIT 2`

`#define OCR2RA_2_MASK 4`

##### OCR2RA_3

`#define OCR2RA_3_BIT 3`

`#define OCR2RA_3_MASK 8`

##### OCR2RA_4

`#define OCR2RA_4_BIT 4`

`#define OCR2RA_4_MASK 16`

##### OCR2RA_5

`#define OCR2RA_5_BIT 5`

`#define OCR2RA_5_MASK 32`

##### OCR2RA_6

`#define OCR2RA_6_BIT 6`

`#define OCR2RA_6_MASK 64`

##### OCR2RA_7

`#define OCR2RA_7_BIT 7`

`#define OCR2RA_7_MASK 128`

### OCR2SAH - Output Compare SA Register High

`sfrb OCR2SAH = 0xF3;`

##### OCR2SA_8

`#define OCR2SA_8_BIT 0`

`#define OCR2SA_8_MASK 1`

##### OCR2SA_9

`#define OCR2SA_9_BIT 1`

`#define OCR2SA_9_MASK 2`

##### OCR2SA_10

`#define OCR2SA_10_BIT 2`

`#define OCR2SA_10_MASK 4`

##### OCR2SA_11

`#define OCR2SA_11_BIT 3`

`#define OCR2SA_11_MASK 8`

### OCR2SAL - Output Compare SA Register Low

`sfrb OCR2SAL = 0xF2;`

##### OCR2SA_0

`#define OCR2SA_0_BIT 0`

`#define OCR2SA_0_MASK 1`

##### OCR2SA_1

`#define OCR2SA_1_BIT 1`

`#define OCR2SA_1_MASK 2`

##### OCR2SA_2

`#define OCR2SA_2_BIT 2`

`#define OCR2SA_2_MASK 4`

##### OCR2SA_3

`#define OCR2SA_3_BIT 3`

`#define OCR2SA_3_MASK 8`

##### OCR2SA_4

`#define OCR2SA_4_BIT 4`

`#define OCR2SA_4_MASK 16`

##### OCR2SA_5

`#define OCR2SA_5_BIT 5`

`#define OCR2SA_5_MASK 32`

##### OCR2SA_6

`#define OCR2SA_6_BIT 6`

`#define OCR2SA_6_MASK 64`

##### OCR2SA_7

`#define OCR2SA_7_BIT 7`

`#define OCR2SA_7_MASK 128`

### POM2 - PSC 2 Output Matrix

`sfrb POM2 = 0xF1;`

##### POMV2A0 - Output Matrix Output A Ramp 0

`#define POMV2A0_BIT 0`

`#define POMV2A0_MASK 1`

##### POMV2A1 - Output Matrix Output A Ramp 1

`#define POMV2A1_BIT 1`

`#define POMV2A1_MASK 2`

##### POMV2A2 - Output Matrix Output A Ramp 2

`#define POMV2A2_BIT 2`

`#define POMV2A2_MASK 4`

##### POMV2A3 - Output Matrix Output A Ramp 3

`#define POMV2A3_BIT 3`

`#define POMV2A3_MASK 8`

##### POMV2B0 - Output Matrix Output B Ramp 0

`#define POMV2B0_BIT 4`

`#define POMV2B0_MASK 16`

##### POMV2B1 - Output Matrix Output B Ramp 2

`#define POMV2B1_BIT 5`

`#define POMV2B1_MASK 32`

##### POMV2B2 - Output Matrix Output B Ramp 2

`#define POMV2B2_BIT 6`

`#define POMV2B2_MASK 64`

##### POMV2B3 - Output Matrix Output B Ramp 3

`#define POMV2B3_BIT 7`

`#define POMV2B3_MASK 128`

### PSOC2 - PSC2 Synchro and Output Configuration

`sfrb PSOC2 = 0xF0;`

##### POEN2A - PSCOUT20 Output Enable

`#define POEN2A_BIT 0`

`#define POEN2A_MASK 1`

##### POEN2C - PSCOUT22 Output Enable

`#define POEN2C_BIT 1`

`#define POEN2C_MASK 2`

##### POEN2B - PSCOUT21 Output Enable

`#define POEN2B_BIT 2`

`#define POEN2B_MASK 4`

##### POEN2D - PSCOUT23 Output Enable

`#define POEN2D_BIT 3`

`#define POEN2D_MASK 8`

##### PSYNC2_0 - Synchronization Out for ADC Selection

`#define PSYNC2_0_BIT 4`

`#define PSYNC2_0_MASK 16`

##### PSYNC2_1 - Synchronization Out for ADC Selection

`#define PSYNC2_1_BIT 5`

`#define PSYNC2_1_MASK 32`

##### POS22 - PSC 2 Output 22 Select

`#define POS22_BIT 6`

`#define POS22_MASK 64`

##### POS23 - PSC 2 Output 23 Select

`#define POS23_BIT 7`

`#define POS23_MASK 128`

### PIM2 - PSC2 Interrupt Mask Register

`sfrb PIM2 = $A5;`

##### PEOPE2 - End of Cycle Interrupt Enable

`#define PEOPE2_BIT 0`

`#define PEOPE2_MASK 1`

##### PEVE2A - External Event A Interrupt Enable

`#define PEVE2A_BIT 3`

`#define PEVE2A_MASK 8`

##### PEVE2B - External Event B Interrupt Enable

`#define PEVE2B_BIT 4`

`#define PEVE2B_MASK 16`

##### PSEIE2 - PSC 2 Synchro Error Interrupt Enable

`#define PSEIE2_BIT 5`

`#define PSEIE2_MASK 32`

### PIFR2 - PSC2 Interrupt Flag Register

`sfrb PIFR2 = $A4;`

##### PEOP2 - End of PSC2 Interrupt

`#define PEOP2_BIT 0`

`#define PEOP2_MASK 1`

##### PRN20 - Ramp Number

`#define PRN20_BIT 1`

`#define PRN20_MASK 2`

##### PRN21 - Ramp Number

`#define PRN21_BIT 2`

`#define PRN21_MASK 4`

##### PEV2A - External Event A Interrupt

`#define PEV2A_BIT 3`

`#define PEV2A_MASK 8`

##### PEV2B - External Event B Interrupt

`#define PEV2B_BIT 4`

`#define PEV2B_MASK 16`

##### PSEI2 - PSC 2 Synchro Error Interrupt

`#define PSEI2_BIT 5`

`#define PSEI2_MASK 32`

##### POAC2A - PSC 2 Output A Activity

`#define POAC2A_BIT 6`

`#define POAC2A_MASK 64`

##### POAC2B - PSC 2 Output A Activity

`#define POAC2B_BIT 7`

`#define POAC2B_MASK 128`