This documentation was generated automatically from the AVR Studio part description file `ATtiny13.pdf`.

## AD CONVERTER

AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode Noise

### ADMUX - The ADC multiplexer Selection Register

`sfrb ADMUX = $07;`

##### MUX0 - Analog Channel and Gain Selection Bits

`#define MUX0_BIT 0`

`#define MUX0_MASK 1`

The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).

##### MUX1 - Analog Channel and Gain Selection Bits

`#define MUX1_BIT 1`

`#define MUX1_MASK 2`

The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).

##### ADLAR - Left Adjust Result

`#define ADLAR_BIT 5`

`#define ADLAR_MASK 32`

The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see ?The ADC Data Register -ADCL and ADCH? on page 198.

##### REFS0 - Reference Selection Bit 0

`#define REFS0_BIT 6`

`#define REFS0_MASK 64`

These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.

### ADCSRA - The ADC Control and Status register

`sfrb ADCSRA = $06;`

##### ADPS0 - ADC Prescaler Select Bits

`#define ADPS0_BIT 0`

`#define ADPS0_MASK 1`

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

##### ADPS1 - ADC Prescaler Select Bits

`#define ADPS1_BIT 1`

`#define ADPS1_MASK 2`

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

##### ADPS2 - ADC Prescaler Select Bits

`#define ADPS2_BIT 2`

`#define ADPS2_MASK 4`

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

##### ADIE - ADC Interrupt Enable

`#define ADIE_BIT 3`

`#define ADIE_MASK 8`

When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.

##### ADIF - ADC Interrupt Flag

`#define ADIF_BIT 4`

`#define ADIF_MASK 16`

This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.

##### ADATE - ADC Auto Trigger Enable

`#define ADATE_BIT 5`

`#define ADATE_MASK 32`

When this bit is written to one,Auto Triggering of the ADC is enabled.The ADC will start a conversion on a positive edge of the selected trigger signal.The trigger source is selected by setting the ADC Trigger Select bits,ADTS in ADCSRB.

##### ADSC - ADC Start Conversion

`#define ADSC_BIT 6`

`#define ADSC_MASK 64`

In Single Conversion Mode, a logical ?1? must be written to this bit to start each conversion. In Free Running Mode, a logical ?1? must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect

##### ADEN - ADC Enable

`#define ADEN_BIT 7`

`#define ADEN_MASK 128`

Writing a logical ?1? to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.

### ADCH - ADC Data Register High Byte

`sfrb ADCH = $05;`

##### ADCH0 - ADC Data Register High Byte Bit 0

`#define ADCH0_BIT 0`

`#define ADCH0_MASK 1`

##### ADCH1 - ADC Data Register High Byte Bit 1

`#define ADCH1_BIT 1`

`#define ADCH1_MASK 2`

##### ADCH2 - ADC Data Register High Byte Bit 2

`#define ADCH2_BIT 2`

`#define ADCH2_MASK 4`

##### ADCH3 - ADC Data Register High Byte Bit 3

`#define ADCH3_BIT 3`

`#define ADCH3_MASK 8`

##### ADCH4 - ADC Data Register High Byte Bit 4

`#define ADCH4_BIT 4`

`#define ADCH4_MASK 16`

##### ADCH5 - ADC Data Register High Byte Bit 5

`#define ADCH5_BIT 5`

`#define ADCH5_MASK 32`

##### ADCH6 - ADC Data Register High Byte Bit 6

`#define ADCH6_BIT 6`

`#define ADCH6_MASK 64`

##### ADCH7 - ADC Data Register High Byte Bit 7

`#define ADCH7_BIT 7`

`#define ADCH7_MASK 128`

### ADCL - ADC Data Register Low Byte

`sfrb ADCL = $04;`

##### ADCL0 - ADC Data Register Low Byte Bit 0

`#define ADCL0_BIT 0`

`#define ADCL0_MASK 1`

##### ADCL1 - ADC Data Register Low Byte Bit 1

`#define ADCL1_BIT 1`

`#define ADCL1_MASK 2`

##### ADCL2 - ADC Data Register Low Byte Bit 2

`#define ADCL2_BIT 2`

`#define ADCL2_MASK 4`

##### ADCL3 - ADC Data Register Low Byte Bit 3

`#define ADCL3_BIT 3`

`#define ADCL3_MASK 8`

##### ADCL4 - ADC Data Register Low Byte Bit 4

`#define ADCL4_BIT 4`

`#define ADCL4_MASK 16`

##### ADCL5 - ADC Data Register Low Byte Bit 5

`#define ADCL5_BIT 5`

`#define ADCL5_MASK 32`

##### ADCL6 - ADC Data Register Low Byte Bit 6

`#define ADCL6_BIT 6`

`#define ADCL6_MASK 64`

##### ADCL7 - ADC Data Register Low Byte Bit 7

`#define ADCL7_BIT 7`

`#define ADCL7_MASK 128`

### ADCSRB - ADC Control and Status Register B

`sfrb ADCSRB = $03;`

##### ADTS0 - ADC Auto Trigger Source 0

`#define ADTS0_BIT 0`

`#define ADTS0_MASK 1`

If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set .

##### ADTS1 - ADC Auto Trigger Source 1

`#define ADTS1_BIT 1`

`#define ADTS1_MASK 2`

If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set .

##### ADTS2 - ADC Auto Trigger Source 2

`#define ADTS2_BIT 2`

`#define ADTS2_MASK 4`

If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set .

### DIDR0 - Digital Input Disable Register 0

`sfrb DIDR0 = $14;`

##### ADC1D - ADC2 Digital input Disable

`#define ADC1D_BIT 2`

`#define ADC1D_MASK 4`

When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

##### ADC3D - ADC3 Digital input Disable

`#define ADC3D_BIT 3`

`#define ADC3D_MASK 8`

When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

##### ADC2D - ADC2 Digital input Disable

`#define ADC2D_BIT 4`

`#define ADC2D_MASK 16`

When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

##### ADC0D - ADC0 Digital input Disable

`#define ADC0D_BIT 5`

`#define ADC0D_MASK 32`

When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

## ANALOG COMPARATOR

### ADCSRB - ADC Control and Status Register B

`sfrb ADCSRB = $03;`

##### ACME - Analog Comparator Multiplexer Enable

`#define ACME_BIT 6`

`#define ACME_MASK 64`

When this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see ?Analog Comparator Multiplexed Input? on page 186.

### ACSR - Analog Comparator Control And Status Register

`sfrb ACSR = $08;`

##### ACIS0 - Analog Comparator Interrupt Mode Select bit 0

`#define ACIS0_BIT 0`

`#define ACIS0_MASK 1`

These bits determine which comparator events that trigger the Analog Comparator interrupt.

##### ACIS1 - Analog Comparator Interrupt Mode Select bit 1

`#define ACIS1_BIT 1`

`#define ACIS1_MASK 2`

These bits determine which comparator events that trigger the Analog Comparator interrupt.

##### ACIE - Analog Comparator Interrupt Enable

`#define ACIE_BIT 3`

`#define ACIE_MASK 8`

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.

##### ACI - Analog Comparator Interrupt Flag

`#define ACI_BIT 4`

`#define ACI_MASK 16`

This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

##### ACO - Analog Compare Output

`#define ACO_BIT 5`

`#define ACO_MASK 32`

The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.

##### ACBG - Analog Comparator Bandgap Select

`#define ACBG_BIT 6`

`#define ACBG_MASK 64`

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See ?Internal Voltage Reference? on page 42.

##### ACD - Analog Comparator Disable

`#define ACD_BIT 7`

`#define ACD_MASK 128`

When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

### DIDR0 -

`sfrb DIDR0 = $14;`

##### AIN0D - AIN0 Digital Input Disable

`#define AIN0D_BIT 0`

`#define AIN0D_MASK 1`

When this bit is written logic one,the digital input buffer on the AIN1/0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

##### AIN1D - AIN1 Digital Input Disable

`#define AIN1D_BIT 1`

`#define AIN1D_MASK 2`

When this bit is written logic one,the digital input buffer on the AIN1/0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

## EEPROM

### EEAR - EEPROM Read/Write Access

`sfrb EEAR = $1E;`

##### EEAR0 - EEPROM Read/Write Access bit 0

`#define EEAR0_BIT 0`

`#define EEAR0_MASK 1`

##### EEAR1 - EEPROM Read/Write Access bit 1

`#define EEAR1_BIT 1`

`#define EEAR1_MASK 2`

##### EEAR2 - EEPROM Read/Write Access bit 2

`#define EEAR2_BIT 2`

`#define EEAR2_MASK 4`

##### EEAR3 - EEPROM Read/Write Access bit 3

`#define EEAR3_BIT 3`

`#define EEAR3_MASK 8`

##### EEAR4 - EEPROM Read/Write Access bit 4

`#define EEAR4_BIT 4`

`#define EEAR4_MASK 16`

##### EEAR5 - EEPROM Read/Write Access bit 5

`#define EEAR5_BIT 5`

`#define EEAR5_MASK 32`

### EEDR - EEPROM Data Register

`sfrb EEDR = $1D;`

##### EEDR0 - EEPROM Data Register bit 0

`#define EEDR0_BIT 0`

`#define EEDR0_MASK 1`

##### EEDR1 - EEPROM Data Register bit 1

`#define EEDR1_BIT 1`

`#define EEDR1_MASK 2`

##### EEDR2 - EEPROM Data Register bit 2

`#define EEDR2_BIT 2`

`#define EEDR2_MASK 4`

##### EEDR3 - EEPROM Data Register bit 3

`#define EEDR3_BIT 3`

`#define EEDR3_MASK 8`

##### EEDR4 - EEPROM Data Register bit 4

`#define EEDR4_BIT 4`

`#define EEDR4_MASK 16`

##### EEDR5 - EEPROM Data Register bit 5

`#define EEDR5_BIT 5`

`#define EEDR5_MASK 32`

##### EEDR6 - EEPROM Data Register bit 6

`#define EEDR6_BIT 6`

`#define EEDR6_MASK 64`

##### EEDR7 - EEPROM Data Register bit 7

`#define EEDR7_BIT 7`

`#define EEDR7_MASK 128`

### EECR - EEPROM Control Register

`sfrb EECR = $1C;`

##### EERE - EEPROM Read Enable

`#define EERE_BIT 0`

`#define EERE_MASK 1`

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined.

##### EEWE - EEPROM Write Enable

`#define EEWE_BIT 1`

`#define EEWE_MASK 2`

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one to the EEMWE bit, the EEWE bit mustbewritten to zero in thesamecycle). 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at V CC =5Vor 4msatV CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted or two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems.

##### EEMWE - EEPROM Master Write Enable

`#define EEMWE_BIT 2`

`#define EEMWE_MASK 4`

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure.

##### EERIE - EEProm Ready Interrupt Enable

`#define EERIE_BIT 3`

`#define EERIE_MASK 8`

When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero).

##### EEPM0

`#define EEPM0_BIT 4`

`#define EEPM0_MASK 16`

##### EEPM1

`#define EEPM1_BIT 5`

`#define EEPM1_MASK 32`

## CPU

### SREG - Status Register

`sfrb SREG = $3F;`

### SPL - Stack Pointer Low Byte

`sfrb SPL = $3D;`

##### SP0 - Stack Pointer Bit 0

`#define SP0_BIT 0`

`#define SP0_MASK 1`

##### SP1 - Stack Pointer Bit 1

`#define SP1_BIT 1`

`#define SP1_MASK 2`

##### SP2 - Stack Pointer Bit 2

`#define SP2_BIT 2`

`#define SP2_MASK 4`

##### SP3 - Stack Pointer Bit 3

`#define SP3_BIT 3`

`#define SP3_MASK 8`

##### SP4

`#define SP4_BIT 4`

`#define SP4_MASK 16`

##### SP5 - Stack Pointer Bit 5

`#define SP5_BIT 5`

`#define SP5_MASK 32`

##### SP6 - Stack Pointer Bit 6

`#define SP6_BIT 6`

`#define SP6_MASK 64`

##### SP7 - Stack Pointer Bit 7

`#define SP7_BIT 7`

`#define SP7_MASK 128`

### MCUCR - MCU Control Register

`sfrb MCUCR = $35;`

##### ISC00 - Interrupt Sense Control 0 bit 0

`#define ISC00_BIT 0`

`#define ISC00_MASK 1`

##### ISC01 - Interrupt Sense Control 0 bit 1

`#define ISC01_BIT 1`

`#define ISC01_MASK 2`

##### SM0 - Sleep Mode Select Bit 0

`#define SM0_BIT 3`

`#define SM0_MASK 8`

##### SM1 - Sleep Mode Select Bit 1

`#define SM1_BIT 4`

`#define SM1_MASK 16`

##### SE - Sleep Enable

`#define SE_BIT 5`

`#define SE_MASK 32`

The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.

##### PUD - Pull-up Disable

`#define PUD_BIT 6`

`#define PUD_MASK 64`

### MCUSR - MCU Status register

`sfrb MCUSR = $34;`

##### PORF - Power-On Reset Flag

`#define PORF_BIT 0`

`#define PORF_MASK 1`

This bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchanged

##### EXTRF - External Reset Flag

`#define EXTRF_BIT 1`

`#define EXTRF_MASK 2`

After a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged.

##### BORF - Brown-out Reset Flag

`#define BORF_BIT 2`

`#define BORF_MASK 4`

##### WDRF - Watchdog Reset Flag

`#define WDRF_BIT 3`

`#define WDRF_MASK 8`

### OSCCAL - Oscillator Calibration Register

`sfrb OSCCAL = $31;`

##### CAL0 - Oscillatro Calibration Value Bit 0

`#define CAL0_BIT 0`

`#define CAL0_MASK 1`

##### CAL1 - Oscillatro Calibration Value Bit 1

`#define CAL1_BIT 1`

`#define CAL1_MASK 2`

##### CAL2 - Oscillatro Calibration Value Bit 2

`#define CAL2_BIT 2`

`#define CAL2_MASK 4`

##### CAL3 - Oscillatro Calibration Value Bit 3

`#define CAL3_BIT 3`

`#define CAL3_MASK 8`

##### CAL4 - Oscillatro Calibration Value Bit 4

`#define CAL4_BIT 4`

`#define CAL4_MASK 16`

##### CAL5 - Oscillatro Calibration Value Bit 5

`#define CAL5_BIT 5`

`#define CAL5_MASK 32`

##### CAL6 - Oscillatro Calibration Value Bit 6

`#define CAL6_BIT 6`

`#define CAL6_MASK 64`

### CLKPR - Clock Prescale Register

`sfrb CLKPR = $26;`

##### CLKPS0 - Clock Prescaler Select Bit 0

`#define CLKPS0_BIT 0`

`#define CLKPS0_MASK 1`

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given a table in the device user guide.. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted

##### CLKPS1 - Clock Prescaler Select Bit 1

`#define CLKPS1_BIT 1`

`#define CLKPS1_MASK 2`

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given a table in the device user guide.. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted

##### CLKPS2 - Clock Prescaler Select Bit 2

`#define CLKPS2_BIT 2`

`#define CLKPS2_MASK 4`

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given a table in the device user guide.. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted

##### CLKPS3 - Clock Prescaler Select Bit 3

`#define CLKPS3_BIT 3`

`#define CLKPS3_MASK 8`

##### CLKPCE - Clock Prescaler Change Enable

`#define CLKPCE_BIT 7`

`#define CLKPCE_MASK 128`

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only update when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS is written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.

### DWDR - Debug Wire Data Register

`sfrb DWDR = $2E;`

##### DWDR0 - Debug Wire Data Register Bit 0

`#define DWDR0_BIT 0`

`#define DWDR0_MASK 1`

##### DWDR1 - Debug Wire Data Register Bit 1

`#define DWDR1_BIT 1`

`#define DWDR1_MASK 2`

##### DWDR2 - Debug Wire Data Register Bit 2

`#define DWDR2_BIT 2`

`#define DWDR2_MASK 4`

##### DWDR3 - Debug Wire Data Register Bit 3

`#define DWDR3_BIT 3`

`#define DWDR3_MASK 8`

##### DWDR4 - Debug Wire Data Register Bit 4

`#define DWDR4_BIT 4`

`#define DWDR4_MASK 16`

##### DWDR5 - Debug Wire Data Register Bit 5

`#define DWDR5_BIT 5`

`#define DWDR5_MASK 32`

##### DWDR6 - Debug Wire Data Register Bit 6

`#define DWDR6_BIT 6`

`#define DWDR6_MASK 64`

##### DWDR7 - Debug Wire Data Register Bit 7

`#define DWDR7_BIT 7`

`#define DWDR7_MASK 128`

### SPMCSR - Store Program Memory Control and Status Register

`sfrb SPMCSR = $37;`

##### SPMEN - Store program Memory Enable

`#define SPMEN_BIT 0`

`#define SPMEN_MASK 1`

This bit enables the SPM instruction for the next four clock cycles. If written to one together with either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. Writing any other combination than ?10001?, ?01001?, ?00101?, ?00011? or ?00001? in the lower five bits will have no effect

##### PGERS - Page Erase

`#define PGERS_BIT 1`

`#define PGERS_MASK 2`

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation.

##### PGWRT - Page Write

`#define PGWRT_BIT 2`

`#define PGWRT_MASK 4`

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation.

##### RFLB - Read Fuse and Lock Bits

`#define RFLB_BIT 3`

`#define RFLB_MASK 8`

An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Zpointer) into the destination register. See ?EEPROM Write Prevents Writing to SPMCSR? on page 98 in the data sheet for details.

##### CTPB - Clear Temporary Page Buffer

`#define CTPB_BIT 4`

`#define CTPB_MASK 16`

If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost.

## PORTB

### PORTB - Data Register, Port B

`sfrb PORTB = $18;`

##### PORTB0

`#define PORTB0_BIT 0`

`#define PORTB0_MASK 1`

##### PORTB1

`#define PORTB1_BIT 1`

`#define PORTB1_MASK 2`

##### PORTB2

`#define PORTB2_BIT 2`

`#define PORTB2_MASK 4`

##### PORTB3

`#define PORTB3_BIT 3`

`#define PORTB3_MASK 8`

##### PORTB4

`#define PORTB4_BIT 4`

`#define PORTB4_MASK 16`

##### PORTB5

`#define PORTB5_BIT 5`

`#define PORTB5_MASK 32`

### DDRB - Data Direction Register, Port B

`sfrb DDRB = $17;`

##### DDB0

`#define DDB0_BIT 0`

`#define DDB0_MASK 1`

##### DDB1

`#define DDB1_BIT 1`

`#define DDB1_MASK 2`

##### DDB2

`#define DDB2_BIT 2`

`#define DDB2_MASK 4`

##### DDB3

`#define DDB3_BIT 3`

`#define DDB3_MASK 8`

##### DDB4

`#define DDB4_BIT 4`

`#define DDB4_MASK 16`

##### DDB5

`#define DDB5_BIT 5`

`#define DDB5_MASK 32`

### PINB - Input Pins, Port B

`sfrb PINB = $16;`

##### PINB0

`#define PINB0_BIT 0`

`#define PINB0_MASK 1`

##### PINB1

`#define PINB1_BIT 1`

`#define PINB1_MASK 2`

##### PINB2

`#define PINB2_BIT 2`

`#define PINB2_MASK 4`

##### PINB3

`#define PINB3_BIT 3`

`#define PINB3_MASK 8`

##### PINB4

`#define PINB4_BIT 4`

`#define PINB4_MASK 16`

##### PINB5

`#define PINB5_BIT 5`

`#define PINB5_MASK 32`

## EXTERNAL INTERRUPT

### MCUCR - MCU Control Register

`sfrb MCUCR = $35;`

##### ISC00 - Interrupt Sense Control 0 Bit 0

`#define ISC00_BIT 0`

`#define ISC00_MASK 1`

##### ISC01 - Interrupt Sense Control 0 Bit 1

`#define ISC01_BIT 1`

`#define ISC01_MASK 2`

### GIMSK - General Interrupt Mask Register

`sfrb GIMSK = $3B;`

##### PCIE - Pin Change Interrupt Enable

`#define PCIE_BIT 5`

`#define PCIE_MASK 32`

##### INT0 - External Interrupt Request 0 Enable

`#define INT0_BIT 6`

`#define INT0_MASK 64`

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also ?External Interrupts.? ? Bits 5..0 - Res: Reserved bits

### GIFR - General Interrupt Flag register

`sfrb GIFR = $3A;`

##### PCIF - Pin Change Interrupt Flag

`#define PCIF_BIT 5`

`#define PCIF_MASK 32`

##### INTF0 - External Interrupt Flag 0

`#define INTF0_BIT 6`

`#define INTF0_MASK 64`

When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

### PCMSK - Pin Change Enable Mask

`sfrb PCMSK = $15;`

##### PCINT0 - Pin Change Enable Mask Bit 0

`#define PCINT0_BIT 0`

`#define PCINT0_MASK 1`

##### PCINT1 - Pin Change Enable Mask Bit 1

`#define PCINT1_BIT 1`

`#define PCINT1_MASK 2`

##### PCINT2 - Pin Change Enable Mask Bit 2

`#define PCINT2_BIT 2`

`#define PCINT2_MASK 4`

##### PCINT3 - Pin Change Enable Mask Bit 3

`#define PCINT3_BIT 3`

`#define PCINT3_MASK 8`

##### PCINT4 - Pin Change Enable Mask Bit 4

`#define PCINT4_BIT 4`

`#define PCINT4_MASK 16`

##### PCINT5 - Pin Change Enable Mask Bit 5

`#define PCINT5_BIT 5`

`#define PCINT5_MASK 32`

## TIMER COUNTER 0

### TIMSK0 - Timer/Counter0 Interrupt Mask Register

`sfrb TIMSK0 = $39;`

##### TOIE0 - Timer/Counter0 Overflow Interrupt Enable

`#define TOIE0_BIT 1`

`#define TOIE0_MASK 2`

##### OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable

`#define OCIE0A_BIT 2`

`#define OCIE0A_MASK 4`

##### OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable

`#define OCIE0B_BIT 3`

`#define OCIE0B_MASK 8`

### TIFR0 - Timer/Counter0 Interrupt Flag register

`sfrb TIFR0 = $38;`

##### TOV0 - Timer/Counter0 Overflow Flag

`#define TOV0_BIT 1`

`#define TOV0_MASK 2`

##### OCF0A - Timer/Counter0 Output Compare Flag 0A

`#define OCF0A_BIT 2`

`#define OCF0A_MASK 4`

##### OCF0B - Timer/Counter0 Output Compare Flag 0B

`#define OCF0B_BIT 3`

`#define OCF0B_MASK 8`

### OCR0A - Timer/Counter0 Output Compare Register

`sfrb OCR0A = $36;`

##### OCR0_0

`#define OCR0_0_BIT 0`

`#define OCR0_0_MASK 1`

##### OCR0_1

`#define OCR0_1_BIT 1`

`#define OCR0_1_MASK 2`

##### OCR0_2

`#define OCR0_2_BIT 2`

`#define OCR0_2_MASK 4`

##### OCR0_3

`#define OCR0_3_BIT 3`

`#define OCR0_3_MASK 8`

##### OCR0_4

`#define OCR0_4_BIT 4`

`#define OCR0_4_MASK 16`

##### OCR0_5

`#define OCR0_5_BIT 5`

`#define OCR0_5_MASK 32`

##### OCR0_6

`#define OCR0_6_BIT 6`

`#define OCR0_6_MASK 64`

##### OCR0_7

`#define OCR0_7_BIT 7`

`#define OCR0_7_MASK 128`

### TCCR0A - Timer/Counter Control Register A

`sfrb TCCR0A = $2F;`

##### WGM00 - Waveform Generation Mode

`#define WGM00_BIT 0`

`#define WGM00_MASK 1`

##### WGM01 - Waveform Generation Mode

`#define WGM01_BIT 1`

`#define WGM01_MASK 2`

##### COM0B0 - Compare Match Output B Mode

`#define COM0B0_BIT 4`

`#define COM0B0_MASK 16`

##### COM0B1 - Compare Match Output B Mode

`#define COM0B1_BIT 5`

`#define COM0B1_MASK 32`

##### COM0A0 - Compare Match Output A Mode

`#define COM0A0_BIT 6`

`#define COM0A0_MASK 64`

##### COM0A1 - Compare Match Output A Mode

`#define COM0A1_BIT 7`

`#define COM0A1_MASK 128`

### TCNT0 - Timer/Counter0

`sfrb TCNT0 = $32;`

##### TCNT0_0

`#define TCNT0_0_BIT 0`

`#define TCNT0_0_MASK 1`

##### TCNT0_1

`#define TCNT0_1_BIT 1`

`#define TCNT0_1_MASK 2`

##### TCNT0_2

`#define TCNT0_2_BIT 2`

`#define TCNT0_2_MASK 4`

##### TCNT0_3

`#define TCNT0_3_BIT 3`

`#define TCNT0_3_MASK 8`

##### TCNT0_4

`#define TCNT0_4_BIT 4`

`#define TCNT0_4_MASK 16`

##### TCNT0_5

`#define TCNT0_5_BIT 5`

`#define TCNT0_5_MASK 32`

##### TCNT0_6

`#define TCNT0_6_BIT 6`

`#define TCNT0_6_MASK 64`

##### TCNT0_7

`#define TCNT0_7_BIT 7`

`#define TCNT0_7_MASK 128`

### TCCR0B - Timer/Counter Control Register B

`sfrb TCCR0B = $33;`

##### CS00 - Clock Select

`#define CS00_BIT 0`

`#define CS00_MASK 1`

##### CS01 - Clock Select

`#define CS01_BIT 1`

`#define CS01_MASK 2`

##### CS02 - Clock Select

`#define CS02_BIT 2`

`#define CS02_MASK 4`

##### WGM02 - Waveform Generation Mode

`#define WGM02_BIT 3`

`#define WGM02_MASK 8`

##### FOC0B - Force Output Compare B

`#define FOC0B_BIT 6`

`#define FOC0B_MASK 64`

##### FOC0A - Force Output Compare A

`#define FOC0A_BIT 7`

`#define FOC0A_MASK 128`

### OCR0B - Timer/Counter0 Output Compare Register

`sfrb OCR0B = $29;`

##### OCR0_0

`#define OCR0_0_BIT 0`

`#define OCR0_0_MASK 1`

##### OCR0_1

`#define OCR0_1_BIT 1`

`#define OCR0_1_MASK 2`

##### OCR0_2

`#define OCR0_2_BIT 2`

`#define OCR0_2_MASK 4`

##### OCR0_3

`#define OCR0_3_BIT 3`

`#define OCR0_3_MASK 8`

##### OCR0_4

`#define OCR0_4_BIT 4`

`#define OCR0_4_MASK 16`

##### OCR0_5

`#define OCR0_5_BIT 5`

`#define OCR0_5_MASK 32`

##### OCR0_6

`#define OCR0_6_BIT 6`

`#define OCR0_6_MASK 64`

##### OCR0_7

`#define OCR0_7_BIT 7`

`#define OCR0_7_MASK 128`

### GTCCR - General Timer Conuter Register

`sfrb GTCCR = $28;`

##### PSR10 - Prescaler Reset Timer/Counter0

`#define PSR10_BIT 0`

`#define PSR10_MASK 1`

##### TSM - Timer/Counter Synchronization Mode

`#define TSM_BIT 7`

`#define TSM_MASK 128`

## WATCHDOG

### WDTCR - Watchdog Timer Control Register

`sfrb WDTCR = $21;`

##### WDP0 - Watch Dog Timer Prescaler bit 0

`#define WDP0_BIT 0`

`#define WDP0_MASK 1`

##### WDP1 - Watch Dog Timer Prescaler bit 1

`#define WDP1_BIT 1`

`#define WDP1_MASK 2`

##### WDP2 - Watch Dog Timer Prescaler bit 2

`#define WDP2_BIT 2`

`#define WDP2_MASK 4`

##### WDE - Watch Dog Enable

`#define WDE_BIT 3`

`#define WDE_MASK 8`

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog

##### WDCE - Watchdog Change Enable

`#define WDCE_BIT 4`

`#define WDCE_MASK 16`

##### WDP3 - Watchdog Timer Prescaler Bit 3

`#define WDP3_BIT 5`

`#define WDP3_MASK 32`

##### WDTIE - Watchdog Timeout Interrupt Enable

`#define WDTIE_BIT 6`

`#define WDTIE_MASK 64`

##### WDTIF - Watchdog Timeout Interrupt Flag

`#define WDTIF_BIT 7`

`#define WDTIF_MASK 128`