This documentation was generated automatically from the AVR Studio part description file AT86RF401.pdf.
sfrb LOCKDET1 = $10;
#define CS0_BIT 0
#define CS0_MASK 1
#define CS1_BIT 1
#define CS1_MASK 2
#define BOD_BIT 2
#define BOD_MASK 4
#define ENKO_BIT 3
#define ENKO_MASK 8
#define UPOK_BIT 4
#define UPOK_MASK 16
sfrb LOCKDET1 = $17;
#define LC0_BIT 0
#define LC0_MASK 1
#define LC1_BIT 1
#define LC1_MASK 2
#define LC2_BIT 2
#define LC2_MASK 4
#define ULC0_BIT 3
#define ULC0_MASK 8
#define ULC1_BIT 4
#define ULC1_MASK 16
#define ULC2_BIT 5
#define ULC2_MASK 32
#define LAT_BIT 6
#define LAT_MASK 64
#define EUD_BIT 7
#define EUD_MASK 128
sfrb TX_CNTL = $12;
#define LOC_BIT 2
#define LOC_MASK 4
#define TXK_BIT 4
#define TXK_MASK 16
#define TXE_BIT 5
#define TXE_MASK 32
#define FSK_BIT 6
#define FSK_MASK 64
sfrb PWR_ATTEN = $14;
#define PCF0_BIT 0
#define PCF0_MASK 1
#define PCF1_BIT 1
#define PCF1_MASK 2
#define PCF2_BIT 2
#define PCF2_MASK 4
#define PCC0_BIT 3
#define PCC0_MASK 8
#define PCC1_BIT 4
#define PCC1_MASK 16
#define PCC2_BIT 5
#define PCC2_MASK 32
sfrb VCOTUNE = $16;
#define VCOTUNE0_BIT 0
#define VCOTUNE0_MASK 1
#define VCOTUNE1_BIT 1
#define VCOTUNE1_MASK 2
#define VCOTUNE2_BIT 2
#define VCOTUNE2_MASK 4
#define VCOTUNE3_BIT 3
#define VCOTUNE3_MASK 8
#define VCOTUNE4_BIT 4
#define VCOTUNE4_MASK 16
#define VCOVDET0_BIT 6
#define VCOVDET0_MASK 64
#define VCOVDET1_BIT 7
#define VCOVDET1_MASK 128
sfrb DEEAR = $1E;
#define BA0_BIT 0
#define BA0_MASK 1
#define BA1_BIT 1
#define BA1_MASK 2
#define BA2_BIT 2
#define BA2_MASK 4
#define PA3_BIT 3
#define PA3_MASK 8
#define PA4_BIT 4
#define PA4_MASK 16
#define PA5_BIT 5
#define PA5_MASK 32
#define PA6_BIT 6
#define PA6_MASK 64
sfrb DEEDR = $1D;
#define ED0_BIT 0
#define ED0_MASK 1
#define ED1_BIT 1
#define ED1_MASK 2
#define ED2_BIT 2
#define ED2_MASK 4
#define ED3_BIT 3
#define ED3_MASK 8
#define ED4_BIT 4
#define ED4_MASK 16
#define ED5_BIT 5
#define ED5_MASK 32
#define ED6_BIT 6
#define ED6_MASK 64
#define ED7_BIT 7
#define ED7_MASK 128
sfrb DEECR = $1C;
#define EER_BIT 0
#define EER_MASK 1
#define EEL_BIT 1
#define EEL_MASK 2
#define EEU_BIT 2
#define EEU_MASK 4
#define BSY_BIT 3
#define BSY_MASK 8
sfrb WDTCR = $22;
#define WDP0_BIT 0
#define WDP0_MASK 1
#define WDP1_BIT 1
#define WDP1_MASK 2
#define WDP2_BIT 2
#define WDP2_MASK 4
#define WDE_BIT 3
#define WDE_MASK 8
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog
#define WDTOE_BIT 4
#define WDTOE_MASK 16
This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.
sfrb BTCNT = $20;
#define C0_BIT 0
#define C0_MASK 1
#define C1_BIT 1
#define C1_MASK 2
#define C2_BIT 2
#define C2_MASK 4
#define C3_BIT 3
#define C3_MASK 8
#define C4_BIT 4
#define C4_MASK 16
#define C5_BIT 5
#define C5_MASK 32
#define C6_BIT 6
#define C6_MASK 64
#define C7_BIT 7
#define C7_MASK 128
sfrb BTCR = $21;
#define F0_BIT 0
#define F0_MASK 1
#define DATA_BIT 1
#define DATA_MASK 2
#define F2_BIT 2
#define F2_MASK 4
#define IE_BIT 3
#define IE_MASK 8
#define M0_BIT 4
#define M0_MASK 16
#define M1_BIT 5
#define M1_MASK 32
#define C8_BIT 6
#define C8_MASK 64
#define C9_BIT 7
#define C9_MASK 128
sfrb IO_ENAB = $30;
#define IOE0_BIT 0
#define IOE0_MASK 1
#define IOE1_BIT 1
#define IOE1_MASK 2
#define IOE2_BIT 2
#define IOE2_MASK 4
#define IOE3_BIT 3
#define IOE3_MASK 8
#define IOE4_BIT 4
#define IOE4_MASK 16
#define IOE5_BIT 5
#define IOE5_MASK 32
sfrb IO_DATOUT = $31;
#define IOO0_BIT 0
#define IOO0_MASK 1
#define IOO1_BIT 1
#define IOO1_MASK 2
#define IOO2_BIT 2
#define IOO2_MASK 4
#define IOO3_BIT 3
#define IOO3_MASK 8
#define IOO4_BIT 4
#define IOO4_MASK 16
#define IOO5_BIT 5
#define IOO5_MASK 32
sfrb IO_DATIN = $32;
#define IOI0_BIT 0
#define IOI0_MASK 1
#define IOI1_BIT 1
#define IOI1_MASK 2
#define IOI2_BIT 2
#define IOI2_MASK 4
#define IOI3_BIT 3
#define IOI3_MASK 8
#define IOI4_BIT 4
#define IOI4_MASK 16
#define IOI5_BIT 5
#define IOI5_MASK 32
sfrb SREG = $3F;
sfrb SPH = $3E;
#define SP8_BIT 0
#define SP8_MASK 1
#define SP9_BIT 1
#define SP9_MASK 2
#define SP10_BIT 2
#define SP10_MASK 4
sfrb SPL = $3D;
#define SP0_BIT 0
#define SP0_MASK 1
#define SP1_BIT 1
#define SP1_MASK 2
#define SP2_BIT 2
#define SP2_MASK 4
#define SP3_BIT 3
#define SP3_MASK 8
#define SP4_BIT 4
#define SP4_MASK 16
#define SP5_BIT 5
#define SP5_MASK 32
#define SP6_BIT 6
#define SP6_MASK 64
#define SP7_BIT 7
#define SP7_MASK 128
sfrb AVR_CONFIG = $33;
#define BBM_BIT 0
#define BBM_MASK 1
#define SLEEP_BIT 1
#define SLEEP_MASK 2
#define BLI_BIT 2
#define BLI_MASK 4
#define BD_BIT 3
#define BD_MASK 8
#define TM_BIT 4
#define TM_MASK 16
#define ACS0_BIT 5
#define ACS0_MASK 32
#define ACS1_BIT 6
#define ACS1_MASK 64
sfrb B_DET = $34;
#define BD0_BIT 0
#define BD0_MASK 1
#define BD1_BIT 1
#define BD1_MASK 2
#define BD2_BIT 2
#define BD2_MASK 4
#define BD3_BIT 3
#define BD3_MASK 8
#define BD4_BIT 4
#define BD4_MASK 16
#define BD5_BIT 5
#define BD5_MASK 32
sfrb BL_CONFIG = $35;
#define BL0_BIT 0
#define BL0_MASK 1
#define BL1_BIT 1
#define BL1_MASK 2
#define BL2_BIT 2
#define BL2_MASK 4
#define BL3_BIT 3
#define BL3_MASK 8
#define BL4_BIT 4
#define BL4_MASK 16
#define BL5_BIT 5
#define BL5_MASK 32
#define BLV_BIT 6
#define BLV_MASK 64
#define BL_BIT 7
#define BL_MASK 128