This documentation was generated automatically from the AVR Studio part description file AT76C.pdf.
sfrb TCCR0 = 0x33;
#define CS00_BIT 0
#define CS00_MASK 1
The three clock select bits select the clock source to be used by the Timer/Counter,
#define CS01_BIT 1
#define CS01_MASK 2
The three clock select bits select the clock source to be used by the Timer/Counter,
#define CS02_BIT 2
#define CS02_MASK 4
The three clock select bits select the clock source to be used by the Timer/Counter,
sfrb TCNT0 = 0x32;
#define TCNT0_0_BIT 0
#define TCNT0_0_MASK 1
#define TCNT0_1_BIT 1
#define TCNT0_1_MASK 2
#define TCNT0_2_BIT 2
#define TCNT0_2_MASK 4
#define TCNT0_3_BIT 3
#define TCNT0_3_MASK 8
#define TCNT0_4_BIT 4
#define TCNT0_4_MASK 16
#define TCNT0_5_BIT 5
#define TCNT0_5_MASK 32
#define TCNT0_6_BIT 6
#define TCNT0_6_MASK 64
#define TCNT0_7_BIT 7
#define TCNT0_7_MASK 128
sfrb PRELD0 = 0x31;
#define OCR0_0_BIT 0
#define OCR0_0_MASK 1
#define OCR0_1_BIT 1
#define OCR0_1_MASK 2
#define BIT2_BIT 2
#define BIT2_MASK 4
#define BIT3_BIT 3
#define BIT3_MASK 8
#define BIT4_BIT 4
#define BIT4_MASK 16
#define BIT5_BIT 5
#define BIT5_MASK 32
#define BIT6_BIT 6
#define BIT6_MASK 64
#define BIT7_BIT 7
#define BIT7_MASK 128
sfrb TCCR1B = 0x2E;
#define CS10_BIT 0
#define CS10_MASK 1
Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.
#define CS11_BIT 1
#define CS11_MASK 2
Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.
#define CS12_BIT 2
#define CS12_MASK 4
Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.
#define CTCA1_BIT 3
#define CTCA1_MASK 8
When it is one the Timer/Counter1 is resetWhen it is one the Timer/Counter1 is reset to $0000 after compare A match. If it is cleared the Timer/Counter1 continues counting after a compare A match.
#define ICES1_BIT 6
#define ICES1_MASK 64
While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.
#define ICNC1_BIT 7
#define ICNC1_MASK 128
When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.
sfrb TCNT1H = 0x2D;
#define TCNT1H0_BIT 0
#define TCNT1H0_MASK 1
#define TCNT1H1_BIT 1
#define TCNT1H1_MASK 2
#define TCNT1H2_BIT 2
#define TCNT1H2_MASK 4
#define TCNT1H3_BIT 3
#define TCNT1H3_MASK 8
#define TCNT1H4_BIT 4
#define TCNT1H4_MASK 16
#define TCNT1H5_BIT 5
#define TCNT1H5_MASK 32
#define TCNT1H6_BIT 6
#define TCNT1H6_MASK 64
#define TCNT1H7_BIT 7
#define TCNT1H7_MASK 128
sfrb TCNT1L = 0x2C;
#define TCNT1L0_BIT 0
#define TCNT1L0_MASK 1
#define TCNT1L1_BIT 1
#define TCNT1L1_MASK 2
#define TCNT1L2_BIT 2
#define TCNT1L2_MASK 4
#define TCNT1L3_BIT 3
#define TCNT1L3_MASK 8
#define TCNT1L4_BIT 4
#define TCNT1L4_MASK 16
#define TCNT1L5_BIT 5
#define TCNT1L5_MASK 32
#define TCNT1L6_BIT 6
#define TCNT1L6_MASK 64
#define TCNT1L7_BIT 7
#define TCNT1L7_MASK 128
sfrb OCR1AH = 0x2B;
#define OCR1AH0_BIT 0
#define OCR1AH0_MASK 1
#define OCR1AH1_BIT 1
#define OCR1AH1_MASK 2
#define OCR1AH2_BIT 2
#define OCR1AH2_MASK 4
#define OCR1AH3_BIT 3
#define OCR1AH3_MASK 8
#define OCR1AH4_BIT 4
#define OCR1AH4_MASK 16
#define OCR1AH5_BIT 5
#define OCR1AH5_MASK 32
#define OCR1AH6_BIT 6
#define OCR1AH6_MASK 64
#define OCR1AH7_BIT 7
#define OCR1AH7_MASK 128
sfrb OCR1AL = 0x2A;
#define OCR1AL0_BIT 0
#define OCR1AL0_MASK 1
#define OCR1AL1_BIT 1
#define OCR1AL1_MASK 2
#define OCR1AL2_BIT 2
#define OCR1AL2_MASK 4
#define OCR1AL3_BIT 3
#define OCR1AL3_MASK 8
#define OCR1AL4_BIT 4
#define OCR1AL4_MASK 16
#define OCR1AL5_BIT 5
#define OCR1AL5_MASK 32
#define OCR1AL6_BIT 6
#define OCR1AL6_MASK 64
#define OCR1AL7_BIT 7
#define OCR1AL7_MASK 128
sfrb OCR1BH = 0x29;
#define OCR1BH0_BIT 0
#define OCR1BH0_MASK 1
#define OCR1BH1_BIT 1
#define OCR1BH1_MASK 2
#define OCR1BH2_BIT 2
#define OCR1BH2_MASK 4
#define OCR1BH3_BIT 3
#define OCR1BH3_MASK 8
#define OCR1BH4_BIT 4
#define OCR1BH4_MASK 16
#define OCR1BH5_BIT 5
#define OCR1BH5_MASK 32
#define OCR1BH6_BIT 6
#define OCR1BH6_MASK 64
#define OCR1BH7_BIT 7
#define OCR1BH7_MASK 128
sfrb OCR1BL = 0x28;
#define OCR1BL0_BIT 0
#define OCR1BL0_MASK 1
#define OCR1BL1_BIT 1
#define OCR1BL1_MASK 2
#define OCR1BL2_BIT 2
#define OCR1BL2_MASK 4
#define OCR1BL3_BIT 3
#define OCR1BL3_MASK 8
#define OCR1BL4_BIT 4
#define OCR1BL4_MASK 16
#define OCR1BL5_BIT 5
#define OCR1BL5_MASK 32
#define OCR1BL6_BIT 6
#define OCR1BL6_MASK 64
#define OCR1BL7_BIT 7
#define OCR1BL7_MASK 128
sfrb ICR1H = 0x27;
#define ICR1H0_BIT 0
#define ICR1H0_MASK 1
#define ICR1H1_BIT 1
#define ICR1H1_MASK 2
#define ICR1H2_BIT 2
#define ICR1H2_MASK 4
#define ICR1H3_BIT 3
#define ICR1H3_MASK 8
#define ICR1H4_BIT 4
#define ICR1H4_MASK 16
#define ICR1H5_BIT 5
#define ICR1H5_MASK 32
#define ICR1H6_BIT 6
#define ICR1H6_MASK 64
#define ICR1H7_BIT 7
#define ICR1H7_MASK 128
sfrb ICR1L = 0x26;
#define ICR1L0_BIT 0
#define ICR1L0_MASK 1
#define ICR1L1_BIT 1
#define ICR1L1_MASK 2
#define ICR1L2_BIT 2
#define ICR1L2_MASK 4
#define ICR1L3_BIT 3
#define ICR1L3_MASK 8
#define ICR1L4_BIT 4
#define ICR1L4_MASK 16
#define ICR1L5_BIT 5
#define ICR1L5_MASK 32
#define ICR1L6_BIT 6
#define ICR1L6_MASK 64
#define ICR1L7_BIT 7
#define ICR1L7_MASK 128
sfrb TIMSK = 0x39;
#define TOIE2_BIT 2
#define TOIE2_MASK 4
When this bit is set and the I-bit in the Status Register is 1, the Timer/Counter 2 Overflow interrupt is enabled. The corresponding interrupt (at vector $001C) is executed if an overflow in Timer/Counter1 occurs. The Timer/Counter1 Overflow Flag is set in the Timer/Counter Interrupt Flag Register b
#define TICIE1_BIT 3
#define TICIE1_MASK 8
When this bit is set and the I-bit in the Status Register is one, the Input Capture Event interrupt is enabled. The corresponding interrupt (at vector $0016) is executed if a capture event occurs on pin PB3. The Input Capture Flag in Timer/Counter1 is set in the Timer/Counter Interrupt Flag Register b
#define OCIE1B_BIT 5
#define OCIE1B_MASK 32
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define OCIE1A_BIT 6
#define OCIE1A_MASK 64
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define TOIE1_BIT 7
#define TOIE1_MASK 128
When this bit is set and the I-bit in the Status Register is 1, the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $001C) is executed if an overflow in Timer/Counter1 occurs. The Timer/Counter1 Overflow Flag is set in the Timer/Counter1 Interrupt Flag Register b
sfrb TIFR = 0x38;
#define TOV0_BIT 0
#define TOV0_MASK 1
The TOV0 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter0 Overflow Interrupt is executed. This flag is cleared when written a logic one.
#define TOV2_BIT 2
#define TOV2_MASK 4
The TOV2 is set (one) when an overflow occurs in Timer/Counter2. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. This flag is cleared when written with a logic one.
#define ICF1_BIT 3
#define ICF1_MASK 8
The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.
#define OCFB_BIT 5
#define OCFB_MASK 32
The OCFB bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.
#define OCFA_BIT 6
#define OCFA_MASK 64
The OCFA bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed.
sfrb TCCR2 = 0x25;
#define CS00_BIT 0
#define CS00_MASK 1
The three clock select bits select the clock source to be used by the Timer/Counter,
#define CS01_BIT 1
#define CS01_MASK 2
The three clock select bits select the clock source to be used by the Timer/Counter,
#define CS02_BIT 2
#define CS02_MASK 4
The three clock select bits select the clock source to be used by the Timer/Counter,
sfrb TCNT2 = 0x32;
#define TCNT2_0_BIT 0
#define TCNT2_0_MASK 1
#define TCNT2_1_BIT 1
#define TCNT2_1_MASK 2
#define TCNT2_2_BIT 2
#define TCNT2_2_MASK 4
#define TCNT2_3_BIT 3
#define TCNT2_3_MASK 8
#define TCNT2_4_BIT 4
#define TCNT2_4_MASK 16
#define TCNT2_5_BIT 5
#define TCNT2_5_MASK 32
#define TCNT2_6_BIT 6
#define TCNT2_6_MASK 64
#define TCNT2_7_BIT 7
#define TCNT2_7_MASK 128
sfrb PRELD2 = 0x23;
#define OCR0_0_BIT 0
#define OCR0_0_MASK 1
#define OCR0_1_BIT 1
#define OCR0_1_MASK 2
#define BIT2_BIT 2
#define BIT2_MASK 4
#define BIT3_BIT 3
#define BIT3_MASK 8
#define BIT4_BIT 4
#define BIT4_MASK 16
#define BIT5_BIT 5
#define BIT5_MASK 32
#define BIT6_BIT 6
#define BIT6_MASK 64
#define BIT7_BIT 7
#define BIT7_MASK 128
sfrb WDTCR = 0x21;
#define WDP0_BIT 0
#define WDP0_MASK 1
The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.
#define WDP1_BIT 1
#define WDP1_MASK 2
The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.
#define WDP2_BIT 2
#define WDP2_MASK 4
The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.
#define WDE_BIT 3
#define WDE_MASK 8
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watch
#define WDTOE_BIT 4
#define WDTOE_MASK 16
This bit must be set when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, H/w will clear this bit to zero after four cycles.
The Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: b
sfrb SPCR = 0x0D;
#define SPR0_BIT 0
#define SPR0_MASK 1
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.
#define SPR1_BIT 1
#define SPR1_MASK 2
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.
#define CPHA_BIT 2
#define CPHA_MASK 4
Refer to Figure 36 or Figure 37 for the functionality of this bit.
#define CPOL_BIT 3
#define CPOL_MASK 8
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.
#define MSTR_BIT 4
#define MSTR_MASK 16
This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.
#define DORD_BIT 5
#define DORD_MASK 32
When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.
#define SPE_BIT 6
#define SPE_MASK 64
When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.
#define SPIE_BIT 7
#define SPIE_MASK 128
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.
sfrb SPSR = 0x0E;
#define WCOL_BIT 6
#define WCOL_MASK 64
The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.
#define SPIF_BIT 7
#define SPIF_MASK 128
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).
sfrb SPDR = 0x0F;
#define SPDR0_BIT 0
#define SPDR0_MASK 1
#define SPDR1_BIT 1
#define SPDR1_MASK 2
#define SPDR2_BIT 2
#define SPDR2_MASK 4
#define SPDR3_BIT 3
#define SPDR3_MASK 8
#define SPDR4_BIT 4
#define SPDR4_MASK 16
#define SPDR5_BIT 5
#define SPDR5_MASK 32
#define SPDR6_BIT 6
#define SPDR6_MASK 64
#define SPDR7_BIT 7
#define SPDR7_MASK 128
sfrb PORTA = 0x1B;
#define PORTA0_BIT 0
#define PORTA0_MASK 1
#define PORTA1_BIT 1
#define PORTA1_MASK 2
#define PORTA2_BIT 2
#define PORTA2_MASK 4
#define PORTA3_BIT 3
#define PORTA3_MASK 8
#define PORTA4_BIT 4
#define PORTA4_MASK 16
#define PORTA5_BIT 5
#define PORTA5_MASK 32
#define PORTA6_BIT 6
#define PORTA6_MASK 64
#define PORTA7_BIT 7
#define PORTA7_MASK 128
sfrb DDRA = 0x1A;
#define DDRA0_BIT 0
#define DDRA0_MASK 1
#define DDRA1_BIT 1
#define DDRA1_MASK 2
#define DDRA2_BIT 2
#define DDRA2_MASK 4
#define DDRA3_BIT 3
#define DDRA3_MASK 8
#define DDRA4_BIT 4
#define DDRA4_MASK 16
#define DDRA5_BIT 5
#define DDRA5_MASK 32
#define DDRA6_BIT 6
#define DDRA6_MASK 64
#define DDRA7_BIT 7
#define DDRA7_MASK 128
sfrb PINA = 0x19;
#define PINA0_BIT 0
#define PINA0_MASK 1
#define PINA1_BIT 1
#define PINA1_MASK 2
#define PINA2_BIT 2
#define PINA2_MASK 4
#define PINA3_BIT 3
#define PINA3_MASK 8
#define PINA4_BIT 4
#define PINA4_MASK 16
#define PINA5_BIT 5
#define PINA5_MASK 32
#define PINA6_BIT 6
#define PINA6_MASK 64
#define PINA7_BIT 7
#define PINA7_MASK 128
sfrb PORTB = 0x18;
#define PORTB0_BIT 0
#define PORTB0_MASK 1
#define PORTB1_BIT 1
#define PORTB1_MASK 2
#define PORTB2_BIT 2
#define PORTB2_MASK 4
#define PORTB3_BIT 3
#define PORTB3_MASK 8
#define PORTB4_BIT 4
#define PORTB4_MASK 16
#define PORTB5_BIT 5
#define PORTB5_MASK 32
#define PORTB6_BIT 6
#define PORTB6_MASK 64
#define PORTB7_BIT 7
#define PORTB7_MASK 128
sfrb DDRB = 0x17;
#define DDRB0_BIT 0
#define DDRB0_MASK 1
#define DDRB1_BIT 1
#define DDRB1_MASK 2
#define DDRB2_BIT 2
#define DDRB2_MASK 4
#define DDRB3_BIT 3
#define DDRB3_MASK 8
#define DDRB4_BIT 4
#define DDRB4_MASK 16
#define DDRB5_BIT 5
#define DDRB5_MASK 32
#define DDRB6_BIT 6
#define DDRB6_MASK 64
#define DDRB7_BIT 7
#define DDRB7_MASK 128
sfrb PINB = 0x16;
#define PINB0_BIT 0
#define PINB0_MASK 1
#define PINB1_BIT 1
#define PINB1_MASK 2
#define PINB2_BIT 2
#define PINB2_MASK 4
#define PINB3_BIT 3
#define PINB3_MASK 8
#define PINB4_BIT 4
#define PINB4_MASK 16
#define PINB5_BIT 5
#define PINB5_MASK 32
#define PINB6_BIT 6
#define PINB6_MASK 64
#define PINB7_BIT 7
#define PINB7_MASK 128
sfrb PORTC = 0x15;
#define PORTC0_BIT 0
#define PORTC0_MASK 1
#define PORTC1_BIT 1
#define PORTC1_MASK 2
#define PORTC2_BIT 2
#define PORTC2_MASK 4
#define PORTC3_BIT 3
#define PORTC3_MASK 8
#define PORTC4_BIT 4
#define PORTC4_MASK 16
#define PORTC5_BIT 5
#define PORTC5_MASK 32
#define PORTC6_BIT 6
#define PORTC6_MASK 64
#define PORTC7_BIT 7
#define PORTC7_MASK 128
sfrb DDRC = 0x14;
#define DDRC0_BIT 0
#define DDRC0_MASK 1
#define DDRC1_BIT 1
#define DDRC1_MASK 2
#define DDRC2_BIT 2
#define DDRC2_MASK 4
#define DDRC3_BIT 3
#define DDRC3_MASK 8
#define DDRC4_BIT 4
#define DDRC4_MASK 16
#define DDRC5_BIT 5
#define DDRC5_MASK 32
#define DDRC6_BIT 6
#define DDRC6_MASK 64
#define DDRC7_BIT 7
#define DDRC7_MASK 128
sfrb PINC = 0x13;
#define PINC0_BIT 0
#define PINC0_MASK 1
#define PINC1_BIT 1
#define PINC1_MASK 2
#define PINC2_BIT 2
#define PINC2_MASK 4
#define PINC3_BIT 3
#define PINC3_MASK 8
#define PINC4_BIT 4
#define PINC4_MASK 16
#define PINC5_BIT 5
#define PINC5_MASK 32
#define PINC6_BIT 6
#define PINC6_MASK 64
#define PINC7_BIT 7
#define PINC7_MASK 128
sfrb PORTD = 0x12;
#define PORTD0_BIT 0
#define PORTD0_MASK 1
#define PORTD1_BIT 1
#define PORTD1_MASK 2
#define PORTD2_BIT 2
#define PORTD2_MASK 4
#define PORTD3_BIT 3
#define PORTD3_MASK 8
#define PORTD4_BIT 4
#define PORTD4_MASK 16
#define PORTD5_BIT 5
#define PORTD5_MASK 32
#define PORTD6_BIT 6
#define PORTD6_MASK 64
#define PORTD7_BIT 7
#define PORTD7_MASK 128
sfrb DDRD = 0x11;
#define DDRD0_BIT 0
#define DDRD0_MASK 1
#define DDRD1_BIT 1
#define DDRD1_MASK 2
#define DDRD2_BIT 2
#define DDRD2_MASK 4
#define DDRD3_BIT 3
#define DDRD3_MASK 8
#define DDRD4_BIT 4
#define DDRD4_MASK 16
#define DDRD5_BIT 5
#define DDRD5_MASK 32
#define DDRD6_BIT 6
#define DDRD6_MASK 64
#define DDRD7_BIT 7
#define DDRD7_MASK 128
sfrb PIND = 0x10;
#define PIND0_BIT 0
#define PIND0_MASK 1
#define PIND1_BIT 1
#define PIND1_MASK 2
#define PIND2_BIT 2
#define PIND2_MASK 4
#define PIND3_BIT 3
#define PIND3_MASK 8
#define PIND4_BIT 4
#define PIND4_MASK 16
#define PIND5_BIT 5
#define PIND5_MASK 32
#define PIND6_BIT 6
#define PIND6_MASK 64
#define PIND7_BIT 7
#define PIND7_MASK 128
sfrb PORTE = 0x0A;
#define PORTE0_BIT 0
#define PORTE0_MASK 1
#define PORTE1_BIT 1
#define PORTE1_MASK 2
#define PORTE2_BIT 2
#define PORTE2_MASK 4
#define PORTE3_BIT 3
#define PORTE3_MASK 8
#define PORTE4_BIT 4
#define PORTE4_MASK 16
#define PORTE5_BIT 5
#define PORTE5_MASK 32
#define PORTE6_BIT 6
#define PORTE6_MASK 64
#define PORTE7_BIT 7
#define PORTE7_MASK 128
sfrb DDRE = 0x09;
#define DDRE0_BIT 0
#define DDRE0_MASK 1
#define DDRE1_BIT 1
#define DDRE1_MASK 2
#define DDRE2_BIT 2
#define DDRE2_MASK 4
#define DDRE3_BIT 3
#define DDRE3_MASK 8
#define DDRE4_BIT 4
#define DDRE4_MASK 16
#define DDRE5_BIT 5
#define DDRE5_MASK 32
#define DDRE6_BIT 6
#define DDRE6_MASK 64
#define DDRE7_BIT 7
#define DDRE7_MASK 128
sfrb PINE = 0x08;
#define PINE0_BIT 0
#define PINE0_MASK 1
#define PINE1_BIT 1
#define PINE1_MASK 2
#define PINE2_BIT 2
#define PINE2_MASK 4
#define PINE3_BIT 3
#define PINE3_MASK 8
#define PINE4_BIT 4
#define PINE4_MASK 16
#define PINE5_BIT 5
#define PINE5_MASK 32
#define PINE6_BIT 6
#define PINE6_MASK 64
#define PINE7_BIT 7
#define PINE7_MASK 128
JTAG Features: JTAG (IEEE std. 1149.1 compliant) Interface. Boundary-Scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard. Debugger Access to: b
sfrb IDR = 0x3C;
#define IDR0_BIT 0
#define IDR0_MASK 1
#define IDR1_BIT 1
#define IDR1_MASK 2
#define IDR2_BIT 2
#define IDR2_MASK 4
#define IDR3_BIT 3
#define IDR3_MASK 8
#define IDR4_BIT 4
#define IDR4_MASK 16
#define IDR5_BIT 5
#define IDR5_MASK 32
#define IDR6_BIT 6
#define IDR6_MASK 64
#define IDRD_BIT 7
#define IDRD_MASK 128
This bit is set to indicate to the debugger that the register has been written.
The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in b
sfrb EIMSK = 0x37;
#define INT0_BIT 0
#define INT0_MASK 1
If it is set and the 1-bit in the Status Register is set, the external pin interrupt 0 is enabled.
#define INT1_BIT 1
#define INT1_MASK 2
If it is set and the 1-bit in the Status Register is set, the external pin interrupt 1 is enabled.
#define INT2_BIT 2
#define INT2_MASK 4
If it is set and the 1-bit in the Status Register is set, the external pin interrupt 2 is enabled.
#define INT3_BIT 3
#define INT3_MASK 8
If it is set and the 1-bit in the Status Register is set, the external pin interrupt 3 is enabled.
#define POL0_BIT 4
#define POL0_MASK 16
INT0 is active high when this bit is low.
#define POL1_BIT 5
#define POL1_MASK 32
INT1 is active high when this bit is low.
#define POL2_BIT 6
#define POL2_MASK 64
INT2 is active high when this bit is low.
#define POL3_BIT 7
#define POL3_MASK 128
INT3 is active high when this bit is low.
External Memory Interface
sfrb EMICRA = 0x1C;
#define WM0_BIT 0
#define WM0_MASK 1
These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.
#define WM1_BIT 1
#define WM1_MASK 2
These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.
#define WW0_BIT 2
#define WW0_MASK 4
These bits control the Wait states inserted inthe corresponding (read, write and ALE) signals.
#define WW1_BIT 3
#define WW1_MASK 8
These bits control the Wait states inserted inthe corresponding (read, write and ALE) signals.
#define RM0_BIT 4
#define RM0_MASK 16
These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.
#define RM1_BIT 5
#define RM1_MASK 32
These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.
#define RW0_BIT 6
#define RW0_MASK 64
These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.
#define RW1_BIT 7
#define RW1_MASK 128
These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.
sfrb EMICRB = 0x1D;
#define EMD1_BIT 0
#define EMD1_MASK 1
These bits select the external memory interface mode
#define EMD0_BIT 1
#define EMD0_MASK 2
These bits select the external memory interface mode
#define AM0_BIT 4
#define AM0_MASK 16
These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.
#define AM1_BIT 5
#define AM1_MASK 32
These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.
#define AW0_BIT 6
#define AW0_MASK 64
These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.
#define AW1_BIT 7
#define AW1_MASK 128
These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.
sfrb MEMMAP = 0xF800;
#define MEMMAP0_BIT 0
#define MEMMAP0_MASK 1
#define MEMMAP1_BIT 1
#define MEMMAP1_MASK 2
#define MEMMAP2_BIT 2
#define MEMMAP2_MASK 4
#define MEMMAP3_BIT 3
#define MEMMAP3_MASK 8
#define MEMMAP4_BIT 4
#define MEMMAP4_MASK 16
#define MEMMAP5_BIT 5
#define MEMMAP5_MASK 32
#define MEMMAP6_BIT 6
#define MEMMAP6_MASK 64
#define MEMMAP7_BIT 7
#define MEMMAP7_MASK 128
sfrb DMA_EMICRA = 0xF801;
#define WM0_BIT 0
#define WM0_MASK 1
These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.
#define WM1_BIT 1
#define WM1_MASK 2
These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.
#define WW0_BIT 2
#define WW0_MASK 4
These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.
#define WW1_BIT 3
#define WW1_MASK 8
These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.
#define RM0_BIT 4
#define RM0_MASK 16
These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.
#define RM1_BIT 5
#define RM1_MASK 32
These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.
#define RW0_BIT 6
#define RW0_MASK 64
These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.
#define RW1_BIT 7
#define RW1_MASK 128
These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.
sfrb DMA_EMICRB = 0xF802;
#define EMD0_BIT 0
#define EMD0_MASK 1
These bits select the external memory interface mode.
#define EMD1_BIT 1
#define EMD1_MASK 2
These bits select the external memory interface mode.
#define AM0_BIT 4
#define AM0_MASK 16
These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.
#define AM1_BIT 5
#define AM1_MASK 32
These bits control the mode (waveform) of the corresponding (read, write and ALE) signals.
#define AW0_BIT 6
#define AW0_MASK 64
These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.
#define AW1_BIT 7
#define AW1_MASK 128
These bits control the Wait states inserted in the corresponding (read, write and ALE) signals.
sfrb REMAP = 0xF404;
#define REMAP_BIT 0
#define REMAP_MASK 1
This bit indicates the active memory. If this bit is low (zero) we are in ROM mode, while if it is high ( one) we are in SRAM mode
sfrb IRDACR = 0x22;
#define IRDAEN_BIT 0
#define IRDAEN_MASK 1
When set enables the IrDA codec. When cleared the codec is transparent to UART0/1 SIN/SOUT pins
#define USEL_BIT 1
#define USEL_MASK 2
When cleared the codec uses UART0. When set the codec uses UART1
#define MODE_BIT 2
#define MODE_MASK 4
When cleared enables the 3/16 Return-to-Zero encoding scheme. When set enables the 4/16 Return-to-Zero encoding scheme
#define RXPOL_BIT 3
#define RXPOL_MASK 8
When set, the SIN signal is inverted before entering the IrDA codec
#define TXPOL_BIT 4
#define TXPOL_MASK 16
If set the SOUT signal is inverted.
sfrb SREG = 0x3F;
sfrb SPH = 0x3E;
#define SP8_BIT 0
#define SP8_MASK 1
#define SP9_BIT 1
#define SP9_MASK 2
#define SP10_BIT 2
#define SP10_MASK 4
#define SP11_BIT 3
#define SP11_MASK 8
#define SP12_BIT 4
#define SP12_MASK 16
#define SP13_BIT 5
#define SP13_MASK 32
#define SP14_BIT 6
#define SP14_MASK 64
#define SP15_BIT 7
#define SP15_MASK 128
sfrb SPL = 0x3D;
#define SP0_BIT 0
#define SP0_MASK 1
#define SP1_BIT 1
#define SP1_MASK 2
#define SP2_BIT 2
#define SP2_MASK 4
#define SP3_BIT 3
#define SP3_MASK 8
#define SP4_BIT 4
#define SP4_MASK 16
#define SP5_BIT 5
#define SP5_MASK 32
#define SP6_BIT 6
#define SP6_MASK 64
#define SP7_BIT 7
#define SP7_MASK 128
sfrb MCUCR = 0x35;
#define SM_BIT 5
#define SM_MASK 32
Thsi bit selects between the two available sleep modes
#define SE_BIT 6
#define SE_MASK 64
When set permits the MCU to enter in sleep mode when the SLEEP instruction is executed.
sfrb MCUSR = 0x34;
#define PORF_BIT 0
#define PORF_MASK 1
This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.
#define EXTRF_BIT 1
#define EXTRF_MASK 2
This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
sfrb CLK_CNTR = 0x0C;
#define MCSP0_BIT 0
#define MCSP0_MASK 1
These bits control the AVR clock divisor according to table 19 of datasheet
#define MCSP1_BIT 1
#define MCSP1_MASK 2
These bits control the AVR clock divisor according to table 19 of datasheet
#define MUL16_BIT 2
#define MUL16_MASK 4
Selects the multiplier of the PLL. When set the external 12MHz crystal frequency is multiplied by 16 to generate an internal fast clock of 192MHz. When cleared, the external 12MHz crystal frequency is multiplied by 8 generating an internal fast clock of 96MHz.
#define PIVCO1_BIT 3
#define PIVCO1_MASK 8
Selects the PLL frequency range. Normally, this bit must be eual to the MUL16 bit.
#define UDPLL_BIT 5
#define UDPLL_MASK 32
Select DPLL96 instead of DPLL48 for USB clock recovery.
#define PLCK_BIT 6
#define PLCK_MASK 64
If set the PLL Lock signal is used for "PLL Stable indication. If cleared , the "PLL Stable" indication is equal to the "PLL Enable" signal delayed by a significant factor.
#define NPICP_BIT 7
#define NPICP_MASK 128
This bit controls the PLL Charge-Pump current
sfrb PERIPHEN = 0x0B;
#define EMIEN_BIT 0
#define EMIEN_MASK 1
When set, the exetrnal memory interface is enabled and the pin functions of PortA and Port C are set to their alternative pin functions. the EMIEN bit overrides any bit direction settings in the respective data direction registers
#define USBE_BIT 1
#define USBE_MASK 2
When set enables the function of USB (clock Enable).
#define UATTACH_BIT 2
#define UATTACH_MASK 4
When set deactivates (logic 0) the USB_ATTACH pin.
#define UART0_BIT 3
#define UART0_MASK 8
When set enables the function of UART0
#define UART1_BIT 4
#define UART1_MASK 16
When set enables the function of UART1
#define SPI_BIT 5
#define SPI_MASK 32
If set enables the SPI Controller
sfrb PMOD = 0x1F;
#define PMODE0_BIT 0
#define PMODE0_MASK 1
The value of the PMODE0 input pin.
#define PMODE1_BIT 1
#define PMODE1_MASK 2
The value of the PMODE1 input pin.
The base address for UART0 registers is $F200 and for UART1 registers is $F300. Each read or write access of UART registers consumes at least 2 CPU cycles, since the UART core clock is asynchronous and fixed to 14.769MHz.
sfrb HR = $F200;
#define HR0_BIT 0
#define HR0_MASK 1
#define HR1_BIT 1
#define HR1_MASK 2
#define HR2_BIT 2
#define HR2_MASK 4
#define HR3_BIT 3
#define HR3_MASK 8
#define HR4_BIT 4
#define HR4_MASK 16
#define HR5_BIT 5
#define HR5_MASK 32
#define HR6_BIT 6
#define HR6_MASK 64
#define HR7_BIT 7
#define HR7_MASK 128
sfrb IER = $F201;
#define RDAI_BIT 0
#define RDAI_MASK 1
If set enables the Rx data available interrupt. Also enables and the time-out interrupt when time-out counter is enabled (in FIFO mode or if RTO is not zero, see XR1[5] and RTO).
#define TRI_BIT 1
#define TRI_MASK 2
If set enables THR Ready Interrupt
#define RSLI_BIT 2
#define RSLI_MASK 4
If set enables Receive Line Status Interrupt
#define MSI_BIT 3
#define MSI_MASK 8
If set enables the MODEM status interrupt
sfrb IIR = $F202;
#define NIP_BIT 0
#define NIP_MASK 1
If in logic b
#define ID0_BIT 1
#define ID0_MASK 2
Interrupt ID Bit 0
#define ID1_BIT 2
#define ID1_MASK 4
Interrupt ID Bit 1
#define ID2_BIT 3
#define ID2_MASK 8
Interrupt ID Bit 2
#define FIFOEN_BIT 6
#define FIFOEN_MASK 64
These two bits are set when FCR[0] is set.
#define FIFOEN_BIT 7
#define FIFOEN_MASK 128
These two bits are set when FCR[0] is set.
sfrb FCR = $F202;
#define FEN_BIT 0
#define FEN_MASK 1
When set, enables the 16 byte receive and transmit FIFOs. When cleared FIFOs are disabled and reset.
#define FRS_BIT 1
#define FRS_MASK 2
When set, resets the receive FIFO
#define TRS_BIT 2
#define TRS_MASK 4
When set, resets the transmit FIFO.
#define RDMA_BIT 3
#define RDMA_MASK 8
When FIFOs are disabled (FCR[0] is low), this bit is forced to b
#define RCVR0_BIT 6
#define RCVR0_MASK 64
These bits indicate the minimum number of bytes required in the receive FIFO to generate a receive ready interrupt. The trigger level is shown from the following table
#define RCVR1_BIT 7
#define RCVR1_MASK 128
These bits indicate the minimum number of bytes required in the receive FIFO to generate a receive ready interrupt. The trigger level is shown from the following table
sfrb LCR = $F203;
#define WL1_BIT 1
#define WL1_MASK 2
These bits determine the word length
#define SB_BIT 2
#define SB_MASK 4
This bit determines the number of stop bits
#define ENPAR_BIT 3
#define ENPAR_MASK 8
Setting this bit to logic '1' a parity bit is transmitted or checked. Resetting this bit to '0' no parity bit is transmitted or checked.
#define EVPAR_BIT 4
#define EVPAR_MASK 16
When the Enable Parity bit is a '1' and the Stick Parity bit is a '0', then setting to logic '1' the Even parity an even number of logic 1s is transmitted or checked in the data word bits and the Parity bit. When Even Parity bit is reset to logic '0' an odd number of 1s are transmitted or checked.When the Enable Parity bit is a '1' and the Stick Parity bit is a '0', then setting to logic '1' the Even parity an even number of logic 1s is transmitted or checked in the data word bits and the Parity bit. When Even Parity bit is reset to logic '0' an odd number of 1s are transmitted or checked.When the Enable Parity bit is a '1' and the Stick Parity bit is a '0', then setting to logic '1' the Even parity an even number of logic 1s is transmitted or checked in the data word bits and the Parity bit. When Even Parity bit is reset to logic '0' an odd number of 1s are transmitted or checked.When the Enable Parity bit is a '1' and the Stick Parity bit is a '0', then setting to logic '1' the Even parity an even number of logic 1s is transmitted or checked in the data word bits and the Parity bit. When Even Parity bit is reset to logic '0' an odd number of 1s are transmitted or checked
#define SPAR_BIT 5
#define SPAR_MASK 32
When the Parity Enable bit and the Parity Stick bit are set to logic '1' then the Even Parity bit controls the transmitted parity value. Resetting the Even parity bit to logic '0' then the parity bit is transmitted and checked as '1'. Setting the Even parity bit to logic '1' then the parity bit is transmitted and checked as '0'.
#define SBRK_BIT 6
#define SBRK_MASK 64
If set then it causes a break condition to to be transmitted to the receiving UART. The SOUT pin is forced to the spacing state (logic '0'). Resetting to logic '0' stops the break condition.The break control bit acts only on SOUT pin and has no effect on the transmitter logic. Note that UART waits before starting the break condition command for the complete transmission of the word in the transmit shift register. There is no need for software synchronization.
#define DLAB_BIT 7
#define DLAB_MASK 128
It must be set to logic b
sfrb MCR = $F204;
#define DTR_BIT 0
#define DTR_MASK 1
The compliment value of the bidirectional pin nDTR
#define RTS_BIT 1
#define RTS_MASK 2
The compliment value of the bidirectional pin nRTS
#define OUT1_BIT 2
#define OUT1_MASK 4
The compliment value of the bidirectional pin nOUT1
#define OUT2_BIT 3
#define OUT2_MASK 8
The compliment value of the bidirectional pin nOUT2
#define LB_BIT 4
#define LB_MASK 16
f Set enables the loopback mode. you can not set this bit at logic b
sfrb LSR = $F205;
#define RDA_BIT 0
#define RDA_MASK 1
If set indicates that there are data available in the RHR. This bit resets to logic '0' by reading all of the data from the Receive Holding Register or the Rx FIFO.
#define OE_BIT 1
#define OE_MASK 2
If set indicates an overrun error. Indicates that data in RHR was not read by the core before the next word was transferred into the RHR, thereby destroying the previous word. In FIFO Mode an overrun error will occur only after the Rx FIFO is full and the next word has been completely received in shift register. The word in the shift register is overwritten, but it is not transferred to the Rx FIFO. Overrun error is indicated to the core as soon as it happens. This bit is reset to a logic '0' whenever the core reads the LSR
#define PE_BIT 2
#define PE_MASK 4
If set indicates a parity error. Indicates that the received word in RHR does not have the correct parity bit. In FIFO mode this error is associated with the word at the top of the FIFO which is equivalent to RHR. This bit is reset to a logic '0' whenever the core reads the LSR.
#define FE_BIT 3
#define FE_MASK 8
If set indicates a framing error. Indicates that the received word in RHR does not have the correct stop bit. In FIFO mode this error is associated with the word at the top of the Rx FIFO which is equivalent to RHR. This bit is reset to a logic '0' whenever the core reads the LSR.
#define BI_BIT 4
#define BI_MASK 16
If set indicates a Break Interrupt. Indicates that the receive data input is held in the spacing state (logic '0') for longer than a full word transmission time.In FIFO mode this error is associated with the word at the top of the Rx FIFO which is equivalent to RHR. This bit is reset to a logic '0' whenever the core reads the LSR.
#define THRR_BIT 5
#define THRR_MASK 32
If set indicates that the THR is ready to accept a new word for transmission. This bit is set when a word is transferred from the THR into the Tx shift register. This bit is reset concurrently with the loading of the THR by the core. If Tx FIFO is enabled (FCR[0]=1, XR2[7]=0), the function of this bit is controlled by XR2[4]. If XR2[4] is '0', then this bit is set when the Tx FIFO is empty; it is cleared when at least 1 word is written to the Tx FIFO. If XR2[4] is '1', then this bit is set when the TxFIFO is not full
#define TE_BIT 6
#define TE_MASK 64
When set indicates that both the Transmit Shift Register and Transmit Holding Register, or the Tx FIFO if Tx FIFO is enabled, are empty.
#define ERF_BIT 7
#define ERF_MASK 128
If the FIFOs are disabled this bit is a '0'. If FIFOs are enabled this bit indicates that at least one word in the Rx FIFO has it's Parity Error or Framing Error or Break Indication bits high.
sfrb MSR = $F206;
#define DCTS_BIT 0
#define DCTS_MASK 1
#define DDSR_BIT 1
#define DDSR_MASK 2
#define TRI_BIT 2
#define TRI_MASK 4
#define DCD_BIT 3
#define DCD_MASK 8
#define CTS_BIT 4
#define CTS_MASK 16
#define DSR_BIT 5
#define DSR_MASK 32
#define RI_BIT 6
#define RI_MASK 64
#define CD_BIT 7
#define CD_MASK 128
sfrb SCR = $F207;
#define SCR0_BIT 0
#define SCR0_MASK 1
#define SCR1_BIT 1
#define SCR1_MASK 2
#define SCR2_BIT 2
#define SCR2_MASK 4
#define SCR3_BIT 3
#define SCR3_MASK 8
#define SCR4_BIT 4
#define SCR4_MASK 16
#define SCR5_BIT 5
#define SCR5_MASK 32
#define SCR6_BIT 6
#define SCR6_MASK 64
#define SCR7_BIT 7
#define SCR7_MASK 128
sfrb DLL = $F200;
#define DLL0_BIT 0
#define DLL0_MASK 1
#define DLL1_BIT 1
#define DLL1_MASK 2
#define DLL2_BIT 2
#define DLL2_MASK 4
#define DLL3_BIT 3
#define DLL3_MASK 8
#define DLL4_BIT 4
#define DLL4_MASK 16
#define DLL5_BIT 5
#define DLL5_MASK 32
#define DLL6_BIT 6
#define DLL6_MASK 64
#define DLL7_BIT 7
#define DLL7_MASK 128
sfrb DLL = $F201;
#define DLH0_BIT 0
#define DLH0_MASK 1
#define DLH1_BIT 1
#define DLH1_MASK 2
#define DLH2_BIT 2
#define DLH2_MASK 4
#define DLH3_BIT 3
#define DLH3_MASK 8
#define DLH4_BIT 4
#define DLH4_MASK 16
#define DLH5_BIT 5
#define DLH5_MASK 32
#define DLH6_BIT 6
#define DLH6_MASK 64
#define DLH7_BIT 7
#define DLH7_MASK 128
sfrb XR1 = $F208;
#define RXDIS_BIT 0
#define RXDIS_MASK 1
#define TXDIS_BIT 1
#define TXDIS_MASK 2
#define RXR_BIT 2
#define RXR_MASK 4
#define TXR_BIT 3
#define TXR_MASK 8
#define RTO_BIT 4
#define RTO_MASK 16
#define STOC_BIT 5
#define STOC_MASK 32
#define SA_BIT 6
#define SA_MASK 64
#define OPL_BIT 7
#define OPL_MASK 128
sfrb XR2 = $F209;
#define MDM_BIT 0
#define MDM_MASK 1
#define THRRC_BIT 4
#define THRRC_MASK 16
#define THRR_BIT 5
#define THRR_MASK 32
#define TE_BIT 6
#define TE_MASK 64
#define TxFD_BIT 7
#define TxFD_MASK 128
sfrb MDR = $F20A;
#define DTRD_BIT 0
#define DTRD_MASK 1
#define RTSD_BIT 1
#define RTSD_MASK 2
#define OUT1D_BIT 2
#define OUT1D_MASK 4
#define OUT2D_BIT 3
#define OUT2D_MASK 8
#define CTSD_BIT 4
#define CTSD_MASK 16
#define DSRD_BIT 5
#define DSRD_MASK 32
#define RID_BIT 6
#define RID_MASK 64
#define CDD_BIT 7
#define CDD_MASK 128
sfrb RTO = $F20B;
#define RTO0_BIT 0
#define RTO0_MASK 1
#define RTO1_BIT 1
#define RTO1_MASK 2
#define RTO2_BIT 2
#define RTO2_MASK 4
#define RTO3_BIT 3
#define RTO3_MASK 8
#define RTO4_BIT 4
#define RTO4_MASK 16
#define RTO5_BIT 5
#define RTO5_MASK 32
#define RTO6_BIT 6
#define RTO6_MASK 64
#define RTO7_BIT 7
#define RTO7_MASK 128
sfrb TTG = $F20C;
#define TTG0_BIT 0
#define TTG0_MASK 1
#define TTG1_BIT 1
#define TTG1_MASK 2
#define TTG2_BIT 2
#define TTG2_MASK 4
#define TTG3_BIT 3
#define TTG3_MASK 8
#define TTG4_BIT 4
#define TTG4_MASK 16
#define TTG5_BIT 5
#define TTG5_MASK 32
#define TTG6_BIT 6
#define TTG6_MASK 64
#define TTG7_BIT 7
#define TTG7_MASK 128
The base address for UART0 registers is $F200 and for UART1 registers is $F300. Each read or write access of UART registers consumes at least 2 CPU cycles, since the UART core clock is asynchronous and fixed to 14.769MHz.
sfrb HR = $F300;
#define HR0_BIT 0
#define HR0_MASK 1
#define HR1_BIT 1
#define HR1_MASK 2
#define HR2_BIT 2
#define HR2_MASK 4
#define HR3_BIT 3
#define HR3_MASK 8
#define HR4_BIT 4
#define HR4_MASK 16
#define HR5_BIT 5
#define HR5_MASK 32
#define HR6_BIT 6
#define HR6_MASK 64
#define HR7_BIT 7
#define HR7_MASK 128
sfrb IER = $F301;
#define RDAI_BIT 0
#define RDAI_MASK 1
If set enables the Rx data available interrupt. Also enables and the time-out interrupt when time-out counter is enabled (in FIFO mode or if RTO is not zero, see XR1[5] and RTO).
#define TRI_BIT 1
#define TRI_MASK 2
If set enables THR Ready Interrupt
#define RSLI_BIT 2
#define RSLI_MASK 4
If set enables Receive Line Status Interrupt
#define MSI_BIT 3
#define MSI_MASK 8
If set enables the MODEM status interrupt
sfrb IIR = $F302;
#define NIP_BIT 0
#define NIP_MASK 1
If in logic b
#define ID0_BIT 1
#define ID0_MASK 2
Interrupt ID Bit 0
#define ID1_BIT 2
#define ID1_MASK 4
Interrupt ID Bit 1
#define ID2_BIT 3
#define ID2_MASK 8
Interrupt ID Bit 2
#define FIFOEN_BIT 6
#define FIFOEN_MASK 64
These two bits are set when FCR[0] is set.
#define FIFOEN_BIT 7
#define FIFOEN_MASK 128
These two bits are set when FCR[0] is set.
sfrb FCR = $F302;
#define FEN_BIT 0
#define FEN_MASK 1
When set, enables the 16 byte receive and transmit FIFOs. When cleared FIFOs are disabled and reset.
#define FRS_BIT 1
#define FRS_MASK 2
When set, resets the receive FIFO
#define TRS_BIT 2
#define TRS_MASK 4
When set, resets the transmit FIFO.
#define RDMA_BIT 3
#define RDMA_MASK 8
When FIFOs are disabled (FCR[0] is low), this bit is forced to b
#define RCVR0_BIT 6
#define RCVR0_MASK 64
These bits indicate the minimum number of bytes required in the receive FIFO to generate a receive ready interrupt. The trigger level is shown from the following table
#define RCVR1_BIT 7
#define RCVR1_MASK 128
These bits indicate the minimum number of bytes required in the receive FIFO to generate a receive ready interrupt. The trigger level is shown from the following table
sfrb LCR = $F303;
#define WL1_BIT 1
#define WL1_MASK 2
These bits determine the word length
#define SB_BIT 2
#define SB_MASK 4
This bit determines the number of stop bits
#define ENPAR_BIT 3
#define ENPAR_MASK 8
Setting this bit to logic '1' a parity bit is transmitted or checked. Resetting this bit to '0' no parity bit is transmitted or checked.
#define EVPAR_BIT 4
#define EVPAR_MASK 16
When the Enable Parity bit is a '1' and the Stick Parity bit is a '0', then setting to logic '1' the Even parity an even number of logic 1s is transmitted or checked in the data word bits and the Parity bit. When Even Parity bit is reset to logic '0' an odd number of 1s are transmitted or checked.When the Enable Parity bit is a '1' and the Stick Parity bit is a '0', then setting to logic '1' the Even parity an even number of logic 1s is transmitted or checked in the data word bits and the Parity bit. When Even Parity bit is reset to logic '0' an odd number of 1s are transmitted or checked.When the Enable Parity bit is a '1' and the Stick Parity bit is a '0', then setting to logic '1' the Even parity an even number of logic 1s is transmitted or checked in the data word bits and the Parity bit. When Even Parity bit is reset to logic '0' an odd number of 1s are transmitted or checked.When the Enable Parity bit is a '1' and the Stick Parity bit is a '0', then setting to logic '1' the Even parity an even number of logic 1s is transmitted or checked in the data word bits and the Parity bit. When Even Parity bit is reset to logic '0' an odd number of 1s are transmitted or checked
#define SPAR_BIT 5
#define SPAR_MASK 32
When the Parity Enable bit and the Parity Stick bit are set to logic '1' then the Even Parity bit controls the transmitted parity value. Resetting the Even parity bit to logic '0' then the parity bit is transmitted and checked as '1'. Setting the Even parity bit to logic '1' then the parity bit is transmitted and checked as '0'.
#define SBRK_BIT 6
#define SBRK_MASK 64
If set then it causes a break condition to to be transmitted to the receiving UART. The SOUT pin is forced to the spacing state (logic '0'). Resetting to logic '0' stops the break condition.The break control bit acts only on SOUT pin and has no effect on the transmitter logic. Note that UART waits before starting the break condition command for the complete transmission of the word in the transmit shift register. There is no need for software synchronization.
#define DLAB_BIT 7
#define DLAB_MASK 128
It must be set to logic b
sfrb MCR = $F304;
#define DTR_BIT 0
#define DTR_MASK 1
The compliment value of the bidirectional pin nDTR
#define RTS_BIT 1
#define RTS_MASK 2
The compliment value of the bidirectional pin nRTS
#define OUT1_BIT 2
#define OUT1_MASK 4
The compliment value of the bidirectional pin nOUT1
#define OUT2_BIT 3
#define OUT2_MASK 8
The compliment value of the bidirectional pin nOUT2
#define LB_BIT 4
#define LB_MASK 16
f Set enables the loopback mode. you can not set this bit at logic b
sfrb LSR = $F305;
#define RDA_BIT 0
#define RDA_MASK 1
If set indicates that there are data available in the RHR. This bit resets to logic '0' by reading all of the data from the Receive Holding Register or the Rx FIFO.
#define OE_BIT 1
#define OE_MASK 2
If set indicates an overrun error. Indicates that data in RHR was not read by the core before the next word was transferred into the RHR, thereby destroying the previous word. In FIFO Mode an overrun error will occur only after the Rx FIFO is full and the next word has been completely received in shift register. The word in the shift register is overwritten, but it is not transferred to the Rx FIFO. Overrun error is indicated to the core as soon as it happens. This bit is reset to a logic '0' whenever the core reads the LSR
#define PE_BIT 2
#define PE_MASK 4
If set indicates a parity error. Indicates that the received word in RHR does not have the correct parity bit. In FIFO mode this error is associated with the word at the top of the FIFO which is equivalent to RHR. This bit is reset to a logic '0' whenever the core reads the LSR.
#define FE_BIT 3
#define FE_MASK 8
If set indicates a framing error. Indicates that the received word in RHR does not have the correct stop bit. In FIFO mode this error is associated with the word at the top of the Rx FIFO which is equivalent to RHR. This bit is reset to a logic '0' whenever the core reads the LSR.
#define BI_BIT 4
#define BI_MASK 16
If set indicates a Break Interrupt. Indicates that the receive data input is held in the spacing state (logic '0') for longer than a full word transmission time.In FIFO mode this error is associated with the word at the top of the Rx FIFO which is equivalent to RHR. This bit is reset to a logic '0' whenever the core reads the LSR.
#define THRR_BIT 5
#define THRR_MASK 32
If set indicates that the THR is ready to accept a new word for transmission. This bit is set when a word is transferred from the THR into the Tx shift register. This bit is reset concurrently with the loading of the THR by the core. If Tx FIFO is enabled (FCR[0]=1, XR2[7]=0), the function of this bit is controlled by XR2[4]. If XR2[4] is '0', then this bit is set when the Tx FIFO is empty; it is cleared when at least 1 word is written to the Tx FIFO. If XR2[4] is '1', then this bit is set when the TxFIFO is not full
#define TE_BIT 6
#define TE_MASK 64
When set indicates that both the Transmit Shift Register and Transmit Holding Register, or the Tx FIFO if Tx FIFO is enabled, are empty.
#define ERF_BIT 7
#define ERF_MASK 128
If the FIFOs are disabled this bit is a '0'. If FIFOs are enabled this bit indicates that at least one word in the Rx FIFO has it's Parity Error or Framing Error or Break Indication bits high.
sfrb MSR = $F306;
#define DCTS_BIT 0
#define DCTS_MASK 1
#define DDSR_BIT 1
#define DDSR_MASK 2
#define TRI_BIT 2
#define TRI_MASK 4
#define DCD_BIT 3
#define DCD_MASK 8
#define CTS_BIT 4
#define CTS_MASK 16
#define DSR_BIT 5
#define DSR_MASK 32
#define RI_BIT 6
#define RI_MASK 64
#define CD_BIT 7
#define CD_MASK 128
sfrb SCR = $F307;
#define SCR0_BIT 0
#define SCR0_MASK 1
#define SCR1_BIT 1
#define SCR1_MASK 2
#define SCR2_BIT 2
#define SCR2_MASK 4
#define SCR3_BIT 3
#define SCR3_MASK 8
#define SCR4_BIT 4
#define SCR4_MASK 16
#define SCR5_BIT 5
#define SCR5_MASK 32
#define SCR6_BIT 6
#define SCR6_MASK 64
#define SCR7_BIT 7
#define SCR7_MASK 128
sfrb DLL = $F300;
#define DLL0_BIT 0
#define DLL0_MASK 1
#define DLL1_BIT 1
#define DLL1_MASK 2
#define DLL2_BIT 2
#define DLL2_MASK 4
#define DLL3_BIT 3
#define DLL3_MASK 8
#define DLL4_BIT 4
#define DLL4_MASK 16
#define DLL5_BIT 5
#define DLL5_MASK 32
#define DLL6_BIT 6
#define DLL6_MASK 64
#define DLL7_BIT 7
#define DLL7_MASK 128
sfrb DLL = $F301;
#define DLH0_BIT 0
#define DLH0_MASK 1
#define DLH1_BIT 1
#define DLH1_MASK 2
#define DLH2_BIT 2
#define DLH2_MASK 4
#define DLH3_BIT 3
#define DLH3_MASK 8
#define DLH4_BIT 4
#define DLH4_MASK 16
#define DLH5_BIT 5
#define DLH5_MASK 32
#define DLH6_BIT 6
#define DLH6_MASK 64
#define DLH7_BIT 7
#define DLH7_MASK 128
sfrb XR1 = $F308;
#define RXDIS_BIT 0
#define RXDIS_MASK 1
#define TXDIS_BIT 1
#define TXDIS_MASK 2
#define RXR_BIT 2
#define RXR_MASK 4
#define TXR_BIT 3
#define TXR_MASK 8
#define RTO_BIT 4
#define RTO_MASK 16
#define STOC_BIT 5
#define STOC_MASK 32
#define SA_BIT 6
#define SA_MASK 64
#define OPL_BIT 7
#define OPL_MASK 128
sfrb XR2 = $F309;
#define MDM_BIT 0
#define MDM_MASK 1
#define THRRC_BIT 4
#define THRRC_MASK 16
#define THRR_BIT 5
#define THRR_MASK 32
#define TE_BIT 6
#define TE_MASK 64
#define TxFD_BIT 7
#define TxFD_MASK 128
sfrb MDR = $F30A;
#define DTRD_BIT 0
#define DTRD_MASK 1
#define RTSD_BIT 1
#define RTSD_MASK 2
#define OUT1D_BIT 2
#define OUT1D_MASK 4
#define OUT2D_BIT 3
#define OUT2D_MASK 8
#define CTSD_BIT 4
#define CTSD_MASK 16
#define DSRD_BIT 5
#define DSRD_MASK 32
#define RID_BIT 6
#define RID_MASK 64
#define CDD_BIT 7
#define CDD_MASK 128
sfrb RTO = $F30B;
#define RTO0_BIT 0
#define RTO0_MASK 1
#define RTO1_BIT 1
#define RTO1_MASK 2
#define RTO2_BIT 2
#define RTO2_MASK 4
#define RTO3_BIT 3
#define RTO3_MASK 8
#define RTO4_BIT 4
#define RTO4_MASK 16
#define RTO5_BIT 5
#define RTO5_MASK 32
#define RTO6_BIT 6
#define RTO6_MASK 64
#define RTO7_BIT 7
#define RTO7_MASK 128
sfrb TTG = $F30C;
#define TTG0_BIT 0
#define TTG0_MASK 1
#define TTG1_BIT 1
#define TTG1_MASK 2
#define TTG2_BIT 2
#define TTG2_MASK 4
#define TTG3_BIT 3
#define TTG3_MASK 8
#define TTG4_BIT 4
#define TTG4_MASK 16
#define TTG5_BIT 5
#define TTG5_MASK 32
#define TTG6_BIT 6
#define TTG6_MASK 64
#define TTG7_BIT 7
#define TTG7_MASK 128
sfrb SLP_MODE = $F000;
#define SLP_BIT 5
#define SLP_MASK 32
If set, puts the USB Controller in sleep Mode
sfrb IRQ_EN = $F001;
#define RSM_INT_EN_BIT 0
#define RSM_INT_EN_MASK 1
If this bit is high, an interrupt is generated when the USB enters resume mode. A J-to-K state change on the USB port signal resume.
#define SUSP_INT_EN_BIT 1
#define SUSP_INT_EN_MASK 2
If this bit is high, an interrupt is generated when the USB enters suspend mode. A USB device enters in suspend mode only when requested by the USB host through bus inactivity for at least 3ms.
#define INT_EN_BIT 6
#define INT_EN_MASK 64
When thsi bit is high, enables the USB protocol handler to cause Interrupt.
sfrb IRQ_STAT = $F002;
#define RSM_BIT 0
#define RSM_MASK 1
When this bit is high, the USB has entered the resume state.
#define SUSP_BIT 1
#define SUSP_MASK 2
When this bit is high, the USB has entered the suspend mode.
#define INT_BIT 6
#define INT_MASK 64
Interrupt from the USB protocol handler. When this bit is high, then at least one bit of UISR is set.
sfrb RES_STAT = $F003;
#define USB_RES_BIT 3
#define USB_RES_MASK 8
Set when USB enters reset State
sfrb PAIR_EN = $F004;
#define UPA1_BIT 1
#define UPA1_MASK 2
UPA[1]: EP4 has the same USB physical address with EP1
#define UPA2_BIT 2
#define UPA2_MASK 4
UPA[2]: EP4 has the same USB physical address with EP2
#define UPA3_BIT 3
#define UPA3_MASK 8
UPA[3]: EP4 has the same USB physical address with EP3
sfrb USB_DMA_ADL = $F005;
#define UDA0_BIT 0
#define UDA0_MASK 1
#define UDA1_BIT 1
#define UDA1_MASK 2
#define UDA2_BIT 2
#define UDA2_MASK 4
#define UDA3_BIT 3
#define UDA3_MASK 8
#define UDA4_BIT 4
#define UDA4_MASK 16
#define UDA5_BIT 5
#define UDA5_MASK 32
#define UDA6_BIT 6
#define UDA6_MASK 64
#define UDA7_BIT 7
#define UDA7_MASK 128
sfrb USB_DMA_ADH = $F006;
#define UDA8_BIT 1
#define UDA8_MASK 2
#define UDA9_BIT 2
#define UDA9_MASK 4
#define UDA10_BIT 3
#define UDA10_MASK 8
#define UDA11_BIT 4
#define UDA11_MASK 16
#define UDA12_BIT 5
#define UDA12_MASK 32
#define UDA13_BIT 6
#define UDA13_MASK 64
#define UDA14_BIT 7
#define UDA14_MASK 128
sfrb USB_DMA_LEN = $F007;
#define PLEN0_BIT 0
#define PLEN0_MASK 1
#define PLEN1_BIT 1
#define PLEN1_MASK 2
#define PLEN2_BIT 2
#define PLEN2_MASK 4
#define PLEN3_BIT 3
#define PLEN3_MASK 8
#define PLEN4_BIT 4
#define PLEN4_MASK 16
#define PLEN5_BIT 5
#define PLEN5_MASK 32
#define PLEN6_BIT 6
#define PLEN6_MASK 64
#define PLEN7_BIT 7
#define PLEN7_MASK 128
sfrb USB_DMA_EAD = $F008;
#define EAD0_BIT 0
#define EAD0_MASK 1
#define EAD1_BIT 1
#define EAD1_MASK 2
#define EAD2_BIT 2
#define EAD2_MASK 4
#define EAD3_BIT 3
#define EAD3_MASK 8
#define EAD4_BIT 4
#define EAD4_MASK 16
#define EAD5_BIT 5
#define EAD5_MASK 32
#define EAD6_BIT 6
#define EAD6_MASK 64
#define EAD7_BIT 7
#define EAD7_MASK 128
sfrb USB_DMA_PLT = $F009;
#define TPL0_BIT 0
#define TPL0_MASK 1
#define TPL1_BIT 1
#define TPL1_MASK 2
#define TPL2_BIT 2
#define TPL2_MASK 4
#define TPL3_BIT 3
#define TPL3_MASK 8
#define TPL4_BIT 4
#define TPL4_MASK 16
#define TPL5_BIT 5
#define TPL5_MASK 32
#define TPL6_BIT 6
#define TPL6_MASK 64
#define TPL7_BIT 7
#define TPL7_MASK 128
sfrb USB_DMA_EN = $F00A;
#define USB_TDMA_EN_BIT 0
#define USB_TDMA_EN_MASK 1
Enables Transmit DMA (for IN EPs). This bit is automatically cleared after the end of the DMA.
#define USB_RDMA_EN_BIT 1
#define USB_RDMA_EN_MASK 2
Enables Receive DMA (for OUT EPs). This bit is automatically cleared after the end of the DMA.
sfrb FBYTE_CNT7_H = $F0A8;
#define BYTECNT8_BIT 0
#define BYTECNT8_MASK 1
#define BYTECNT9_BIT 1
#define BYTECNT9_MASK 2
#define BYTECNT10_BIT 2
#define BYTECNT10_MASK 4
sfrb FBYTE_CNT6_H = $F0A9;
#define BYTECNT8_BIT 0
#define BYTECNT8_MASK 1
#define BYTECNT9_BIT 1
#define BYTECNT9_MASK 2
#define BYTECNT10_BIT 2
#define BYTECNT10_MASK 4
sfrb FBYTE_CNT5_H = $F0AA;
#define BYTECNT8_BIT 0
#define BYTECNT8_MASK 1
#define BYTECNT9_BIT 1
#define BYTECNT9_MASK 2
#define BYTECNT10_BIT 2
#define BYTECNT10_MASK 4
sfrb FBYTE_CNT4_H = $F0AB;
#define BYTECNT8_BIT 0
#define BYTECNT8_MASK 1
#define BYTECNT9_BIT 1
#define BYTECNT9_MASK 2
#define BYTECNT10_BIT 2
#define BYTECNT10_MASK 4
sfrb FBYTE_CNT3_H = $F0AC;
#define BYTECNT8_BIT 0
#define BYTECNT8_MASK 1
#define BYTECNT9_BIT 1
#define BYTECNT9_MASK 2
#define BYTECNT10_BIT 2
#define BYTECNT10_MASK 4
sfrb FBYTE_CNT2_H = $F0AD;
#define BYTECNT8_BIT 0
#define BYTECNT8_MASK 1
#define BYTECNT9_BIT 1
#define BYTECNT9_MASK 2
#define BYTECNT10_BIT 2
#define BYTECNT10_MASK 4
sfrb FBYTE_CNT1_H = $F0AE;
#define BYTECNT8_BIT 0
#define BYTECNT8_MASK 1
#define BYTECNT9_BIT 1
#define BYTECNT9_MASK 2
#define BYTECNT10_BIT 2
#define BYTECNT10_MASK 4
sfrb FBYTE_CNT0_H = $F0AF;
#define BYTECNT8_BIT 0
#define BYTECNT8_MASK 1
#define BYTECNT9_BIT 1
#define BYTECNT9_MASK 2
#define BYTECNT10_BIT 2
#define BYTECNT10_MASK 4
sfrb FBYTE_CNT7_L = $F0B8;
#define BYTECNT0_BIT 0
#define BYTECNT0_MASK 1
#define BYTECNT1_BIT 1
#define BYTECNT1_MASK 2
#define BYTECNT2_BIT 2
#define BYTECNT2_MASK 4
#define BYTECNT3_BIT 3
#define BYTECNT3_MASK 8
#define BYTECNT4_BIT 4
#define BYTECNT4_MASK 16
#define BYTECNT5_BIT 5
#define BYTECNT5_MASK 32
#define BYTECNT6_BIT 6
#define BYTECNT6_MASK 64
#define BYTECNT7_BIT 7
#define BYTECNT7_MASK 128
sfrb FBYTE_CNT6_L = $F0B9;
#define BYTECNT0_BIT 0
#define BYTECNT0_MASK 1
#define BYTECNT1_BIT 1
#define BYTECNT1_MASK 2
#define BYTECNT2_BIT 2
#define BYTECNT2_MASK 4
#define BYTECNT3_BIT 3
#define BYTECNT3_MASK 8
#define BYTECNT4_BIT 4
#define BYTECNT4_MASK 16
#define BYTECNT5_BIT 5
#define BYTECNT5_MASK 32
#define BYTECNT6_BIT 6
#define BYTECNT6_MASK 64
#define BYTECNT7_BIT 7
#define BYTECNT7_MASK 128
sfrb FBYTE_CNT5_L = $F0BA;
#define BYTECNT0_BIT 0
#define BYTECNT0_MASK 1
#define BYTECNT1_BIT 1
#define BYTECNT1_MASK 2
#define BYTECNT2_BIT 2
#define BYTECNT2_MASK 4
#define BYTECNT3_BIT 3
#define BYTECNT3_MASK 8
#define BYTECNT4_BIT 4
#define BYTECNT4_MASK 16
#define BYTECNT5_BIT 5
#define BYTECNT5_MASK 32
#define BYTECNT6_BIT 6
#define BYTECNT6_MASK 64
#define BYTECNT7_BIT 7
#define BYTECNT7_MASK 128
sfrb FBYTE_CNT4_L = $F0BB;
#define BYTECNT0_BIT 0
#define BYTECNT0_MASK 1
#define BYTECNT1_BIT 1
#define BYTECNT1_MASK 2
#define BYTECNT2_BIT 2
#define BYTECNT2_MASK 4
#define BYTECNT3_BIT 3
#define BYTECNT3_MASK 8
#define BYTECNT4_BIT 4
#define BYTECNT4_MASK 16
#define BYTECNT5_BIT 5
#define BYTECNT5_MASK 32
#define BYTECNT6_BIT 6
#define BYTECNT6_MASK 64
#define BYTECNT7_BIT 7
#define BYTECNT7_MASK 128
sfrb FBYTE_CNT3_L = $F0BC;
#define BYTECNT0_BIT 0
#define BYTECNT0_MASK 1
#define BYTECNT1_BIT 1
#define BYTECNT1_MASK 2
#define BYTECNT2_BIT 2
#define BYTECNT2_MASK 4
#define BYTECNT3_BIT 3
#define BYTECNT3_MASK 8
#define BYTECNT4_BIT 4
#define BYTECNT4_MASK 16
#define BYTECNT5_BIT 5
#define BYTECNT5_MASK 32
#define BYTECNT6_BIT 6
#define BYTECNT6_MASK 64
#define BYTECNT7_BIT 7
#define BYTECNT7_MASK 128
sfrb FBYTE_CNT2_L = $F0BD;
#define BYTECNT0_BIT 0
#define BYTECNT0_MASK 1
#define BYTECNT1_BIT 1
#define BYTECNT1_MASK 2
#define BYTECNT2_BIT 2
#define BYTECNT2_MASK 4
#define BYTECNT3_BIT 3
#define BYTECNT3_MASK 8
#define BYTECNT4_BIT 4
#define BYTECNT4_MASK 16
#define BYTECNT5_BIT 5
#define BYTECNT5_MASK 32
#define BYTECNT6_BIT 6
#define BYTECNT6_MASK 64
#define BYTECNT7_BIT 7
#define BYTECNT7_MASK 128
sfrb FBYTE_CNT1_L = $F0BE;
#define BYTECNT0_BIT 0
#define BYTECNT0_MASK 1
#define BYTECNT1_BIT 1
#define BYTECNT1_MASK 2
#define BYTECNT2_BIT 2
#define BYTECNT2_MASK 4
#define BYTECNT3_BIT 3
#define BYTECNT3_MASK 8
#define BYTECNT4_BIT 4
#define BYTECNT4_MASK 16
#define BYTECNT5_BIT 5
#define BYTECNT5_MASK 32
#define BYTECNT6_BIT 6
#define BYTECNT6_MASK 64
#define BYTECNT7_BIT 7
#define BYTECNT7_MASK 128
sfrb FBYTE_CNT0_L = $F0BF;
#define BYTECNT0_BIT 0
#define BYTECNT0_MASK 1
#define BYTECNT1_BIT 1
#define BYTECNT1_MASK 2
#define BYTECNT2_BIT 2
#define BYTECNT2_MASK 4
#define BYTECNT3_BIT 3
#define BYTECNT3_MASK 8
#define BYTECNT4_BIT 4
#define BYTECNT4_MASK 16
#define BYTECNT5_BIT 5
#define BYTECNT5_MASK 32
#define BYTECNT6_BIT 6
#define BYTECNT6_MASK 64
#define BYTECNT7_BIT 7
#define BYTECNT7_MASK 128
sfrb FDR7 = $F0C8;
#define FIFODATA0_BIT 0
#define FIFODATA0_MASK 1
#define FIFODATA1_BIT 1
#define FIFODATA1_MASK 2
#define FIFODATA2_BIT 2
#define FIFODATA2_MASK 4
#define FIFODATA3_BIT 3
#define FIFODATA3_MASK 8
#define FIFODATA4_BIT 4
#define FIFODATA4_MASK 16
#define FIFODATA5_BIT 5
#define FIFODATA5_MASK 32
#define FIFODATA6_BIT 6
#define FIFODATA6_MASK 64
#define FIFODATA7_BIT 7
#define FIFODATA7_MASK 128
sfrb FDR6 = $F0C9;
#define FIFODATA0_BIT 0
#define FIFODATA0_MASK 1
#define FIFODATA1_BIT 1
#define FIFODATA1_MASK 2
#define FIFODATA2_BIT 2
#define FIFODATA2_MASK 4
#define FIFODATA3_BIT 3
#define FIFODATA3_MASK 8
#define FIFODATA4_BIT 4
#define FIFODATA4_MASK 16
#define FIFODATA5_BIT 5
#define FIFODATA5_MASK 32
#define FIFODATA6_BIT 6
#define FIFODATA6_MASK 64
#define FIFODATA7_BIT 7
#define FIFODATA7_MASK 128
sfrb FDR5 = $F0CA;
#define FIFODATA0_BIT 0
#define FIFODATA0_MASK 1
#define FIFODATA1_BIT 1
#define FIFODATA1_MASK 2
#define FIFODATA2_BIT 2
#define FIFODATA2_MASK 4
#define FIFODATA3_BIT 3
#define FIFODATA3_MASK 8
#define FIFODATA4_BIT 4
#define FIFODATA4_MASK 16
#define FIFODATA5_BIT 5
#define FIFODATA5_MASK 32
#define FIFODATA6_BIT 6
#define FIFODATA6_MASK 64
#define FIFODATA7_BIT 7
#define FIFODATA7_MASK 128
sfrb FDR4 = $F0CB;
#define FIFODATA0_BIT 0
#define FIFODATA0_MASK 1
#define FIFODATA1_BIT 1
#define FIFODATA1_MASK 2
#define FIFODATA2_BIT 2
#define FIFODATA2_MASK 4
#define FIFODATA3_BIT 3
#define FIFODATA3_MASK 8
#define FIFODATA4_BIT 4
#define FIFODATA4_MASK 16
#define FIFODATA5_BIT 5
#define FIFODATA5_MASK 32
#define FIFODATA6_BIT 6
#define FIFODATA6_MASK 64
#define FIFODATA7_BIT 7
#define FIFODATA7_MASK 128
sfrb FDR3 = $F0CC;
#define FIFODATA0_BIT 0
#define FIFODATA0_MASK 1
#define FIFODATA1_BIT 1
#define FIFODATA1_MASK 2
#define FIFODATA2_BIT 2
#define FIFODATA2_MASK 4
#define FIFODATA3_BIT 3
#define FIFODATA3_MASK 8
#define FIFODATA4_BIT 4
#define FIFODATA4_MASK 16
#define FIFODATA5_BIT 5
#define FIFODATA5_MASK 32
#define FIFODATA6_BIT 6
#define FIFODATA6_MASK 64
#define FIFODATA7_BIT 7
#define FIFODATA7_MASK 128
sfrb FDR2 = $F0CD;
#define FIFODATA0_BIT 0
#define FIFODATA0_MASK 1
#define FIFODATA1_BIT 1
#define FIFODATA1_MASK 2
#define FIFODATA2_BIT 2
#define FIFODATA2_MASK 4
#define FIFODATA3_BIT 3
#define FIFODATA3_MASK 8
#define FIFODATA4_BIT 4
#define FIFODATA4_MASK 16
#define FIFODATA5_BIT 5
#define FIFODATA5_MASK 32
#define FIFODATA6_BIT 6
#define FIFODATA6_MASK 64
#define FIFODATA7_BIT 7
#define FIFODATA7_MASK 128
sfrb FDR1 = $F0CE;
#define FIFODATA0_BIT 0
#define FIFODATA0_MASK 1
#define FIFODATA1_BIT 1
#define FIFODATA1_MASK 2
#define FIFODATA2_BIT 2
#define FIFODATA2_MASK 4
#define FIFODATA3_BIT 3
#define FIFODATA3_MASK 8
#define FIFODATA4_BIT 4
#define FIFODATA4_MASK 16
#define FIFODATA5_BIT 5
#define FIFODATA5_MASK 32
#define FIFODATA6_BIT 6
#define FIFODATA6_MASK 64
#define FIFODATA7_BIT 7
#define FIFODATA7_MASK 128
sfrb FDR0 = $F0CF;
#define FIFODATA0_BIT 0
#define FIFODATA0_MASK 1
#define FIFODATA1_BIT 1
#define FIFODATA1_MASK 2
#define FIFODATA2_BIT 2
#define FIFODATA2_MASK 4
#define FIFODATA3_BIT 3
#define FIFODATA3_MASK 8
#define FIFODATA4_BIT 4
#define FIFODATA4_MASK 16
#define FIFODATA5_BIT 5
#define FIFODATA5_MASK 32
#define FIFODATA6_BIT 6
#define FIFODATA6_MASK 64
#define FIFODATA7_BIT 7
#define FIFODATA7_MASK 128
sfrb ECSR7 = $F0D8;
#define TXComplete_BIT 0
#define TXComplete_MASK 1
#define RXOUT_BIT 1
#define RXOUT_MASK 2
#define RXSETUP_BIT 2
#define RXSETUP_MASK 4
#define StallSnd_BIT 3
#define StallSnd_MASK 8
#define TxPacketReady_BIT 4
#define TxPacketReady_MASK 16
#define ForceStall_BIT 5
#define ForceStall_MASK 32
#define DataEnd_BIT 6
#define DataEnd_MASK 64
#define ControlDirection_BIT 7
#define ControlDirection_MASK 128
sfrb ECSR6 = $F0D9;
#define TXComplete_BIT 0
#define TXComplete_MASK 1
#define RXOUT_BIT 1
#define RXOUT_MASK 2
#define RXSETUP_BIT 2
#define RXSETUP_MASK 4
#define StallSnd_BIT 3
#define StallSnd_MASK 8
#define TxPacketReady_BIT 4
#define TxPacketReady_MASK 16
#define ForceStall_BIT 5
#define ForceStall_MASK 32
#define DataEnd_BIT 6
#define DataEnd_MASK 64
#define ControlDirection_BIT 7
#define ControlDirection_MASK 128
sfrb ECSR5 = $F0DA;
#define TXComplete_BIT 0
#define TXComplete_MASK 1
#define RXOUT_BIT 1
#define RXOUT_MASK 2
#define RXSETUP_BIT 2
#define RXSETUP_MASK 4
#define StallSnd_BIT 3
#define StallSnd_MASK 8
#define TxPacketReady_BIT 4
#define TxPacketReady_MASK 16
#define ForceStall_BIT 5
#define ForceStall_MASK 32
#define DataEnd_BIT 6
#define DataEnd_MASK 64
#define ControlDirection_BIT 7
#define ControlDirection_MASK 128
sfrb ECSR4 = $F0DB;
#define TXComplete_BIT 0
#define TXComplete_MASK 1
#define RXOUT_BIT 1
#define RXOUT_MASK 2
#define RXSETUP_BIT 2
#define RXSETUP_MASK 4
#define StallSnd_BIT 3
#define StallSnd_MASK 8
#define TxPacketReady_BIT 4
#define TxPacketReady_MASK 16
#define ForceStall_BIT 5
#define ForceStall_MASK 32
#define DataEnd_BIT 6
#define DataEnd_MASK 64
#define ControlDirection_BIT 7
#define ControlDirection_MASK 128
sfrb ECSR3 = $F0DC;
#define TXComplete_BIT 0
#define TXComplete_MASK 1
#define RXOUT_BIT 1
#define RXOUT_MASK 2
#define RXSETUP_BIT 2
#define RXSETUP_MASK 4
#define StallSnd_BIT 3
#define StallSnd_MASK 8
#define TxPacketReady_BIT 4
#define TxPacketReady_MASK 16
#define ForceStall_BIT 5
#define ForceStall_MASK 32
#define DataEnd_BIT 6
#define DataEnd_MASK 64
#define ControlDirection_BIT 7
#define ControlDirection_MASK 128
sfrb ECSR2 = $F0DD;
#define TXComplete_BIT 0
#define TXComplete_MASK 1
#define RXOUT_BIT 1
#define RXOUT_MASK 2
#define RXSETUP_BIT 2
#define RXSETUP_MASK 4
#define StallSnd_BIT 3
#define StallSnd_MASK 8
#define TxPacketReady_BIT 4
#define TxPacketReady_MASK 16
#define ForceStall_BIT 5
#define ForceStall_MASK 32
#define DataEnd_BIT 6
#define DataEnd_MASK 64
#define ControlDirection_BIT 7
#define ControlDirection_MASK 128
sfrb ECSR1 = $F0DE;
#define TXComplete_BIT 0
#define TXComplete_MASK 1
#define RXOUT_BIT 1
#define RXOUT_MASK 2
#define RXSETUP_BIT 2
#define RXSETUP_MASK 4
#define StallSnd_BIT 3
#define StallSnd_MASK 8
#define TxPacketReady_BIT 4
#define TxPacketReady_MASK 16
#define ForceStall_BIT 5
#define ForceStall_MASK 32
#define DataEnd_BIT 6
#define DataEnd_MASK 64
#define ControlDirection_BIT 7
#define ControlDirection_MASK 128
sfrb ECSR0 = $F0DF;
#define TXComplete_BIT 0
#define TXComplete_MASK 1
#define RXOUT_BIT 1
#define RXOUT_MASK 2
#define RXSETUP_BIT 2
#define RXSETUP_MASK 4
#define StallSnd_BIT 3
#define StallSnd_MASK 8
#define TxPacketReady_BIT 4
#define TxPacketReady_MASK 16
#define ForceStall_BIT 5
#define ForceStall_MASK 32
#define DataEnd_BIT 6
#define DataEnd_MASK 64
#define ControlDirection_BIT 7
#define ControlDirection_MASK 128
sfrb ECR7 = $F0E8;
#define EPTYPE0_BIT 0
#define EPTYPE0_MASK 1
These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.
#define EPTYPE1_BIT 1
#define EPTYPE1_MASK 2
These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.
#define EPDIR_BIT 2
#define EPDIR_MASK 4
Only applicable for non-Control Endpoints (0 =Out, 1 =In).
#define DTGLE_BIT 3
#define DTGLE_MASK 8
Identifies DATA0 or DATA1 packets
#define EPEDS_BIT 7
#define EPEDS_MASK 128
(0 = Disable Endpoint, 1 = Enable Endpoint)
sfrb ECR6 = $F0E9;
#define EPTYPE0_BIT 0
#define EPTYPE0_MASK 1
These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.
#define EPTYPE1_BIT 1
#define EPTYPE1_MASK 2
These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.
#define EPDIR_BIT 2
#define EPDIR_MASK 4
Only applicable for non-Control Endpoints (0 =Out, 1 =In).
#define DTGLE_BIT 3
#define DTGLE_MASK 8
Identifies DATA0 or DATA1 packets
#define EPEDS_BIT 7
#define EPEDS_MASK 128
(0 = Disable Endpoint, 1 = Enable Endpoint)
sfrb ECR6 = $F0EA;
#define EPTYPE0_BIT 0
#define EPTYPE0_MASK 1
These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.
#define EPTYPE1_BIT 1
#define EPTYPE1_MASK 2
These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.
#define EPDIR_BIT 2
#define EPDIR_MASK 4
Only applicable for non-Control Endpoints (0 =Out, 1 =In).
#define DTGLE_BIT 3
#define DTGLE_MASK 8
Identifies DATA0 or DATA1 packets
#define EPEDS_BIT 7
#define EPEDS_MASK 128
(0 = Disable Endpoint, 1 = Enable Endpoint)
sfrb ECR4 = $F0EB;
#define EPTYPE0_BIT 0
#define EPTYPE0_MASK 1
These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.
#define EPTYPE1_BIT 1
#define EPTYPE1_MASK 2
These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.
#define EPDIR_BIT 2
#define EPDIR_MASK 4
Only applicable for non-Control Endpoints (0 =Out, 1 =In).
#define DTGLE_BIT 3
#define DTGLE_MASK 8
Identifies DATA0 or DATA1 packets
#define EPEDS_BIT 7
#define EPEDS_MASK 128
(0 = Disable Endpoint, 1 = Enable Endpoint)
sfrb ECR3 = $F0EC;
#define EPTYPE0_BIT 0
#define EPTYPE0_MASK 1
These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.
#define EPTYPE1_BIT 1
#define EPTYPE1_MASK 2
These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.
#define EPDIR_BIT 2
#define EPDIR_MASK 4
Only applicable for non-Control Endpoints (0 =Out, 1 =In).
#define DTGLE_BIT 3
#define DTGLE_MASK 8
Identifies DATA0 or DATA1 packets
#define EPEDS_BIT 7
#define EPEDS_MASK 128
(0 = Disable Endpoint, 1 = Enable Endpoint)
sfrb ECR2 = $F0EC;
#define EPTYPE0_BIT 0
#define EPTYPE0_MASK 1
These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.
#define EPTYPE1_BIT 1
#define EPTYPE1_MASK 2
These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.
#define EPDIR_BIT 2
#define EPDIR_MASK 4
Only applicable for non-Control Endpoints (0 =Out, 1 =In).
#define DTGLE_BIT 3
#define DTGLE_MASK 8
Identifies DATA0 or DATA1 packets
#define EPEDS_BIT 7
#define EPEDS_MASK 128
(0 = Disable Endpoint, 1 = Enable Endpoint)
sfrb ECR1 = $F0ED;
#define EPTYPE0_BIT 0
#define EPTYPE0_MASK 1
These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.
#define EPTYPE1_BIT 1
#define EPTYPE1_MASK 2
These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.
#define EPDIR_BIT 2
#define EPDIR_MASK 4
Only applicable for non-Control Endpoints (0 =Out, 1 =In).
#define DTGLE_BIT 3
#define DTGLE_MASK 8
Identifies DATA0 or DATA1 packets
#define EPEDS_BIT 7
#define EPEDS_MASK 128
(0 = Disable Endpoint, 1 = Enable Endpoint)
sfrb ECR0 = $F0EF;
#define EPTYPE0_BIT 0
#define EPTYPE0_MASK 1
These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.
#define EPTYPE1_BIT 1
#define EPTYPE1_MASK 2
These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type : 0 0 Control,0 1 Isochronous,1 0 Bulk, 1 1 Interrupt.
#define EPDIR_BIT 2
#define EPDIR_MASK 4
Only applicable for non-Control Endpoints (0 =Out, 1 =In).
#define DTGLE_BIT 3
#define DTGLE_MASK 8
Identifies DATA0 or DATA1 packets
#define EPEDS_BIT 7
#define EPEDS_MASK 128
(0 = Disable Endpoint, 1 = Enable Endpoint)
sfrb ENDPPGPG = $F0F1;
#define PGPG0EN_BIT 0
#define PGPG0EN_MASK 1
#define PGPG1EN_BIT 1
#define PGPG1EN_MASK 2
#define PGPG2EN_BIT 2
#define PGPG2EN_MASK 4
#define PGPG3EN_BIT 3
#define PGPG3EN_MASK 8
#define PGPG4EN_BIT 4
#define PGPG4EN_MASK 16
#define PGPG5EN_BIT 5
#define PGPG5EN_MASK 32
#define PGPG6EN_BIT 6
#define PGPG6EN_MASK 64
sfrb FADDR = $F0F2;
#define FADD0_BIT 0
#define FADD0_MASK 1
#define FADD1_BIT 1
#define FADD1_MASK 2
#define FADD2_BIT 2
#define FADD2_MASK 4
#define FADD3_BIT 3
#define FADD3_MASK 8
#define FADD4_BIT 4
#define FADD4_MASK 16
#define FADD5_BIT 5
#define FADD5_MASK 32
#define FADD6_BIT 6
#define FADD6_MASK 64
#define FEN_BIT 7
#define FEN_MASK 128
sfrb UIER = $F0F3;
#define EP0IE_BIT 0
#define EP0IE_MASK 1
#define EP1IE_BIT 1
#define EP1IE_MASK 2
#define EP2IE_BIT 2
#define EP2IE_MASK 4
#define EP3IE_BIT 3
#define EP3IE_MASK 8
#define EP5IE_BIT 4
#define EP5IE_MASK 16
#define EP5IE_BIT 5
#define EP5IE_MASK 32
#define EP6IE_BIT 6
#define EP6IE_MASK 64
#define SOF IE_BIT 7
#define SOF IE_MASK 128
sfrb UIAR = $F0F5;
#define EP0INTA_BIT 0
#define EP0INTA_MASK 1
#define EP1INTA_BIT 1
#define EP1INTA_MASK 2
#define EP2INTA_BIT 2
#define EP2INTA_MASK 4
#define EP3INTA_BIT 3
#define EP3INTA_MASK 8
#define EP4INTA_BIT 4
#define EP4INTA_MASK 16
#define EP5INTA_BIT 5
#define EP5INTA_MASK 32
#define EP6INTA_BIT 6
#define EP6INTA_MASK 64
sfrb UISR = $F0F7;
#define EP0INT_BIT 0
#define EP0INT_MASK 1
#define EP1INT_BIT 1
#define EP1INT_MASK 2
#define EP2INT_BIT 2
#define EP2INT_MASK 4
#define EP3INT_BIT 3
#define EP3INT_MASK 8
#define EP4INT_BIT 4
#define EP4INT_MASK 16
#define EP5INT_BIT 5
#define EP5INT_MASK 32
#define EP6INT_BIT 6
#define EP6INT_MASK 64
sfrb SPRSIE = $F0F9;
#define SUSPIE_BIT 0
#define SUSPIE_MASK 1
#define RCVDRSNIE_BIT 1
#define RCVDRSNIE_MASK 2
#define EXTRSMIE_BIT 2
#define EXTRSMIE_MASK 4
#define SOF IE_BIT 3
#define SOF IE_MASK 8
sfrb SPRSR = $F0FA;
#define SUSP_BIT 0
#define SUSP_MASK 1
#define RCVDRSM_BIT 1
#define RCVDRSM_MASK 2
#define EXTRSM_BIT 2
#define EXTRSM_MASK 4
#define SOF INT_BIT 3
#define SOF INT_MASK 8
sfrb GLB_STATE = $F0FB;
#define FADD_BIT 0
#define FADD_MASK 1
#define CONFG_BIT 1
#define CONFG_MASK 2
#define RMWUPE_BIT 2
#define RMWUPE_MASK 4
#define RSMINPR_BIT 3
#define RSMINPR_MASK 8
sfrb FRM_NUM_L = $F0FC;
#define FCL0_BIT 0
#define FCL0_MASK 1
#define FCL1_BIT 1
#define FCL1_MASK 2
#define FCL2_BIT 2
#define FCL2_MASK 4
#define FCL3_BIT 3
#define FCL3_MASK 8
#define FCL4_BIT 4
#define FCL4_MASK 16
#define FCL5_BIT 5
#define FCL5_MASK 32
#define FCL6_BIT 6
#define FCL6_MASK 64
#define FCL7_BIT 7
#define FCL7_MASK 128
sfrb FRM_NUM_H = $F0FD;
#define FCH8_BIT 0
#define FCH8_MASK 1
#define FCH9_BIT 1
#define FCH9_MASK 2
#define FCH10_BIT 2
#define FCH10_MASK 4