This documentation was generated automatically from the AVR Studio part description file AT86RF401.pdf.

RF CONTROL

LOCKDET1 - Lock Detector Configuration Register 1

sfrb LOCKDET1 = $10;

CS0 - Cycle Slip Counter bit 0

#define CS0_BIT 0

#define CS0_MASK 1

CS1 - Cycle Slip Counter bit 1

#define CS1_BIT 1

#define CS1_MASK 2

BOD - Black Out Disable

#define BOD_BIT 2

#define BOD_MASK 4

ENKO - Enable Key On Bit

#define ENKO_BIT 3

#define ENKO_MASK 8

UPOK - Unlock Conuter Control

#define UPOK_BIT 4

#define UPOK_MASK 16

LOCKDET1 - Lock Detector Configuration register 2

sfrb LOCKDET1 = $17;

LC0 - Lock Count bit 0

#define LC0_BIT 0

#define LC0_MASK 1

LC1 - Lock Count bit 1

#define LC1_BIT 1

#define LC1_MASK 2

LC2 - Lock Count bit 2

#define LC2_BIT 2

#define LC2_MASK 4

ULC0 - Unlock Count bit 0

#define ULC0_BIT 3

#define ULC0_MASK 8

ULC1 - Unlock Count bit 1

#define ULC1_BIT 4

#define ULC1_MASK 16

ULC2 - Unlock Count bit 2

#define ULC2_BIT 5

#define ULC2_MASK 32

LAT - Lock Always True

#define LAT_BIT 6

#define LAT_MASK 64

EUD - Enable Unlock Detect

#define EUD_BIT 7

#define EUD_MASK 128

TX_CNTL - Transmit Control Register

sfrb TX_CNTL = $12;

LOC - PLL Lock

#define LOC_BIT 2

#define LOC_MASK 4

TXK - Transmitter Key

#define TXK_BIT 4

#define TXK_MASK 16

TXE - Transmitter Enable

#define TXE_BIT 5

#define TXE_MASK 32

FSK - FSK Mode

#define FSK_BIT 6

#define FSK_MASK 64

PWR_ATTEN - Power Attenuation Control Register

sfrb PWR_ATTEN = $14;

PCF0 - Power Control Fine bit 0

#define PCF0_BIT 0

#define PCF0_MASK 1

PCF1 - Power Control Fine bit 1

#define PCF1_BIT 1

#define PCF1_MASK 2

PCF2 - Power Control Fine bit 2

#define PCF2_BIT 2

#define PCF2_MASK 4

PCC0 - Power Control Coarse bit 0

#define PCC0_BIT 3

#define PCC0_MASK 8

PCC1 - Power Control Coarse bit 1

#define PCC1_BIT 4

#define PCC1_MASK 16

PCC2 - Power Control Coarse bit 2

#define PCC2_BIT 5

#define PCC2_MASK 32

VCOTUNE - VCO Tuning Register

sfrb VCOTUNE = $16;

VCOTUNE0 - VCO Tuning Register bit 0

#define VCOTUNE0_BIT 0

#define VCOTUNE0_MASK 1

VCOTUNE1 - VCO Tuning Register bit 1

#define VCOTUNE1_BIT 1

#define VCOTUNE1_MASK 2

VCOTUNE2 - VCO Tuning Register bit 2

#define VCOTUNE2_BIT 2

#define VCOTUNE2_MASK 4

VCOTUNE3 - VCO Tuning Register bit 3

#define VCOTUNE3_BIT 3

#define VCOTUNE3_MASK 8

VCOTUNE4 - VCO Tuning Register bit 4

#define VCOTUNE4_BIT 4

#define VCOTUNE4_MASK 16

VCOVDET0 - VCO Voltage Detector bit 0

#define VCOVDET0_BIT 6

#define VCOVDET0_MASK 64

VCOVDET1 - VCO Voltage Detector bit 1

#define VCOVDET1_BIT 7

#define VCOVDET1_MASK 128

EEPROM

DEEAR - EERPOM Address Register

sfrb DEEAR = $1E;

BA0 - EEPROM Byte Address bit 0

#define BA0_BIT 0

#define BA0_MASK 1

BA1 - EEPROM Byte Address bit 1

#define BA1_BIT 1

#define BA1_MASK 2

BA2 - EEPROM Byte Address bit 2

#define BA2_BIT 2

#define BA2_MASK 4

PA3 - EEPROM Page Address bit 3

#define PA3_BIT 3

#define PA3_MASK 8

PA4 - EEPROM Page Address bit 4

#define PA4_BIT 4

#define PA4_MASK 16

PA5 - EEPROM Page Address bit 5

#define PA5_BIT 5

#define PA5_MASK 32

PA6 - EEPROM Page Address bit 6

#define PA6_BIT 6

#define PA6_MASK 64

DEEDR - EEPROM Data Register

sfrb DEEDR = $1D;

ED0 - EEPROM Data Register bit 0

#define ED0_BIT 0

#define ED0_MASK 1

ED1 - EEPROM Data Register bit 1

#define ED1_BIT 1

#define ED1_MASK 2

ED2 - EEPROM Data Register bit 2

#define ED2_BIT 2

#define ED2_MASK 4

ED3 - EEPROM Data Register bit 3

#define ED3_BIT 3

#define ED3_MASK 8

ED4 - EEPROM Data Register bit 4

#define ED4_BIT 4

#define ED4_MASK 16

ED5 - EEPROM Data Register bit 5

#define ED5_BIT 5

#define ED5_MASK 32

ED6 - EEPROM Data Register bit 6

#define ED6_BIT 6

#define ED6_MASK 64

ED7 - EEPROM Data Register bit 7

#define ED7_BIT 7

#define ED7_MASK 128

DEECR - EEPROM Control Register

sfrb DEECR = $1C;

EER - EEPROM Read Bit

#define EER_BIT 0

#define EER_MASK 1

EEL - EEPROM Load Bit

#define EEL_BIT 1

#define EEL_MASK 2

EEU - EEPROM Unlock Bit

#define EEU_BIT 2

#define EEU_MASK 4

BSY - EERPOM Busy Bit

#define BSY_BIT 3

#define BSY_MASK 8

WATCHDOG

WDTCR - Watchdog Timer Control Register

sfrb WDTCR = $22;

WDP0 - Watch Dog Timer Prescaler bit 0

#define WDP0_BIT 0

#define WDP0_MASK 1

WDP1 - Watch Dog Timer Prescaler bit 1

#define WDP1_BIT 1

#define WDP1_MASK 2

WDP2 - Watch Dog Timer Prescaler bit 2

#define WDP2_BIT 2

#define WDP2_MASK 4

WDE - Watch Dog Enable

#define WDE_BIT 3

#define WDE_MASK 8

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog

WDTOE - RW

#define WDTOE_BIT 4

#define WDTOE_MASK 16

This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.

TIMER COUNTER 0

BTCNT - Timer Count register

sfrb BTCNT = $20;

C0 - Timer Count Register bit 7

#define C0_BIT 0

#define C0_MASK 1

C1 - Timer Count Register bit 7

#define C1_BIT 1

#define C1_MASK 2

C2 - Timer Count Register bit 7

#define C2_BIT 2

#define C2_MASK 4

C3 - Timer Count Register bit 7

#define C3_BIT 3

#define C3_MASK 8

C4 - Timer Count Register bit 7

#define C4_BIT 4

#define C4_MASK 16

C5 - Timer Count Register bit 7

#define C5_BIT 5

#define C5_MASK 32

C6 - Timer Count Register bit 7

#define C6_BIT 6

#define C6_MASK 64

C7 - Timer Count Register bit 7

#define C7_BIT 7

#define C7_MASK 128

BTCR - Bit Timer Counter Control Register

sfrb BTCR = $21;

F0 - Flag 0

#define F0_BIT 0

#define F0_MASK 1

DATA - Data Bit

#define DATA_BIT 1

#define DATA_MASK 2

F2 - Flag 2

#define F2_BIT 2

#define F2_MASK 4

IE - Interrupt Enable

#define IE_BIT 3

#define IE_MASK 8

M0 - Bit Timer Mode bit 0

#define M0_BIT 4

#define M0_MASK 16

M1 - Bit Timer Mode bit 1

#define M1_BIT 5

#define M1_MASK 32

C8 - Timer Count Register bit 8

#define C8_BIT 6

#define C8_MASK 64

C9 - Timer Count Register bit 9

#define C9_BIT 7

#define C9_MASK 128

PORT

IO_ENAB - I/O Enable Register

sfrb IO_ENAB = $30;

IOE0 - I/O Enable bit 0

#define IOE0_BIT 0

#define IOE0_MASK 1

IOE1 - I/O Enable bit 1

#define IOE1_BIT 1

#define IOE1_MASK 2

IOE2 - I/O Enable bit 2

#define IOE2_BIT 2

#define IOE2_MASK 4

IOE3 - I/O Enable bit 3

#define IOE3_BIT 3

#define IOE3_MASK 8

IOE4 - I/O Enable bit 4

#define IOE4_BIT 4

#define IOE4_MASK 16

IOE5 - I/O Enable bit 5

#define IOE5_BIT 5

#define IOE5_MASK 32

IO_DATOUT - I/O Data Out Register

sfrb IO_DATOUT = $31;

IOO0 - I/O Data Out Register bit 0

#define IOO0_BIT 0

#define IOO0_MASK 1

IOO1 - I/O Data Out Register bit 1

#define IOO1_BIT 1

#define IOO1_MASK 2

IOO2 - I/O Data Out Register bit 2

#define IOO2_BIT 2

#define IOO2_MASK 4

IOO3 - I/O Data Out Register bit 3

#define IOO3_BIT 3

#define IOO3_MASK 8

IOO4 - I/O Data Out Register bit 4

#define IOO4_BIT 4

#define IOO4_MASK 16

IOO5 - I/O Data Out Register bit 5

#define IOO5_BIT 5

#define IOO5_MASK 32

IO_DATIN - I/O Data In register

sfrb IO_DATIN = $32;

IOI0 - I/O Data In Register bit 0

#define IOI0_BIT 0

#define IOI0_MASK 1

IOI1 - I/O Data In Register bit 1

#define IOI1_BIT 1

#define IOI1_MASK 2

IOI2 - I/O Data In Register bit 2

#define IOI2_BIT 2

#define IOI2_MASK 4

IOI3 - I/O Data In Register bit 3

#define IOI3_BIT 3

#define IOI3_MASK 8

IOI4 - I/O Data In Register bit 4

#define IOI4_BIT 4

#define IOI4_MASK 16

IOI5 - I/O Data In Register bit 5

#define IOI5_BIT 5

#define IOI5_MASK 32

CPU

SREG - Status Register

sfrb SREG = $3F;

SPH - Stack Pointer High

sfrb SPH = $3E;

SP8 - Stack pointer bit 8

#define SP8_BIT 0

#define SP8_MASK 1

SP9 - Stack pointer bit 9

#define SP9_BIT 1

#define SP9_MASK 2

SP10 - Stack pointer bit 10

#define SP10_BIT 2

#define SP10_MASK 4

SPL - Stack Pointer Low

sfrb SPL = $3D;

SP0 - Stack pointer bit 0

#define SP0_BIT 0

#define SP0_MASK 1

SP1 - Stack pointer bit 1

#define SP1_BIT 1

#define SP1_MASK 2

SP2 - Stack pointer bit 2

#define SP2_BIT 2

#define SP2_MASK 4

SP3 - Stack pointer bit 3

#define SP3_BIT 3

#define SP3_MASK 8

SP4

#define SP4_BIT 4

#define SP4_MASK 16

SP5 - Stack pointer bit 5

#define SP5_BIT 5

#define SP5_MASK 32

SP6 - Stack pointer bit 6

#define SP6_BIT 6

#define SP6_MASK 64

SP7 - Stack pointer bit 7

#define SP7_BIT 7

#define SP7_MASK 128

AVR_CONFIG - AVR Configuration Register

sfrb AVR_CONFIG = $33;

BBM - Button Boot Mode

#define BBM_BIT 0

#define BBM_MASK 1

SLEEP - Sleep Bit

#define SLEEP_BIT 1

#define SLEEP_MASK 2

BLI - Battery Low Indicator

#define BLI_BIT 2

#define BLI_MASK 4

BD - Battery Dead

#define BD_BIT 3

#define BD_MASK 8

TM

#define TM_BIT 4

#define TM_MASK 16

ACS0 - AVR System Clock Select bit 0

#define ACS0_BIT 5

#define ACS0_MASK 32

ACS1 - AVR System Clock Select bit 1

#define ACS1_BIT 6

#define ACS1_MASK 64

B_DET - Button Detect Register

sfrb B_DET = $34;

BD0 - Button Detect bit 0

#define BD0_BIT 0

#define BD0_MASK 1

BD1 - Button Detect bit 1

#define BD1_BIT 1

#define BD1_MASK 2

BD2 - Button Detect bit 2

#define BD2_BIT 2

#define BD2_MASK 4

BD3 - Button Detect bit 3

#define BD3_BIT 3

#define BD3_MASK 8

BD4

#define BD4_BIT 4

#define BD4_MASK 16

BD5 - Button Detect bit 5

#define BD5_BIT 5

#define BD5_MASK 32

BL_CONFIG - Battery Low Configuration Register

sfrb BL_CONFIG = $35;

BL0 - Battery Low Detection Level bit 0

#define BL0_BIT 0

#define BL0_MASK 1

BL1 - Battery Low Detection Level bit 1

#define BL1_BIT 1

#define BL1_MASK 2

BL2 - Battery Low Detection Level bit 2

#define BL2_BIT 2

#define BL2_MASK 4

BL3 - Battery Low Detection Level bit 3

#define BL3_BIT 3

#define BL3_MASK 8

BL4

#define BL4_BIT 4

#define BL4_MASK 16

BL5 - Battery Low Detection Level bit 5

#define BL5_BIT 5

#define BL5_MASK 32

BLV - Battery Low Valid

#define BLV_BIT 6

#define BLV_MASK 64

BL - Battery Low

#define BL_BIT 7

#define BL_MASK 128