This documentation was generated automatically from the AVR Studio part description file `ATtiny26.pdf`.

## AD CONVERTER

AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode Noise

### ADMUX - The ADC multiplexer Selection Register

`sfrb ADMUX = $07;`

##### MUX0 - Analog Channel and Gain Selection Bits

`#define MUX0_BIT 0`

`#define MUX0_MASK 1`

The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).

##### MUX1 - Analog Channel and Gain Selection Bits

`#define MUX1_BIT 1`

`#define MUX1_MASK 2`

The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).

##### MUX2 - Analog Channel and Gain Selection Bits

`#define MUX2_BIT 2`

`#define MUX2_MASK 4`

The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).

##### MUX3 - Analog Channel and Gain Selection Bits

`#define MUX3_BIT 3`

`#define MUX3_MASK 8`

The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).

##### MUX4 - Analog Channel and Gain Selection Bits

`#define MUX4_BIT 4`

`#define MUX4_MASK 16`

The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).

##### ADLAR - Left Adjust Result

`#define ADLAR_BIT 5`

`#define ADLAR_MASK 32`

The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see ?The ADC Data Register -ADCL and ADCH? on page 198.

##### REFS0 - Reference Selection Bit 0

`#define REFS0_BIT 6`

`#define REFS0_MASK 64`

These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.

##### REFS1 - Reference Selection Bit 1

`#define REFS1_BIT 7`

`#define REFS1_MASK 128`

These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.

### ADCSR - The ADC Control and Status register

`sfrb ADCSR = $06;`

##### ADPS0 - ADC Prescaler Select Bits

`#define ADPS0_BIT 0`

`#define ADPS0_MASK 1`

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

##### ADPS1 - ADC Prescaler Select Bits

`#define ADPS1_BIT 1`

`#define ADPS1_MASK 2`

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

##### ADPS2 - ADC Prescaler Select Bits

`#define ADPS2_BIT 2`

`#define ADPS2_MASK 4`

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

##### ADIE - ADC Interrupt Enable

`#define ADIE_BIT 3`

`#define ADIE_MASK 8`

When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.

##### ADIF - ADC Interrupt Flag

`#define ADIF_BIT 4`

`#define ADIF_MASK 16`

This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.

##### ADFR - ADC Free Running Select

`#define ADFR_BIT 5`

`#define ADFR_MASK 32`

When this bit is set (one) the ADC operates in Free Running Mode. In this mode, the ADC samples and updates the data registers continuously. Clearing this bit (zero) will terminate Free Running Mode.

##### ADSC - ADC Start Conversion

`#define ADSC_BIT 6`

`#define ADSC_MASK 64`

In Single Conversion Mode, a logical ?1? must be written to this bit to start each conversion. In Free Running Mode, a logical ?1? must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect

##### ADEN - ADC Enable

`#define ADEN_BIT 7`

`#define ADEN_MASK 128`

Writing a logical ?1? to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.

### ADCH - ADC Data Register High Byte

`sfrb ADCH = $05;`

##### ADCH0 - ADC Data Register High Byte Bit 0

`#define ADCH0_BIT 0`

`#define ADCH0_MASK 1`

##### ADCH1 - ADC Data Register High Byte Bit 1

`#define ADCH1_BIT 1`

`#define ADCH1_MASK 2`

##### ADCH2 - ADC Data Register High Byte Bit 2

`#define ADCH2_BIT 2`

`#define ADCH2_MASK 4`

##### ADCH3 - ADC Data Register High Byte Bit 3

`#define ADCH3_BIT 3`

`#define ADCH3_MASK 8`

##### ADCH4 - ADC Data Register High Byte Bit 4

`#define ADCH4_BIT 4`

`#define ADCH4_MASK 16`

##### ADCH5 - ADC Data Register High Byte Bit 5

`#define ADCH5_BIT 5`

`#define ADCH5_MASK 32`

##### ADCH6 - ADC Data Register High Byte Bit 6

`#define ADCH6_BIT 6`

`#define ADCH6_MASK 64`

##### ADCH7 - ADC Data Register High Byte Bit 7

`#define ADCH7_BIT 7`

`#define ADCH7_MASK 128`

### ADCL - ADC Data Register Low Byte

`sfrb ADCL = $04;`

##### ADCL0 - ADC Data Register Low Byte Bit 0

`#define ADCL0_BIT 0`

`#define ADCL0_MASK 1`

##### ADCL1 - ADC Data Register Low Byte Bit 1

`#define ADCL1_BIT 1`

`#define ADCL1_MASK 2`

##### ADCL2 - ADC Data Register Low Byte Bit 2

`#define ADCL2_BIT 2`

`#define ADCL2_MASK 4`

##### ADCL3 - ADC Data Register Low Byte Bit 3

`#define ADCL3_BIT 3`

`#define ADCL3_MASK 8`

##### ADCL4 - ADC Data Register Low Byte Bit 4

`#define ADCL4_BIT 4`

`#define ADCL4_MASK 16`

##### ADCL5 - ADC Data Register Low Byte Bit 5

`#define ADCL5_BIT 5`

`#define ADCL5_MASK 32`

##### ADCL6 - ADC Data Register Low Byte Bit 6

`#define ADCL6_BIT 6`

`#define ADCL6_MASK 64`

##### ADCL7 - ADC Data Register Low Byte Bit 7

`#define ADCL7_BIT 7`

`#define ADCL7_MASK 128`

## ANALOG COMPARATOR

### ACSR - Analog Comparator Control And Status Register

`sfrb ACSR = $08;`

##### ACIS0 - Analog Comparator Interrupt Mode Select bit 0

`#define ACIS0_BIT 0`

`#define ACIS0_MASK 1`

These bits determine which comparator events that trigger the Analog Comparator interrupt.

##### ACIS1 - Analog Comparator Interrupt Mode Select bit 1

`#define ACIS1_BIT 1`

`#define ACIS1_MASK 2`

These bits determine which comparator events that trigger the Analog Comparator interrupt.

##### ACME - Analog Comparator Multiplexer Enable

`#define ACME_BIT 2`

`#define ACME_MASK 4`

When the ACME bit is set (one) and the ADC is switched off (ADEN in ADCSR is zero), MUX3...0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in the table in the datasheet. If ACME is cleared (zero) or ADEN is set (one), PA7(AIN1) is applied to the negative input to the Analog Comparator.

##### ACIE - Analog Comparator Interrupt Enable

`#define ACIE_BIT 3`

`#define ACIE_MASK 8`

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.

##### ACI - Analog Comparator Interrupt Flag

`#define ACI_BIT 4`

`#define ACI_MASK 16`

This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

##### ACO - Analog Compare Output

`#define ACO_BIT 5`

`#define ACO_MASK 32`

The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.

##### ACBG - Analog Comparator Bandgap Select

`#define ACBG_BIT 6`

`#define ACBG_MASK 64`

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See ?Internal Voltage Reference? on page 42.

##### ACD - Analog Comparator Disable

`#define ACD_BIT 7`

`#define ACD_MASK 128`

When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

## USI

Universal Serial Interface

### USIDR - USI Data Register

`sfrb USIDR = $0F;`

##### USIDR0 - USI Data Register bit 0

`#define USIDR0_BIT 0`

`#define USIDR0_MASK 1`

##### USIDR1 - USI Data Register bit 1

`#define USIDR1_BIT 1`

`#define USIDR1_MASK 2`

##### USIDR2 - USI Data Register bit 2

`#define USIDR2_BIT 2`

`#define USIDR2_MASK 4`

##### USIDR3 - USI Data Register bit 3

`#define USIDR3_BIT 3`

`#define USIDR3_MASK 8`

##### USIDR4 - USI Data Register bit 4

`#define USIDR4_BIT 4`

`#define USIDR4_MASK 16`

##### USIDR5 - USI Data Register bit 5

`#define USIDR5_BIT 5`

`#define USIDR5_MASK 32`

##### USIDR6 - USI Data Register bit 6

`#define USIDR6_BIT 6`

`#define USIDR6_MASK 64`

##### USIDR7 - USI Data Register bit 7

`#define USIDR7_BIT 7`

`#define USIDR7_MASK 128`

### USISR - USI Status Register

`sfrb USISR = $0E;`

##### USICNT0 - USI Counter Value Bit 0

`#define USICNT0_BIT 0`

`#define USICNT0_MASK 1`

##### USICNT1 - USI Counter Value Bit 1

`#define USICNT1_BIT 1`

`#define USICNT1_MASK 2`

##### USICNT2 - USI Counter Value Bit 2

`#define USICNT2_BIT 2`

`#define USICNT2_MASK 4`

##### USICNT3 - USI Counter Value Bit 3

`#define USICNT3_BIT 3`

`#define USICNT3_MASK 8`

##### USIDC - Data Output Collision

`#define USIDC_BIT 4`

`#define USIDC_MASK 16`

##### USIPF - Stop Condition Flag

`#define USIPF_BIT 5`

`#define USIPF_MASK 32`

##### USIOIF - Counter Overflow Interrupt Flag

`#define USIOIF_BIT 6`

`#define USIOIF_MASK 64`

##### USISIF - Start Condition Interrupt Flag

`#define USISIF_BIT 7`

`#define USISIF_MASK 128`

### USICR - USI Control Register

`sfrb USICR = $0D;`

##### USITC - Toggle Clock Port Pin

`#define USITC_BIT 0`

`#define USITC_MASK 1`

##### USICLK - Clock Strobe

`#define USICLK_BIT 1`

`#define USICLK_MASK 2`

##### USICS0 - USI Clock Source Select Bit 0

`#define USICS0_BIT 2`

`#define USICS0_MASK 4`

##### USICS1 - USI Clock Source Select Bit 1

`#define USICS1_BIT 3`

`#define USICS1_MASK 8`

##### USIWM0 - USI Wire Mode Bit 0

`#define USIWM0_BIT 4`

`#define USIWM0_MASK 16`

##### USIWM1 - USI Wire Mode Bit 1

`#define USIWM1_BIT 5`

`#define USIWM1_MASK 32`

##### USIOIE - Counter Overflow Interrupt Enable

`#define USIOIE_BIT 6`

`#define USIOIE_MASK 64`

##### USISIE - Start Condition Interrupt Enable

`#define USISIE_BIT 7`

`#define USISIE_MASK 128`

## PORTA

### PORTA - Port A Data Register

`sfrb PORTA = $1B;`

##### PORTA0 - Port A Data Register bit 0

`#define PORTA0_BIT 0`

`#define PORTA0_MASK 1`

##### PORTA1 - Port A Data Register bit 1

`#define PORTA1_BIT 1`

`#define PORTA1_MASK 2`

##### PORTA2 - Port A Data Register bit 2

`#define PORTA2_BIT 2`

`#define PORTA2_MASK 4`

##### PORTA3 - Port A Data Register bit 3

`#define PORTA3_BIT 3`

`#define PORTA3_MASK 8`

##### PORTA4 - Port A Data Register bit 4

`#define PORTA4_BIT 4`

`#define PORTA4_MASK 16`

##### PORTA5 - Port A Data Register bit 5

`#define PORTA5_BIT 5`

`#define PORTA5_MASK 32`

##### PORTA6 - Port A Data Register bit 6

`#define PORTA6_BIT 6`

`#define PORTA6_MASK 64`

##### PORTA7 - Port A Data Register bit 7

`#define PORTA7_BIT 7`

`#define PORTA7_MASK 128`

### DDRA - Port A Data Direction Register

`sfrb DDRA = $1A;`

##### DDA0 - Data Direction Register, Port A, bit 0

`#define DDA0_BIT 0`

`#define DDA0_MASK 1`

##### DDA1 - Data Direction Register, Port A, bit 1

`#define DDA1_BIT 1`

`#define DDA1_MASK 2`

##### DDA2 - Data Direction Register, Port A, bit 2

`#define DDA2_BIT 2`

`#define DDA2_MASK 4`

##### DDA3 - Data Direction Register, Port A, bit 3

`#define DDA3_BIT 3`

`#define DDA3_MASK 8`

##### DDA4 - Data Direction Register, Port A, bit 4

`#define DDA4_BIT 4`

`#define DDA4_MASK 16`

##### DDA5 - Data Direction Register, Port A, bit 5

`#define DDA5_BIT 5`

`#define DDA5_MASK 32`

##### DDA6 - Data Direction Register, Port A, bit 6

`#define DDA6_BIT 6`

`#define DDA6_MASK 64`

##### DDA7 - Data Direction Register, Port A, bit 7

`#define DDA7_BIT 7`

`#define DDA7_MASK 128`

### PINA - Port A Input Pins

`sfrb PINA = $19;`

##### PINA0 - Input Pins, Port A bit 0

`#define PINA0_BIT 0`

`#define PINA0_MASK 1`

##### PINA1 - Input Pins, Port A bit 1

`#define PINA1_BIT 1`

`#define PINA1_MASK 2`

##### PINA2 - Input Pins, Port A bit 2

`#define PINA2_BIT 2`

`#define PINA2_MASK 4`

##### PINA3 - Input Pins, Port A bit 3

`#define PINA3_BIT 3`

`#define PINA3_MASK 8`

##### PINA4 - Input Pins, Port A bit 4

`#define PINA4_BIT 4`

`#define PINA4_MASK 16`

##### PINA5 - Input Pins, Port A bit 5

`#define PINA5_BIT 5`

`#define PINA5_MASK 32`

##### PINA6 - Input Pins, Port A bit 6

`#define PINA6_BIT 6`

`#define PINA6_MASK 64`

##### PINA7 - Input Pins, Port A bit 7

`#define PINA7_BIT 7`

`#define PINA7_MASK 128`

## PORTB

### PORTB - Port B Data Register

`sfrb PORTB = $18;`

##### PORTB0 - Port B Data Register bit 0

`#define PORTB0_BIT 0`

`#define PORTB0_MASK 1`

##### PORTB1 - Port B Data Register bit 1

`#define PORTB1_BIT 1`

`#define PORTB1_MASK 2`

##### PORTB2 - Port B Data Register bit 2

`#define PORTB2_BIT 2`

`#define PORTB2_MASK 4`

##### PORTB3 - Port B Data Register bit 3

`#define PORTB3_BIT 3`

`#define PORTB3_MASK 8`

##### PORTB4 - Port B Data Register bit 4

`#define PORTB4_BIT 4`

`#define PORTB4_MASK 16`

##### PORTB5 - Port B Data Register bit 5

`#define PORTB5_BIT 5`

`#define PORTB5_MASK 32`

##### PORTB6 - Port B Data Register bit 6

`#define PORTB6_BIT 6`

`#define PORTB6_MASK 64`

##### PORTB7 - Port B Data Register bit 7

`#define PORTB7_BIT 7`

`#define PORTB7_MASK 128`

### DDRB - Port B Data Direction Register

`sfrb DDRB = $17;`

##### DDB0 - Port B Data Direction Register bit 0

`#define DDB0_BIT 0`

`#define DDB0_MASK 1`

##### DDB1 - Port B Data Direction Register bit 1

`#define DDB1_BIT 1`

`#define DDB1_MASK 2`

##### DDB2 - Port B Data Direction Register bit 2

`#define DDB2_BIT 2`

`#define DDB2_MASK 4`

##### DDB3 - Port B Data Direction Register bit 3

`#define DDB3_BIT 3`

`#define DDB3_MASK 8`

##### DDB4 - Port B Data Direction Register bit 4

`#define DDB4_BIT 4`

`#define DDB4_MASK 16`

##### DDB5 - Port B Data Direction Register bit 5

`#define DDB5_BIT 5`

`#define DDB5_MASK 32`

##### DDB6 - Port B Data Direction Register bit 6

`#define DDB6_BIT 6`

`#define DDB6_MASK 64`

##### DDB7 - Port B Data Direction Register bit 7

`#define DDB7_BIT 7`

`#define DDB7_MASK 128`

### PINB - Port B Input Pins

`sfrb PINB = $16;`

##### PINB0 - Port B Input Pins bit 0

`#define PINB0_BIT 0`

`#define PINB0_MASK 1`

##### PINB1 - Port B Input Pins bit 1

`#define PINB1_BIT 1`

`#define PINB1_MASK 2`

##### PINB2 - Port B Input Pins bit 2

`#define PINB2_BIT 2`

`#define PINB2_MASK 4`

##### PINB3 - Port B Input Pins bit 3

`#define PINB3_BIT 3`

`#define PINB3_MASK 8`

##### PINB4 - Port B Input Pins bit 4

`#define PINB4_BIT 4`

`#define PINB4_MASK 16`

##### PINB5 - Port B Input Pins bit 5

`#define PINB5_BIT 5`

`#define PINB5_MASK 32`

##### PINB6 - Port B Input Pins bit 6

`#define PINB6_BIT 6`

`#define PINB6_MASK 64`

##### PINB7 - Port B Input Pins bit 7

`#define PINB7_BIT 7`

`#define PINB7_MASK 128`

## EEPROM

### EEAR - EEPROM Read/Write Access

`sfrb EEAR = $1E;`

##### EEAR0 - EEPROM Read/Write Access bit 0

`#define EEAR0_BIT 0`

`#define EEAR0_MASK 1`

##### EEAR1 - EEPROM Read/Write Access bit 1

`#define EEAR1_BIT 1`

`#define EEAR1_MASK 2`

##### EEAR2 - EEPROM Read/Write Access bit 2

`#define EEAR2_BIT 2`

`#define EEAR2_MASK 4`

##### EEAR3 - EEPROM Read/Write Access bit 3

`#define EEAR3_BIT 3`

`#define EEAR3_MASK 8`

##### EEAR4 - EEPROM Read/Write Access bit 4

`#define EEAR4_BIT 4`

`#define EEAR4_MASK 16`

##### EEAR5 - EEPROM Read/Write Access bit 5

`#define EEAR5_BIT 5`

`#define EEAR5_MASK 32`

##### EEAR6 - EEPROM Read/Write Access bit 6

`#define EEAR6_BIT 6`

`#define EEAR6_MASK 64`

### EEDR - EEPROM Data Register

`sfrb EEDR = $1D;`

##### EEDR0 - EEPROM Data Register bit 0

`#define EEDR0_BIT 0`

`#define EEDR0_MASK 1`

##### EEDR1 - EEPROM Data Register bit 1

`#define EEDR1_BIT 1`

`#define EEDR1_MASK 2`

##### EEDR2 - EEPROM Data Register bit 2

`#define EEDR2_BIT 2`

`#define EEDR2_MASK 4`

##### EEDR3 - EEPROM Data Register bit 3

`#define EEDR3_BIT 3`

`#define EEDR3_MASK 8`

##### EEDR4 - EEPROM Data Register bit 4

`#define EEDR4_BIT 4`

`#define EEDR4_MASK 16`

##### EEDR5 - EEPROM Data Register bit 5

`#define EEDR5_BIT 5`

`#define EEDR5_MASK 32`

##### EEDR6 - EEPROM Data Register bit 6

`#define EEDR6_BIT 6`

`#define EEDR6_MASK 64`

##### EEDR7 - EEPROM Data Register bit 7

`#define EEDR7_BIT 7`

`#define EEDR7_MASK 128`

### EECR - EEPROM Control Register

`sfrb EECR = $1C;`

##### EERE - EEPROM Read Enable

`#define EERE_BIT 0`

`#define EERE_MASK 1`

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined.

##### EEWE - EEPROM Write Enable

`#define EEWE_BIT 1`

`#define EEWE_MASK 2`

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one to the EEMWE bit, the EEWE bit mustbewritten to zero in thesamecycle). 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at V CC =5Vor 4msatV CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted or two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems.

##### EEMWE - EEPROM Master Write Enable

`#define EEMWE_BIT 2`

`#define EEMWE_MASK 4`

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure.

##### EERIE - EEProm Ready Interrupt Enable

`#define EERIE_BIT 3`

`#define EERIE_MASK 8`

When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero).

## WATCHDOG

### WDTCR - Watchdog Timer Control Register

`sfrb WDTCR = $21;`

##### WDP0 - Watch Dog Timer Prescaler bit 0

`#define WDP0_BIT 0`

`#define WDP0_MASK 1`

The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.

##### WDP1 - Watch Dog Timer Prescaler bit 1

`#define WDP1_BIT 1`

`#define WDP1_MASK 2`

The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.

##### WDP2 - Watch Dog Timer Prescaler bit 2

`#define WDP2_BIT 2`

`#define WDP2_MASK 4`

The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.

##### WDE - Watch Dog Enable

`#define WDE_BIT 3`

`#define WDE_MASK 8`

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog

##### WDCE - Watchdog Change Enable

`#define WDCE_BIT 4`

`#define WDCE_MASK 16`

This bit must be set when the WDE bit is written to logic zero.Otherwise,the watchdog will not be disabled.Once written to one,hardware will clear this bit after four clock cycles.Refer to the description of the WDE bit for a watchdog disable procedure.This bit must also be set when changing the prescaler bits.

## CPU

### SREG - Status Register

`sfrb SREG = $3F;`

### SP - Stack Pointer

`sfrb SP = $3D;`

##### SP0 - Stack Pointer Bit 0

`#define SP0_BIT 0`

`#define SP0_MASK 1`

##### SP1 - Stack Pointer Bit 1

`#define SP1_BIT 1`

`#define SP1_MASK 2`

##### SP2 - Stack Pointer Bit 2

`#define SP2_BIT 2`

`#define SP2_MASK 4`

##### SP3 - Stack Pointer Bit 3

`#define SP3_BIT 3`

`#define SP3_MASK 8`

##### SP4

`#define SP4_BIT 4`

`#define SP4_MASK 16`

##### SP5 - Stack Pointer Bit 5

`#define SP5_BIT 5`

`#define SP5_MASK 32`

##### SP6 - Stack Pointer Bit 6

`#define SP6_BIT 6`

`#define SP6_MASK 64`

##### SP7 - Stack Pointer Bit 7

`#define SP7_BIT 7`

`#define SP7_MASK 128`

### MCUCR - MCU Control Register

`sfrb MCUCR = $35;`

##### ISC00 - Interrupt Sense Control 0 bit 0

`#define ISC00_BIT 0`

`#define ISC00_MASK 1`

##### ISC01 - Interrupt Sense Control 0 bit 1

`#define ISC01_BIT 1`

`#define ISC01_MASK 2`

##### SM0 - Sleep Mode Select Bit 0

`#define SM0_BIT 3`

`#define SM0_MASK 8`

##### SM1 - Sleep Mode Select Bit 1

`#define SM1_BIT 4`

`#define SM1_MASK 16`

##### SE - Sleep Enable

`#define SE_BIT 5`

`#define SE_MASK 32`

The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.

##### PUD - Pull-up Disable

`#define PUD_BIT 6`

`#define PUD_MASK 64`

### MCUSR - MCU Status register

`sfrb MCUSR = $34;`

##### PORF - Power-On Reset Flag

`#define PORF_BIT 0`

`#define PORF_MASK 1`

This bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchanged

##### EXTRF - External Reset Flag

`#define EXTRF_BIT 1`

`#define EXTRF_MASK 2`

After a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged.

##### BORF - Brown-out Reset Flag

`#define BORF_BIT 2`

`#define BORF_MASK 4`

##### WDRF - Watchdog Reset Flag

`#define WDRF_BIT 3`

`#define WDRF_MASK 8`

### OSCCAL - Status Register

`sfrb OSCCAL = $31;`

##### CAL0 - Oscillator Calibration Value Bit 0

`#define CAL0_BIT 0`

`#define CAL0_MASK 1`

##### CAL1 - Oscillator Calibration Value Bit 1

`#define CAL1_BIT 1`

`#define CAL1_MASK 2`

##### CAL2 - Oscillator Calibration Value Bit 2

`#define CAL2_BIT 2`

`#define CAL2_MASK 4`

##### CAL3 - Oscillator Calibration Value Bit 3

`#define CAL3_BIT 3`

`#define CAL3_MASK 8`

##### CAL4

`#define CAL4_BIT 4`

`#define CAL4_MASK 16`

##### CAL5 - Oscillator Calibration Value Bit 5

`#define CAL5_BIT 5`

`#define CAL5_MASK 32`

##### CAL6 - Oscillator Calibration Value Bit 6

`#define CAL6_BIT 6`

`#define CAL6_MASK 64`

##### CAL7 - Oscillator Calibration Value Bit 7

`#define CAL7_BIT 7`

`#define CAL7_MASK 128`

## TIMER COUNTER 0

The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in ?Timer/Counter0 Control Register - TCCR0? on page 35. The overflow status flag is found in ?The Timer/Counter Interrupt Flag Register - TIFR? on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in ?The Timer/Counter Interrupt Mask Regis-ter - TIMSK? on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions

### TIMSK - Timer/Counter Interrupt Mask Register

`sfrb TIMSK = $39;`

##### TOIE0 - Timer/Counter0 Overflow Interrupt Enable

`#define TOIE0_BIT 1`

`#define TOIE0_MASK 2`

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

### TIFR - Timer/Counter Interrupt Flag register

`sfrb TIFR = $38;`

##### TOV0 - Timer/Counter0 Overflow Flag

`#define TOV0_BIT 1`

`#define TOV0_MASK 2`

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.

### TCCR0 - Timer/Counter0 Control Register

`sfrb TCCR0 = $33;`

##### CS00 - Clock Select0 bit 0

`#define CS00_BIT 0`

`#define CS00_MASK 1`

##### CS01 - Clock Select0 bit 1

`#define CS01_BIT 1`

`#define CS01_MASK 2`

##### CS02 - Clock Select0 bit 2

`#define CS02_BIT 2`

`#define CS02_MASK 4`

##### PSR0 - Prescaler Reset Timer/Counter0

`#define PSR0_BIT 3`

`#define PSR0_MASK 8`

When this bit is set (one), the prescaler of the Timer/Counter0 will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always be read as zero.

### TCNT0 - Timer Counter 0

`sfrb TCNT0 = $32;`

##### TCNT00 - Timer Counter 0 bit 0

`#define TCNT00_BIT 0`

`#define TCNT00_MASK 1`

##### TCNT01 - Timer Counter 0 bit 1

`#define TCNT01_BIT 1`

`#define TCNT01_MASK 2`

##### TCNT02 - Timer Counter 0 bit 2

`#define TCNT02_BIT 2`

`#define TCNT02_MASK 4`

##### TCNT03 - Timer Counter 0 bit 3

`#define TCNT03_BIT 3`

`#define TCNT03_MASK 8`

##### TCNT04 - Timer Counter 0 bit 4

`#define TCNT04_BIT 4`

`#define TCNT04_MASK 16`

##### TCNT05 - Timer Counter 0 bit 5

`#define TCNT05_BIT 5`

`#define TCNT05_MASK 32`

##### TCNT06 - Timer Counter 0 bit 6

`#define TCNT06_BIT 6`

`#define TCNT06_MASK 64`

##### TCNT07 - Timer Counter 0 bit 7

`#define TCNT07_BIT 7`

`#define TCNT07_MASK 128`

## TIMER COUNTER 1

### TCCR1A - Timer/Counter Control Register A

`sfrb TCCR1A = $30;`

##### PWM1B - Pulse Width Modulator B Enable

`#define PWM1B_BIT 0`

`#define PWM1B_MASK 1`

When set (one) this bit enables PWM mode based on comparator OCR1B in Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value.

##### PWM1A - Pulse Width Modulator A Enable

`#define PWM1A_BIT 1`

`#define PWM1A_MASK 2`

When set (one) this bit enables PWM mode based on comparator OCR1A in Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value.

##### FOC1B - Force Output Compare Match 1B

`#define FOC1B_BIT 2`

`#define FOC1B_MASK 4`

Writing a logical one to this bit forces a change in the compare match output pin PB3 (OC1B) according to the values already set in COM1B1 and COM1B0. If COM1B1 and COM1B0 written in the same cycle as FOC1B, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1B1 and COM1B0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1B bit always reads as zero. FOC1B is not in use if PWM1B bit is set

##### FOC1A - Force Output Compare Match 1A

`#define FOC1A_BIT 3`

`#define FOC1A_MASK 8`

Writing a logical one to this bit forces a change in the compare match output pin PB1 (OC1A) according to the values already set in COM1A1 and COM1A0. If COM1A1 and COM1A0 written in the same cycle as FOC1A, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1A1 and COM1A0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1A bit always reads as zero. FOC1A is not in use if PWM1A bit is

##### COM1B0 - Comparator B Output Mode Bit 0

`#define COM1B0_BIT 4`

`#define COM1B0_MASK 16`

The COM1B1 and COM1B0 control bits determine any output pin action following a compare match with compare register B in Timer/Counter1. Output pin actions affect pin PB3 (OC1B). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1B is not connected in normal mode.

##### COM1B1 - Comparator B Output Mode Bit 1

`#define COM1B1_BIT 5`

`#define COM1B1_MASK 32`

The COM1B1 and COM1B0 control bits determine any output pin action following a compare match with compare register B in Timer/Counter1. Output pin actions affect pin PB3 (OC1B). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1B is not connected in normal mode.

##### COM1A0 - Comparator A Output Mode Bit 0

`#define COM1A0_BIT 6`

`#define COM1A0_MASK 64`

The COM1A1 and COM1A0 control bits determine any output pin action following a compare match with compare register A in Timer/Counter1. Output pin actions affect pin PB1 (OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1A is not connected in normal mode.

##### COM1A1 - Comparator A Output Mode Bit 1

`#define COM1A1_BIT 7`

`#define COM1A1_MASK 128`

The COM1A1 and COM1A0 control bits determine any output pin action following a compare match with compare register A in Timer/Counter1. Output pin actions affect pin PB1 (OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1A is not connected in normal mode.

### TCCR1B - Timer/Counter Control Register B

`sfrb TCCR1B = $2F;`

##### CS10 - Clock Select Bits

`#define CS10_BIT 0`

`#define CS10_MASK 1`

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

##### CS11 - Clock Select Bits

`#define CS11_BIT 1`

`#define CS11_MASK 2`

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

##### CS12 - Clock Select Bits

`#define CS12_BIT 2`

`#define CS12_MASK 4`

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

##### CS13 - Clock Select Bits

`#define CS13_BIT 3`

`#define CS13_MASK 8`

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

##### PSR1 - Prescaler Reset Timer/Counter1

`#define PSR1_BIT 6`

`#define PSR1_MASK 64`

When this bit is set (one), the Timer/Counter prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always read as zero.

##### CTC1 - Clear Timer/Counter on Compare Match

`#define CTC1_BIT 7`

`#define CTC1_MASK 128`

When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value. If the control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match.

### TCNT1 - Timer/Counter Register

`sfrb TCNT1 = $2E;`

##### TCNT1_0 - Timer/Counter Register Bit 0

`#define TCNT1_0_BIT 0`

`#define TCNT1_0_MASK 1`

##### TCNT1_1 - Timer/Counter Register Bit 1

`#define TCNT1_1_BIT 1`

`#define TCNT1_1_MASK 2`

##### TCNT1_2 - Timer/Counter Register Bit 2

`#define TCNT1_2_BIT 2`

`#define TCNT1_2_MASK 4`

##### TCNT1_3 - Timer/Counter Register Bit 3

`#define TCNT1_3_BIT 3`

`#define TCNT1_3_MASK 8`

##### TCNT1_4 - Timer/Counter Register Bit 4

`#define TCNT1_4_BIT 4`

`#define TCNT1_4_MASK 16`

##### TCNT1_5 - Timer/Counter Register Bit 5

`#define TCNT1_5_BIT 5`

`#define TCNT1_5_MASK 32`

##### TCNT1_6 - Timer/Counter Register Bit 6

`#define TCNT1_6_BIT 6`

`#define TCNT1_6_MASK 64`

##### TCNT1_7 - Timer/Counter Register Bit 7

`#define TCNT1_7_BIT 7`

`#define TCNT1_7_MASK 128`

### OCR1A - Output Compare Register

`sfrb OCR1A = $2D;`

##### OCR1A0 - Output Compare Register A Bit 0

`#define OCR1A0_BIT 0`

`#define OCR1A0_MASK 1`

##### OCR1A1 - Output Compare Register A Bit 1

`#define OCR1A1_BIT 1`

`#define OCR1A1_MASK 2`

##### OCR1A2 - Output Compare Register A Bit 2

`#define OCR1A2_BIT 2`

`#define OCR1A2_MASK 4`

##### OCR1A3 - Output Compare Register A Bit 3

`#define OCR1A3_BIT 3`

`#define OCR1A3_MASK 8`

##### OCR1A4 - Output Compare Register A Bit 4

`#define OCR1A4_BIT 4`

`#define OCR1A4_MASK 16`

##### OCR1A5 - Output Compare Register A Bit 5

`#define OCR1A5_BIT 5`

`#define OCR1A5_MASK 32`

##### OCR1A6 - Output Compare Register A Bit 6

`#define OCR1A6_BIT 6`

`#define OCR1A6_MASK 64`

##### OCR1A7 - Output Compare Register A Bit 7

`#define OCR1A7_BIT 7`

`#define OCR1A7_MASK 128`

### OCR1B - Output Compare Register

`sfrb OCR1B = $2C;`

##### OCR1B0 - Output Compare Register B Bit 0

`#define OCR1B0_BIT 0`

`#define OCR1B0_MASK 1`

##### OCR1B1 - Output Compare Register B Bit 1

`#define OCR1B1_BIT 1`

`#define OCR1B1_MASK 2`

##### OCR1B2 - Output Compare Register B Bit 2

`#define OCR1B2_BIT 2`

`#define OCR1B2_MASK 4`

##### OCR1B3 - Output Compare Register B Bit 3

`#define OCR1B3_BIT 3`

`#define OCR1B3_MASK 8`

##### OCR1B4 - Output Compare Register B Bit 4

`#define OCR1B4_BIT 4`

`#define OCR1B4_MASK 16`

##### OCR1B5 - Output Compare Register B Bit 5

`#define OCR1B5_BIT 5`

`#define OCR1B5_MASK 32`

##### OCR1B6 - Output Compare Register B Bit 6

`#define OCR1B6_BIT 6`

`#define OCR1B6_MASK 64`

##### OCR1B7 - Output Compare Register B Bit 7

`#define OCR1B7_BIT 7`

`#define OCR1B7_MASK 128`

### OCR1C - Output Compare Register

`sfrb OCR1C = $2B;`

##### OCR1C0 - Output Compare Register C Bit 0

`#define OCR1C0_BIT 0`

`#define OCR1C0_MASK 1`

##### OCR1C1 - Output Compare Register C Bit 1

`#define OCR1C1_BIT 1`

`#define OCR1C1_MASK 2`

##### OCR1C2 - Output Compare Register C Bit 2

`#define OCR1C2_BIT 2`

`#define OCR1C2_MASK 4`

##### OCR1C3 - Output Compare Register C Bit 3

`#define OCR1C3_BIT 3`

`#define OCR1C3_MASK 8`

##### OCR1C4 - Output Compare Register C Bit 4

`#define OCR1C4_BIT 4`

`#define OCR1C4_MASK 16`

##### OCR1C5 - Output Compare Register C Bit 5

`#define OCR1C5_BIT 5`

`#define OCR1C5_MASK 32`

##### OCR1C6 - Output Compare Register C Bit 6

`#define OCR1C6_BIT 6`

`#define OCR1C6_MASK 64`

##### OCR1C7 - Output Compare Register C Bit 7

`#define OCR1C7_BIT 7`

`#define OCR1C7_MASK 128`

### TIMSK - Timer/Counter Interrupt Mask Register

`sfrb TIMSK = $39;`

##### TOIE1 - Timer/Counter1 Overflow Interrupt Enable

`#define TOIE1_BIT 2`

`#define TOIE1_MASK 4`

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs (i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).

##### OCIE1B - Timer/Counter1 Output Compare Interrupt Enable

`#define OCIE1B_BIT 5`

`#define OCIE1B_MASK 32`

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchB, interrupt is enabled. The corresponding interrupt at vector $004 is executed if a compare matchB occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.

##### OCIE1A - Timer/Counter1 Output Compare Interrupt Enable

`#define OCIE1A_BIT 6`

`#define OCIE1A_MASK 64`

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchA, interrupt is enabled. The corresponding interrupt at vector $003 is executed if a compare matchA occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.

### TIFR - Timer/Counter Interrupt Flag Register

`sfrb TIFR = $38;`

##### TOV1 - Timer/Counter1 Overflow Flag

`#define TOV1_BIT 2`

`#define TOV1_MASK 4`

The bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logical ?1? to the flag. When the SREG I-bit, TOIE1 (Timer/Counter1 Overf low Interrupt Enable) and TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed.

##### OCF1B - Timer/Counter1 Output Compare Flag 1B

`#define OCF1B_BIT 5`

`#define OCF1B_MASK 32`

The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1B ? Output Compare Register 1A. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1B is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1B, and OCF1B are set (one), the Timer/Counter1 B compare match interrupt is executed.

##### OCF1A - Timer/Counter1 Output Compare Flag 1A

`#define OCF1A_BIT 6`

`#define OCF1A_MASK 64`

The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A (Output Compare Register 1A). OCF1A is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logical ?1? to the flag. When the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 compare match A interrupt is executed.

### PLLCSR - PLL Control and Status Register

`sfrb PLLCSR = $29;`

##### PLOCK - PLL Lock Detector

`#define PLOCK_BIT 0`

`#define PLOCK_MASK 1`

##### PLLE - PLL Enable

`#define PLLE_BIT 1`

`#define PLLE_MASK 2`

##### PCKE - PCK Enable

`#define PCKE_BIT 2`

`#define PCKE_MASK 4`

## EXTERNAL INTERRUPT

### GIMSK - General Interrupt Mask Register

`sfrb GIMSK = $3B;`

##### PCIE0 - Pin Change Interrupt Enable 0

`#define PCIE0_BIT 4`

`#define PCIE0_MASK 16`

##### PCIE1 - Pin Change Interrupt Enable 1

`#define PCIE1_BIT 5`

`#define PCIE1_MASK 32`

##### INT0 - External Interrupt Request 0 Enable

`#define INT0_BIT 6`

`#define INT0_MASK 64`

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also ?External Interrupts.? ? Bits 5..0 - Res: Reserved bits

### GIFR - General Interrupt Flag register

`sfrb GIFR = $3A;`

##### PCIF - Pin Change Interrupt Flag

`#define PCIF_BIT 5`

`#define PCIF_MASK 32`

##### INTF0 - External Interrupt Flag 0

`#define INTF0_BIT 6`

`#define INTF0_MASK 64`

When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.