This documentation was generated automatically from the AVR Studio part description file `AT90S2343.pdf`.

## CPU

### SREG - Status Register

`sfrb SREG = $3F;`

### SPL - Stack Pointer Low

`sfrb SPL = $3D;`

##### SP0 - Stack pointer bit 0

`#define SP0_BIT 0`

`#define SP0_MASK 1`

##### SP1 - Stack pointer bit 1

`#define SP1_BIT 1`

`#define SP1_MASK 2`

##### SP2 - Stack pointer bit 2

`#define SP2_BIT 2`

`#define SP2_MASK 4`

##### SP3 - Stack pointer bit 3

`#define SP3_BIT 3`

`#define SP3_MASK 8`

##### SP4

`#define SP4_BIT 4`

`#define SP4_MASK 16`

##### SP5 - Stack pointer bit 5

`#define SP5_BIT 5`

`#define SP5_MASK 32`

##### SP6 - Stack pointer bit 6

`#define SP6_BIT 6`

`#define SP6_MASK 64`

##### SP7 - Stack pointer bit 7

`#define SP7_BIT 7`

`#define SP7_MASK 128`

### MCUCR - MCU Control Register

`sfrb MCUCR = $35;`

##### ISC00 - Interrupt Sense Control 0 bit 0

`#define ISC00_BIT 0`

`#define ISC00_MASK 1`

##### ISC01 - Interrupt Sense Control 0 bit 1

`#define ISC01_BIT 1`

`#define ISC01_MASK 2`

##### SM - Sleep Mode

`#define SM_BIT 4`

`#define SM_MASK 16`

When SM is set (one), Power Down mode is selected as sleep mode. For details, refer to the paragraph ?Sleep Modes? below.

##### SE - Sleep Enable

`#define SE_BIT 5`

`#define SE_MASK 32`

The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.

### MCUSR -

`sfrb MCUSR = $34;`

##### PORF - Power On Reset Flag

`#define PORF_BIT 0`

`#define PORF_MASK 1`

##### EXTRF - Externl Reset Flag

`#define EXTRF_BIT 1`

`#define EXTRF_MASK 2`

### GIMSK - General Interrupt Mask Register

`sfrb GIMSK = $3B;`

##### INT0 - External Interrupt Request 0 Enable

`#define INT0_BIT 6`

`#define INT0_MASK 64`

### GIFR - General Interrupt Flag Register

`sfrb GIFR = $3A;`

##### INTF0 - External Interrupt Flag 0

`#define INTF0_BIT 6`

`#define INTF0_MASK 64`

## EEPROM

### EEAR - EEPROM Read/Write Access

`sfrb EEAR = $1E;`

##### EEAR0 - EEPROM Read/Write Access bit 0

`#define EEAR0_BIT 0`

`#define EEAR0_MASK 1`

##### EEAR1 - EEPROM Read/Write Access bit 1

`#define EEAR1_BIT 1`

`#define EEAR1_MASK 2`

##### EEAR2 - EEPROM Read/Write Access bit 2

`#define EEAR2_BIT 2`

`#define EEAR2_MASK 4`

##### EEAR3 - EEPROM Read/Write Access bit 3

`#define EEAR3_BIT 3`

`#define EEAR3_MASK 8`

##### EEAR4 - EEPROM Read/Write Access bit 4

`#define EEAR4_BIT 4`

`#define EEAR4_MASK 16`

##### EEAR5 - EEPROM Read/Write Access bit 5

`#define EEAR5_BIT 5`

`#define EEAR5_MASK 32`

##### EEAR6 - EEPROM Read/Write Access bit 6

`#define EEAR6_BIT 6`

`#define EEAR6_MASK 64`

### EEDR - EEPROM Data Register

`sfrb EEDR = $1D;`

##### EEDR0 - EEPROM Data Register bit 0

`#define EEDR0_BIT 0`

`#define EEDR0_MASK 1`

##### EEDR1 - EEPROM Data Register bit 1

`#define EEDR1_BIT 1`

`#define EEDR1_MASK 2`

##### EEDR2 - EEPROM Data Register bit 2

`#define EEDR2_BIT 2`

`#define EEDR2_MASK 4`

##### EEDR3 - EEPROM Data Register bit 3

`#define EEDR3_BIT 3`

`#define EEDR3_MASK 8`

##### EEDR4 - EEPROM Data Register bit 4

`#define EEDR4_BIT 4`

`#define EEDR4_MASK 16`

##### EEDR5 - EEPROM Data Register bit 5

`#define EEDR5_BIT 5`

`#define EEDR5_MASK 32`

##### EEDR6 - EEPROM Data Register bit 6

`#define EEDR6_BIT 6`

`#define EEDR6_MASK 64`

##### EEDR7 - EEPROM Data Register bit 7

`#define EEDR7_BIT 7`

`#define EEDR7_MASK 128`

### EECR - EEPROM Control Register

`sfrb EECR = $1C;`

##### EERE - EEPROM Read Enable

`#define EERE_BIT 0`

`#define EERE_MASK 1`

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined.

##### EEWE - EEPROM Write Enable

`#define EEWE_BIT 1`

`#define EEWE_MASK 2`

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one to the EEMWE bit, the EEWE bit mustbewritten to zero in thesamecycle). 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at V CC =5Vor 4msatV CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted or two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems.

##### EEMWE - EEPROM Master Write Enable

`#define EEMWE_BIT 2`

`#define EEMWE_MASK 4`

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure.

## WATCHDOG

### WDTCR - Watchdog Timer Control Register

`sfrb WDTCR = $21;`

##### WDP0 - Watch Dog Timer Prescaler bit 0

`#define WDP0_BIT 0`

`#define WDP0_MASK 1`

##### WDP1 - Watch Dog Timer Prescaler bit 1

`#define WDP1_BIT 1`

`#define WDP1_MASK 2`

##### WDP2 - Watch Dog Timer Prescaler bit 2

`#define WDP2_BIT 2`

`#define WDP2_MASK 4`

##### WDE - Watch Dog Enable

`#define WDE_BIT 3`

`#define WDE_MASK 8`

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog

##### WDTOE - RW

`#define WDTOE_BIT 4`

`#define WDTOE_MASK 16`

This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.

## PORTB

### PORTB - Data Register, Port B

`sfrb PORTB = $18;`

##### PORTB0

`#define PORTB0_BIT 0`

`#define PORTB0_MASK 1`

##### PORTB1

`#define PORTB1_BIT 1`

`#define PORTB1_MASK 2`

##### PORTB2

`#define PORTB2_BIT 2`

`#define PORTB2_MASK 4`

##### PORTB3

`#define PORTB3_BIT 3`

`#define PORTB3_MASK 8`

##### PORTB4

`#define PORTB4_BIT 4`

`#define PORTB4_MASK 16`

### DDRB - Data Direction Register, Port B

`sfrb DDRB = $17;`

##### DDB0

`#define DDB0_BIT 0`

`#define DDB0_MASK 1`

##### DDB1

`#define DDB1_BIT 1`

`#define DDB1_MASK 2`

##### DDB2

`#define DDB2_BIT 2`

`#define DDB2_MASK 4`

##### DDB3

`#define DDB3_BIT 3`

`#define DDB3_MASK 8`

##### DDB4

`#define DDB4_BIT 4`

`#define DDB4_MASK 16`

### PINB - Input Pins, Port B

`sfrb PINB = $16;`

##### PINB0

`#define PINB0_BIT 0`

`#define PINB0_MASK 1`

##### PINB1

`#define PINB1_BIT 1`

`#define PINB1_MASK 2`

##### PINB2

`#define PINB2_BIT 2`

`#define PINB2_MASK 4`

##### PINB3

`#define PINB3_BIT 3`

`#define PINB3_MASK 8`

##### PINB4

`#define PINB4_BIT 4`

`#define PINB4_MASK 16`

## TIMER COUNTER 0

The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in ?Timer/Counter0 Control Register - TCCR0? on page 35. The overflow status flag is found in ?The Timer/Counter Interrupt Flag Register - TIFR? on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in ?The Timer/Counter Interrupt Mask Regis-ter - TIMSK? on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions

### TIMSK - Timer/Counter Interrupt Mask Register

`sfrb TIMSK = $39;`

##### TOIE0 - Timer/Counter0 Overflow Interrupt Enable

`#define TOIE0_BIT 1`

`#define TOIE0_MASK 2`

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

### TIFR - Timer/Counter Interrupt Flag register

`sfrb TIFR = $38;`

##### TOV0 - Timer/Counter0 Overflow Flag

`#define TOV0_BIT 1`

`#define TOV0_MASK 2`

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.

### TCCR0 - Timer/Counter0 Control Register

`sfrb TCCR0 = $33;`

##### CS00 - Clock Select0 bit 0

`#define CS00_BIT 0`

`#define CS00_MASK 1`

##### CS01 - Clock Select0 bit 1

`#define CS01_BIT 1`

`#define CS01_MASK 2`

##### CS02 - Clock Select0 bit 2

`#define CS02_BIT 2`

`#define CS02_MASK 4`

### TCNT0 - Timer Counter 0

`sfrb TCNT0 = $32;`

##### TCNT00 - Timer Counter 0 bit 0

`#define TCNT00_BIT 0`

`#define TCNT00_MASK 1`

##### TCNT01 - Timer Counter 0 bit 1

`#define TCNT01_BIT 1`

`#define TCNT01_MASK 2`

##### TCNT02 - Timer Counter 0 bit 2

`#define TCNT02_BIT 2`

`#define TCNT02_MASK 4`

##### TCNT03 - Timer Counter 0 bit 3

`#define TCNT03_BIT 3`

`#define TCNT03_MASK 8`

##### TCNT04 - Timer Counter 0 bit 4

`#define TCNT04_BIT 4`

`#define TCNT04_MASK 16`

##### TCNT05 - Timer Counter 0 bit 5

`#define TCNT05_BIT 5`

`#define TCNT05_MASK 32`

##### TCNT06 - Timer Counter 0 bit 6

`#define TCNT06_BIT 6`

`#define TCNT06_MASK 64`

##### TCNT07 - Timer Counter 0 bit 7

`#define TCNT07_BIT 7`

`#define TCNT07_MASK 128`