This documentation was generated automatically from the AVR Studio part description file `ATtiny11.pdf`.

## ANALOG COMPARATOR

The analog comparator compares the input values on the positive input PB2 (AIN0) and negative input PB3 (AIN1). When the voltage on the positive input PB2 (AIN0) is higher than the voltage on the negative input PB3 (AIN1), the Analog Com-parator Output, ACO is set (one). The comparator?s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Inter-rupt triggering on comparator output rise, fall or toggle

### ACSR - Analog Comparator Control And Status Register

`sfrb ACSR = $08;`

##### ACIS0 - Analog Comparator Interrupt Mode Select bit 0

`#define ACIS0_BIT 0`

`#define ACIS0_MASK 1`

These bits determine which comparator events that trigger the Analog Comparator interrupt.

##### ACIS1 - Analog Comparator Interrupt Mode Select bit 1

`#define ACIS1_BIT 1`

`#define ACIS1_MASK 2`

These bits determine which comparator events that trigger the Analog Comparator interrupt.

##### ACIE - Analog Comparator Interrupt Enable

`#define ACIE_BIT 3`

`#define ACIE_MASK 8`

When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the analog comparator interrupt is activated. When Cleared (Zero), the interrupt is disabled.

##### ACI - Analog Comparator Interrupt Flag

`#define ACI_BIT 4`

`#define ACI_MASK 16`

This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. Observe however, that if another bit in this register is modified using the SBI or CBI instruction, ACI will be cleared if it has become set before the operation

##### ACO - Analog Comparator Output

`#define ACO_BIT 5`

`#define ACO_MASK 32`

When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

##### ACD - Analog Comparator Disable

`#define ACD_BIT 7`

`#define ACD_MASK 128`

When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

## EXTERNAL INTERRUPT

### GIMSK - General Interrupt Mask Register

`sfrb GIMSK = $3B;`

##### PCIE - Pin Change Interrupt Enable

`#define PCIE_BIT 5`

`#define PCIE_MASK 32`

##### INT0 - External Interrupt Request 0 Enable

`#define INT0_BIT 6`

`#define INT0_MASK 64`

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also ?External Interrupts.? ? Bits 5..0 - Res: Reserved bits

### GIFR - General Interrupt Flag register

`sfrb GIFR = $3A;`

##### PCIF - Pin Change Interrupt Flag

`#define PCIF_BIT 5`

`#define PCIF_MASK 32`

##### INTF0 - External Interrupt Flag 0

`#define INTF0_BIT 6`

`#define INTF0_MASK 64`

When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

## PORTB

### PORTB - Data Register, Port B

`sfrb PORTB = $18;`

##### PORTB0

`#define PORTB0_BIT 0`

`#define PORTB0_MASK 1`

##### PORTB1

`#define PORTB1_BIT 1`

`#define PORTB1_MASK 2`

##### PORTB2

`#define PORTB2_BIT 2`

`#define PORTB2_MASK 4`

##### PORTB3

`#define PORTB3_BIT 3`

`#define PORTB3_MASK 8`

##### PORTB4

`#define PORTB4_BIT 4`

`#define PORTB4_MASK 16`

### DDRB - Data Direction Register, Port B

`sfrb DDRB = $17;`

##### DDB0

`#define DDB0_BIT 0`

`#define DDB0_MASK 1`

##### DDB1

`#define DDB1_BIT 1`

`#define DDB1_MASK 2`

##### DDB2

`#define DDB2_BIT 2`

`#define DDB2_MASK 4`

##### DDB3

`#define DDB3_BIT 3`

`#define DDB3_MASK 8`

##### DDB4

`#define DDB4_BIT 4`

`#define DDB4_MASK 16`

### PINB - Input Pins, Port B

`sfrb PINB = $16;`

##### PINB0

`#define PINB0_BIT 0`

`#define PINB0_MASK 1`

##### PINB1

`#define PINB1_BIT 1`

`#define PINB1_MASK 2`

##### PINB2

`#define PINB2_BIT 2`

`#define PINB2_MASK 4`

##### PINB3

`#define PINB3_BIT 3`

`#define PINB3_MASK 8`

##### PINB4

`#define PINB4_BIT 4`

`#define PINB4_MASK 16`

##### PINB5

`#define PINB5_BIT 5`

`#define PINB5_MASK 32`

## TIMER COUNTER 0

The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in ?Timer/Counter0 Control Register - TCCR0? on page 35. The overflow status flag is found in ?The Timer/Counter Interrupt Flag Register - TIFR? on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in ?The Timer/Counter Interrupt Mask Regis-ter - TIMSK? on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions

### TIMSK - Timer/Counter Interrupt Mask Register

`sfrb TIMSK = $39;`

##### TOIE0 - Timer/Counter0 Overflow Interrupt Enable

`#define TOIE0_BIT 1`

`#define TOIE0_MASK 2`

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

### TIFR - Timer/Counter Interrupt Flag register

`sfrb TIFR = $38;`

##### TOV0 - Timer/Counter0 Overflow Flag

`#define TOV0_BIT 1`

`#define TOV0_MASK 2`

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.

### TCCR0 - Timer/Counter0 Control Register

`sfrb TCCR0 = $33;`

##### CS00 - Clock Select0 bit 0

`#define CS00_BIT 0`

`#define CS00_MASK 1`

##### CS01 - Clock Select0 bit 1

`#define CS01_BIT 1`

`#define CS01_MASK 2`

##### CS02 - Clock Select0 bit 2

`#define CS02_BIT 2`

`#define CS02_MASK 4`

### TCNT0 - Timer Counter 0

`sfrb TCNT0 = $32;`

##### TCNT00 - Timer Counter 0 bit 0

`#define TCNT00_BIT 0`

`#define TCNT00_MASK 1`

##### TCNT01 - Timer Counter 0 bit 1

`#define TCNT01_BIT 1`

`#define TCNT01_MASK 2`

##### TCNT02 - Timer Counter 0 bit 2

`#define TCNT02_BIT 2`

`#define TCNT02_MASK 4`

##### TCNT03 - Timer Counter 0 bit 3

`#define TCNT03_BIT 3`

`#define TCNT03_MASK 8`

##### TCNT04 - Timer Counter 0 bit 4

`#define TCNT04_BIT 4`

`#define TCNT04_MASK 16`

##### TCNT05 - Timer Counter 0 bit 5

`#define TCNT05_BIT 5`

`#define TCNT05_MASK 32`

##### TCNT06 - Timer Counter 0 bit 6

`#define TCNT06_BIT 6`

`#define TCNT06_MASK 64`

##### TCNT07 - Timer Counter 0 bit 7

`#define TCNT07_BIT 7`

`#define TCNT07_MASK 128`

## WATCHDOG

### WDTCR - Watchdog Timer Control Register

`sfrb WDTCR = $21;`

##### WDP0 - Watch Dog Timer Prescaler bit 0

`#define WDP0_BIT 0`

`#define WDP0_MASK 1`

##### WDP1 - Watch Dog Timer Prescaler bit 1

`#define WDP1_BIT 1`

`#define WDP1_MASK 2`

##### WDP2 - Watch Dog Timer Prescaler bit 2

`#define WDP2_BIT 2`

`#define WDP2_MASK 4`

##### WDE - Watch Dog Enable

`#define WDE_BIT 3`

`#define WDE_MASK 8`

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog

##### WDTOE - RW

`#define WDTOE_BIT 4`

`#define WDTOE_MASK 16`

This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.

## CPU

### SREG - Status Register

`sfrb SREG = $3F;`

### MCUSR - MCU Status register

`sfrb MCUSR = $34;`

##### PORF - Power-On Reset Flag

`#define PORF_BIT 0`

`#define PORF_MASK 1`

This bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchanged

##### EXTRF - External Reset Flag

`#define EXTRF_BIT 1`

`#define EXTRF_MASK 2`

After a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged.

### MCUCR - MCU Control Register

`sfrb MCUCR = $35;`

##### ISC00 - Interrupt Sense Control 0 bit 0

`#define ISC00_BIT 0`

`#define ISC00_MASK 1`

##### ISC01 - Interrupt Sense Control 0 bit 1

`#define ISC01_BIT 1`

`#define ISC01_MASK 2`

##### SM - Sleep Mode

`#define SM_BIT 4`

`#define SM_MASK 16`

This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode. When SM is set (one), Power Down mode is selected as sleep mode. For details, refer to the section ?Sleep Modes? on page 25.

##### SE - Sleep Enable

`#define SE_BIT 5`

`#define SE_MASK 32`

The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.