#ifndef __ATtiny45_h
#define __ATtiny45_h

// Interrupt vectors

#define RESET_vect 0x0000
#define INT0_vect 0x0002
#define PCINT0_vect 0x0004
#define TIM1_COMPA_vect 0x0006
#define TIM1_OVF_vect 0x0008
#define TIM0_OVF_vect 0x000a
#define EE_RDY_vect 0x000c
#define ANA_COMP_vect 0x000e
#define ADC_vect 0x0010
#define TIM1_COMPB_vect 0x0012
#define TIM0_COMPA_vect 0x0014
#define TIM0_COMPB_vect 0x0016
#define WDT_vect 0x0018
#define USI_START_vect 0x001a
#define USI_OVF_vect 0x001c

// I/O addresses


sfrb SREG = 0x5f;

sfrb SPH = 0x5e;

sfrb SPL = 0x5d;
#define SP0 0
#define SP1 1
#define SP2 2
#define SP3 3
#define SP4 4
#define SP5 5
#define SP6 6
#define SP7 7

sfrw SPW = 0x5d;

sfrb GIMSK = 0x5b;
#define PCIE 5
#define INT0 6

sfrb GIFR = 0x5a;
#define PCIF 5
#define INTF0 6

sfrb TIMSK = 0x59;
#define TOIE0 1
#define TOIE1 2
#define OCIE0B 3
#define OCIE0A 4
#define OCIE1B 5
#define OCE1A 6

sfrb TIFR = 0x58;
#define TOV0 1
#define TOV1 2
#define OCF0B 3
#define OCF0A 4
#define OCF1B 5
#define OCF1A 6

sfrb SPMCSR = 0x57;
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define RFLB 3
#define CTPB 4

sfrb MCUCR = 0x55;
#define ISC00 0
#define ISC01 1
#define SM0 3
#define SM1 4
#define SE 5
#define PUD 6

sfrb MCUSR = 0x54;
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3

sfrb TCCR0B = 0x53;
#define CS00 0
#define CS01 1
#define CS02 2
#define WGM02 3
#define FOC0B 6
#define FOC0A 7

sfrb TCNT0 = 0x52;
#define TCNT0_0 0
#define TCNT0_1 1
#define TCNT0_2 2
#define TCNT0_3 3
#define TCNT0_4 4
#define TCNT0_5 5
#define TCNT0_6 6
#define TCNT0_7 7

sfrb OSCCAL = 0x51;
#define CAL0 0
#define CAL1 1
#define CAL2 2
#define CAL3 3
#define CAL4 4
#define CAL5 5
#define CAL6 6

sfrb TCCR1 = 0x50;
#define CS10 0
#define CS11 1
#define CS12 2
#define CS13 3
#define COM1A0 4
#define COM1A1 5
#define PWM1A 6
#define CTC1 7

sfrb TCNT1 = 0x4f;
#define TCNT1_0 0
#define TCNT1_1 1
#define TCNT1_2 2
#define TCNT1_3 3
#define TCNT1_4 4
#define TCNT1_5 5
#define TCNT1_6 6
#define TCNT1_7 7

sfrb OCR1A = 0x4e;
#define OCR1A0 0
#define OCR1A1 1
#define OCR1A2 2
#define OCR1A3 3
#define OCR1A4 4
#define OCR1A5 5
#define OCR1A6 6
#define OCR1A7 7

sfrb OCR1C = 0x4d;
#define OCR1C0 0
#define OCR1C1 1
#define OCR1C2 2
#define OCR1C3 3
#define OCR1C4 4
#define OCR1C5 5
#define OCR1C6 6
#define OCR1C7 7

sfrb GTCCR = 0x4c;
#define PSR0 0
#define PSR1 1
#define FOC1A 2
#define FOC1B 3
#define COM1B0 4
#define COM1B1 5
#define PWM1B 6
#define TSM 7

sfrb OCR1B = 0x4b;
#define OCR1B0 0
#define OCR1B1 1
#define OCR1B2 2
#define OCR1B3 3
#define OCR1B4 4
#define OCR1B5 5
#define OCR1B6 6
#define OCR1B7 7

sfrb TCCR0A = 0x4a;
#define WGM00 0
#define WGM01 1
#define COM0B0 4
#define COM0B1 5
#define COM0A0 6
#define COM0A1 7

sfrb OCR0A = 0x49;
#define OCR0_0 0
#define OCR0_1 1
#define OCR0_2 2
#define OCR0_3 3
#define OCR0_4 4
#define OCR0_5 5
#define OCR0_6 6
#define OCR0_7 7

sfrb OCR0B = 0x48;
#define OCR0_0 0
#define OCR0_1 1
#define OCR0_2 2
#define OCR0_3 3
#define OCR0_4 4
#define OCR0_5 5
#define OCR0_6 6
#define OCR0_7 7

sfrb PLLCSR = 0x47;
#define PLOCK 0
#define PLLE 1
#define PCKE 2
#define LSM 7

sfrb CLKPR = 0x46;
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CLKPCE 7

sfrb DTVALA = 0x45;
#define DTVL0 0
#define DTVL1 1
#define DTVL2 2
#define DTVL3 3
#define DTVH0 4
#define DTVH1 5
#define DTVH2 6
#define DTVH3 7

sfrb DTVALB = 0x44;
#define DTVL0 0
#define DTVL1 1
#define DTVL2 2
#define DTVL3 3
#define DTVH0 4
#define DTVH1 5
#define DTVH2 6
#define DTVH3 7

sfrb DTPS = 0x43;
#define DTPS0 0
#define DTPS1 1

sfrb DWDR = 0x42;
#define DWDR0 0
#define DWDR1 1
#define DWDR2 2
#define DWDR3 3
#define DWDR4 4
#define DWDR5 5
#define DWDR6 6
#define DWDR7 7

sfrb WDTCR = 0x41;
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDE 3
#define WDCE 4
#define WDP3 5
#define WDIE 6
#define WDIF 7

sfrb PRR = 0x40;
#define PRADC 0
#define PRUSI 1
#define PRTIM0 2
#define PRTIM1 3

sfrb EEARH = 0x3f;
#define EEAR8 0

sfrb EEARL = 0x3e;
#define EEAR0 0
#define EEAR1 1
#define EEAR2 2
#define EEAR3 3
#define EEAR4 4
#define EEAR5 5
#define EEAR6 6
#define EEAR7 7

sfrw EEARW = 0x3e;

sfrb EEDR = 0x3d;
#define EEDR0 0
#define EEDR1 1
#define EEDR2 2
#define EEDR3 3
#define EEDR4 4
#define EEDR5 5
#define EEDR6 6
#define EEDR7 7

sfrb EECR = 0x3c;
#define EERE 0
#define EEPE 1
#define EEMPE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5

sfrb PORTB = 0x38;
#define PORTB0 0
#define PORTB1 1
#define PORTB2 2
#define PORTB3 3
#define PORTB4 4
#define PORTB5 5

sfrb DDRB = 0x37;
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3
#define DDB4 4
#define DDB5 5

sfrb PINB = 0x36;
#define PINB0 0
#define PINB1 1
#define PINB2 2
#define PINB3 3
#define PINB4 4
#define PINB5 5

sfrb PCMSK = 0x35;
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5

sfrb DIDR0 = 0x34;
#define AIN0D 0
#define AIN1D 1
#define ADC1D 2
#define ADC3D 3
#define ADC2D 4
#define ADC0D 5

sfrb GPIOR2 = 0x33;
#define GPIOR20 0
#define GPIOR21 1
#define GPIOR22 2
#define GPIOR23 3
#define GPIOR24 4
#define GPIOR25 5
#define GPIOR26 6
#define GPIOR27 7

sfrb GPIOR1 = 0x32;
#define GPIOR10 0
#define GPIOR11 1
#define GPIOR12 2
#define GPIOR13 3
#define GPIOR14 4
#define GPIOR15 5
#define GPIOR16 6
#define GPIOR17 7

sfrb GPIOR0 = 0x31;
#define GPIOR00 0
#define GPIOR01 1
#define GPIOR02 2
#define GPIOR03 3
#define GPIOR04 4
#define GPIOR05 5
#define GPIOR06 6
#define GPIOR07 7

sfrb USIBR = 0x30;
#define USIBR0 0
#define USIBR1 1
#define USIBR2 2
#define USIBR3 3
#define USIBR4 4
#define USIBR5 5
#define USIBR6 6
#define USIBR7 7

sfrb USIDR = 0x2f;
#define USIDR0 0
#define USIDR1 1
#define USIDR2 2
#define USIDR3 3
#define USIDR4 4
#define USIDR5 5
#define USIDR6 6
#define USIDR7 7

sfrb USISR = 0x2e;
#define USICNT0 0
#define USICNT1 1
#define USICNT2 2
#define USICNT3 3
#define USIDC 4
#define USIPF 5
#define USIOIF 6
#define USISIF 7

sfrb USICR = 0x2d;
#define USITC 0
#define USICLK 1
#define USICS0 2
#define USICS1 3
#define USIWM0 4
#define USIWM1 5
#define USIOIE 6
#define USISIE 7

sfrb ACSR = 0x28;
#define ACIS0 0
#define ACIS1 1
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACBG 6
#define ACD 7

sfrb ADMUX = 0x27;
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define REFS2 4
#define ADLAR 5
#define REFS0 6
#define REFS1 7

sfrb ADCSRA = 0x26;
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7

sfrb ADCH = 0x25;
#define ADCH0 0
#define ADCH1 1
#define ADCH2 2
#define ADCH3 3
#define ADCH4 4
#define ADCH5 5
#define ADCH6 6
#define ADCH7 7

sfrb ADCL = 0x24;
#define ADCL0 0
#define ADCL1 1
#define ADCL2 2
#define ADCL3 3
#define ADCL4 4
#define ADCL5 5
#define ADCL6 6
#define ADCL7 7

sfrw ADCW = 0x24;

sfrb ADCSRB = 0x23;
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define IPR 5
#define ACME 6
#define BIN 7

#endif