#ifndef __ATtiny24_h
#define __ATtiny24_h

// Interrupt vectors

#define RESET_vect 0x0000
#define INT0_vect 0x0002
#define PCINT0_vect 0x0004
#define PCINT1_vect 0x0006
#define WDT_vect 0x0008
#define TIMER1_CAPT_vect 0x000a
#define TIM1_COMPA_vect 0x000c
#define TIM1_COMPB_vect 0x000e
#define TIM1_OVF_vect 0x0010
#define TIM0_COMPA_vect 0x0012
#define TIM0_COMPB_vect 0x0014
#define TIM0_OVF_vect 0x0016
#define ANA_COMP_vect 0x0018
#define ADC_vect 0x001a
#define EE_RDY_vect 0x001c
#define USI_START_vect 0x001e
#define USI_OVF_vect 0x0020

// I/O addresses


sfrb SREG = 0x5f;

sfrb SPH = 0x5e;
#define SP8 0
#define SP9 1

sfrb SPL = 0x5d;
#define SP0 0
#define SP1 1
#define SP2 2
#define SP3 3
#define SP4 4
#define SP5 5
#define SP6 6
#define SP7 7

sfrw SPW = 0x5d;

sfrb OCR0B = 0x5c;
#define OCR0_0 0
#define OCR0_1 1
#define OCR0_2 2
#define OCR0_3 3
#define OCR0_4 4
#define OCR0_5 5
#define OCR0_6 6
#define OCR0_7 7

sfrb GIMSK = 0x5b;
#define PCIE0 4
#define PCIE1 5
#define INT0 6

sfrb GIFR = 0x5a;
#define PCIF0 4
#define PCIF1 5
#define INTF0 6

sfrb TIMSK0 = 0x59;
#define TOIE0 0
#define OCIE0A 1
#define OCIE0B 2

sfrb TIFR0 = 0x58;
#define TOV0 0
#define OCF0A 1
#define OCF0B 2

sfrb SPMCSR = 0x57;

sfrb OCR0A = 0x56;
#define OCR0_0 0
#define OCR0_1 1
#define OCR0_2 2
#define OCR0_3 3
#define OCR0_4 4
#define OCR0_5 5
#define OCR0_6 6
#define OCR0_7 7

sfrb MCUCR = 0x55;
#define ISC00 0
#define ISC01 1
#define SM0 3
#define SM1 4
#define SE 5
#define PUD 6

sfrb MCUSR = 0x54;
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3

sfrb TCCR0B = 0x53;
#define CS00 0
#define CS01 1
#define CS02 2
#define WGM02 3
#define FOC0B 6
#define FOC0A 7

sfrb TCNT0 = 0x52;
#define TCNT0_0 0
#define TCNT0_1 1
#define TCNT0_2 2
#define TCNT0_3 3
#define TCNT0_4 4
#define TCNT0_5 5
#define TCNT0_6 6
#define TCNT0_7 7

sfrb OSCCAL = 0x51;
#define CAL0 0
#define CAL1 1
#define CAL2 2
#define CAL3 3
#define CAL4 4
#define CAL5 5
#define CAL6 6
#define CAL7 7

sfrb TCCR0A = 0x50;
#define WGM00 0
#define WGM01 1
#define COM0B0 4
#define COM0B1 5
#define COM0A0 6
#define COM0A1 7

sfrb TCCR1A = 0x4f;
#define WGM10 0
#define WGM11 1
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7

sfrb TCCR1B = 0x4e;
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM12 3
#define WGM13 4
#define ICES1 6
#define ICNC1 7

sfrb TCNT1H = 0x4d;
#define TCNT1H0 0
#define TCNT1H1 1
#define TCNT1H2 2
#define TCNT1H3 3
#define TCNT1H4 4
#define TCNT1H5 5
#define TCNT1H6 6
#define TCNT1H7 7

sfrb TCNT1L = 0x4c;
#define TCNT1L0 0
#define TCNT1L1 1
#define TCNT1L2 2
#define TCNT1L3 3
#define TCNT1L4 4
#define TCNT1L5 5
#define TCNT1L6 6
#define TCNT1L7 7

sfrw TCNT1W = 0x4c;

sfrb OCR1AH = 0x4b;
#define OCR1AH0 0
#define OCR1AH1 1
#define OCR1AH2 2
#define OCR1AH3 3
#define OCR1AH4 4
#define OCR1AH5 5
#define OCR1AH6 6
#define OCR1AH7 7

sfrb OCR1AL = 0x4a;
#define OCR1AL0 0
#define OCR1AL1 1
#define OCR1AL2 2
#define OCR1AL3 3
#define OCR1AL4 4
#define OCR1AL5 5
#define OCR1AL6 6
#define OCR1AL7 7

sfrw OCR1AW = 0x4a;

sfrb OCR1BH = 0x49;
#define OCR1AH0 0
#define OCR1AH1 1
#define OCR1AH2 2
#define OCR1AH3 3
#define OCR1AH4 4
#define OCR1AH5 5
#define OCR1AH6 6
#define OCR1AH7 7

sfrb OCR1BL = 0x48;
#define OCR1AL0 0
#define OCR1AL1 1
#define OCR1AL2 2
#define OCR1AL3 3
#define OCR1AL4 4
#define OCR1AL5 5
#define OCR1AL6 6
#define OCR1AL7 7

sfrw OCR1BW = 0x48;

sfrb DWDR = 0x47;

sfrb CLKPR = 0x46;

sfrb ICR1H = 0x45;
#define ICR1H0 0
#define ICR1H1 1
#define ICR1H2 2
#define ICR1H3 3
#define ICR1H4 4
#define ICR1H5 5
#define ICR1H6 6
#define ICR1H7 7

sfrb ICR1L = 0x44;
#define ICR1L0 0
#define ICR1L1 1
#define ICR1L2 2
#define ICR1L3 3
#define ICR1L4 4
#define ICR1L5 5
#define ICR1L6 6
#define ICR1L7 7

sfrw ICR1W = 0x44;

sfrb GTCCR = 0x43;
#define PSR0 0
#define TSM 7

sfrb TCCR1C = 0x42;
#define FOC1B 6
#define FOC1A 7

sfrb WDTCSR = 0x41;
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDE 3
#define WDCE 4
#define WDP3 5
#define WDIE 6
#define WDIF 7

sfrb PCMSK1 = 0x40;
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3

sfrb EEARH = 0x3f;
#define EEAR8 0

sfrb EEARL = 0x3e;
#define EEAR0 0
#define EEAR1 1
#define EEAR2 2
#define EEAR3 3
#define EEAR4 4
#define EEAR5 5
#define EEAR6 6
#define EEAR7 7

sfrw EEARW = 0x3e;

sfrb EEDR = 0x3d;
#define EEDR0 0
#define EEDR1 1
#define EEDR2 2
#define EEDR3 3
#define EEDR4 4
#define EEDR5 5
#define EEDR6 6
#define EEDR7 7

sfrb EECR = 0x3c;
#define EERE 0
#define EEPE 1
#define EEMPE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5

sfrb PORTA = 0x3b;
#define PORTA0 0
#define PORTA1 1
#define PORTA2 2
#define PORTA3 3
#define PORTA4 4
#define PORTA5 5
#define PORTA6 6
#define PORTA7 7

sfrb DDRA = 0x3a;
#define DDA0 0
#define DDA1 1
#define DDA2 2
#define DDA3 3
#define DDA4 4
#define DDA5 5
#define DDA6 6
#define DDA7 7

sfrb PINA = 0x39;
#define PINA0 0
#define PINA1 1
#define PINA2 2
#define PINA3 3
#define PINA4 4
#define PINA5 5
#define PINA6 6
#define PINA7 7

sfrb PORTB = 0x38;
#define PORTB0 0
#define PORTB1 1
#define PORTB2 2
#define PORTB3 3

sfrb DDRB = 0x37;
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3

sfrb PINB = 0x36;
#define PINB0 0
#define PINB1 1
#define PINB2 2
#define PINB3 3

sfrb GPIOR2 = 0x35;
#define GPIOR20 0
#define GPIOR21 1
#define GPIOR22 2
#define GPIOR23 3
#define GPIOR24 4
#define GPIOR25 5
#define GPIOR26 6
#define GPIOR27 7

sfrb GPIOR1 = 0x34;
#define GPIOR10 0
#define GPIOR11 1
#define GPIOR12 2
#define GPIOR13 3
#define GPIOR14 4
#define GPIOR15 5
#define GPIOR16 6
#define GPIOR17 7

sfrb GPIOR0 = 0x33;
#define GPIOR00 0
#define GPIOR01 1
#define GPIOR02 2
#define GPIOR03 3
#define GPIOR04 4
#define GPIOR05 5
#define GPIOR06 6
#define GPIOR07 7

sfrb PCMSK0 = 0x32;
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7

sfrb USIBR = 0x30;
#define USIBR0 0
#define USIBR1 1
#define USIBR2 2
#define USIBR3 3
#define USIBR4 4
#define USIBR5 5
#define USIBR6 6
#define USIBR7 7

sfrb USIDR = 0x2f;
#define USIDR0 0
#define USIDR1 1
#define USIDR2 2
#define USIDR3 3
#define USIDR4 4
#define USIDR5 5
#define USIDR6 6
#define USIDR7 7

sfrb USISR = 0x2e;
#define USICNT0 0
#define USICNT1 1
#define USICNT2 2
#define USICNT3 3
#define USIDC 4
#define USIPF 5
#define USIOIF 6
#define USISIF 7

sfrb USICR = 0x2d;
#define USITC 0
#define USICLK 1
#define USICS0 2
#define USICS1 3
#define USIWM0 4
#define USIWM1 5
#define USIOIE 6
#define USISIE 7

sfrb TIMSK1 = 0x2c;
#define TOIE1 0
#define OCIE1A 1
#define OCIE1B 2
#define ICIE1 5

sfrb TIFR1 = 0x2b;
#define TOV1 0
#define OCF1A 1
#define OCF1B 2
#define ICF1 5

sfrb ACSR = 0x28;
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACBG 6
#define ACD 7

sfrb ADMUX = 0x27;
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define MUX4 4
#define MUX5 5
#define REFS0 6
#define REFS1 7

sfrb ADCSRA = 0x26;
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7

sfrb ADCH = 0x25;
#define ADCH0 0
#define ADCH1 1
#define ADCH2 2
#define ADCH3 3
#define ADCH4 4
#define ADCH5 5
#define ADCH6 6
#define ADCH7 7

sfrb ADCL = 0x24;
#define ADCL0 0
#define ADCL1 1
#define ADCL2 2
#define ADCL3 3
#define ADCL4 4
#define ADCL5 5
#define ADCL6 6
#define ADCL7 7

sfrw ADCW = 0x24;

sfrb ADCSRB = 0x23;
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define ADLAR 4
#define ACME 6
#define BIN 7

sfrb DIDR0 = 0x21;
#define ADC0D 0
#define ADC1D 1
#define ADC2D 2
#define ADC3D 3
#define ADC4D 4
#define ADC5D 5
#define ADC6D 6
#define ADC7D 7

sfrb PRR = 0x20;
#define PRADC 0
#define PRUSI 1
#define PRTIM0 2
#define PRTIM1 3

#endif