#ifndef __ATtiny15_h
#define __ATtiny15_h

// Interrupt vectors

#define RESET_vect 0x0000
#define INT0_vect 0x0002
#define I/O_PINS_vect 0x0004
#define TIMER1_COMP_vect 0x0006
#define TIMER1_OVF_vect 0x0008
#define TIMER0_OVF_vect 0x000a
#define EE_RDY_vect 0x000c
#define ANA_COMP_vect 0x000e
#define ADC_vect 0x0010

// I/O addresses


sfrb SREG = 0x5f;

sfrb GIMSK = 0x5b;
#define PCIE 5
#define INT0 6

sfrb GIFR = 0x5a;
#define PCIF 5
#define INTF0 6

sfrb TIMSK = 0x59;
#define TOIE0 1
#define TOIE1 2
#define OCIE1A 6

sfrb TIFR = 0x58;
#define TOV0 1
#define TOV1 2
#define OCF1A 6

sfrb MCUCR = 0x55;
#define ISC00 0
#define ISC01 1
#define SM0 3
#define SM1 4
#define SE 5
#define PUD 6

sfrb MCUSR = 0x54;
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3

sfrb TCCR0 = 0x53;
#define CS00 0
#define CS01 1
#define CS02 2

sfrb TCNT0 = 0x52;
#define TCNT00 0
#define TCNT01 1
#define TCNT02 2
#define TCNT03 3
#define TCNT04 4
#define TCNT05 5
#define TCNT06 6
#define TCNT07 7

sfrb OSCCAL = 0x51;
#define CAL0 0
#define CAL1 1
#define CAL2 2
#define CAL3 3
#define CAL4 4
#define CAL5 5
#define CAL6 6
#define CAL7 7

sfrb TCCR1 = 0x50;
#define CS10 0
#define CS11 1
#define CS12 2
#define CS13 3
#define COM1A0 4
#define COM1A1 5
#define PWM1 6
#define CTC1 7

sfrb TCNT1 = 0x4f;
#define TCNT1_0 0
#define TCNT1_1 1
#define TCNT1_2 2
#define TCNT1_3 3
#define TCNT1_4 4
#define TCNT1_5 5
#define TCNT1_6 6
#define TCNT1_7 7

sfrb OCR1A = 0x4e;
#define OCR1A0 0
#define OCR1A1 1
#define OCR1A2 2
#define OCR1A3 3
#define OCR1A4 4
#define OCR1A5 5
#define OCR1A6 6
#define OCR1A7 7

sfrb OCR1B = 0x4d;
#define OCR1B0 0
#define OCR1B1 1
#define OCR1B2 2
#define OCR1B3 3
#define OCR1B4 4
#define OCR1B5 5
#define OCR1B6 6
#define OCR1B7 7

sfrb SFIOR = 0x4c;
#define PSR0 0
#define PSR1 1
#define FOC1A 2

sfrb WDTCR = 0x41;
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDE 3
#define WDTOE 4

sfrb EEAR = 0x3e;
#define EEAR0 0
#define EEAR1 1
#define EEAR2 2
#define EEAR3 3
#define EEAR4 4
#define EEAR5 5

sfrb EEDR = 0x3d;
#define EEDR0 0
#define EEDR1 1
#define EEDR2 2
#define EEDR3 3
#define EEDR4 4
#define EEDR5 5
#define EEDR6 6
#define EEDR7 7

sfrb EECR = 0x3c;
#define EERE 0
#define EEWE 1
#define EEMWE 2
#define EERIE 3

sfrb PORTB = 0x38;
#define PORTB0 0
#define PORTB1 1
#define PORTB2 2
#define PORTB3 3
#define PORTB4 4

sfrb DDRB = 0x37;
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3
#define DDB4 4
#define DDB5 5

sfrb PINB = 0x36;
#define PINB0 0
#define PINB1 1
#define PINB2 2
#define PINB3 3
#define PINB4 4
#define PINB5 5

sfrb ACSR = 0x28;
#define ACIS0 0
#define ACIS1 1
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACBG 6
#define ACD 7

sfrb ADMUX = 0x27;
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define ADLAR 5
#define REFS0 6
#define REFS1 7

sfrb ADCSR = 0x26;
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADFR 5
#define ADSC 6
#define ADEN 7

sfrb ADCH = 0x25;
#define ADCH0 0
#define ADCH1 1
#define ADCH2 2
#define ADCH3 3
#define ADCH4 4
#define ADCH5 5
#define ADCH6 6
#define ADCH7 7

sfrb ADCL = 0x24;
#define ADCL0 0
#define ADCL1 1
#define ADCL2 2
#define ADCL3 3
#define ADCL4 4
#define ADCL5 5
#define ADCL6 6
#define ADCL7 7

#endif