#ifndef __ATtiny13_h
#define __ATtiny13_h

// Interrupt vectors

#define RESET_vect 0x0000
#define INT0_vect 0x0002
#define PCINT0_vect 0x0004
#define TIM0_OVF_vect 0x0006
#define EE_RDY_vect 0x0008
#define ANA_COMP_vect 0x000a
#define TIM0_COMPA_vect 0x000c
#define TIM0_COMPB_vect 0x000e
#define WDT_vect 0x0010
#define ADC_vect 0x0012

// I/O addresses


sfrb SREG = 0x5f;

sfrb SPL = 0x5d;
#define SP0 0
#define SP1 1
#define SP2 2
#define SP3 3
#define SP4 4
#define SP5 5
#define SP6 6
#define SP7 7

sfrb GIMSK = 0x5b;
#define PCIE 5
#define INT0 6

sfrb GIFR = 0x5a;
#define PCIF 5
#define INTF0 6

sfrb TIMSK0 = 0x59;
#define TOIE0 1
#define OCIE0A 2
#define OCIE0B 3

sfrb TIFR0 = 0x58;
#define TOV0 1
#define OCF0A 2
#define OCF0B 3

sfrb SPMCSR = 0x57;
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define RFLB 3
#define CTPB 4

sfrb OCR0A = 0x56;
#define OCR0_0 0
#define OCR0_1 1
#define OCR0_2 2
#define OCR0_3 3
#define OCR0_4 4
#define OCR0_5 5
#define OCR0_6 6
#define OCR0_7 7

sfrb MCUCR = 0x55;
#define ISC00 0
#define ISC01 1
#define SM0 3
#define SM1 4
#define SE 5
#define PUD 6

sfrb MCUSR = 0x54;
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3

sfrb TCCR0B = 0x53;
#define CS00 0
#define CS01 1
#define CS02 2
#define WGM02 3
#define FOC0B 6
#define FOC0A 7

sfrb TCNT0 = 0x52;
#define TCNT0_0 0
#define TCNT0_1 1
#define TCNT0_2 2
#define TCNT0_3 3
#define TCNT0_4 4
#define TCNT0_5 5
#define TCNT0_6 6
#define TCNT0_7 7

sfrb OSCCAL = 0x51;
#define CAL0 0
#define CAL1 1
#define CAL2 2
#define CAL3 3
#define CAL4 4
#define CAL5 5
#define CAL6 6

sfrb TCCR0A = 0x4f;
#define WGM00 0
#define WGM01 1
#define COM0B0 4
#define COM0B1 5
#define COM0A0 6
#define COM0A1 7

sfrb DWDR = 0x4e;
#define DWDR0 0
#define DWDR1 1
#define DWDR2 2
#define DWDR3 3
#define DWDR4 4
#define DWDR5 5
#define DWDR6 6
#define DWDR7 7

sfrb OCR0B = 0x49;
#define OCR0_0 0
#define OCR0_1 1
#define OCR0_2 2
#define OCR0_3 3
#define OCR0_4 4
#define OCR0_5 5
#define OCR0_6 6
#define OCR0_7 7

sfrb GTCCR = 0x48;
#define PSR10 0
#define TSM 7

sfrb CLKPR = 0x46;
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CLKPCE 7

sfrb WDTCR = 0x41;
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDE 3
#define WDCE 4
#define WDP3 5
#define WDTIE 6
#define WDTIF 7

sfrb EEAR = 0x3e;
#define EEAR0 0
#define EEAR1 1
#define EEAR2 2
#define EEAR3 3
#define EEAR4 4
#define EEAR5 5

sfrb EEDR = 0x3d;
#define EEDR0 0
#define EEDR1 1
#define EEDR2 2
#define EEDR3 3
#define EEDR4 4
#define EEDR5 5
#define EEDR6 6
#define EEDR7 7

sfrb EECR = 0x3c;
#define EERE 0
#define EEWE 1
#define EEMWE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5

sfrb PORTB = 0x38;
#define PORTB0 0
#define PORTB1 1
#define PORTB2 2
#define PORTB3 3
#define PORTB4 4
#define PORTB5 5

sfrb DDRB = 0x37;
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3
#define DDB4 4
#define DDB5 5

sfrb PINB = 0x36;
#define PINB0 0
#define PINB1 1
#define PINB2 2
#define PINB3 3
#define PINB4 4
#define PINB5 5

sfrb PCMSK = 0x35;
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5

sfrb DIDR0 = 0x34;
#define AIN0D 0
#define AIN1D 1
#define ADC1D 2
#define ADC3D 3
#define ADC2D 4
#define ADC0D 5

sfrb ACSR = 0x28;
#define ACIS0 0
#define ACIS1 1
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACBG 6
#define ACD 7

sfrb ADMUX = 0x27;
#define MUX0 0
#define MUX1 1
#define ADLAR 5
#define REFS0 6

sfrb ADCSRA = 0x26;
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7

sfrb ADCH = 0x25;
#define ADCH0 0
#define ADCH1 1
#define ADCH2 2
#define ADCH3 3
#define ADCH4 4
#define ADCH5 5
#define ADCH6 6
#define ADCH7 7

sfrb ADCL = 0x24;
#define ADCL0 0
#define ADCL1 1
#define ADCL2 2
#define ADCL3 3
#define ADCL4 4
#define ADCL5 5
#define ADCL6 6
#define ADCL7 7

sfrw ADCW = 0x24;

sfrb ADCSRB = 0x23;
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define ACME 6

#endif