#ifndef __ATmega406_h
#define __ATmega406_h

// Interrupt vectors

#define RESET_vect 0x0000
#define BPINT_vect 0x0004
#define INT0_vect 0x0008
#define INT1_vect 0x000c
#define INT2_vect 0x0010
#define INT3_vect 0x0014
#define PCINT0_vect 0x0018
#define PCINT1_vect 0x001c
#define WDT_vect 0x0020
#define WAKE_UP_vect 0x0024
#define TIM1_COMP_vect 0x0028
#define TIM1_OVF_vect 0x002c
#define TIM0_COMPA_vect 0x0030
#define TIM0_COMPB_vect 0x0034
#define TIM0_OVF_vect 0x0038
#define TWI_BUS_CD_vect 0x003c
#define TWI_vect 0x0040
#define VADC_vect 0x0044
#define CCADC_CONV_vect 0x0048
#define CCADC_REG_CUR_vect 0x004c
#define CCADC_ACC_vect 0x0050
#define EE_READY_vect 0x0054
#define SPM_READY_vect 0x0058

// I/O addresses


sfrb BPPLR = 0xf8;
#define BPPL 0
#define BPPLE 1

sfrb BPCR = 0xf7;
#define CCD 0
#define DCD 1
#define SCD 2
#define DUVD 3

sfrb CBPTR = 0xf6;
#define OCPT0 0
#define OCPT1 1
#define OCPT2 2
#define OCPT3 3
#define SCPT0 4
#define SCPT1 5
#define SCPT2 6
#define SCPT3 7

sfrb BPOCD = 0xf5;
#define CCDL0 0
#define CCDL1 1
#define CCDL2 2
#define CCDL3 3
#define DCDL0 4
#define DCDL1 5
#define DCDL2 6
#define DCDL3 7

sfrb BPSCD = 0xf4;
#define SCDL0 0
#define SCDL1 1
#define SCDL2 2
#define SCDL3 3

sfrb BPDUV = 0xf3;
#define DUDL0 0
#define DUDL1 1
#define DUDL2 2
#define DUDL3 3
#define DUVT0 4
#define DUVT1 5

sfrb BPIR = 0xf2;
#define SCIE 0
#define DOCIE 1
#define COCIE 2
#define DUVIE 3
#define SCIF 4
#define DOCIF 5
#define COCIF 6
#define DUVIF 7

sfrb CBCR = 0xf1;
#define CBE1 0
#define CBE2 1
#define CBE3 2
#define CBE4 3

sfrb FCSR = 0xf0;
#define PFD 0
#define CFE 1
#define DFE 2
#define CPS 3
#define PWMOPC 4
#define PWMOC 5

sfrb CADICH = 0xe9;
#define CADICH0 0
#define CADICH1 1
#define CADICH2 2
#define CADICH3 3
#define CADICH4 4
#define CADICH5 5
#define CADICH6 6
#define CADICH7 7

sfrb CADICL = 0xe8;
#define CADICL0 0
#define CADICL1 1
#define CADICL2 2
#define CADICL3 3
#define CADICL4 4
#define CADICL5 5
#define CADICL6 6
#define CADICL7 7

sfrw CADICW = 0xe8;

sfrb CADRDC = 0xe7;
#define CADRDC0 0
#define CADRDC1 1
#define CADRDC2 2
#define CADRDC3 3
#define CADRDC4 4
#define CADRDC5 5
#define CADRDC6 6
#define CADRDC7 7

sfrb CADRCC = 0xe6;
#define CADRCC0 0
#define CADRCC1 1
#define CADRCC2 2
#define CADRCC3 3
#define CADRCC4 4
#define CADRCC5 5
#define CADRCC6 6
#define CADRCC7 7

sfrb CADCSRB = 0xe5;
#define CADICIF 0
#define CADRCIF 1
#define CADACIF 2
#define CADICIE 4
#define CADRCIE 5
#define CADACIE 6

sfrb CADCSRA = 0xe4;
#define CADSE 0
#define CADSI0 1
#define CADSI1 2
#define CADAS0 3
#define CADAS1 4
#define CADUB 5
#define CADEN 7

sfrb CADAC3 = 0xe3;
#define CADAC24 0
#define CADAC25 1
#define CADAC26 2
#define CADAC27 3
#define CADAC28 4
#define CADAC29 5
#define CADAC30 6
#define CADAC31 7

sfrb CADAC2 = 0xe2;
#define CADAC16 0
#define CADAC17 1
#define CADAC18 2
#define CADAC19 3
#define CADAC20 4
#define CADAC21 5
#define CADAC22 6
#define CADAC23 7

sfrb CADAC1 = 0xe1;
#define CADAC08 0
#define CADAC09 1
#define CADAC10 2
#define CADAC11 3
#define CADAC12 4
#define CADAC13 5
#define CADAC14 6
#define CADAC15 7

sfrb CADAC0 = 0xe0;
#define CADAC00 0
#define CADAC01 1
#define CADAC02 2
#define CADAC03 3
#define CADAC04 4
#define CADAC05 5
#define CADAC06 6
#define CADAC07 7

sfrb BGCRR = 0xd1;
#define BGCR0 0
#define BGCR1 1
#define BGCR2 2
#define BGCR3 3
#define BGCR4 4
#define BGCR5 5
#define BGCR6 6
#define BGCR7 7

sfrb BGCCR = 0xd0;
#define BGCC0 0
#define BGCC1 1
#define BGCC2 2
#define BGCC3 3
#define BGCC4 4
#define BGCC5 5
#define BGEN 7

sfrb CCSR = 0xc0;
#define ACS 0
#define XOE 1

sfrb TWBCSR = 0xbe;
#define TWBCIP 0
#define TWBDT0 1
#define TWBDT1 2
#define TWBCIE 6
#define TWBCIF 7

sfrb TWAMR = 0xbd;
#define TWAM0 1
#define TWAM1 2
#define TWAM2 3
#define TWAM3 4
#define TWAM4 5
#define TWAM5 6
#define TWAM6 7

sfrb TWCR = 0xbc;
#define TWIE 0
#define TWEN 2
#define TWWC 3
#define TWSTO 4
#define TWSTA 5
#define TWEA 6
#define TWINT 7

sfrb TWDR = 0xbb;
#define TWD0 0
#define TWD1 1
#define TWD2 2
#define TWD3 3
#define TWD4 4
#define TWD5 5
#define TWD6 6
#define TWD7 7

sfrb TWAR = 0xba;
#define TWGCE 0
#define TWA0 1
#define TWA1 2
#define TWA2 3
#define TWA3 4
#define TWA4 5
#define TWA5 6
#define TWA6 7

sfrb TWSR = 0xb9;
#define TWPS0 0
#define TWPS1 1
#define TWS3 3
#define TWS4 4
#define TWS5 5
#define TWS6 6
#define TWS7 7

sfrb TWBR = 0xb8;
#define TWBR0 0
#define TWBR1 1
#define TWBR2 2
#define TWBR3 3
#define TWBR4 4
#define TWBR5 5
#define TWBR6 6
#define TWBR7 7

sfrb OCR1AH = 0x89;
#define OCR1AH0 0
#define OCR1AH1 1
#define OCR1AH2 2
#define OCR1AH3 3
#define OCR1AH4 4
#define OCR1AH5 5
#define OCR1AH6 6
#define OCR1AH7 7

sfrb OCR1AL = 0x88;
#define OCR1AL0 0
#define OCR1AL1 1
#define OCR1AL2 2
#define OCR1AL3 3
#define OCR1AL4 4
#define OCR1AL5 5
#define OCR1AL6 6
#define OCR1AL7 7

sfrw OCR1AW = 0x88;

sfrb TCNT1H = 0x85;
#define TCNT1H0 0
#define TCNT1H1 1
#define TCNT1H2 2
#define TCNT1H3 3
#define TCNT1H4 4
#define TCNT1H5 5
#define TCNT1H6 6
#define TCNT1H7 7

sfrb TCNT1L = 0x84;
#define TCNT1L0 0
#define TCNT1L1 1
#define TCNT1L2 2
#define TCNT1L3 3
#define TCNT1L4 4
#define TCNT1L5 5
#define TCNT1L6 6
#define TCNT1L7 7

sfrw TCNT1W = 0x84;

sfrb TCCR1B = 0x81;
#define CS10 0
#define CS11 1
#define CS12 2
#define CTC1 3

sfrb DIDR0 = 0x7e;
#define VADC0D 0
#define VADC1D 1
#define VADC2D 2
#define VADC3D 3

sfrb VADMUX = 0x7c;
#define VADMUX0 0
#define VADMUX1 1
#define VADMUX2 2
#define VADMUX3 3

sfrb VADCSR = 0x7a;
#define VADCCIE 0
#define VADCCIF 1
#define VADSC 2
#define VADEN 3

sfrb VADCH = 0x79;
#define VADCH0 0
#define VADCH1 1
#define VADCH2 2
#define VADCH3 3

sfrb VADCL = 0x78;
#define VADCL0 0
#define VADCL1 1
#define VADCL2 2
#define VADCL3 3
#define VADCL4 4
#define VADCL5 5
#define VADCL6 6
#define VADCL7 7

sfrw VADCW = 0x78;

sfrb TIMSK1 = 0x6f;
#define TOIE1 0
#define OCIE1A 1

sfrb TIMSK0 = 0x6e;
#define TOIE0 0
#define OCIE0A 1
#define OCIE0B 2

sfrb PCMSK1 = 0x6c;
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCINT15 7

sfrb PCMSK0 = 0x6b;
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7

sfrb EICRA = 0x69;
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
#define ISC20 4
#define ISC21 5
#define ISC30 6
#define ISC31 7

sfrb PCICR = 0x68;
#define PCIE0 0
#define PCIE1 1

sfrb FOSCCAL = 0x66;
#define FCAL0 0
#define FCAL1 1
#define FCAL2 2
#define FCAL3 3
#define FCAL4 4
#define FCAL5 5
#define FCAL6 6
#define FCAL7 7

sfrb PRR0 = 0x64;
#define PRVADC 0
#define PRTIM0 1
#define PRTIM1 2
#define PRTWI 3

sfrb WUTCSR = 0x62;
#define WUTP0 0
#define WUTP1 1
#define WUTP2 2
#define WUTE 3
#define WUTR 4
#define WUTCF 5
#define WUTIE 6
#define WUTIF 7

sfrb WDTCSR = 0x60;
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDE 3
#define WDCE 4
#define WDP3 5
#define WDIE 6
#define WDIF 7

sfrb SREG = 0x5f;

sfrb SPH = 0x5e;
#define SP8 0
#define SP9 1
#define SP10 2
#define SP11 3
#define SP12 4
#define SP13 5
#define SP14 6
#define SP15 7

sfrb SPL = 0x5d;
#define SP0 0
#define SP1 1
#define SP2 2
#define SP3 3
#define SP4 4
#define SP5 5
#define SP6 6
#define SP7 7

sfrw SPW = 0x5d;

sfrb SPMCSR = 0x57;
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define SIGRD 5
#define RWWSB 6
#define SPMIE 7

sfrb MCUCR = 0x55;
#define IVCE 0
#define IVSEL 1
#define PUD 4
#define JTD 7

sfrb MCUSR = 0x54;
#define PORF 0
#define EXTRF 1
#define BODRF 2
#define WDRF 3
#define JTRF 4

sfrb SMCR = 0x53;
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3

sfrb OCDR = 0x51;

sfrb GPIOR2 = 0x4b;
#define GPIOR20 0
#define GPIOR21 1
#define GPIOR22 2
#define GPIOR23 3
#define GPIOR24 4
#define GPIOR25 5
#define GPIOR26 6
#define GPIOR27 7

sfrb GPIOR1 = 0x4a;
#define GPIOR10 0
#define GPIOR11 1
#define GPIOR12 2
#define GPIOR13 3
#define GPIOR14 4
#define GPIOR15 5
#define GPIOR16 6
#define GPIOR17 7

sfrb OCR0B = 0x48;
#define OCR0B0 0
#define OCR0B1 1
#define OCR0B2 2
#define OCR0B3 3
#define OCR0B4 4
#define OCR0B5 5
#define OCR0B6 6
#define OCR0B7 7

sfrb OCR0A = 0x47;
#define OCR0A0 0
#define OCR0A1 1
#define OCR0A2 2
#define OCR0A3 3
#define OCR0A4 4
#define OCR0A5 5
#define OCR0A6 6
#define OCR0A7 7

sfrb TCNT0 = 0x46;
#define TCNT00 0
#define TCNT01 1
#define TCNT02 2
#define TCNT03 3
#define TCNT04 4
#define TCNT05 5
#define TCNT06 6
#define TCNT07 7

sfrb TCCR0B = 0x45;
#define CS00 0
#define CS01 1
#define CS02 2
#define WGM02 3
#define FOC0B 6
#define FOC0A 7

sfrb TCCR0A = 0x44;
#define WGM00 0
#define WGM01 1
#define COM0B0 4
#define COM0B1 5
#define COM0A0 6
#define COM0A1 7

sfrb GTCCR = 0x43;
#define PSRSYNC 0
#define PSRASY 1
#define TSM 7

sfrb EEARH = 0x42;
#define EEAR8 0

sfrb EEARL = 0x41;
#define EEAR0 0
#define EEAR1 1
#define EEAR2 2
#define EEAR3 3
#define EEAR4 4
#define EEAR5 5
#define EEAR6 6
#define EEAR7 7

sfrw EEARW = 0x41;

sfrb EEDR = 0x40;
#define EEDR0 0
#define EEDR1 1
#define EEDR2 2
#define EEDR3 3
#define EEDR4 4
#define EEDR5 5
#define EEDR6 6
#define EEDR7 7

sfrb EECR = 0x3f;
#define EERE 0
#define EEWE 1
#define EEMWE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5

sfrb GPIOR0 = 0x3e;
#define GPIOR00 0
#define GPIOR01 1
#define GPIOR02 2
#define GPIOR03 3
#define GPIOR04 4
#define GPIOR05 5
#define GPIOR06 6
#define GPIOR07 7

sfrb EIMSK = 0x3d;
#define INT0 0
#define INT1 1
#define INT2 2
#define INT3 3

sfrb EIFR = 0x3c;
#define INTF0 0
#define INTF1 1
#define INTF2 2
#define INTF3 3

sfrb PCIFR = 0x3b;
#define PCIF0 0
#define PCIF1 1

sfrb TIFR1 = 0x36;
#define TOV1 0
#define OCF1A 1

sfrb TIFR0 = 0x35;
#define TOV0 0
#define OCF0A 1
#define OCF0B 2

sfrb PORTD = 0x2b;
#define PORTD0 0
#define PORTD1 1

sfrb DDRD = 0x2a;
#define DDD0 0
#define DDD1 1

sfrb PIND = 0x29;
#define PIND0 0
#define PIND1 1

sfrb PORTC = 0x28;
#define PORTC0 0

sfrb PORTB = 0x25;
#define PORTB0 0
#define PORTB1 1
#define PORTB2 2
#define PORTB3 3
#define PORTB4 4
#define PORTB5 5
#define PORTB6 6
#define PORTB7 7

sfrb DDRB = 0x24;
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3
#define DDB4 4
#define DDB5 5
#define DDB6 6
#define DDB7 7

sfrb PINB = 0x23;
#define PINB0 0
#define PINB1 1
#define PINB2 2
#define PINB3 3
#define PINB4 4
#define PINB5 5
#define PINB6 6
#define PINB7 7

sfrb PORTA = 0x22;
#define PORTA0 0
#define PORTA1 1
#define PORTA2 2
#define PORTA3 3
#define PORTA4 4
#define PORTA5 5
#define PORTA6 6
#define PORTA7 7

sfrb DDRA = 0x21;
#define DDA0 0
#define DDA1 1
#define DDA2 2
#define DDA3 3
#define DDA4 4
#define DDA5 5
#define DDA6 6
#define DDA7 7

sfrb PINA = 0x20;
#define PINA0 0
#define PINA1 1
#define PINA2 2
#define PINA3 3
#define PINA4 4
#define PINA5 5
#define PINA6 6
#define PINA7 7

#endif