#ifndef __ATmega2560_h
#define __ATmega2560_h

// Interrupt vectors

#define RESET_vect 0x0000
#define INT0_vect 0x0004
#define INT1_vect 0x0008
#define INT2_vect 0x000c
#define INT3_vect 0x0010
#define INT4_vect 0x0014
#define INT5_vect 0x0018
#define INT6_vect 0x001c
#define INT7_vect 0x0020
#define PCINT0_vect 0x0024
#define PCINT1_vect 0x0028
#define PCINT2_vect 0x002c
#define WDT_vect 0x0030
#define TIMER2_COMPA_vect 0x0034
#define TIMER2_COMPB_vect 0x0038
#define TIMER2_OVF_vect 0x003c
#define TIMER1_CAPT_vect 0x0040
#define TIMER1_COMPA_vect 0x0044
#define TIMER1_COMPB_vect 0x0048
#define TIMER1_COMPC_vect 0x004c
#define TIMER1_OVF_vect 0x0050
#define TIMER0_COMPA_vect 0x0054
#define TIMER0_COMPB_vect 0x0058
#define TIMER0_OVF_vect 0x005c
#define SPI_STC_vect 0x0060
#define USART0_RX_vect 0x0064
#define USART0_UDRE_vect 0x0068
#define USART0_TX_vect 0x006c
#define ANALOG_COMP_vect 0x0070
#define ADC_vect 0x0074
#define EE_READY_vect 0x0078
#define TIMER3_CAPT_vect 0x007c
#define TIMER3_COMPA_vect 0x0080
#define TIMER3_COMPB_vect 0x0084
#define TIMER3_COMPC_vect 0x0088
#define TIMER3_OVF_vect 0x008c
#define USART1_RX_vect 0x0090
#define USART1_UDRE_vect 0x0094
#define USART1_TX_vect 0x0098
#define TWI_vect 0x009c
#define SPM_READY_vect 0x00a0
#define TIMER4_CAPT_vect 0x00a4
#define TIMER4_COMPA_vect 0x00a8
#define TIMER4_COMPB_vect 0x00ac
#define TIMER4_COMPC_vect 0x00b0
#define TIMER4_OVF_vect 0x00b4
#define TIMER5_CAPT_vect 0x00b8
#define TIMER5_COMPA_vect 0x00bc
#define TIMER5_COMPB_vect 0x00c0
#define TIMER5_COMPC_vect 0x00c4
#define TIMER5_OVF_vect 0x00c8
#define USART2_RX_vect 0x00cc
#define USART2_UDRE_vect 0x00d0
#define USART2_TX_vect 0x00d4
#define USART3_RX_vect 0x00d8
#define USART3_UDRE_vect 0x00dc
#define USART3_TX_vect 0x00e0

// I/O addresses


sfrb UDR3 = 0x136;
#define UDR3_0 0
#define UDR3_1 1
#define UDR3_2 2
#define UDR3_3 3
#define UDR3_4 4
#define UDR3_5 5
#define UDR3_6 6
#define UDR3_7 7

sfrb UBRR3H = 0x135;
#define UBRR8 0
#define UBRR9 1
#define UBRR10 2
#define UBRR11 3

sfrb UBRR3L = 0x134;
#define UBRR0 0
#define UBRR1 1
#define UBRR2 2
#define UBRR3 3
#define UBRR4 4
#define UBRR5 5
#define UBRR6 6
#define UBRR7 7

sfrw UBRR3W = 0x134;

sfrb UCSR3C = 0x132;
#define UCPOL3 0
#define UCSZ30_UCPHA3 1
#define UCSZ31_UDORD3 2
#define USBS3 3
#define UPM30 4
#define UPM31 5
#define UMSEL30 6
#define UMSEL31 7

sfrb UCSR3B = 0x131;
#define TXB83 0
#define RXB83 1
#define UCSZ32 2
#define TXEN3 3
#define RXEN3 4
#define UDRIE3 5
#define TXCIE3 6
#define RXCIE3 7

sfrb UCSR3A = 0x130;
#define MPCM3 0
#define U2X3 1
#define UPE3 2
#define DOR3 3
#define FE3 4
#define UDRE3 5
#define TXC3 6
#define RXC3 7

sfrb OCR5CH = 0x12d;
#define OCR5CH0 0
#define OCR5CH1 1
#define OCR5CH2 2
#define OCR5CH3 3
#define OCR5CH4 4
#define OCR5CH5 5
#define OCR5CH6 6
#define OCR5CH7 7

sfrb OCR5CL = 0x12c;
#define OCR5CL0 0
#define OCR5CL1 1
#define OCR5CL2 2
#define OCR5CL3 3
#define OCR5CL4 4
#define OCR5CL5 5
#define OCR5CL6 6
#define OCR5CL7 7

sfrw OCR5CW = 0x12c;

sfrb OCR5BH = 0x12b;
#define OCR5BH0 0
#define OCR5BH1 1
#define OCR5BH2 2
#define OCR5BH3 3
#define OCR5BH4 4
#define OCR5BH5 5
#define OCR5BH6 6
#define OCR5BH7 7

sfrb OCR5BL = 0x12a;
#define OCR5BL0 0
#define OCR5BL1 1
#define OCR5BL2 2
#define OCR5BL3 3
#define OCR5BL4 4
#define OCR5BL5 5
#define OCR5BL6 6
#define OCR5BL7 7

sfrw OCR5BW = 0x12a;

sfrb OCR5AH = 0x129;
#define OCR5AH0 0
#define OCR5AH1 1
#define OCR5AH2 2
#define OCR5AH3 3
#define OCR5AH4 4
#define OCR5AH5 5
#define OCR5AH6 6
#define OCR5AH7 7

sfrb OCR5AL = 0x128;
#define OCR5AL0 0
#define OCR5AL1 1
#define OCR5AL2 2
#define OCR5AL3 3
#define OCR5AL4 4
#define OCR5AL5 5
#define OCR5AL6 6
#define OCR5AL7 7

sfrw OCR5AW = 0x128;

sfrb ICR5H = 0x127;
#define ICR5H0 0
#define ICR5H1 1
#define ICR5H2 2
#define ICR5H3 3
#define ICR5H4 4
#define ICR5H5 5
#define ICR5H6 6
#define ICR5H7 7

sfrb ICR5L = 0x126;
#define ICR5L0 0
#define ICR5L1 1
#define ICR5L2 2
#define ICR5L3 3
#define ICR5L4 4
#define ICR5L5 5
#define ICR5L6 6
#define ICR5L7 7

sfrw ICR5W = 0x126;

sfrb TCNT5H = 0x125;
#define TCNT5H0 0
#define TCNT5H1 1
#define TCNT5H2 2
#define TCNT5H3 3
#define TCNT5H4 4
#define TCNT5H5 5
#define TCNT5H6 6
#define TCNT5H7 7

sfrb TCNT5L = 0x124;
#define TCNT5L0 0
#define TCNT5L1 1
#define TCNT5L2 2
#define TCNT5L3 3
#define TCNT5L4 4
#define TCNT5L5 5
#define TCNT5L6 6
#define TCNT5L7 7

sfrw TCNT5W = 0x124;

sfrb TCCR5C = 0x122;
#define FOC5C 5
#define FOC5B 6
#define FOC5A 7

sfrb TCCR5B = 0x121;
#define CS50 0
#define CS51 1
#define CS52 2
#define WGM52 3
#define WGM53 4
#define ICES5 6
#define ICNC5 7

sfrb TCCR5A = 0x120;
#define WGM50 0
#define WGM51 1
#define COM5C0 2
#define COM5C1 3
#define COM5B0 4
#define COM5B1 5
#define COM5A0 6
#define COM5A1 7

sfrb PORTL = 0x10b;
#define PORTL0 0
#define PORTL1 1
#define PORTL2 2
#define PORTL3 3
#define PORTL4 4
#define PORTL5 5
#define PORTL6 6
#define PORTL7 7

sfrb DDRL = 0x10a;
#define DDL0 0
#define DDL1 1
#define DDL2 2
#define DDL3 3
#define DDL4 4
#define DDL5 5
#define DDL6 6
#define DDL7 7

sfrb PINL = 0x109;
#define PINL0 0
#define PINL1 1
#define PINL2 2
#define PINL3 3
#define PINL4 4
#define PINL5 5
#define PINL6 6
#define PINL7 7

sfrb PORTK = 0x108;
#define PORTK0 0
#define PORTK1 1
#define PORTK2 2
#define PORTK3 3
#define PORTK4 4
#define PORTK5 5
#define PORTK6 6
#define PORTK7 7

sfrb DDRK = 0x107;
#define DDK0 0
#define DDK1 1
#define DDK2 2
#define DDK3 3
#define DDK4 4
#define DDK5 5
#define DDK6 6
#define DDK7 7

sfrb PINK = 0x106;
#define PINK0 0
#define PINK1 1
#define PINK2 2
#define PINK3 3
#define PINK4 4
#define PINK5 5
#define PINK6 6
#define PINK7 7

sfrb PORTJ = 0x105;
#define PORTJ0 0
#define PORTJ1 1
#define PORTJ2 2
#define PORTJ3 3
#define PORTJ4 4
#define PORTJ5 5
#define PORTJ6 6
#define PORTJ7 7

sfrb DDRJ = 0x104;
#define DDJ0 0
#define DDJ1 1
#define DDJ2 2
#define DDJ3 3
#define DDJ4 4
#define DDJ5 5
#define DDJ6 6
#define DDJ7 7

sfrb PINJ = 0x103;
#define PINJ0 0
#define PINJ1 1
#define PINJ2 2
#define PINJ3 3
#define PINJ4 4
#define PINJ5 5
#define PINJ6 6
#define PINJ7 7

sfrb PORTH = 0x102;
#define PORTH0 0
#define PORTH1 1
#define PORTH2 2
#define PORTH3 3
#define PORTH4 4
#define PORTH5 5
#define PORTH6 6
#define PORTH7 7

sfrb DDRH = 0x101;
#define DDH0 0
#define DDH1 1
#define DDH2 2
#define DDH3 3
#define DDH4 4
#define DDH5 5
#define DDH6 6
#define DDH7 7

sfrb PINH = 0x100;
#define PINH0 0
#define PINH1 1
#define PINH2 2
#define PINH3 3
#define PINH4 4
#define PINH5 5
#define PINH6 6
#define PINH7 7

sfrb UDR2 = 0xd6;
#define UDR2_0 0
#define UDR2_1 1
#define UDR2_2 2
#define UDR2_3 3
#define UDR2_4 4
#define UDR2_5 5
#define UDR2_6 6
#define UDR2_7 7

sfrb UBRR2H = 0xd5;
#define UBRR8 0
#define UBRR9 1
#define UBRR10 2
#define UBRR11 3

sfrb UBRR2L = 0xd4;
#define UBRR0 0
#define UBRR1 1
#define UBRR2 2
#define UBRR3 3
#define UBRR4 4
#define UBRR5 5
#define UBRR6 6
#define UBRR7 7

sfrw UBRR2W = 0xd4;

sfrb UCSR2C = 0xd2;
#define UCPOL2 0
#define UCSZ20_UCPHA2 1
#define UCSZ21_UDORD2 2
#define USBS2 3
#define UPM20 4
#define UPM21 5
#define UMSEL20 6
#define UMSEL21 7

sfrb UCSR2B = 0xd1;
#define TXB82 0
#define RXB82 1
#define UCSZ22 2
#define TXEN2 3
#define RXEN2 4
#define UDRIE2 5
#define TXCIE2 6
#define RXCIE2 7

sfrb UCSR2A = 0xd0;
#define MPCM2 0
#define U2X2 1
#define UPE2 2
#define DOR2 3
#define FE2 4
#define UDRE2 5
#define TXC2 6
#define RXC2 7

sfrb UDR1 = 0xce;
#define UDR1_0 0
#define UDR1_1 1
#define UDR1_2 2
#define UDR1_3 3
#define UDR1_4 4
#define UDR1_5 5
#define UDR1_6 6
#define UDR1_7 7

sfrb UBRR1H = 0xcd;
#define UBRR8 0
#define UBRR9 1
#define UBRR10 2
#define UBRR11 3

sfrb UBRR1L = 0xcc;
#define UBRR0 0
#define UBRR1 1
#define UBRR2 2
#define UBRR3 3
#define UBRR4 4
#define UBRR5 5
#define UBRR6 6
#define UBRR7 7

sfrw UBRR1W = 0xcc;

sfrb UCSR1C = 0xca;
#define UCPOL1 0
#define UCSZ10_UCPHA1 1
#define UCSZ11_UDORD1 2
#define USBS1 3
#define UPM10 4
#define UPM11 5
#define UMSEL10 6
#define UMSEL11 7

sfrb UCSR1B = 0xc9;
#define TXB81 0
#define RXB81 1
#define UCSZ12 2
#define TXEN1 3
#define RXEN1 4
#define UDRIE1 5
#define TXCIE1 6
#define RXCIE1 7

sfrb UCSR1A = 0xc8;
#define MPCM1 0
#define U2X1 1
#define UPE1 2
#define DOR1 3
#define FE1 4
#define UDRE1 5
#define TXC1 6
#define RXC1 7

sfrb UDR0 = 0xc6;
#define UDR0_0 0
#define UDR0_1 1
#define UDR0_2 2
#define UDR0_3 3
#define UDR0_4 4
#define UDR0_5 5
#define UDR0_6 6
#define UDR0_7 7

sfrb UBRR0H = 0xc5;
#define UBRR8 0
#define UBRR9 1
#define UBRR10 2
#define UBRR11 3

sfrb UBRR0L = 0xc4;
#define UBRR0 0
#define UBRR1 1
#define UBRR2 2
#define UBRR3 3
#define UBRR4 4
#define UBRR5 5
#define UBRR6 6
#define UBRR7 7

sfrw UBRR0W = 0xc4;

sfrb UCSR0C = 0xc2;
#define UCPOL0 0
#define UCSZ00 1
#define UCSZ01 2
#define USBS0 3
#define UPM00 4
#define UPM01 5
#define UMSEL00 6
#define UMSEL01 7

sfrb UCSR0B = 0xc1;
#define TXB80 0
#define RXB80 1
#define UCSZ02 2
#define TXEN0 3
#define RXEN0 4
#define UDRIE0 5
#define TXCIE0 6
#define RXCIE0 7

sfrb UCSR0A = 0xc0;
#define MPCM0 0
#define U2X0 1
#define UPE0 2
#define DOR0 3
#define FE0 4
#define UDRE0 5
#define TXC0 6
#define RXC0 7

sfrb TWAMR = 0xbd;
#define TWAM0 1
#define TWAM1 2
#define TWAM2 3
#define TWAM3 4
#define TWAM4 5
#define TWAM5 6
#define TWAM6 7

sfrb TWCR = 0xbc;
#define TWIE 0
#define TWEN 2
#define TWWC 3
#define TWSTO 4
#define TWSTA 5
#define TWEA 6
#define TWINT 7

sfrb TWDR = 0xbb;
#define TWD0 0
#define TWD1 1
#define TWD2 2
#define TWD3 3
#define TWD4 4
#define TWD5 5
#define TWD6 6
#define TWD7 7

sfrb TWAR = 0xba;
#define TWGCE 0
#define TWA0 1
#define TWA1 2
#define TWA2 3
#define TWA3 4
#define TWA4 5
#define TWA5 6
#define TWA6 7

sfrb TWSR = 0xb9;
#define TWPS0 0
#define TWPS1 1
#define TWS3 3
#define TWS4 4
#define TWS5 5
#define TWS6 6
#define TWS7 7

sfrb TWBR = 0xb8;
#define TWBR0 0
#define TWBR1 1
#define TWBR2 2
#define TWBR3 3
#define TWBR4 4
#define TWBR5 5
#define TWBR6 6
#define TWBR7 7

sfrb ASSR = 0xb6;
#define TCR2BUB 0
#define TCR2AUB 1
#define OCR2BUB 2
#define OCR2AUB 3
#define TCN2UB 4
#define AS2 5
#define EXCLK 6

sfrb OCR2B = 0xb4;
#define OCR2_0 0
#define OCR2_1 1
#define OCR2_2 2
#define OCR2_3 3
#define OCR2_4 4
#define OCR2_5 5
#define OCR2_6 6
#define OCR2_7 7

sfrb OCR2A = 0xb3;
#define OCR2_0 0
#define OCR2_1 1
#define OCR2_2 2
#define OCR2_3 3
#define OCR2_4 4
#define OCR2_5 5
#define OCR2_6 6
#define OCR2_7 7

sfrb TCNT2 = 0xb2;
#define TCNT2_0 0
#define TCNT2_1 1
#define TCNT2_2 2
#define TCNT2_3 3
#define TCNT2_4 4
#define TCNT2_5 5
#define TCNT2_6 6
#define TCNT2_7 7

sfrb TCCR2B = 0xb1;
#define CS20 0
#define CS21 1
#define CS22 2
#define WGM22 3
#define FOC2B 6
#define FOC2A 7

sfrb TCCR2A = 0xb0;
#define WGM20 0
#define WGM21 1
#define COM2B0 4
#define COM2B1 5
#define COM2A0 6
#define COM2A1 7

sfrb OCR4CH = 0xad;
#define OCR4CH0 0
#define OCR4CH1 1
#define OCR4CH2 2
#define OCR4CH3 3
#define OCR4CH4 4
#define OCR4CH5 5
#define OCR4CH6 6
#define OCR4CH7 7

sfrb OCR4CL = 0xac;
#define OCR4CL0 0
#define OCR4CL1 1
#define OCR4CL2 2
#define OCR4CL3 3
#define OCR4CL4 4
#define OCR4CL5 5
#define OCR4CL6 6
#define OCR4CL7 7

sfrw OCR4CW = 0xac;

sfrb OCR4BH = 0xab;
#define OCR4BH0 0
#define OCR4BH1 1
#define OCR4BH2 2
#define OCR4BH3 3
#define OCR4BH4 4
#define OCR4BH5 5
#define OCR4BH6 6
#define OCR4BH7 7

sfrb OCR4BL = 0xaa;
#define OCR4BL0 0
#define OCR4BL1 1
#define OCR4BL2 2
#define OCR4BL3 3
#define OCR4BL4 4
#define OCR4BL5 5
#define OCR4BL6 6
#define OCR4BL7 7

sfrw OCR4BW = 0xaa;

sfrb OCR4AH = 0xa9;
#define OCR4AH0 0
#define OCR4AH1 1
#define OCR4AH2 2
#define OCR4AH3 3
#define OCR4AH4 4
#define OCR4AH5 5
#define OCR4AH6 6
#define OCR4AH7 7

sfrb OCR4AL = 0xa8;
#define OCR4AL0 0
#define OCR4AL1 1
#define OCR4AL2 2
#define OCR4AL3 3
#define OCR4AL4 4
#define OCR4AL5 5
#define OCR4AL6 6
#define OCR4AL7 7

sfrw OCR4AW = 0xa8;

sfrb ICR4H = 0xa7;
#define ICR4H0 0
#define ICR4H1 1
#define ICR4H2 2
#define ICR4H3 3
#define ICR4H4 4
#define ICR4H5 5
#define ICR4H6 6
#define ICR4H7 7

sfrb ICR4L = 0xa6;
#define ICR4L0 0
#define ICR4L1 1
#define ICR4L2 2
#define ICR4L3 3
#define ICR4L4 4
#define ICR4L5 5
#define ICR4L6 6
#define ICR4L7 7

sfrw ICR4W = 0xa6;

sfrb TCNT4H = 0xa5;
#define TCNT4H0 0
#define TCNT4H1 1
#define TCNT4H2 2
#define TCNT4H3 3
#define TCNT4H4 4
#define TCNT4H5 5
#define TCNT4H6 6
#define TCNT4H7 7

sfrb TCNT4L = 0xa4;
#define TCNT4L0 0
#define TCNT4L1 1
#define TCNT4L2 2
#define TCNT4L3 3
#define TCNT4L4 4
#define TCNT4L5 5
#define TCNT4L6 6
#define TCNT4L7 7

sfrw TCNT4W = 0xa4;

sfrb TCCR4C = 0xa2;
#define FOC4C 5
#define FOC4B 6
#define FOC4A 7

sfrb TCCR4B = 0xa1;
#define CS40 0
#define CS41 1
#define CS42 2
#define WGM42 3
#define WGM43 4
#define ICES4 6
#define ICNC4 7

sfrb TCCR4A = 0xa0;
#define WGM40 0
#define WGM41 1
#define COM4C0 2
#define COM4C1 3
#define COM4B0 4
#define COM4B1 5
#define COM4A0 6
#define COM4A1 7

sfrb OCR3CH = 0x9d;
#define OCR3CH0 0
#define OCR3CH1 1
#define OCR3CH2 2
#define OCR3CH3 3
#define OCR3CH4 4
#define OCR3CH5 5
#define OCR3CH6 6
#define OCR3CH7 7

sfrb OCR3CL = 0x9c;
#define OCR3CL0 0
#define OCR3CL1 1
#define OCR3CL2 2
#define OCR3CL3 3
#define OCR3CL4 4
#define OCR3CL5 5
#define OCR3CL6 6
#define OCR3CL7 7

sfrw OCR3CW = 0x9c;

sfrb OCR3BH = 0x9b;
#define OCR3BH0 0
#define OCR3BH1 1
#define OCR3BH2 2
#define OCR3BH3 3
#define OCR3BH4 4
#define OCR3BH5 5
#define OCR3BH6 6
#define OCR3BH7 7

sfrb OCR3BL = 0x9a;
#define OCR3BL0 0
#define OCR3BL1 1
#define OCR3BL2 2
#define OCR3BL3 3
#define OCR3BL4 4
#define OCR3BL5 5
#define OCR3BL6 6
#define OCR3BL7 7

sfrw OCR3BW = 0x9a;

sfrb OCR3AH = 0x99;
#define OCR3AH0 0
#define OCR3AH1 1
#define OCR3AH2 2
#define OCR3AH3 3
#define OCR3AH4 4
#define OCR3AH5 5
#define OCR3AH6 6
#define OCR3AH7 7

sfrb OCR3AL = 0x98;
#define OCR3AL0 0
#define OCR3AL1 1
#define OCR3AL2 2
#define OCR3AL3 3
#define OCR3AL4 4
#define OCR3AL5 5
#define OCR3AL6 6
#define OCR3AL7 7

sfrw OCR3AW = 0x98;

sfrb ICR3H = 0x97;
#define ICR3H0 0
#define ICR3H1 1
#define ICR3H2 2
#define ICR3H3 3
#define ICR3H4 4
#define ICR3H5 5
#define ICR3H6 6
#define ICR3H7 7

sfrb ICR3L = 0x96;
#define ICR3L0 0
#define ICR3L1 1
#define ICR3L2 2
#define ICR3L3 3
#define ICR3L4 4
#define ICR3L5 5
#define ICR3L6 6
#define ICR3L7 7

sfrw ICR3W = 0x96;

sfrb TCNT3H = 0x95;
#define TCNT3H0 0
#define TCNT3H1 1
#define TCNT3H2 2
#define TCNT3H3 3
#define TCNT3H4 4
#define TCNT3H5 5
#define TCNT3H6 6
#define TCNT3H7 7

sfrb TCNT3L = 0x94;
#define TCNT3L0 0
#define TCNT3L1 1
#define TCNT3L2 2
#define TCNT3L3 3
#define TCNT3L4 4
#define TCNT3L5 5
#define TCNT3L6 6
#define TCNT3L7 7

sfrw TCNT3W = 0x94;

sfrb TCCR3C = 0x92;
#define FOC3C 5
#define FOC3B 6
#define FOC3A 7

sfrb TCCR3B = 0x91;
#define CS30 0
#define CS31 1
#define CS32 2
#define WGM32 3
#define WGM33 4
#define ICES3 6
#define ICNC3 7

sfrb TCCR3A = 0x90;
#define WGM30 0
#define WGM31 1
#define COM3C0 2
#define COM3C1 3
#define COM3B0 4
#define COM3B1 5
#define COM3A0 6
#define COM3A1 7

sfrb OCR1CH = 0x8d;
#define OCR1CH0 0
#define OCR1CH1 1
#define OCR1CH2 2
#define OCR1CH3 3
#define OCR1CH4 4
#define OCR1CH5 5
#define OCR1CH6 6
#define OCR1CH7 7

sfrb OCR1CL = 0x8c;
#define OCR1CL0 0
#define OCR1CL1 1
#define OCR1CL2 2
#define OCR1CL3 3
#define OCR1CL4 4
#define OCR1CL5 5
#define OCR1CL6 6
#define OCR1CL7 7

sfrw OCR1CW = 0x8c;

sfrb OCR1BH = 0x8b;
#define OCR1BH0 0
#define OCR1BH1 1
#define OCR1BH2 2
#define OCR1BH3 3
#define OCR1BH4 4
#define OCR1BH5 5
#define OCR1BH6 6
#define OCR1BH7 7

sfrb OCR1BL = 0x8a;
#define OCR1BL0 0
#define OCR1BL1 1
#define OCR1BL2 2
#define OCR1BL3 3
#define OCR1BL4 4
#define OCR1BL5 5
#define OCR1BL6 6
#define OCR1BL7 7

sfrw OCR1BW = 0x8a;

sfrb OCR1AH = 0x89;
#define OCR1AH0 0
#define OCR1AH1 1
#define OCR1AH2 2
#define OCR1AH3 3
#define OCR1AH4 4
#define OCR1AH5 5
#define OCR1AH6 6
#define OCR1AH7 7

sfrb OCR1AL = 0x88;
#define OCR1AL0 0
#define OCR1AL1 1
#define OCR1AL2 2
#define OCR1AL3 3
#define OCR1AL4 4
#define OCR1AL5 5
#define OCR1AL6 6
#define OCR1AL7 7

sfrw OCR1AW = 0x88;

sfrb ICR1H = 0x87;
#define ICR1H0 0
#define ICR1H1 1
#define ICR1H2 2
#define ICR1H3 3
#define ICR1H4 4
#define ICR1H5 5
#define ICR1H6 6
#define ICR1H7 7

sfrb ICR1L = 0x86;
#define ICR1L0 0
#define ICR1L1 1
#define ICR1L2 2
#define ICR1L3 3
#define ICR1L4 4
#define ICR1L5 5
#define ICR1L6 6
#define ICR1L7 7

sfrw ICR1W = 0x86;

sfrb TCNT1H = 0x85;
#define TCNT1H0 0
#define TCNT1H1 1
#define TCNT1H2 2
#define TCNT1H3 3
#define TCNT1H4 4
#define TCNT1H5 5
#define TCNT1H6 6
#define TCNT1H7 7

sfrb TCNT1L = 0x84;
#define TCNT1L0 0
#define TCNT1L1 1
#define TCNT1L2 2
#define TCNT1L3 3
#define TCNT1L4 4
#define TCNT1L5 5
#define TCNT1L6 6
#define TCNT1L7 7

sfrw TCNT1W = 0x84;

sfrb TCCR1C = 0x82;
#define FOC1C 5
#define FOC1B 6
#define FOC1A 7

sfrb TCCR1B = 0x81;
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM12 3
#define WGM13 4
#define ICES1 6
#define ICNC1 7

sfrb TCCR1A = 0x80;
#define WGM10 0
#define WGM11 1
#define COM1C0 2
#define COM1C1 3
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7

sfrb DIDR1 = 0x7f;
#define AIN0D 0
#define AIN1D 1

sfrb DIDR0 = 0x7e;
#define ADC0D 0
#define ADC1D 1
#define ADC2D 2
#define ADC3D 3
#define ADC4D 4
#define ADC5D 5
#define ADC6D 6
#define ADC7D 7

sfrb DIDR2 = 0x7d;
#define ADC8D 0
#define ADC9D 1
#define ADC10D 2
#define ADC11D 3
#define ADC12D 4
#define ADC13D 5
#define ADC14D 6
#define ADC15D 7

sfrb ADMUX = 0x7c;
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define MUX4 4
#define ADLAR 5
#define REFS0 6
#define REFS1 7

sfrb ADCSRB = 0x7b;
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define MUX5 3
#define ACME 6

sfrb ADCSRA = 0x7a;
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7

sfrb ADCH = 0x79;
#define ADCH0 0
#define ADCH1 1
#define ADCH2 2
#define ADCH3 3
#define ADCH4 4
#define ADCH5 5
#define ADCH6 6
#define ADCH7 7

sfrb ADCL = 0x78;
#define ADCL0 0
#define ADCL1 1
#define ADCL2 2
#define ADCL3 3
#define ADCL4 4
#define ADCL5 5
#define ADCL6 6
#define ADCL7 7

sfrw ADCW = 0x78;

sfrb XMCRB = 0x75;
#define XMM0 0
#define XMM1 1
#define XMM2 2
#define XMBK 7

sfrb XMCRA = 0x74;
#define SRW00 0
#define SRW01 1
#define SRW10 2
#define SRW11 3
#define SRL0 4
#define SRL1 5
#define SRL2 6
#define SRE 7

sfrb TIMSK5 = 0x73;
#define TOIE5 0
#define OCIE5A 1
#define OCIE5B 2
#define OCIE5C 3
#define ICIE5 5

sfrb TIMSK4 = 0x72;
#define TOIE4 0
#define OCIE4A 1
#define OCIE4B 2
#define OCIE4C 3
#define ICIE4 5

sfrb TIMSK3 = 0x71;
#define TOIE3 0
#define OCIE3A 1
#define OCIE3B 2
#define OCIE3C 3
#define ICIE3 5

sfrb TIMSK2 = 0x70;
#define TOIE2 0
#define OCIE2A 1
#define OCIE2B 2

sfrb TIMSK1 = 0x6f;
#define TOIE1 0
#define OCIE1A 1
#define OCIE1B 2
#define OCIE1C 3
#define ICIE1 5

sfrb TIMSK0 = 0x6e;
#define TOIE0 0
#define OCIE0A 1
#define OCIE0B 2

sfrb PCMSK2 = 0x6d;
#define PCINT16 0
#define PCINT17 1
#define PCINT18 2
#define PCINT19 3
#define PCINT20 4
#define PCINT21 5
#define PCINT22 6
#define PCINT23 7

sfrb PCMSK1 = 0x6c;
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCINT15 7

sfrb PCMSK0 = 0x6b;
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7

sfrb EICRB = 0x6a;
#define ISC40 0
#define ISC41 1
#define ISC50 2
#define ISC51 3
#define ISC60 4
#define ISC61 5
#define ISC70 6
#define ISC71 7

sfrb EICRA = 0x69;
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
#define ISC20 4
#define ISC21 5
#define ISC30 6
#define ISC31 7

sfrb PCICR = 0x68;
#define PCIE0 0
#define PCIE1 1
#define PCIE2 2

sfrb OSCCAL = 0x66;
#define CAL0 0
#define CAL1 1
#define CAL2 2
#define CAL3 3
#define CAL4 4
#define CAL5 5
#define CAL6 6
#define CAL7 7

sfrb PRR1 = 0x65;
#define PRUSART1 0
#define PRUSART2 1
#define PRUSART3 2
#define PRTIM3 3
#define PRTIM4 4
#define PRTIM5 5

sfrb PRR0 = 0x64;
#define PRADC 0
#define PRUSART0 1
#define PRSPI 2
#define PRTIM1 3
#define PRTIM0 5
#define PRTIM2 6
#define PRTWI 7

sfrb CLKPR = 0x61;
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CPKPCE 7

sfrb WDTCSR = 0x60;
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDE 3
#define WDCE 4
#define WDP3 5
#define WDIE 6
#define WDIF 7

sfrb SREG = 0x5f;

sfrb SPH = 0x5e;
#define SP8 0
#define SP9 1
#define SP10 2
#define SP11 3
#define SP12 4
#define SP13 5
#define SP14 6
#define SP15 7

sfrb SPL = 0x5d;
#define SP0 0
#define SP1 1
#define SP2 2
#define SP3 3
#define SP4 4
#define SP5 5
#define SP6 6
#define SP7 7

sfrw SPW = 0x5d;

sfrb EIND = 0x5c;
#define EIND0 0

sfrb RAMPZ = 0x5b;
#define RAMPZ0 0
#define RAMPZ1 1

sfrb SPMCSR = 0x57;
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define SIGRD 5
#define RWWSB 6
#define SPMIE 7

sfrb MCUCR = 0x55;
#define IVCE 0
#define IVSEL 1
#define PUD 4
#define JTD 7

sfrb MCUSR = 0x54;
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define JTRF 4

sfrb SMCR = 0x53;
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3

sfrb OCDR = 0x51;
#define OCDR0 0
#define OCDR1 1
#define OCDR2 2
#define OCDR3 3
#define OCDR4 4
#define OCDR5 5
#define OCDR6 6
#define OCDR7 7

sfrb ACSR = 0x50;
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACBG 6
#define ACD 7

sfrb SPDR = 0x4e;
#define SPDR0 0
#define SPDR1 1
#define SPDR2 2
#define SPDR3 3
#define SPDR4 4
#define SPDR5 5
#define SPDR6 6
#define SPDR7 7

sfrb SPSR = 0x4d;
#define SPI2X 0
#define WCOL 6
#define SPIF 7

sfrb SPCR = 0x4c;
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7

sfrb GPIOR2 = 0x4b;
#define GPIOR20 0
#define GPIOR21 1
#define GPIOR22 2
#define GPIOR23 3
#define GPIOR24 4
#define GPIOR25 5
#define GPIOR26 6
#define GPIOR27 7

sfrb GPIOR1 = 0x4a;
#define GPIOR10 0
#define GPIOR11 1
#define GPIOR12 2
#define GPIOR13 3
#define GPIOR14 4
#define GPIOR15 5
#define GPIOR16 6
#define GPIOR17 7

sfrb OCR0B = 0x48;
#define OCR0B_0 0
#define OCR0B_1 1
#define OCR0B_2 2
#define OCR0B_3 3
#define OCR0B_4 4
#define OCR0B_5 5
#define OCR0B_6 6
#define OCR0B_7 7

sfrb OCR0A = 0x47;
#define OCROA_0 0
#define OCROA_1 1
#define OCROA_2 2
#define OCROA_3 3
#define OCROA_4 4
#define OCROA_5 5
#define OCROA_6 6
#define OCROA_7 7

sfrb TCNT0 = 0x46;
#define TCNT0_0 0
#define TCNT0_1 1
#define TCNT0_2 2
#define TCNT0_3 3
#define TCNT0_4 4
#define TCNT0_5 5
#define TCNT0_6 6
#define TCNT0_7 7

sfrb TCCR0B = 0x45;
#define CS00 0
#define CS01 1
#define CS02 2
#define WGM02 3
#define FOC0B 6
#define FOC0A 7

sfrb TCCR0A = 0x44;
#define WGM00 0
#define WGM01 1
#define COM0B0 4
#define COM0B1 5
#define COM0A0 6
#define COM0A1 7

sfrb GTCCR = 0x43;
#define PSRSYNC 0
#define PSRASY 1
#define TSM 7

sfrb EEARH = 0x42;
#define EEAR8 0
#define EEAR9 1
#define EEAR10 2
#define EEAR11 3

sfrb EEARL = 0x41;
#define EEAR0 0
#define EEAR1 1
#define EEAR2 2
#define EEAR3 3
#define EEAR4 4
#define EEAR5 5
#define EEAR6 6
#define EEAR7 7

sfrw EEARW = 0x41;

sfrb EEDR = 0x40;
#define EEDR0 0
#define EEDR1 1
#define EEDR2 2
#define EEDR3 3
#define EEDR4 4
#define EEDR5 5
#define EEDR6 6
#define EEDR7 7

sfrb EECR = 0x3f;
#define EERE 0
#define EEPE 1
#define EEMPE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5

sfrb GPIOR0 = 0x3e;
#define GPIOR00 0
#define GPIOR01 1
#define GPIOR02 2
#define GPIOR03 3
#define GPIOR04 4
#define GPIOR05 5
#define GPIOR06 6
#define GPIOR07 7

sfrb EIMSK = 0x3d;
#define INT0 0
#define INT1 1
#define INT2 2
#define INT3 3
#define INT4 4
#define INT5 5
#define INT6 6
#define INT7 7

sfrb EIFR = 0x3c;
#define INTF0 0
#define INTF1 1
#define INTF2 2
#define INTF3 3
#define INTF4 4
#define INTF5 5
#define INTF6 6
#define INTF7 7

sfrb PCIFR = 0x3b;
#define PCIF0 0
#define PCIF1 1
#define PCIF2 2

sfrb TIFR5 = 0x3a;
#define TOV5 0
#define OCF5A 1
#define OCF5B 2
#define OCF5C 3
#define ICF5 5

sfrb TIFR4 = 0x39;
#define TOV4 0
#define OCF4A 1
#define OCF4B 2
#define OCF4C 3
#define ICF4 5

sfrb TIFR3 = 0x38;
#define TOV3 0
#define OCF3A 1
#define OCF3B 2
#define OCF3C 3
#define ICF3 5

sfrb TIFR2 = 0x37;
#define TOV2 0
#define OCF2A 1
#define OCF2B 2

sfrb TIFR1 = 0x36;
#define TOV1 0
#define OCF1A 1
#define OCF1B 2
#define OCF1C 3
#define ICF1 5

sfrb TIFR0 = 0x35;
#define TOV0 0
#define OCF0A 1
#define OCF0B 2

sfrb PORTG = 0x34;
#define PORTG0 0
#define PORTG1 1
#define PORTG2 2
#define PORTG3 3
#define PORTG4 4
#define PORTG5 5

sfrb DDRG = 0x33;
#define DDG0 0
#define DDG1 1
#define DDG2 2
#define DDG3 3
#define DDG4 4
#define DDG5 5

sfrb PING = 0x32;
#define PING0 0
#define PING1 1
#define PING2 2
#define PING3 3
#define PING4 4
#define PING5 5

sfrb PORTF = 0x31;
#define PORTF0 0
#define PORTF1 1
#define PORTF2 2
#define PORTF3 3
#define PORTF4 4
#define PORTF5 5
#define PORTF6 6
#define PORTF7 7

sfrb DDRF = 0x30;
#define DDF0 0
#define DDF1 1
#define DDF2 2
#define DDF3 3
#define DDF4 4
#define DDF5 5
#define DDF6 6
#define DDF7 7

sfrb PINF = 0x2f;
#define PINF0 0
#define PINF1 1
#define PINF2 2
#define PINF3 3
#define PINF4 4
#define PINF5 5
#define PINF6 6
#define PINF7 7

sfrb PORTE = 0x2e;
#define PORTE0 0
#define PORTE1 1
#define PORTE2 2
#define PORTE3 3
#define PORTE4 4
#define PORTE5 5
#define PORTE6 6
#define PORTE7 7

sfrb DDRE = 0x2d;
#define DDE0 0
#define DDE1 1
#define DDE2 2
#define DDE3 3
#define DDE4 4
#define DDE5 5
#define DDE6 6
#define DDE7 7

sfrb PINE = 0x2c;
#define PINE0 0
#define PINE1 1
#define PINE2 2
#define PINE3 3
#define PINE4 4
#define PINE5 5
#define PINE6 6
#define PINE7 7

sfrb PORTD = 0x2b;
#define PORTD0 0
#define PORTD1 1
#define PORTD2 2
#define PORTD3 3
#define PORTD4 4
#define PORTD5 5
#define PORTD6 6
#define PORTD7 7

sfrb DDRD = 0x2a;
#define DDD0 0
#define DDD1 1
#define DDD2 2
#define DDD3 3
#define DDD4 4
#define DDD5 5
#define DDD6 6
#define DDD7 7

sfrb PIND = 0x29;
#define PIND0 0
#define PIND1 1
#define PIND2 2
#define PIND3 3
#define PIND4 4
#define PIND5 5
#define PIND6 6
#define PIND7 7

sfrb PORTC = 0x28;
#define PORTC0 0
#define PORTC1 1
#define PORTC2 2
#define PORTC3 3
#define PORTC4 4
#define PORTC5 5
#define PORTC6 6
#define PORTC7 7

sfrb DDRC = 0x27;
#define DDC0 0
#define DDC1 1
#define DDC2 2
#define DDC3 3
#define DDC4 4
#define DDC5 5
#define DDC6 6
#define DDC7 7

sfrb PINC = 0x26;
#define PINC0 0
#define PINC1 1
#define PINC2 2
#define PINC3 3
#define PINC4 4
#define PINC5 5
#define PINC6 6
#define PINC7 7

sfrb PORTB = 0x25;
#define PORTB0 0
#define PORTB1 1
#define PORTB2 2
#define PORTB3 3
#define PORTB4 4
#define PORTB5 5
#define PORTB6 6
#define PORTB7 7

sfrb DDRB = 0x24;
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3
#define DDB4 4
#define DDB5 5
#define DDB6 6
#define DDB7 7

sfrb PINB = 0x23;
#define PINB0 0
#define PINB1 1
#define PINB2 2
#define PINB3 3
#define PINB4 4
#define PINB5 5
#define PINB6 6
#define PINB7 7

sfrb PORTA = 0x22;
#define PORTA0 0
#define PORTA1 1
#define PORTA2 2
#define PORTA3 3
#define PORTA4 4
#define PORTA5 5
#define PORTA6 6
#define PORTA7 7

sfrb DDRA = 0x21;
#define DDA0 0
#define DDA1 1
#define DDA2 2
#define DDA3 3
#define DDA4 4
#define DDA5 5
#define DDA6 6
#define DDA7 7

sfrb PINA = 0x20;
#define PINA0 0
#define PINA1 1
#define PINA2 2
#define PINA3 3
#define PINA4 4
#define PINA5 5
#define PINA6 6
#define PINA7 7

#endif