#ifndef __ATmega161_h
#define __ATmega161_h

// Interrupt vectors

#define RESET_vect 0x0000
#define INT0_vect 0x0004
#define INT1_vect 0x0008
#define INT2_vect 0x000c
#define TIMER2_COMP_vect 0x0010
#define TIMER2_OVF_vect 0x0014
#define TIMER1_CAPT_vect 0x0018
#define TIMER1_COMPA_vect 0x001c
#define TIMER1_COMPB_vect 0x0020
#define TIMER1_OVF_vect 0x0024
#define TIMER0_COMP_vect 0x0028
#define TIMER0_OVF_vect 0x002c
#define SPISTC_vect 0x0030
#define UART0RX_vect 0x0034
#define UART1RX_vect 0x0038
#define UART0UDRE_vect 0x003c
#define UART1UDRE_vect 0x0040
#define UART0TX_vect 0x0044
#define UART1TX_vect 0x0048
#define EE_RDY_vect 0x004c
#define ANA_COMP_vect 0x0050

// I/O addresses


sfrb SREG = 0x5f;

sfrb SPH = 0x5e;
#define SP8 0
#define SP9 1
#define SP10 2
#define SP11 3
#define SP12 4
#define SP13 5
#define SP14 6
#define SP15 7

sfrb SPL = 0x5d;
#define SP0 0
#define SP1 1
#define SP2 2
#define SP3 3
#define SP4 4
#define SP5 5
#define SP6 6
#define SP7 7

sfrw SPW = 0x5d;

sfrb GIMSK = 0x5b;
#define INT2 5
#define INT0 6
#define INT1 7

sfrb GIFR = 0x5a;
#define INTF2 5
#define INTF0 6
#define INTF1 7

sfrb TIMSK = 0x59;
#define OCIE0 0
#define TOIE0 1
#define OCIE2 2
#define TICIE1 3
#define TOIE2 4
#define OCIE1B 5
#define OCIE1A 6
#define TOIE1 7

sfrb TIFR = 0x58;
#define OCF0 0
#define TOV0 1
#define OCF2 2
#define ICF1 3
#define TOV2 4
#define OCF1B 5
#define OCF1A 6
#define TOV1 7

sfrb SPMCR = 0x57;
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3

sfrb EMCUCR = 0x56;
#define ISC2 0
#define SRW11 1
#define SRW00 2
#define SRW01 3
#define SRL0 4
#define SRL1 5
#define SRL2 6
#define SM0 7

sfrb MCUCR = 0x55;
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
#define SM1 4
#define SE 5
#define SRW10 6
#define SRE 7

sfrb MCUSR = 0x54;
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3

sfrb TCCR0 = 0x53;
#define CS00 0
#define CS01 1
#define CS02 2
#define WGM01 3
#define COM00 4
#define COM01 5
#define WGM00 6
#define FOC0 7

sfrb TCNT0 = 0x52;
#define TCNT0_0 0
#define TCNT0_1 1
#define TCNT0_2 2
#define TCNT0_3 3
#define TCNT0_4 4
#define TCNT0_5 5
#define TCNT0_6 6
#define TCNT0_7 7

sfrb OCR0 = 0x51;
#define OCR0_0 0
#define OCR0_1 1
#define OCR0_2 2
#define OCR0_3 3
#define OCR0_4 4
#define OCR0_5 5
#define OCR0_6 6
#define OCR0_7 7

sfrb SFIOR = 0x50;
#define PSR10 0
#define PSR2 1

sfrb TCCR1A = 0x4f;
#define WGM10 0
#define WGM11 1
#define FOC1B 2
#define FOC1A 3
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7

sfrb TCCR1B = 0x4e;
#define CS10 0
#define CS11 1
#define CS12 2
#define CTC1 3
#define ICES1 6
#define ICNC1 7

sfrb TCNT1H = 0x4d;
#define TCNT1H0 0
#define TCNT1H1 1
#define TCNT1H2 2
#define TCNT1H3 3
#define TCNT1H4 4
#define TCNT1H5 5
#define TCNT1H6 6
#define TCNT1H7 7

sfrb TCNT1L = 0x4c;
#define TCNT1L0 0
#define TCNT1L1 1
#define TCNT1L2 2
#define TCNT1L3 3
#define TCNT1L4 4
#define TCNT1L5 5
#define TCNT1L6 6
#define TCNT1L7 7

sfrw TCNT1W = 0x4c;

sfrb OCR1AH = 0x4b;
#define OCR1AH0 0
#define OCR1AH1 1
#define OCR1AH2 2
#define OCR1AH3 3
#define OCR1AH4 4
#define OCR1AH5 5
#define OCR1AH6 6
#define OCR1AH7 7

sfrb OCR1AL = 0x4a;
#define OCR1AL0 0
#define OCR1AL1 1
#define OCR1AL2 2
#define OCR1AL3 3
#define OCR1AL4 4
#define OCR1AL5 5
#define OCR1AL6 6
#define OCR1AL7 7

sfrw OCR1AW = 0x4a;

sfrb OCR1BH = 0x49;
#define OCR1BH0 0
#define OCR1BH1 1
#define OCR1BH2 2
#define OCR1BH3 3
#define OCR1BH4 4
#define OCR1BH5 5
#define OCR1BH6 6
#define OCR1BH7 7

sfrb OCR1BL = 0x48;
#define OCR1BL0 0
#define OCR1BL1 1
#define OCR1BL2 2
#define OCR1BL3 3
#define OCR1BL4 4
#define OCR1BL5 5
#define OCR1BL6 6
#define OCR1BL7 7

sfrw OCR1BW = 0x48;

sfrb TCCR2 = 0x47;
#define CS20 0
#define CS21 1
#define CS22 2
#define CTC2 3
#define COM20 4
#define COM21 5
#define PWM2 6
#define FOC2 7

sfrb ASSR = 0x46;
#define TCR2UB 0
#define OCR2UB 1
#define TCN2UB 2
#define AS2 3

sfrb ICR1H = 0x45;
#define ICR1H0 0
#define ICR1H1 1
#define ICR1H2 2
#define ICR1H3 3
#define ICR1H4 4
#define ICR1H5 5
#define ICR1H6 6
#define ICR1H7 7

sfrb ICR1L = 0x44;
#define ICR1L0 0
#define ICR1L1 1
#define ICR1L2 2
#define ICR1L3 3
#define ICR1L4 4
#define ICR1L5 5
#define ICR1L6 6
#define ICR1L7 7

sfrw ICR1W = 0x44;

sfrb TCNT2 = 0x43;
#define TCNT2_0 0
#define TCNT2_1 1
#define TCNT2_2 2
#define TCNT2_3 3
#define TCNT2_4 4
#define TCNT2_5 5
#define TCNT2_6 6
#define TCNT2_7 7

sfrb OCR2 = 0x42;
#define OCR2_0 0
#define OCR2_1 1
#define OCR2_2 2
#define OCR2_3 3
#define OCR2_4 4
#define OCR2_5 5
#define OCR2_6 6
#define OCR2_7 7

sfrb WDTCR = 0x41;
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDE 3
#define WDTOE 4

sfrb UBRRHI = 0x40;
#define UBRRHI00 0
#define UBRRHI01 1
#define UBRRHI02 2
#define UBRRHI03 3
#define UBRRHI10 4
#define UBRRHI11 5
#define UBRRHI12 6
#define UBRRHI13 7

sfrb EEARH = 0x3f;
#define EEAR8 0

sfrb EEARL = 0x3e;
#define EEAR0 0
#define EEAR1 1
#define EEAR2 2
#define EEAR3 3
#define EEAR4 4
#define EEAR5 5
#define EEAR6 6
#define EEAR7 7

sfrw EEARW = 0x3e;

sfrb EEDR = 0x3d;
#define EEDR0 0
#define EEDR1 1
#define EEDR2 2
#define EEDR3 3
#define EEDR4 4
#define EEDR5 5
#define EEDR6 6
#define EEDR7 7

sfrb EECR = 0x3c;
#define EERE 0
#define EEWE 1
#define EEMWE 2
#define EERIE 3

sfrb PORTA = 0x3b;
#define PORTA0 0
#define PORTA1 1
#define PORTA2 2
#define PORTA3 3
#define PORTA4 4
#define PORTA5 5
#define PORTA6 6
#define PORTA7 7

sfrb DDRA = 0x3a;
#define DDA0 0
#define DDA1 1
#define DDA2 2
#define DDA3 3
#define DDA4 4
#define DDA5 5
#define DDA6 6
#define DDA7 7

sfrb PINA = 0x39;
#define PINA0 0
#define PINA1 1
#define PINA2 2
#define PINA3 3
#define PINA4 4
#define PINA5 5
#define PINA6 6
#define PINA7 7

sfrb PORTB = 0x38;
#define PORTB0 0
#define PORTB1 1
#define PORTB2 2
#define PORTB3 3
#define PORTB4 4
#define PORTB5 5
#define PORTB6 6
#define PORTB7 7

sfrb DDRB = 0x37;
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3
#define DDB4 4
#define DDB5 5
#define DDB6 6
#define DDB7 7

sfrb PINB = 0x36;
#define PINB0 0
#define PINB1 1
#define PINB2 2
#define PINB3 3
#define PINB4 4
#define PINB5 5
#define PINB6 6
#define PINB7 7

sfrb PORTC = 0x35;
#define PORTC0 0
#define PORTC1 1
#define PORTC2 2
#define PORTC3 3
#define PORTC4 4
#define PORTC5 5
#define PORTC6 6
#define PORTC7 7

sfrb DDRC = 0x34;
#define DDC0 0
#define DDC1 1
#define DDC2 2
#define DDC3 3
#define DDC4 4
#define DDC5 5
#define DDC6 6
#define DDC7 7

sfrb PINC = 0x33;
#define PINC0 0
#define PINC1 1
#define PINC2 2
#define PINC3 3
#define PINC4 4
#define PINC5 5
#define PINC6 6
#define PINC7 7

sfrb PORTD = 0x32;
#define PORTD0 0
#define PORTD1 1
#define PORTD2 2
#define PORTD3 3
#define PORTD4 4
#define PORTD5 5
#define PORTD6 6
#define PORTD7 7

sfrb DDRD = 0x31;
#define DDD0 0
#define DDD1 1
#define DDD2 2
#define DDD3 3
#define DDD4 4
#define DDD5 5
#define DDD6 6
#define DDD7 7

sfrb PIND = 0x30;
#define PIND0 0
#define PIND1 1
#define PIND2 2
#define PIND3 3
#define PIND4 4
#define PIND5 5
#define PIND6 6
#define PIND7 7

sfrb SPDR = 0x2f;
#define SPDR0 0
#define SPDR1 1
#define SPDR2 2
#define SPDR3 3
#define SPDR4 4
#define SPDR5 5
#define SPDR6 6
#define SPDR7 7

sfrb SPSR = 0x2e;
#define SPI2X 0
#define WCOL 6
#define SPIF 7

sfrb SPCR = 0x2d;
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7

sfrb UDR0 = 0x2c;
#define UDR00 0
#define UDR01 1
#define UDR02 2
#define UDR03 3
#define UDR04 4
#define UDR05 5
#define UDR06 6
#define UDR07 7

sfrb UCSR0A = 0x2b;
#define MPCM0 0
#define U2X0 1
#define OR0 3
#define FE0 4
#define UDRE0 5
#define TXC0 6
#define RXC0 7

sfrb UCSR0B = 0x2a;
#define TXB80 0
#define RXB80 1
#define CHR90 2
#define TXEN0 3
#define RXEN0 4
#define UDR0IE0 5
#define TXCIE0 6
#define RXCIE0 7

sfrb UBRR0 = 0x29;
#define UBRR00 0
#define UBRR01 1
#define UBRR02 2
#define UBRR03 3
#define UBRR04 4
#define UBRR05 5
#define UBRR06 6
#define UBRR07 7

sfrb ACSR = 0x28;
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define AINBG 6
#define ACD 7

sfrb PORTE = 0x27;
#define PORTE0 0
#define PORTE1 1
#define PORTE2 2

sfrb DDRE = 0x26;
#define DDE0 0
#define DDE1 1
#define DDE2 2

sfrb PINE = 0x25;
#define PINE0 0
#define PINE1 1
#define PINE2 2

sfrb UDR1 = 0x23;
#define UDR10 0
#define UDR11 1
#define UDR12 2
#define UDR13 3
#define UDR14 4
#define UDR15 5
#define UDR16 6
#define UDR17 7

sfrb UCSR1A = 0x22;
#define MPCM1 0
#define U2X1 1
#define OR1 3
#define FE1 4
#define UDRE1 5
#define TXC1 6
#define RXC1 7

sfrb UCSR1B = 0x21;
#define TXB81 0
#define RXB81 1
#define CHR91 2
#define TXEN1 3
#define RXEN1 4
#define UDR1IE1 5
#define TXCIE1 6
#define RXCIE1 7

sfrb UBRR1 = 0x20;
#define UBRR10 0
#define UBRR11 1
#define UBRR12 2
#define UBRR13 3
#define UBRR14 4
#define UBRR15 5
#define UBRR16 6
#define UBRR17 7

#endif