#ifndef __AT90S2323_h
#define __AT90S2323_h

// Interrupt vectors

#define RESET_vect 0x0000
#define INT0_vect 0x0002
#define TIMER0_OVF0_vect 0x0004

// I/O addresses


sfrb SREG = 0x5f;

sfrb SPL = 0x5d;
#define SP0 0
#define SP1 1
#define SP2 2
#define SP3 3
#define SP4 4
#define SP5 5
#define SP6 6
#define SP7 7

sfrb GIMSK = 0x5b;
#define INT0 6

sfrb GIFR = 0x5a;
#define INTF0 6

sfrb TIMSK = 0x59;
#define TOIE0 1

sfrb TIFR = 0x58;
#define TOV0 1

sfrb MCUCR = 0x55;
#define ISC00 0
#define ISC01 1
#define SM 4
#define SE 5

sfrb MCUSR = 0x54;
#define PORF 0
#define EXTRF 1

sfrb TCCR0 = 0x53;
#define CS00 0
#define CS01 1
#define CS02 2

sfrb TCNT0 = 0x52;
#define TCNT00 0
#define TCNT01 1
#define TCNT02 2
#define TCNT03 3
#define TCNT04 4
#define TCNT05 5
#define TCNT06 6
#define TCNT07 7

sfrb WDTCR = 0x41;
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDE 3
#define WDTOE 4

sfrb EEAR = 0x3e;
#define EEAR0 0
#define EEAR1 1
#define EEAR2 2
#define EEAR3 3
#define EEAR4 4
#define EEAR5 5
#define EEAR6 6

sfrb EEDR = 0x3d;
#define EEDR0 0
#define EEDR1 1
#define EEDR2 2
#define EEDR3 3
#define EEDR4 4
#define EEDR5 5
#define EEDR6 6
#define EEDR7 7

sfrb EECR = 0x3c;
#define EERE 0
#define EEWE 1
#define EEMWE 2

sfrb PORTB = 0x38;
#define PORTB0 0
#define PORTB1 1
#define PORTB2 2

sfrb DDRB = 0x37;
#define DDB0 0
#define DDB1 1
#define DDB2 2

sfrb PINB = 0x36;
#define PINB0 0
#define PINB1 1
#define PINB2 2

#endif