#ifndef __AT90S2313_h
#define __AT90S2313_h

// Interrupt vectors

#define RESET_vect 0x0000
#define INT0_vect 0x0002
#define INT1_vect 0x0004
#define TIMER1_CAPT1_vect 0x0006
#define TIMER1_COMP1_vect 0x0008
#define TIMER1_OVF1_vect 0x000a
#define TIMER0_OVF0_vect 0x000c
#define UART_RX_vect 0x000e
#define UART_UDRE_vect 0x0010
#define UART_TX_vect 0x0012
#define ANA_COMP_vect 0x0014

// I/O addresses


sfrb SREG = 0x5f;

sfrb SPL = 0x5d;
#define SP0 0
#define SP1 1
#define SP2 2
#define SP3 3
#define SP4 4
#define SP5 5
#define SP6 6
#define SP7 7

sfrb GIMSK = 0x5b;
#define INT0 6
#define INT1 7

sfrb GIFR = 0x5a;
#define INTF0 6
#define INTF1 7

sfrb TIMSK = 0x59;
#define TOIE0 1
#define TICIE1 3
#define OCIE1A 6
#define TOIE1 7

sfrb TIFR = 0x58;
#define TOV0 1
#define ICF1 3
#define OCF1A 6
#define TOV1 7

sfrb MCUCR = 0x55;
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
#define SM 4
#define SE 5

sfrb TCCR0 = 0x53;
#define CS00 0
#define CS01 1
#define CS02 2

sfrb TCNT0 = 0x52;
#define TCNT00 0
#define TCNT01 1
#define TCNT02 2
#define TCNT03 3
#define TCNT04 4
#define TCNT05 5
#define TCNT06 6
#define TCNT07 7

sfrb TCCR1A = 0x4f;
#define PWM10 0
#define PWM11 1
#define COM1A0 6
#define COM1A1 7

sfrb TCCR1B = 0x4e;
#define CS10 0
#define CS11 1
#define CS12 2
#define CTC1 3
#define ICES1 6
#define ICNC1 7

sfrb TCNT1H = 0x4d;
#define TCNT1H0 0
#define TCNT1H1 1
#define TCNT1H2 2
#define TCNT1H3 3
#define TCNT1H4 4
#define TCNT1H5 5
#define TCNT1H6 6
#define TCNT1H7 7

sfrb TCNT1L = 0x4c;
#define TCNT1L0 0
#define TCNT1L1 1
#define TCNT1L2 2
#define TCNT1L3 3
#define TCNT1L4 4
#define TCNT1L5 5
#define TCNT1L6 6
#define TCNT1L7 7

sfrw TCNT1W = 0x4c;

sfrb OCR1AH = 0x4b;
#define OCR1AH0 0
#define OCR1AH1 1
#define OCR1AH2 2
#define OCR1AH3 3
#define OCR1AH4 4
#define OCR1AH5 5
#define OCR1AH6 6
#define OCR1AH7 7

sfrb OCR1AL = 0x4a;
#define OCR1AL0 0
#define OCR1AL1 1
#define OCR1AL2 2
#define OCR1AL3 3
#define OCR1AL4 4
#define OCR1AL5 5
#define OCR1AL6 6
#define OCR1AL7 7

sfrw OCR1AW = 0x4a;

sfrb ICR1H = 0x45;
#define ICR1H0 0
#define ICR1H1 1
#define ICR1H2 2
#define ICR1H3 3
#define ICR1H4 4
#define ICR1H5 5
#define ICR1H6 6
#define ICR1H7 7

sfrb ICR1L = 0x44;
#define ICR1L0 0
#define ICR1L1 1
#define ICR1L2 2
#define ICR1L3 3
#define ICR1L4 4
#define ICR1L5 5
#define ICR1L6 6
#define ICR1L7 7

sfrw ICR1W = 0x44;

sfrb WDTCR = 0x41;
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDE 3
#define WDTOE 4

sfrb EEAR = 0x3e;
#define EEAR0 0
#define EEAR1 1
#define EEAR2 2
#define EEAR3 3
#define EEAR4 4
#define EEAR5 5
#define EEAR6 6

sfrb EEDR = 0x3d;
#define EEDR0 0
#define EEDR1 1
#define EEDR2 2
#define EEDR3 3
#define EEDR4 4
#define EEDR5 5
#define EEDR6 6
#define EEDR7 7

sfrb EECR = 0x3c;
#define EERE 0
#define EEWE 1
#define EEMWE 2

sfrb PORTB = 0x38;
#define PORTB0 0
#define PORTB1 1
#define PORTB2 2
#define PORTB3 3
#define PORTB4 4
#define PORTB5 5
#define PORTB6 6
#define PORTB7 7

sfrb DDRB = 0x37;
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3
#define DDB4 4
#define DDB5 5
#define DDB6 6
#define DDB7 7

sfrb PINB = 0x36;
#define PINB0 0
#define PINB1 1
#define PINB2 2
#define PINB3 3
#define PINB4 4
#define PINB5 5
#define PINB6 6
#define PINB7 7

sfrb PORTD = 0x32;
#define PORTD0 0
#define PORTD1 1
#define PORTD2 2
#define PORTD3 3
#define PORTD4 4
#define PORTD5 5
#define PORTD6 6

sfrb DDRD = 0x31;
#define DDD0 0
#define DDD1 1
#define DDD2 2
#define DDD3 3
#define DDD4 4
#define DDD5 5
#define DDD6 6

sfrb PIND = 0x30;
#define PIND0 0
#define PIND1 1
#define PIND2 2
#define PIND3 3
#define PIND4 4
#define PIND5 5
#define PIND6 6

sfrb UDR = 0x2c;
#define UDR0 0
#define UDR1 1
#define UDR2 2
#define UDR3 3
#define UDR4 4
#define UDR5 5
#define UDR6 6
#define UDR7 7

sfrb USR = 0x2b;
#define OR 3
#define FE 4
#define UDRE 5
#define TXC 6
#define RXC 7

sfrb UCR = 0x2a;
#define TXB8 0
#define RXB8 1
#define CHR9 2
#define TXEN 3
#define RXEN 4
#define UDRIE 5
#define TXCIE 6
#define RXCIE 7

sfrb UBRR = 0x29;
#define UBRR0 0
#define UBRR1 1
#define UBRR2 2
#define UBRR3 3
#define UBRR4 4
#define UBRR5 5
#define UBRR6 6
#define UBRR7 7

sfrb ACSR = 0x28;
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACD 7

#endif