<ATtiny45.h>

This documentation was generated automatically from the AVR Studio part description file ATtiny45.pdf.

PORTB

PORTB - Data Register, Port B

sfrb PORTB = $18;

PORTB0

#define PORTB0 0

PORTB1

#define PORTB1 1

PORTB2

#define PORTB2 2

PORTB3

#define PORTB3 3

PORTB4

#define PORTB4 4

PORTB5

#define PORTB5 5

DDRB - Data Direction Register, Port B

sfrb DDRB = $17;

DDB0

#define DDB0 0

DDB1

#define DDB1 1

DDB2

#define DDB2 2

DDB3

#define DDB3 3

DDB4

#define DDB4 4

DDB5

#define DDB5 5

PINB - Input Pins, Port B

sfrb PINB = $16;

PINB0

#define PINB0 0

PINB1

#define PINB1 1

PINB2

#define PINB2 2

PINB3

#define PINB3 3

PINB4

#define PINB4 4

PINB5

#define PINB5 5

ANALOG COMPARATOR

ADCSRB - ADC Control and Status Register B

sfrb ADCSRB = $03;

ACME - Analog Comparator Multiplexer Enable

#define ACME 6

When this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see ?Analog Comparator Multiplexed Input? on page 186.

ACSR - Analog Comparator Control And Status Register

sfrb ACSR = $08;

ACIS0 - Analog Comparator Interrupt Mode Select bit 0

#define ACIS0 0

These bits determine which comparator events that trigger the Analog Comparator interrupt.

ACIS1 - Analog Comparator Interrupt Mode Select bit 1

#define ACIS1 1

These bits determine which comparator events that trigger the Analog Comparator interrupt.

ACIE - Analog Comparator Interrupt Enable

#define ACIE 3

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.

ACI - Analog Comparator Interrupt Flag

#define ACI 4

This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

ACO - Analog Compare Output

#define ACO 5

The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.

ACBG - Analog Comparator Bandgap Select

#define ACBG 6

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See ?Internal Voltage Reference? on page 42.

ACD - Analog Comparator Disable

#define ACD 7

When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

DIDR0 -

sfrb DIDR0 = $14;

AIN0D - AIN0 Digital Input Disable

#define AIN0D 0

When this bit is written logic one,the digital input buffer on the AIN1/0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

AIN1D - AIN1 Digital Input Disable

#define AIN1D 1

AD CONVERTER

AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 盜 Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode N

ADMUX - The ADC multiplexer Selection Register

sfrb ADMUX = $07;

MUX0 - Analog Channel and Gain Selection Bits

#define MUX0 0

The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).

MUX1 - Analog Channel and Gain Selection Bits

#define MUX1 1

MUX2 - Analog Channel and Gain Selection Bits

#define MUX2 2

MUX3 - Analog Channel and Gain Selection Bits

#define MUX3 3

REFS2 - Reference Selection Bit 2

#define REFS2 4

These bits select the voltage reference for the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.

ADLAR - Left Adjust Result

#define ADLAR 5

The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see ?The ADC Data Register -ADCL and ADCH? on page 198.

REFS0 - Reference Selection Bit 0

#define REFS0 6

REFS1 - Reference Selection Bit 1

#define REFS1 7

ADCSRA - The ADC Control and Status register

sfrb ADCSRA = $06;

ADPS0 - ADC Prescaler Select Bits

#define ADPS0 0

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

ADPS1 - ADC Prescaler Select Bits

#define ADPS1 1

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

ADPS2 - ADC Prescaler Select Bits

#define ADPS2 2

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

ADIE - ADC Interrupt Enable

#define ADIE 3

When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.

ADIF - ADC Interrupt Flag

#define ADIF 4

This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.

ADATE - ADC Auto Trigger Enable

#define ADATE 5

When this bit is written to one,Auto Triggering of the ADC is enabled.The ADC will start a conversion on a positive edge of the selected trigger signal.The trigger source is selected by setting the ADC Trigger Select bits,ADTS in ADCSRB.

ADSC - ADC Start Conversion

#define ADSC 6

In Single Conversion Mode, a logical ?1? must be written to this bit to start each conversion. In Free Running Mode, a logical ?1? must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect

ADEN - ADC Enable

#define ADEN 7

Writing a logical ?1? to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.

ADCH - ADC Data Register High Byte

sfrb ADCH = $05;

ADCH0 - ADC Data Register High Byte Bit 0

#define ADCH0 0

ADCH1 - ADC Data Register High Byte Bit 1

#define ADCH1 1

ADCH2 - ADC Data Register High Byte Bit 2

#define ADCH2 2

ADCH3 - ADC Data Register High Byte Bit 3

#define ADCH3 3

ADCH4 - ADC Data Register High Byte Bit 4

#define ADCH4 4

ADCH5 - ADC Data Register High Byte Bit 5

#define ADCH5 5

ADCH6 - ADC Data Register High Byte Bit 6

#define ADCH6 6

ADCH7 - ADC Data Register High Byte Bit 7

#define ADCH7 7

ADCL - ADC Data Register Low Byte

sfrb ADCL = $04;

ADCL0 - ADC Data Register Low Byte Bit 0

#define ADCL0 0

ADCL1 - ADC Data Register Low Byte Bit 1

#define ADCL1 1

ADCL2 - ADC Data Register Low Byte Bit 2

#define ADCL2 2

ADCL3 - ADC Data Register Low Byte Bit 3

#define ADCL3 3

ADCL4 - ADC Data Register Low Byte Bit 4

#define ADCL4 4

ADCL5 - ADC Data Register Low Byte Bit 5

#define ADCL5 5

ADCL6 - ADC Data Register Low Byte Bit 6

#define ADCL6 6

ADCL7 - ADC Data Register Low Byte Bit 7

#define ADCL7 7

ADCSRB - ADC Control and Status Register B

sfrb ADCSRB = $03;

ADTS0 - ADC Auto Trigger Source 0

#define ADTS0 0

If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set .

ADTS1 - ADC Auto Trigger Source 1

#define ADTS1 1

ADTS2 - ADC Auto Trigger Source 2

#define ADTS2 2

IPR - Input Polarity Mode

#define IPR 5

BIN - Bipolar Input Mode

#define BIN 7

The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected by writing the BIN bit in the ADCSRB register.

DIDR0 - Digital Input Disable Register 0

sfrb DIDR0 = $14;

ADC1D - ADC1 Digital input Disable

#define ADC1D 2

When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

ADC3D - ADC3 Digital input Disable

#define ADC3D 3

ADC2D - ADC2 Digital input Disable

#define ADC2D 4

ADC0D - ADC0 Digital input Disable

#define ADC0D 5

USI

Universal Serial Interface

USIBR - USI Buffer Register

sfrb USIBR = $10;

USIBR0 - USI Buffer Register bit 0

#define USIBR0 0

USIBR1 - USI Buffer Register bit 1

#define USIBR1 1

USIBR2 - USI Buffer Register bit 2

#define USIBR2 2

USIBR3 - USI Buffer Register bit 3

#define USIBR3 3

USIBR4 - USI Buffer Register bit 4

#define USIBR4 4

USIBR5 - USI Buffer Register bit 5

#define USIBR5 5

USIBR6 - USI Buffer Register bit 6

#define USIBR6 6

USIBR7 - USI Buffer Register bit 7

#define USIBR7 7

USIDR - USI Data Register

sfrb USIDR = $0F;

USIDR0 - USI Data Register bit 0

#define USIDR0 0

USIDR1 - USI Data Register bit 1

#define USIDR1 1

USIDR2 - USI Data Register bit 2

#define USIDR2 2

USIDR3 - USI Data Register bit 3

#define USIDR3 3

USIDR4 - USI Data Register bit 4

#define USIDR4 4

USIDR5 - USI Data Register bit 5

#define USIDR5 5

USIDR6 - USI Data Register bit 6

#define USIDR6 6

USIDR7 - USI Data Register bit 7

#define USIDR7 7

USISR - USI Status Register

sfrb USISR = $0E;

USICNT0 - USI Counter Value Bit 0

#define USICNT0 0

USICNT1 - USI Counter Value Bit 1

#define USICNT1 1

USICNT2 - USI Counter Value Bit 2

#define USICNT2 2

USICNT3 - USI Counter Value Bit 3

#define USICNT3 3

USIDC - Data Output Collision

#define USIDC 4

USIPF - Stop Condition Flag

#define USIPF 5

USIOIF - Counter Overflow Interrupt Flag

#define USIOIF 6

USISIF - Start Condition Interrupt Flag

#define USISIF 7

USICR - USI Control Register

sfrb USICR = $0D;

USITC - Toggle Clock Port Pin

#define USITC 0

USICLK - Clock Strobe

#define USICLK 1

USICS0 - USI Clock Source Select Bit 0

#define USICS0 2

USICS1 - USI Clock Source Select Bit 1

#define USICS1 3

USIWM0 - USI Wire Mode Bit 0

#define USIWM0 4

USIWM1 - USI Wire Mode Bit 1

#define USIWM1 5

USIOIE - Counter Overflow Interrupt Enable

#define USIOIE 6

USISIE - Start Condition Interrupt Enable

#define USISIE 7

EXTERNAL INTERRUPT

MCUCR - MCU Control Register

sfrb MCUCR = $35;

ISC00 - Interrupt Sense Control 0 Bit 0

#define ISC00 0

ISC01 - Interrupt Sense Control 0 Bit 1

#define ISC01 1

GIMSK - General Interrupt Mask Register

sfrb GIMSK = $3B;

PCIE - Pin Change Interrupt Enable

#define PCIE 5

INT0 - External Interrupt Request 0 Enable

#define INT0 6

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also ?External Interrupts.? ? Bits 5..0 - Res: Reserved bits

GIFR - General Interrupt Flag register

sfrb GIFR = $3A;

PCIF - Pin Change Interrupt Flag

#define PCIF 5

INTF0 - External Interrupt Flag 0

#define INTF0 6

When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

PCMSK - Pin Change Enable Mask

sfrb PCMSK = $15;

PCINT0 - Pin Change Enable Mask Bit 0

#define PCINT0 0

PCINT1 - Pin Change Enable Mask Bit 1

#define PCINT1 1

PCINT2 - Pin Change Enable Mask Bit 2

#define PCINT2 2

PCINT3 - Pin Change Enable Mask Bit 3

#define PCINT3 3

PCINT4 - Pin Change Enable Mask Bit 4

#define PCINT4 4

PCINT5 - Pin Change Enable Mask Bit 5

#define PCINT5 5

EEPROM

EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See ?Preventing EEPROM Corruption? on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execut

EEARH - EEPROM Address Register High Byte

sfrb EEARH = $1F;

EEAR8 - EEPROM Read/Write Access Bit 0

#define EEAR8 0

EEARL - EEPROM Address Register Low Byte

sfrb EEARL = $1E;

EEAR0 - EEPROM Read/Write Access Bit 0

#define EEAR0 0

EEAR1 - EEPROM Read/Write Access Bit 1

#define EEAR1 1

EEAR2 - EEPROM Read/Write Access Bit 2

#define EEAR2 2

EEAR3 - EEPROM Read/Write Access Bit 3

#define EEAR3 3

EEAR4 - EEPROM Read/Write Access Bit 4

#define EEAR4 4

EEAR5 - EEPROM Read/Write Access Bit 5

#define EEAR5 5

EEAR6 - EEPROM Read/Write Access Bit 6

#define EEAR6 6

EEAR7 - EEPROM Read/Write Access Bit 7

#define EEAR7 7

EEDR - EEPROM Data Register

sfrb EEDR = $1D;

EEDR0 - EEPROM Data Register bit 0

#define EEDR0 0

EEDR1 - EEPROM Data Register bit 1

#define EEDR1 1

EEDR2 - EEPROM Data Register bit 2

#define EEDR2 2

EEDR3 - EEPROM Data Register bit 3

#define EEDR3 3

EEDR4 - EEPROM Data Register bit 4

#define EEDR4 4

EEDR5 - EEPROM Data Register bit 5

#define EEDR5 5

EEDR6 - EEPROM Data Register bit 6

#define EEDR6 6

EEDR7 - EEPROM Data Register bit 7

#define EEDR7 7

EECR - EEPROM Control Register

sfrb EECR = $1C;

EERE - EEPROM Read Enable

#define EERE 0

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU

EEPE - EEPROM Write Enable

#define EEPE 1

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See ?Boot Loader Support - Read While Write self-programming? on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed

EEMPE - EEPROM Master Write Enable

#define EEMPE 2

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

EERIE - EEPROM Ready Interrupt Enable

#define EERIE 3

EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.

EEPM0 - EEPROM Programming Mode Bit 0

#define EEPM0 4

The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

EEPM1 - EEPROM Programming Mode Bit 1

#define EEPM1 5

WATCHDOG

WDTCR - Watchdog Timer Control Register

sfrb WDTCR = $21;

WDP0 - Watch Dog Timer Prescaler bit 0

#define WDP0 0

WDP1 - Watch Dog Timer Prescaler bit 1

#define WDP1 1

WDP2 - Watch Dog Timer Prescaler bit 2

#define WDP2 2

WDE - Watch Dog Enable

#define WDE 3

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog

WDCE - Watchdog Change Enable

#define WDCE 4

WDP3 - Watchdog Timer Prescaler Bit 3

#define WDP3 5

WDIE - Watchdog Timeout Interrupt Enable

#define WDIE 6

WDIF - Watchdog Timeout Interrupt Flag

#define WDIF 7

TIMER COUNTER 0

TIMSK - Timer/Counter Interrupt Mask Register

sfrb TIMSK = $39;

TOIE0 - Timer/Counter0 Overflow Interrupt Enable

#define TOIE0 1

OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable

#define OCIE0B 3

OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable

#define OCIE0A 4

TIFR - Timer/Counter0 Interrupt Flag register

sfrb TIFR = $38;

TOV0 - Timer/Counter0 Overflow Flag

#define TOV0 1

OCF0B - Timer/Counter0 Output Compare Flag 0B

#define OCF0B 3

OCF0A - Timer/Counter0 Output Compare Flag 0A

#define OCF0A 4

TCCR0A - Timer/Counter Control Register A

sfrb TCCR0A = $2A;

WGM00 - Waveform Generation Mode

#define WGM00 0

WGM01 - Waveform Generation Mode

#define WGM01 1

COM0B0 - Compare Output Mode, Fast PWm

#define COM0B0 4

COM0B1 - Compare Output Mode, Fast PWm

#define COM0B1 5

COM0A0 - Compare Output Mode, Phase Correct PWM Mode

#define COM0A0 6

COM0A1 - Compare Output Mode, Phase Correct PWM Mode

#define COM0A1 7

TCCR0B - Timer/Counter Control Register B

sfrb TCCR0B = $33;

CS00 - Clock Select

#define CS00 0

CS01 - Clock Select

#define CS01 1

CS02 - Clock Select

#define CS02 2

WGM02

#define WGM02 3

FOC0B - Force Output Compare B

#define FOC0B 6

FOC0A - Force Output Compare A

#define FOC0A 7

TCNT0 - Timer/Counter0

sfrb TCNT0 = $32;

TCNT0_0

#define TCNT0_0 0

TCNT0_1

#define TCNT0_1 1

TCNT0_2

#define TCNT0_2 2

TCNT0_3

#define TCNT0_3 3

TCNT0_4

#define TCNT0_4 4

TCNT0_5

#define TCNT0_5 5

TCNT0_6

#define TCNT0_6 6

TCNT0_7

#define TCNT0_7 7

OCR0A - Timer/Counter0 Output Compare Register

sfrb OCR0A = $29;

OCR0_0

#define OCR0_0 0

OCR0_1

#define OCR0_1 1

OCR0_2

#define OCR0_2 2

OCR0_3

#define OCR0_3 3

OCR0_4

#define OCR0_4 4

OCR0_5

#define OCR0_5 5

OCR0_6

#define OCR0_6 6

OCR0_7

#define OCR0_7 7

OCR0B - Timer/Counter0 Output Compare Register

sfrb OCR0B = $28;

OCR0_0

#define OCR0_0 0

OCR0_1

#define OCR0_1 1

OCR0_2

#define OCR0_2 2

OCR0_3

#define OCR0_3 3

OCR0_4

#define OCR0_4 4

OCR0_5

#define OCR0_5 5

OCR0_6

#define OCR0_6 6

OCR0_7

#define OCR0_7 7

GTCCR - General Timer/Counter Control Register

sfrb GTCCR = $2C;

PSR0 - Prescaler Reset Timer/Counter1 and Timer/Counter0

#define PSR0 0

When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.

TSM - Timer/Counter Synchronization Mode

#define TSM 7

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneousl

TIMER COUNTER 1

TCCR1 - Timer/Counter Control Register

sfrb TCCR1 = $30;

CS10 - Clock Select Bits

#define CS10 0

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

CS11 - Clock Select Bits

#define CS11 1

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

CS12 - Clock Select Bits

#define CS12 2

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

CS13 - Clock Select Bits

#define CS13 3

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

COM1A0 - Compare Output Mode, Bit 1

#define COM1A0 4

The COM1A1 and COM1A0 control bits determine any output pin action following a compare match A in Timer/Counter1. Output pin actions affect pin PB1(OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) to control an output pin.

COM1A1 - Compare Output Mode, Bit 0

#define COM1A1 5

PWM1A - Pulse Width Modulator Enable

#define PWM1A 6

When set (one), this bit enables PWM mode for Timer/Counter1.

CTC1 - Clear Timer/Counter on Compare Match

#define CTC1 7

When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1A register value. If the control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match.

TCNT1 - Timer/Counter Register

sfrb TCNT1 = $2F;

TCNT1_0 - Timer/Counter Register Bit 0

#define TCNT1_0 0

TCNT1_1 - Timer/Counter Register Bit 1

#define TCNT1_1 1

TCNT1_2 - Timer/Counter Register Bit 2

#define TCNT1_2 2

TCNT1_3 - Timer/Counter Register Bit 3

#define TCNT1_3 3

TCNT1_4 - Timer/Counter Register Bit 4

#define TCNT1_4 4

TCNT1_5 - Timer/Counter Register Bit 5

#define TCNT1_5 5

TCNT1_6 - Timer/Counter Register Bit 6

#define TCNT1_6 6

TCNT1_7 - Timer/Counter Register Bit 7

#define TCNT1_7 7

OCR1A - Output Compare Register

sfrb OCR1A = $2E;

OCR1A0 - Output Compare Register A Bit 0

#define OCR1A0 0

OCR1A1 - Output Compare Register A Bit 1

#define OCR1A1 1

OCR1A2 - Output Compare Register A Bit 2

#define OCR1A2 2

OCR1A3 - Output Compare Register A Bit 3

#define OCR1A3 3

OCR1A4 - Output Compare Register A Bit 4

#define OCR1A4 4

OCR1A5 - Output Compare Register A Bit 5

#define OCR1A5 5

OCR1A6 - Output Compare Register A Bit 6

#define OCR1A6 6

OCR1A7 - Output Compare Register A Bit 7

#define OCR1A7 7

OCR1B - Output Compare Register

sfrb OCR1B = $2B;

OCR1B0 - Output Compare Register B Bit 0

#define OCR1B0 0

OCR1B1 - Output Compare Register B Bit 1

#define OCR1B1 1

OCR1B2 - Output Compare Register B Bit 2

#define OCR1B2 2

OCR1B3 - Output Compare Register B Bit 3

#define OCR1B3 3

OCR1B4 - Output Compare Register B Bit 4

#define OCR1B4 4

OCR1B5 - Output Compare Register B Bit 5

#define OCR1B5 5

OCR1B6 - Output Compare Register B Bit 6

#define OCR1B6 6

OCR1B7 - Output Compare Register B Bit 7

#define OCR1B7 7

OCR1C - Output compare register

sfrb OCR1C = $2D;

OCR1C0

#define OCR1C0 0

OCR1C1

#define OCR1C1 1

OCR1C2

#define OCR1C2 2

OCR1C3

#define OCR1C3 3

OCR1C4

#define OCR1C4 4

OCR1C5

#define OCR1C5 5

OCR1C6

#define OCR1C6 6

OCR1C7

#define OCR1C7 7

TIMSK - Timer/Counter Interrupt Mask Register

sfrb TIMSK = $39;

TOIE1 - Timer/Counter1 Overflow Interrupt Enable

#define TOIE1 2

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs (i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).

OCIE1B - OCIE1A: Timer/Counter1 Output Compare B Interrupt Enable

#define OCIE1B 5

OCE1A - OCIE1A: Timer/Counter1 Output Compare Interrupt Enable

#define OCE1A 6

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare Match, interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a compare match A in Timer/Counter1 occurs, i.e., when the OCF1A bit is set (one) in the Timer/Counter Interrupt Flag Register (TIFR).

TIFR - Timer/Counter Interrupt Flag Register

sfrb TIFR = $38;

TOV1 - Timer/Counter1 Overflow Flag

#define TOV1 2

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical ?1? to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overf low Interrupt Enable) and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.

OCF1B - Timer/Counter1 Output Compare Flag 1B

#define OCF1B 5

OCF1A - Timer/Counter1 Output Compare Flag 1A

#define OCF1A 6

The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A (Output Compare Register 1A). OCF1A is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logical ?1? to the flag. When the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 compare match A interrupt is executed.

GTCCR - Timer counter control register

sfrb GTCCR = $2C;

PSR1 - Prescaler Reset Timer/Counter1

#define PSR1 1

When this bit is set (one) the Timer/Counter1 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a ?0? to this bit will have no effect. This bit will always be read as zero.

FOC1A - Force Output Compare 1A

#define FOC1A 2

Writing a logical ?1? to this bit forces a change in the compare match output pin PB1 (OC1A) according to the values already set in COM1A1 and COM1A0. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in timer. The automatic action programmed in COM1A1 and COM1A0 happens as if a Compare Match had occurred, but no interrupt is generated and the Timer/Counter1 will not be cleared even if CTC1 is set. The FOC1A bit will always be read as zero. The setting of the FOC1A bit has no effect i

FOC1B - Force Output Compare Match 1B

#define FOC1B 3

COM1B0 - Comparator B Output Mode

#define COM1B0 4

COM1B1 - Comparator B Output Mode

#define COM1B1 5

PWM1B - Pulse Width Modulator B Enable

#define PWM1B 6

DTPS - Dead time prescaler register

sfrb DTPS = $23;

DTPS0

#define DTPS0 0

DTPS1

#define DTPS1 1

DTVALA - Dead time value register

sfrb DTVALA = $25;

DTVL0

#define DTVL0 0

DTVL1

#define DTVL1 1

DTVL2

#define DTVL2 2

DTVL3

#define DTVL3 3

DTVH0

#define DTVH0 4

DTVH1

#define DTVH1 5

DTVH2

#define DTVH2 6

DTVH3

#define DTVH3 7

DTVALB - Dead time value B

sfrb DTVALB = $24;

DTVL0

#define DTVL0 0

DTVL1

#define DTVL1 1

DTVL2

#define DTVL2 2

DTVL3

#define DTVL3 3

DTVH0

#define DTVH0 4

DTVH1

#define DTVH1 5

DTVH2

#define DTVH2 6

DTVH3

#define DTVH3 7

CPU

SREG - Status Register

sfrb SREG = $3F;

PRR - Power Reduction Register

sfrb PRR = $20;

PRADC - Power Reduction ADC

#define PRADC 0

Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.

PRUSI - Power Reduction USI

#define PRUSI 1

Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When waking up the USI again, the USI should be re initialized to ensure proper operation.

PRTIM0 - Power Reduction Timer/Counter0

#define PRTIM0 2

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown.

PRTIM1 - Power Reduction Timer/Counter1

#define PRTIM1 3

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown.

SPH - Stack Pointer High Byte

sfrb SPH = $3E;

SP8 - Stack Pointer Bit 8

#define SP8 0

SPL - Stack Pointer Low Byte

sfrb SPL = $3D;

SP0 - Stack Pointer Bit 0

#define SP0 0

SP1 - Stack Pointer Bit 1

#define SP1 1

SP2 - Stack Pointer Bit 2

#define SP2 2

SP3 - Stack Pointer Bit 3

#define SP3 3

SP4

#define SP4 4

SP5 - Stack Pointer Bit 5

#define SP5 5

SP6 - Stack Pointer Bit 6

#define SP6 6

SP7 - Stack Pointer Bit 7

#define SP7 7

MCUCR - MCU Control Register

sfrb MCUCR = $35;

ISC00 - Interrupt Sense Control 0 bit 0

#define ISC00 0

ISC01 - Interrupt Sense Control 0 bit 1

#define ISC01 1

SM0 - Sleep Mode Select Bit 0

#define SM0 3

SM1 - Sleep Mode Select Bit 1

#define SM1 4

SE - Sleep Enable

#define SE 5

The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.

PUD - Pull-up Disable

#define PUD 6

MCUSR - MCU Status register

sfrb MCUSR = $34;

PORF - Power-On Reset Flag

#define PORF 0

This bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchanged

EXTRF - External Reset Flag

#define EXTRF 1

After a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged.

BORF - Brown-out Reset Flag

#define BORF 2

WDRF - Watchdog Reset Flag

#define WDRF 3

OSCCAL - Oscillator Calibration Register

sfrb OSCCAL = $31;

CAL0 - Oscillatro Calibration Value Bit 0

#define CAL0 0

CAL1 - Oscillatro Calibration Value Bit 1

#define CAL1 1

CAL2 - Oscillatro Calibration Value Bit 2

#define CAL2 2

CAL3 - Oscillatro Calibration Value Bit 3

#define CAL3 3

CAL4 - Oscillatro Calibration Value Bit 4

#define CAL4 4

CAL5 - Oscillatro Calibration Value Bit 5

#define CAL5 5

CAL6 - Oscillatro Calibration Value Bit 6

#define CAL6 6

CLKPR - Clock Prescale Register

sfrb CLKPR = $26;

CLKPS0 - Clock Prescaler Select Bit 0

#define CLKPS0 0

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given a table in the device user guide.. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted

CLKPS1 - Clock Prescaler Select Bit 1

#define CLKPS1 1

CLKPS2 - Clock Prescaler Select Bit 2

#define CLKPS2 2

CLKPS3 - Clock Prescaler Select Bit 3

#define CLKPS3 3

CLKPCE - Clock Prescaler Change Enable

#define CLKPCE 7

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only update when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS is written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.

PLLCSR - PLL Control and status register

sfrb PLLCSR = $27;

PLOCK - PLL Lock detector

#define PLOCK 0

PLLE - PLL Enable

#define PLLE 1

PCKE - PCK Enable

#define PCKE 2

LSM - Low speed mode

#define LSM 7

DWDR - debugWire data register

sfrb DWDR = $22;

DWDR0

#define DWDR0 0

DWDR1

#define DWDR1 1

DWDR2

#define DWDR2 2

DWDR3

#define DWDR3 3

DWDR4

#define DWDR4 4

DWDR5

#define DWDR5 5

DWDR6

#define DWDR6 6

DWDR7

#define DWDR7 7

GPIOR2 - General Purpose IO register 2

sfrb GPIOR2 = $13;

GPIOR20

#define GPIOR20 0

GPIOR21

#define GPIOR21 1

GPIOR22

#define GPIOR22 2

GPIOR23

#define GPIOR23 3

GPIOR24

#define GPIOR24 4

GPIOR25

#define GPIOR25 5

GPIOR26

#define GPIOR26 6

GPIOR27

#define GPIOR27 7

GPIOR1 - General Purpose register 1

sfrb GPIOR1 = $12;

GPIOR10

#define GPIOR10 0

GPIOR11

#define GPIOR11 1

GPIOR12

#define GPIOR12 2

GPIOR13

#define GPIOR13 3

GPIOR14

#define GPIOR14 4

GPIOR15

#define GPIOR15 5

GPIOR16

#define GPIOR16 6

GPIOR17

#define GPIOR17 7

GPIOR0 - General purpose register 0

sfrb GPIOR0 = $11;

GPIOR00

#define GPIOR00 0

GPIOR01

#define GPIOR01 1

GPIOR02

#define GPIOR02 2

GPIOR03

#define GPIOR03 3

GPIOR04

#define GPIOR04 4

GPIOR05

#define GPIOR05 5

GPIOR06

#define GPIOR06 6

GPIOR07

#define GPIOR07 7

BOOT LOAD

The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppo

SPMCSR - Store Program Memory Control Register

sfrb SPMCSR = $37;

SPMEN - Store Program Memory Enable

#define SPMEN 0

This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than ?10001?, "01001", "00101", "00011" or "00001" in the lower five bits will have no eff

PGERS - Page Erase

#define PGERS 1

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.

PGWRT - Page Write

#define PGWRT 2

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.

RFLB - Read fuse and lock bits

#define RFLB 3

CTPB - Clear temporary page buffer

#define CTPB 4