<ATtiny28.h>

This documentation was generated automatically from the AVR Studio part description file ATtiny28.pdf.

PORTD

PORTD - Port D Data Register

sfrb PORTD = $12;

PORTD0 - Port D Data Register bit 0

#define PORTD0 0

PORTD1 - Port D Data Register bit 1

#define PORTD1 1

PORTD2 - Port D Data Register bit 2

#define PORTD2 2

PORTD3 - Port D Data Register bit 3

#define PORTD3 3

PORTD4 - Port D Data Register bit 4

#define PORTD4 4

PORTD5 - Port D Data Register bit 5

#define PORTD5 5

PORTD6 - Port D Data Register bit 6

#define PORTD6 6

PORTD7 - Port D Data Register bit 7

#define PORTD7 7

DDRD - Port D Data Direction Register

sfrb DDRD = $11;

DDD0 - Port D Data Direction Register bit 0

#define DDD0 0

DDD1 - Port D Data Direction Register bit 1

#define DDD1 1

DDD2 - Port D Data Direction Register bit 2

#define DDD2 2

DDD3 - Port D Data Direction Register bit 3

#define DDD3 3

DDD4 - Port D Data Direction Register bit 4

#define DDD4 4

DDD5 - Port D Data Direction Register bit 5

#define DDD5 5

DDD6 - Port D Data Direction Register bit 6

#define DDD6 6

DDD7 - Port D Data Direction Register bit 7

#define DDD7 7

PIND - Port D Input Pins

sfrb PIND = $10;

PIND0 - Port D Input Pins bit 0

#define PIND0 0

PIND1 - Port D Input Pins bit 1

#define PIND1 1

PIND2 - Port D Input Pins bit 2

#define PIND2 2

PIND3 - Port D Input Pins bit 3

#define PIND3 3

PIND4 - Port D Input Pins bit 4

#define PIND4 4

PIND5 - Port D Input Pins bit 5

#define PIND5 5

PIND6 - Port D Input Pins bit 6

#define PIND6 6

PIND7 - Port D Input Pins bit 7

#define PIND7 7

CPU

SREG - Status Register

sfrb SREG = $3F;

ICR - Interrupt Control Register

sfrb ICR = $06;

ISC00 - Interrupt Sense Control 0 bit 0

#define ISC00 0

ISC01 - Interrupt Sense Control 0 bit 1

#define ISC01 1

ICS10 - Interrupt Sense Control 1 bit 0

#define ICS10 2

ICS11 - Interrupt Sense Control 1 bit 1

#define ICS11 3

MCUCS - MCU Control and Status Register

sfrb MCUCS = $07;

PORF - Power-On Reset Flag

#define PORF 0

This bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchanged

EXTRF - External Reset Flag

#define EXTRF 1

After a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged.

WDRF - Watchdog Reset Flag

#define WDRF 3

SM - Sleep Mode

#define SM 4

This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode. When SM is set (one), Power Down mode is selected as sleep mode. For details, refer to the section ?Sleep Modes? on page 25.

SE - Sleep Enable

#define SE 5

The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.

PLUPB - Pull-up Enable Port B

#define PLUPB 7

When the PLUPB bit is set (one), pull-up resistors are enabled on all Port B input pins.

OSCCAL - Status Register

sfrb OSCCAL = $00;

CAL0 - Oscillator Calibration Value Bit 0

#define CAL0 0

CAL1 - Oscillator Calibration Value Bit 1

#define CAL1 1

CAL2 - Oscillator Calibration Value Bit 2

#define CAL2 2

CAL3 - Oscillator Calibration Value Bit 3

#define CAL3 3

CAL4

#define CAL4 4

CAL5 - Oscillator Calibration Value Bit 5

#define CAL5 5

CAL6 - Oscillator Calibration Value Bit 6

#define CAL6 6

CAL7 - Oscillator Calibration Value Bit 7

#define CAL7 7

ANALOG COMPARATOR

The analog comparator compares the input values on the positive input PB2 (AIN0) and negative input PB3 (AIN1). When the voltage on the positive input PB2 (AIN0) is higher than the voltage on the negative input PB3 (AIN1), the Analog Com-parator Output, ACO is set (one). The comparator?s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Inter-rupt triggering on comparator output rise, fall or toggle

ACSR - Analog Comparator Control And Status Register

sfrb ACSR = $08;

ACIS0 - Analog Comparator Interrupt Mode Select bit 0

#define ACIS0 0

These bits determine which comparator events that trigger the Analog Comparator interrupt.

ACIS1 - Analog Comparator Interrupt Mode Select bit 1

#define ACIS1 1

These bits determine which comparator events that trigger the Analog Comparator interrupt.

ACIE - Analog Comparator Interrupt Enable

#define ACIE 3

When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the analog comparator interrupt is activated. When Cleared (Zero), the interrupt is disabled.

ACI - Analog Comparator Interrupt Flag

#define ACI 4

This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. Observe however, that if another bit in this register is modified using the SBI or CBI instruction, ACI will be cleared if it has become set before the operation

ACO - Analog Comparator Output

#define ACO 5

When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

ACD - Analog Comparator Disable

#define ACD 7

TIMER COUNTER 0

The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in ?Timer/Counter0 Control Register - TCCR0? on page 35. The overflow status flag is found in ?The Timer/Counter Interrupt Flag Register - TIFR? on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in ?The Timer/Counter Interrupt Mask Regis-ter - TIMSK? on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions

ICR - Interrupt Control Register

sfrb ICR = $06;

TOIE0 - Timer/Counter0 Overflow Interrupt Enable

#define TOIE0 4

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

IFR - Interrupt Flag register

sfrb IFR = $05;

TOV0 - Timer/Counter0 Overflow Flag

#define TOV0 4

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.

TCCR0 - Timer/Counter0 Control Register

sfrb TCCR0 = $04;

CS00 - Clock Select0 bit 0

#define CS00 0

CS01 - Clock Select0 bit 1

#define CS01 1

CS02 - Clock Select0 bit 2

#define CS02 2

OOM00 - Overflow Output Mode, Bit 0

#define OOM00 3

The OOM01 and OOM00 control bits determine any output pin action following an overflow or a forced overflow in Timer/Counter0.

OOM01 - Overflow Output Mode, Bit 1

#define OOM01 4

The OOM01 and OOM00 control bits determine any output pin action following an overflow or a forced overflow in Timer/Counter0.

FOV0 - Force Overflow

#define FOV0 7

Writing a logical "1" to this bit forces a change on the overflow output pin PA2 according to the values already set in OOM01 and OOM00.

TCNT0 - Timer Counter 0

sfrb TCNT0 = $03;

TCNT00 - Timer Counter 0 bit 0

#define TCNT00 0

TCNT01 - Timer Counter 0 bit 1

#define TCNT01 1

TCNT02 - Timer Counter 0 bit 2

#define TCNT02 2

TCNT03 - Timer Counter 0 bit 3

#define TCNT03 3

TCNT04 - Timer Counter 0 bit 4

#define TCNT04 4

TCNT05 - Timer Counter 0 bit 5

#define TCNT05 5

TCNT06 - Timer Counter 0 bit 6

#define TCNT06 6

TCNT07 - Timer Counter 0 bit 7

#define TCNT07 7

WATCHDOG

WDTCR - Watchdog Timer Control Register

sfrb WDTCR = $01;

WDP0 - Watch Dog Timer Prescaler bit 0

#define WDP0 0

WDP1 - Watch Dog Timer Prescaler bit 1

#define WDP1 1

WDP2 - Watch Dog Timer Prescaler bit 2

#define WDP2 2

WDE - Watch Dog Enable

#define WDE 3

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog

WDTOE - RW

#define WDTOE 4

This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.

EXTERNAL INTERRUPT

ICR - Interrupt Control Register

sfrb ICR = $06;

LLIE - Low-level Input Interrupt Enable

#define LLIE 5

When the LLIE is set (one) and the I-bit in the status register (SREG) is set (one), the interrupt on low-level input is activated. Any of the Port B pins pulled low will then cause an interrupt.

INT0 - External Interrupt Request 0 Enable

#define INT0 6

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.The interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) define whether the external interrupt is activated on rising or falling edge, on pin change or low level of the INT0 pin.

INT1 - External Interrupt Request 1 Enable

#define INT1 7

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.The interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) define whether the external interrupt is activated on rising or falling edge, on pin change or low level of the INT0 pin.

IFR - Interrupt Flag register

sfrb IFR = $05;

INTF0 - External Interrupt Flag 0

#define INTF0 6

When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in ICR are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

INTF1 - External Interrupt Flag 1

#define INTF1 7

When the INT1 bit is set (one) and I-bit in the Status Register (SREG) is set (one), the external pin interrupt 1 is enabled.

PORTA

PORTA - Port A Data Register

sfrb PORTA = $1B;

PORTA0 - Port A Data Register bit 0

#define PORTA0 0

PORTA1 - Port A Data Register bit 1

#define PORTA1 1

PORTA2 - Port A Data Register bit 2

#define PORTA2 2

PORTA3 - Port A Data Register bit 3

#define PORTA3 3

PACR - Port A Control Register

sfrb PACR = $1A;

DDA0 - Data Direction Port A, bit 0

#define DDA0 0

DDA1 - Data Direction Port A, bit 1

#define DDA1 1

PA2HC - PORTA2 High Current Enable

#define PA2HC 2

DDA3 - Data Direction Port A, bit 3

#define DDA3 3

PINA - Port A Input Pins

sfrb PINA = $19;

PINA0 - Input Pins, Port A bit 0

#define PINA0 0

PINA1 - Input Pins, Port A bit 1

#define PINA1 1

PINA3 - Input Pins, Port A bit 3

#define PINA3 3

PORTB

PINB - Port B Input Pins

sfrb PINB = $16;

PINB0 - Port B Input Pins bit 0

#define PINB0 0

PINB1 - Port B Input Pins bit 1

#define PINB1 1

PINB2 - Port B Input Pins bit 2

#define PINB2 2

PINB3 - Port B Input Pins bit 3

#define PINB3 3

PINB4 - Port B Input Pins bit 4

#define PINB4 4

PINB5 - Port B Input Pins bit 5

#define PINB5 5

PINB6 - Port B Input Pins bit 6

#define PINB6 6

PINB7 - Port B Input Pins bit 7

#define PINB7 7

MODULATOR

MODCR - Modulation Control Register

sfrb MODCR = $02;

MCONF0 - Modulation Configuration Bit 0

#define MCONF0 0

MODCONF[2:0] determine the relationship between the on- and off-times of the modulat or , and thereby the duty-cycle.

MCONF1 - Modulation Configuration Bit 1

#define MCONF1 1

MODCONF[2:0] determine the relationship between the on- and off-times of the modulat or , and thereby the duty-cycle.

MCONF2 - Modulation Configuration Bit 2

#define MCONF2 2

MODCONF[2:0] determine the relationship between the on- and off-times of the modulat or , and thereby the duty-cycle.