<ATtiny26.h>

This documentation was generated automatically from the AVR Studio part description file ATtiny26.pdf.

AD CONVERTER

AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 盜 Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode Noise

ADMUX - The ADC multiplexer Selection Register

sfrb ADMUX = $07;

MUX0 - Analog Channel and Gain Selection Bits

#define MUX0 0

The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).

MUX1 - Analog Channel and Gain Selection Bits

#define MUX1 1

MUX2 - Analog Channel and Gain Selection Bits

#define MUX2 2

MUX3 - Analog Channel and Gain Selection Bits

#define MUX3 3

MUX4 - Analog Channel and Gain Selection Bits

#define MUX4 4

ADLAR - Left Adjust Result

#define ADLAR 5

The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see ?The ADC Data Register -ADCL and ADCH? on page 198.

REFS0 - Reference Selection Bit 0

#define REFS0 6

These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.

REFS1 - Reference Selection Bit 1

#define REFS1 7

ADCSRA - The ADC Control and Status register

sfrb ADCSRA = $06;

ADPS0 - ADC Prescaler Select Bits

#define ADPS0 0

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

ADPS1 - ADC Prescaler Select Bits

#define ADPS1 1

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

ADPS2 - ADC Prescaler Select Bits

#define ADPS2 2

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

ADIE - ADC Interrupt Enable

#define ADIE 3

When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.

ADIF - ADC Interrupt Flag

#define ADIF 4

This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.

ADFR - ADC Free Running Select

#define ADFR 5

When this bit is set (one) the ADC operates in Free Running Mode. In this mode, the ADC samples and updates the data registers continuously. Clearing this bit (zero) will terminate Free Running Mode.

ADSC - ADC Start Conversion

#define ADSC 6

In Single Conversion Mode, a logical ?1? must be written to this bit to start each conversion. In Free Running Mode, a logical ?1? must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect

ADEN - ADC Enable

#define ADEN 7

Writing a logical ?1? to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.

ADCH - ADC Data Register High Byte

sfrb ADCH = $05;

ADCH0 - ADC Data Register High Byte Bit 0

#define ADCH0 0

ADCH1 - ADC Data Register High Byte Bit 1

#define ADCH1 1

ADCH2 - ADC Data Register High Byte Bit 2

#define ADCH2 2

ADCH3 - ADC Data Register High Byte Bit 3

#define ADCH3 3

ADCH4 - ADC Data Register High Byte Bit 4

#define ADCH4 4

ADCH5 - ADC Data Register High Byte Bit 5

#define ADCH5 5

ADCH6 - ADC Data Register High Byte Bit 6

#define ADCH6 6

ADCH7 - ADC Data Register High Byte Bit 7

#define ADCH7 7

ADCL - ADC Data Register Low Byte

sfrb ADCL = $04;

ADCL0 - ADC Data Register Low Byte Bit 0

#define ADCL0 0

ADCL1 - ADC Data Register Low Byte Bit 1

#define ADCL1 1

ADCL2 - ADC Data Register Low Byte Bit 2

#define ADCL2 2

ADCL3 - ADC Data Register Low Byte Bit 3

#define ADCL3 3

ADCL4 - ADC Data Register Low Byte Bit 4

#define ADCL4 4

ADCL5 - ADC Data Register Low Byte Bit 5

#define ADCL5 5

ADCL6 - ADC Data Register Low Byte Bit 6

#define ADCL6 6

ADCL7 - ADC Data Register Low Byte Bit 7

#define ADCL7 7

ANALOG COMPARATOR

ACSR - Analog Comparator Control And Status Register

sfrb ACSR = $08;

ACIS0 - Analog Comparator Interrupt Mode Select bit 0

#define ACIS0 0

These bits determine which comparator events that trigger the Analog Comparator interrupt.

ACIS1 - Analog Comparator Interrupt Mode Select bit 1

#define ACIS1 1

These bits determine which comparator events that trigger the Analog Comparator interrupt.

ACME - Analog Comparator Multiplexer Enable

#define ACME 2

When the ACME bit is set (one) and the ADC is switched off (ADEN in ADCSR is zero), MUX3...0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in the table in the datasheet. If ACME is cleared (zero) or ADEN is set (one), PA7(AIN1) is applied to the negative input to the Analog Comparator.

ACIE - Analog Comparator Interrupt Enable

#define ACIE 3

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.

ACI - Analog Comparator Interrupt Flag

#define ACI 4

This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

ACO - Analog Compare Output

#define ACO 5

The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.

ACBG - Analog Comparator Bandgap Select

#define ACBG 6

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See ?Internal Voltage Reference? on page 42.

ACD - Analog Comparator Disable

#define ACD 7

When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

USI

Universal Serial Interface

USIDR - USI Data Register

sfrb USIDR = $0F;

USIDR0 - USI Data Register bit 0

#define USIDR0 0

USIDR1 - USI Data Register bit 1

#define USIDR1 1

USIDR2 - USI Data Register bit 2

#define USIDR2 2

USIDR3 - USI Data Register bit 3

#define USIDR3 3

USIDR4 - USI Data Register bit 4

#define USIDR4 4

USIDR5 - USI Data Register bit 5

#define USIDR5 5

USIDR6 - USI Data Register bit 6

#define USIDR6 6

USIDR7 - USI Data Register bit 7

#define USIDR7 7

USISR - USI Status Register

sfrb USISR = $0E;

USICNT0 - USI Counter Value Bit 0

#define USICNT0 0

USICNT1 - USI Counter Value Bit 1

#define USICNT1 1

USICNT2 - USI Counter Value Bit 2

#define USICNT2 2

USICNT3 - USI Counter Value Bit 3

#define USICNT3 3

USIDC - Data Output Collision

#define USIDC 4

USIPF - Stop Condition Flag

#define USIPF 5

USIOIF - Counter Overflow Interrupt Flag

#define USIOIF 6

USISIF - Start Condition Interrupt Flag

#define USISIF 7

USICR - USI Control Register

sfrb USICR = $0D;

USITC - Toggle Clock Port Pin

#define USITC 0

USICLK - Clock Strobe

#define USICLK 1

USICS0 - USI Clock Source Select Bit 0

#define USICS0 2

USICS1 - USI Clock Source Select Bit 1

#define USICS1 3

USIWM0 - USI Wire Mode Bit 0

#define USIWM0 4

USIWM1 - USI Wire Mode Bit 1

#define USIWM1 5

USIOIE - Counter Overflow Interrupt Enable

#define USIOIE 6

USISIE - Start Condition Interrupt Enable

#define USISIE 7

PORTA

PORTA - Port A Data Register

sfrb PORTA = $1B;

PORTA0 - Port A Data Register bit 0

#define PORTA0 0

PORTA1 - Port A Data Register bit 1

#define PORTA1 1

PORTA2 - Port A Data Register bit 2

#define PORTA2 2

PORTA3 - Port A Data Register bit 3

#define PORTA3 3

PORTA4 - Port A Data Register bit 4

#define PORTA4 4

PORTA5 - Port A Data Register bit 5

#define PORTA5 5

PORTA6 - Port A Data Register bit 6

#define PORTA6 6

PORTA7 - Port A Data Register bit 7

#define PORTA7 7

DDRA - Port A Data Direction Register

sfrb DDRA = $1A;

DDA0 - Data Direction Register, Port A, bit 0

#define DDA0 0

DDA1 - Data Direction Register, Port A, bit 1

#define DDA1 1

DDA2 - Data Direction Register, Port A, bit 2

#define DDA2 2

DDA3 - Data Direction Register, Port A, bit 3

#define DDA3 3

DDA4 - Data Direction Register, Port A, bit 4

#define DDA4 4

DDA5 - Data Direction Register, Port A, bit 5

#define DDA5 5

DDA6 - Data Direction Register, Port A, bit 6

#define DDA6 6

DDA7 - Data Direction Register, Port A, bit 7

#define DDA7 7

PINA - Port A Input Pins

sfrb PINA = $19;

PINA0 - Input Pins, Port A bit 0

#define PINA0 0

PINA1 - Input Pins, Port A bit 1

#define PINA1 1

PINA2 - Input Pins, Port A bit 2

#define PINA2 2

PINA3 - Input Pins, Port A bit 3

#define PINA3 3

PINA4 - Input Pins, Port A bit 4

#define PINA4 4

PINA5 - Input Pins, Port A bit 5

#define PINA5 5

PINA6 - Input Pins, Port A bit 6

#define PINA6 6

PINA7 - Input Pins, Port A bit 7

#define PINA7 7

PORTB

PORTB - Port B Data Register

sfrb PORTB = $18;

PORTB0 - Port B Data Register bit 0

#define PORTB0 0

PORTB1 - Port B Data Register bit 1

#define PORTB1 1

PORTB2 - Port B Data Register bit 2

#define PORTB2 2

PORTB3 - Port B Data Register bit 3

#define PORTB3 3

PORTB4 - Port B Data Register bit 4

#define PORTB4 4

PORTB5 - Port B Data Register bit 5

#define PORTB5 5

PORTB6 - Port B Data Register bit 6

#define PORTB6 6

PORTB7 - Port B Data Register bit 7

#define PORTB7 7

DDRB - Port B Data Direction Register

sfrb DDRB = $17;

DDB0 - Port B Data Direction Register bit 0

#define DDB0 0

DDB1 - Port B Data Direction Register bit 1

#define DDB1 1

DDB2 - Port B Data Direction Register bit 2

#define DDB2 2

DDB3 - Port B Data Direction Register bit 3

#define DDB3 3

DDB4 - Port B Data Direction Register bit 4

#define DDB4 4

DDB5 - Port B Data Direction Register bit 5

#define DDB5 5

DDB6 - Port B Data Direction Register bit 6

#define DDB6 6

DDB7 - Port B Data Direction Register bit 7

#define DDB7 7

PINB - Port B Input Pins

sfrb PINB = $16;

PINB0 - Port B Input Pins bit 0

#define PINB0 0

PINB1 - Port B Input Pins bit 1

#define PINB1 1

PINB2 - Port B Input Pins bit 2

#define PINB2 2

PINB3 - Port B Input Pins bit 3

#define PINB3 3

PINB4 - Port B Input Pins bit 4

#define PINB4 4

PINB5 - Port B Input Pins bit 5

#define PINB5 5

PINB6 - Port B Input Pins bit 6

#define PINB6 6

PINB7 - Port B Input Pins bit 7

#define PINB7 7

EEPROM

EEAR - EEPROM Read/Write Access

sfrb EEAR = $1E;

EEAR0 - EEPROM Read/Write Access bit 0

#define EEAR0 0

EEAR1 - EEPROM Read/Write Access bit 1

#define EEAR1 1

EEAR2 - EEPROM Read/Write Access bit 2

#define EEAR2 2

EEAR3 - EEPROM Read/Write Access bit 3

#define EEAR3 3

EEAR4 - EEPROM Read/Write Access bit 4

#define EEAR4 4

EEAR5 - EEPROM Read/Write Access bit 5

#define EEAR5 5

EEAR6 - EEPROM Read/Write Access bit 6

#define EEAR6 6

EEDR - EEPROM Data Register

sfrb EEDR = $1D;

EEDR0 - EEPROM Data Register bit 0

#define EEDR0 0

EEDR1 - EEPROM Data Register bit 1

#define EEDR1 1

EEDR2 - EEPROM Data Register bit 2

#define EEDR2 2

EEDR3 - EEPROM Data Register bit 3

#define EEDR3 3

EEDR4 - EEPROM Data Register bit 4

#define EEDR4 4

EEDR5 - EEPROM Data Register bit 5

#define EEDR5 5

EEDR6 - EEPROM Data Register bit 6

#define EEDR6 6

EEDR7 - EEPROM Data Register bit 7

#define EEDR7 7

EECR - EEPROM Control Register

sfrb EECR = $1C;

EERE - EEPROM Read Enable

#define EERE 0

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined.

EEWE - EEPROM Write Enable

#define EEWE 1

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one to the EEMWE bit, the EEWE bit mustbewritten to zero in thesamecycle). 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at V CC =5Vor 4msatV CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted or two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems.

EEMWE - EEPROM Master Write Enable

#define EEMWE 2

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure.

EERIE - EEProm Ready Interrupt Enable

#define EERIE 3

When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero).

WATCHDOG

WDTCR - Watchdog Timer Control Register

sfrb WDTCR = $21;

WDP0 - Watch Dog Timer Prescaler bit 0

#define WDP0 0

The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.

WDP1 - Watch Dog Timer Prescaler bit 1

#define WDP1 1

The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.

WDP2 - Watch Dog Timer Prescaler bit 2

#define WDP2 2

The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.

WDE - Watch Dog Enable

#define WDE 3

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog

WDCE - Watchdog Change Enable

#define WDCE 4

This bit must be set when the WDE bit is written to logic zero.Otherwise,the watchdog will not be disabled.Once written to one,hardware will clear this bit after four clock cycles.Refer to the description of the WDE bit for a watchdog disable procedure.This bit must also be set when changing the prescaler bits.

CPU

SREG - Status Register

sfrb SREG = $3F;

SP - Stack Pointer

sfrb SP = $3D;

SP0 - Stack Pointer Bit 0

#define SP0 0

SP1 - Stack Pointer Bit 1

#define SP1 1

SP2 - Stack Pointer Bit 2

#define SP2 2

SP3 - Stack Pointer Bit 3

#define SP3 3

SP4

#define SP4 4

SP5 - Stack Pointer Bit 5

#define SP5 5

SP6 - Stack Pointer Bit 6

#define SP6 6

SP7 - Stack Pointer Bit 7

#define SP7 7

MCUCR - MCU Control Register

sfrb MCUCR = $35;

ISC00 - Interrupt Sense Control 0 bit 0

#define ISC00 0

ISC01 - Interrupt Sense Control 0 bit 1

#define ISC01 1

SM0 - Sleep Mode Select Bit 0

#define SM0 3

SM1 - Sleep Mode Select Bit 1

#define SM1 4

SE - Sleep Enable

#define SE 5

The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.

PUD - Pull-up Disable

#define PUD 6

MCUSR - MCU Status register

sfrb MCUSR = $34;

PORF - Power-On Reset Flag

#define PORF 0

This bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchanged

EXTRF - External Reset Flag

#define EXTRF 1

After a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged.

BORF - Brown-out Reset Flag

#define BORF 2

WDRF - Watchdog Reset Flag

#define WDRF 3

OSCCAL - Status Register

sfrb OSCCAL = $31;

CAL0 - Oscillator Calibration Value Bit 0

#define CAL0 0

CAL1 - Oscillator Calibration Value Bit 1

#define CAL1 1

CAL2 - Oscillator Calibration Value Bit 2

#define CAL2 2

CAL3 - Oscillator Calibration Value Bit 3

#define CAL3 3

CAL4

#define CAL4 4

CAL5 - Oscillator Calibration Value Bit 5

#define CAL5 5

CAL6 - Oscillator Calibration Value Bit 6

#define CAL6 6

CAL7 - Oscillator Calibration Value Bit 7

#define CAL7 7

TIMER COUNTER 0

The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in ?Timer/Counter0 Control Register - TCCR0? on page 35. The overflow status flag is found in ?The Timer/Counter Interrupt Flag Register - TIFR? on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in ?The Timer/Counter Interrupt Mask Regis-ter - TIMSK? on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions

TIMSK - Timer/Counter Interrupt Mask Register

sfrb TIMSK = $39;

TOIE0 - Timer/Counter0 Overflow Interrupt Enable

#define TOIE0 1

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

TIFR - Timer/Counter Interrupt Flag register

sfrb TIFR = $38;

TOV0 - Timer/Counter0 Overflow Flag

#define TOV0 1

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.

TCCR0 - Timer/Counter0 Control Register

sfrb TCCR0 = $33;

CS00 - Clock Select0 bit 0

#define CS00 0

CS01 - Clock Select0 bit 1

#define CS01 1

CS02 - Clock Select0 bit 2

#define CS02 2

PSR0 - Prescaler Reset Timer/Counter0

#define PSR0 3

When this bit is set (one), the prescaler of the Timer/Counter0 will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always be read as zero.

TCNT0 - Timer Counter 0

sfrb TCNT0 = $32;

TCNT00 - Timer Counter 0 bit 0

#define TCNT00 0

TCNT01 - Timer Counter 0 bit 1

#define TCNT01 1

TCNT02 - Timer Counter 0 bit 2

#define TCNT02 2

TCNT03 - Timer Counter 0 bit 3

#define TCNT03 3

TCNT04 - Timer Counter 0 bit 4

#define TCNT04 4

TCNT05 - Timer Counter 0 bit 5

#define TCNT05 5

TCNT06 - Timer Counter 0 bit 6

#define TCNT06 6

TCNT07 - Timer Counter 0 bit 7

#define TCNT07 7

TIMER COUNTER 1

TCCR1A - Timer/Counter Control Register A

sfrb TCCR1A = $30;

PWM1B - Pulse Width Modulator B Enable

#define PWM1B 0

When set (one) this bit enables PWM mode based on comparator OCR1B in Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value.

PWM1A - Pulse Width Modulator A Enable

#define PWM1A 1

When set (one) this bit enables PWM mode based on comparator OCR1A in Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value.

FOC1B - Force Output Compare Match 1B

#define FOC1B 2

Writing a logical one to this bit forces a change in the compare match output pin PB3 (OC1B) according to the values already set in COM1B1 and COM1B0. If COM1B1 and COM1B0 written in the same cycle as FOC1B, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1B1 and COM1B0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1B bit always reads as zero. FOC1B is not in use if PWM1B bit is set

FOC1A - Force Output Compare Match 1A

#define FOC1A 3

Writing a logical one to this bit forces a change in the compare match output pin PB1 (OC1A) according to the values already set in COM1A1 and COM1A0. If COM1A1 and COM1A0 written in the same cycle as FOC1A, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1A1 and COM1A0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1A bit always reads as zero. FOC1A is not in use if PWM1A bit is

COM1B0 - Comparator B Output Mode Bit 0

#define COM1B0 4

The COM1B1 and COM1B0 control bits determine any output pin action following a compare match with compare register B in Timer/Counter1. Output pin actions affect pin PB3 (OC1B). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1B is not connected in normal mode.

COM1B1 - Comparator B Output Mode Bit 1

#define COM1B1 5

COM1A0 - Comparator A Output Mode Bit 0

#define COM1A0 6

The COM1A1 and COM1A0 control bits determine any output pin action following a compare match with compare register A in Timer/Counter1. Output pin actions affect pin PB1 (OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1A is not connected in normal mode.

COM1A1 - Comparator A Output Mode Bit 1

#define COM1A1 7

TCCR1B - Timer/Counter Control Register B

sfrb TCCR1B = $2F;

CS10 - Clock Select Bits

#define CS10 0

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

CS11 - Clock Select Bits

#define CS11 1

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

CS12 - Clock Select Bits

#define CS12 2

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

CS13 - Clock Select Bits

#define CS13 3

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

PSR1 - Prescaler Reset Timer/Counter1

#define PSR1 6

When this bit is set (one), the Timer/Counter prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always read as zero.

CTC1 - Clear Timer/Counter on Compare Match

#define CTC1 7

When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value. If the control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match.

TCNT1 - Timer/Counter Register

sfrb TCNT1 = $2E;

TCNT1_0 - Timer/Counter Register Bit 0

#define TCNT1_0 0

TCNT1_1 - Timer/Counter Register Bit 1

#define TCNT1_1 1

TCNT1_2 - Timer/Counter Register Bit 2

#define TCNT1_2 2

TCNT1_3 - Timer/Counter Register Bit 3

#define TCNT1_3 3

TCNT1_4 - Timer/Counter Register Bit 4

#define TCNT1_4 4

TCNT1_5 - Timer/Counter Register Bit 5

#define TCNT1_5 5

TCNT1_6 - Timer/Counter Register Bit 6

#define TCNT1_6 6

TCNT1_7 - Timer/Counter Register Bit 7

#define TCNT1_7 7

OCR1A - Output Compare Register

sfrb OCR1A = $2D;

OCR1A0 - Output Compare Register A Bit 0

#define OCR1A0 0

OCR1A1 - Output Compare Register A Bit 1

#define OCR1A1 1

OCR1A2 - Output Compare Register A Bit 2

#define OCR1A2 2

OCR1A3 - Output Compare Register A Bit 3

#define OCR1A3 3

OCR1A4 - Output Compare Register A Bit 4

#define OCR1A4 4

OCR1A5 - Output Compare Register A Bit 5

#define OCR1A5 5

OCR1A6 - Output Compare Register A Bit 6

#define OCR1A6 6

OCR1A7 - Output Compare Register A Bit 7

#define OCR1A7 7

OCR1B - Output Compare Register

sfrb OCR1B = $2C;

OCR1B0 - Output Compare Register B Bit 0

#define OCR1B0 0

OCR1B1 - Output Compare Register B Bit 1

#define OCR1B1 1

OCR1B2 - Output Compare Register B Bit 2

#define OCR1B2 2

OCR1B3 - Output Compare Register B Bit 3

#define OCR1B3 3

OCR1B4 - Output Compare Register B Bit 4

#define OCR1B4 4

OCR1B5 - Output Compare Register B Bit 5

#define OCR1B5 5

OCR1B6 - Output Compare Register B Bit 6

#define OCR1B6 6

OCR1B7 - Output Compare Register B Bit 7

#define OCR1B7 7

OCR1C - Output Compare Register

sfrb OCR1C = $2B;

OCR1C0 - Output Compare Register C Bit 0

#define OCR1C0 0

OCR1C1 - Output Compare Register C Bit 1

#define OCR1C1 1

OCR1C2 - Output Compare Register C Bit 2

#define OCR1C2 2

OCR1C3 - Output Compare Register C Bit 3

#define OCR1C3 3

OCR1C4 - Output Compare Register C Bit 4

#define OCR1C4 4

OCR1C5 - Output Compare Register C Bit 5

#define OCR1C5 5

OCR1C6 - Output Compare Register C Bit 6

#define OCR1C6 6

OCR1C7 - Output Compare Register C Bit 7

#define OCR1C7 7

TIMSK - Timer/Counter Interrupt Mask Register

sfrb TIMSK = $39;

TOIE0 - Timer/Counter1 Overflow Interrupt Enable

#define TOIE0 1

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs (i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).

TOIE1 - Timer/Counter1 Overflow Interrupt Enable

#define TOIE1 2

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs (i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).

OCIE1B - Timer/Counter1 Output Compare Interrupt Enable

#define OCIE1B 5

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchB, interrupt is enabled. The corresponding interrupt at vector $004 is executed if a compare matchB occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.

OCIE1A - Timer/Counter1 Output Compare Interrupt Enable

#define OCIE1A 6

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchA, interrupt is enabled. The corresponding interrupt at vector $003 is executed if a compare matchA occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.

TIFR - Timer/Counter Interrupt Flag Register

sfrb TIFR = $38;

TOV1 - Timer/Counter1 Overflow Flag

#define TOV1 2

The bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logical ?1? to the flag. When the SREG I-bit, TOIE1 (Timer/Counter1 Overf low Interrupt Enable) and TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed.

OCF1B - Timer/Counter1 Output Compare Flag 1B

#define OCF1B 5

The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1B ? Output Compare Register 1A. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1B is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1B, and OCF1B are set (one), the Timer/Counter1 B compare match interrupt is executed.

OCF1A - Timer/Counter1 Output Compare Flag 1A

#define OCF1A 6

The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A (Output Compare Register 1A). OCF1A is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logical ?1? to the flag. When the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 compare match A interrupt is executed.

PLLCSR - PLL Control and Status Register

sfrb PLLCSR = $29;

PLOCK - PLL Lock Detector

#define PLOCK 0

PLLE - PLL Enable

#define PLLE 1

PCKE - PCK Enable

#define PCKE 2

EXTERNAL INTERRUPT

GIMSK - General Interrupt Mask Register

sfrb GIMSK = $3B;

PCIE0 - Pin Change Interrupt Enable 0

#define PCIE0 4

PCIE1 - Pin Change Interrupt Enable 1

#define PCIE1 5

INT0 - External Interrupt Request 0 Enable

#define INT0 6

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also ?External Interrupts.? ? Bits 5..0 - Res: Reserved bits

GIFR - General Interrupt Flag register

sfrb GIFR = $3A;

PCIF - Pin Change Interrupt Flag

#define PCIF 5

INTF0 - External Interrupt Flag 0

#define INTF0 6

When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.