<ATtiny24.h>

This documentation was generated automatically from the AVR Studio part description file ATtiny24.pdf.

PORTA

PORTA - Port A Data Register

sfrb PORTA = $1B;

PORTA0 - Port A Data Register bit 0

#define PORTA0 0

PORTA1 - Port A Data Register bit 1

#define PORTA1 1

PORTA2 - Port A Data Register bit 2

#define PORTA2 2

PORTA3 - Port A Data Register bit 3

#define PORTA3 3

PORTA4 - Port A Data Register bit 4

#define PORTA4 4

PORTA5 - Port A Data Register bit 5

#define PORTA5 5

PORTA6 - Port A Data Register bit 6

#define PORTA6 6

PORTA7 - Port A Data Register bit 7

#define PORTA7 7

DDRA - Port A Data Direction Register

sfrb DDRA = $1A;

DDA0 - Data Direction Register, Port A, bit 0

#define DDA0 0

DDA1 - Data Direction Register, Port A, bit 1

#define DDA1 1

DDA2 - Data Direction Register, Port A, bit 2

#define DDA2 2

DDA3 - Data Direction Register, Port A, bit 3

#define DDA3 3

DDA4 - Data Direction Register, Port A, bit 4

#define DDA4 4

DDA5 - Data Direction Register, Port A, bit 5

#define DDA5 5

DDA6 - Data Direction Register, Port A, bit 6

#define DDA6 6

DDA7 - Data Direction Register, Port A, bit 7

#define DDA7 7

PINA - Port A Input Pins

sfrb PINA = $19;

PINA0 - Input Pins, Port A bit 0

#define PINA0 0

PINA1 - Input Pins, Port A bit 1

#define PINA1 1

PINA2 - Input Pins, Port A bit 2

#define PINA2 2

PINA3 - Input Pins, Port A bit 3

#define PINA3 3

PINA4 - Input Pins, Port A bit 4

#define PINA4 4

PINA5 - Input Pins, Port A bit 5

#define PINA5 5

PINA6 - Input Pins, Port A bit 6

#define PINA6 6

PINA7 - Input Pins, Port A bit 7

#define PINA7 7

PORTB

PORTB - Data Register, Port B

sfrb PORTB = $18;

PORTB0

#define PORTB0 0

PORTB1

#define PORTB1 1

PORTB2

#define PORTB2 2

PORTB3

#define PORTB3 3

DDRB - Data Direction Register, Port B

sfrb DDRB = $17;

DDB0

#define DDB0 0

DDB1

#define DDB1 1

DDB2

#define DDB2 2

DDB3

#define DDB3 3

PINB - Input Pins, Port B

sfrb PINB = $16;

PINB0

#define PINB0 0

PINB1

#define PINB1 1

PINB2

#define PINB2 2

PINB3

#define PINB3 3

ANALOG COMPARATOR

ADCSRB - ADC Control and Status Register B

sfrb ADCSRB = $03;

ACME - Analog Comparator Multiplexer Enable

#define ACME 6

When this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see ?Analog Comparator Multiplexed Input? on page 186.

ACSR - Analog Comparator Control And Status Register

sfrb ACSR = $08;

ACIS0 - Analog Comparator Interrupt Mode Select bit 0

#define ACIS0 0

These bits determine which comparator events that trigger the Analog Comparator interrupt.

ACIS1 - Analog Comparator Interrupt Mode Select bit 1

#define ACIS1 1

These bits determine which comparator events that trigger the Analog Comparator interrupt.

ACIC - Analog Comparator Input Capture Enable

#define ACIC 2

When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the Analog Comparator.

ACIE - Analog Comparator Interrupt Enable

#define ACIE 3

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.

ACI - Analog Comparator Interrupt Flag

#define ACI 4

This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

ACO - Analog Compare Output

#define ACO 5

The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.

ACBG - Analog Comparator Bandgap Select

#define ACBG 6

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See ?Internal Voltage Reference? on page 42.

ACD - Analog Comparator Disable

#define ACD 7

When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

DIDR0 -

sfrb DIDR0 = $01;

ADC0D - ADC 0 Digital input buffer disable

#define ADC0D 0

When this bit is written logic one,the digital input buffer on the AIN0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

ADC1D - ADC 1 Digital input buffer disable

#define ADC1D 1

When this bit is written logic one,the digital input buffer on the AIN1 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

AD CONVERTER

ADMUX - ADC Multiplexer Selection Register

sfrb ADMUX = $07;

MUX0 - Analog Channel and Gain Selection Bit 0

#define MUX0 0

MUX1 - Analog Channel and Gain Selection Bit 1

#define MUX1 1

MUX2 - Analog Channel and Gain Selection Bit 2

#define MUX2 2

MUX3 - Analog Channel and Gain Selection Bit 3

#define MUX3 3

MUX4 - Analog Channel and Gain Selection Bit 4

#define MUX4 4

MUX5 - Analog Channel and Gain Selection Bit 5

#define MUX5 5

REFS0 - Reference Selection Bit 0

#define REFS0 6

REFS1 - Reference Selection Bit 1

#define REFS1 7

ADCSRA - ADC Control and Status Register A

sfrb ADCSRA = $06;

ADPS0 - ADC Prescaler Select Bit 0

#define ADPS0 0

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

ADPS1 - ADC Prescaler Select Bit 1

#define ADPS1 1

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

ADPS2 - ADC Prescaler Select Bit 2

#define ADPS2 2

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

ADIE - ADC Interrupt Enable

#define ADIE 3

When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.

ADIF - ADC Interrupt Flag

#define ADIF 4

This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.

ADATE - ADC Auto Trigger Enable

#define ADATE 5

When this bit is written to one,Auto Triggering of the ADC is enabled.The ADC will start a conversion on a positive edge of the selected trigger signal.The trigger source is selected by setting the ADC Trigger Select bits,ADTS in ADCSRB.

ADSC - ADC Start Conversion

#define ADSC 6

In Single Conversion Mode, a logical ?1? must be written to this bit to start each conversion. In Free Running Mode, a logical ?1? must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effec

ADEN - ADC Enable

#define ADEN 7

Writing a logical ?1? to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.

ADCH - ADC Data Register High Byte

sfrb ADCH = $05;

ADCH0 - ADC Data Register High Byte Bit 0

#define ADCH0 0

ADCH1 - ADC Data Register High Byte Bit 1

#define ADCH1 1

ADCH2 - ADC Data Register High Byte Bit 2

#define ADCH2 2

ADCH3 - ADC Data Register High Byte Bit 3

#define ADCH3 3

ADCH4 - ADC Data Register High Byte Bit 4

#define ADCH4 4

ADCH5 - ADC Data Register High Byte Bit 5

#define ADCH5 5

ADCH6 - ADC Data Register High Byte Bit 6

#define ADCH6 6

ADCH7 - ADC Data Register High Byte Bit 7

#define ADCH7 7

ADCL - ADC Data Register Low Byte

sfrb ADCL = $04;

ADCL0 - ADC Data Register Low Byte Bit 0

#define ADCL0 0

ADCL1 - ADC Data Register Low Byte Bit 1

#define ADCL1 1

ADCL2 - ADC Data Register Low Byte Bit 2

#define ADCL2 2

ADCL3 - ADC Data Register Low Byte Bit 3

#define ADCL3 3

ADCL4 - ADC Data Register Low Byte Bit 4

#define ADCL4 4

ADCL5 - ADC Data Register Low Byte Bit 5

#define ADCL5 5

ADCL6 - ADC Data Register Low Byte Bit 6

#define ADCL6 6

ADCL7 - ADC Data Register Low Byte Bit 7

#define ADCL7 7

ADCSRB - ADC Control and Status Register B

sfrb ADCSRB = $03;

ADTS0 - ADC Auto Trigger Source bit 0

#define ADTS0 0

If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set .

ADTS1 - ADC Auto Trigger Source bit 1

#define ADTS1 1

ADTS2 - ADC Auto Trigger Source bit 2

#define ADTS2 2

ADLAR - ADC Left Adjust Result

#define ADLAR 4

BIN - Bipolar Input Mode

#define BIN 7

The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected by writing the BIN bit in the ADCSRB register.

DIDR0 - Digital Input Disable Register 0

sfrb DIDR0 = $01;

ADC0D - ADC0 Digital Input Disable

#define ADC0D 0

ADC1D - ADC1 Digital Input Disable

#define ADC1D 1

ADC2D - ADC2 Digital Input Disable

#define ADC2D 2

ADC3D - ADC3 Digital Input Disable

#define ADC3D 3

ADC4D - ADC4 Digital Input Disable

#define ADC4D 4

ADC5D - ADC5 Digital Input Disable

#define ADC5D 5

ADC6D - ADC6 Digital Input Disable

#define ADC6D 6

ADC7D - ADC7 Digital Input Disable

#define ADC7D 7

USI

Universal Serial Interface

USIBR - USI Buffer Register

sfrb USIBR = $10;

USIBR0 - USI Buffer Register bit 0

#define USIBR0 0

USIBR1 - USI Buffer Register bit 1

#define USIBR1 1

USIBR2 - USI Buffer Register bit 2

#define USIBR2 2

USIBR3 - USI Buffer Register bit 3

#define USIBR3 3

USIBR4 - USI Buffer Register bit 4

#define USIBR4 4

USIBR5 - USI Buffer Register bit 5

#define USIBR5 5

USIBR6 - USI Buffer Register bit 6

#define USIBR6 6

USIBR7 - USI Buffer Register bit 7

#define USIBR7 7

USIDR - USI Data Register

sfrb USIDR = $0F;

USIDR0 - USI Data Register bit 0

#define USIDR0 0

USIDR1 - USI Data Register bit 1

#define USIDR1 1

USIDR2 - USI Data Register bit 2

#define USIDR2 2

USIDR3 - USI Data Register bit 3

#define USIDR3 3

USIDR4 - USI Data Register bit 4

#define USIDR4 4

USIDR5 - USI Data Register bit 5

#define USIDR5 5

USIDR6 - USI Data Register bit 6

#define USIDR6 6

USIDR7 - USI Data Register bit 7

#define USIDR7 7

USISR - USI Status Register

sfrb USISR = $0E;

USICNT0 - USI Counter Value Bit 0

#define USICNT0 0

USICNT1 - USI Counter Value Bit 1

#define USICNT1 1

USICNT2 - USI Counter Value Bit 2

#define USICNT2 2

USICNT3 - USI Counter Value Bit 3

#define USICNT3 3

USIDC - Data Output Collision

#define USIDC 4

USIPF - Stop Condition Flag

#define USIPF 5

USIOIF - Counter Overflow Interrupt Flag

#define USIOIF 6

USISIF - Start Condition Interrupt Flag

#define USISIF 7

USICR - USI Control Register

sfrb USICR = $0D;

USITC - Toggle Clock Port Pin

#define USITC 0

USICLK - Clock Strobe

#define USICLK 1

USICS0 - USI Clock Source Select Bit 0

#define USICS0 2

USICS1 - USI Clock Source Select Bit 1

#define USICS1 3

USIWM0 - USI Wire Mode Bit 0

#define USIWM0 4

USIWM1 - USI Wire Mode Bit 1

#define USIWM1 5

USIOIE - Counter Overflow Interrupt Enable

#define USIOIE 6

USISIE - Start Condition Interrupt Enable

#define USISIE 7

EXTERNAL INTERRUPT

MCUCR - MCU Control Register

sfrb MCUCR = $35;

ISC00 - Interrupt Sense Control 0 Bit 0

#define ISC00 0

ISC01 - Interrupt Sense Control 0 Bit 1

#define ISC01 1

GIMSK - General Interrupt Mask Register

sfrb GIMSK = $3B;

PCIE0 - Pin Change Interrupt Enable 0

#define PCIE0 4

PCIE1 - Pin Change Interrupt Enable 1

#define PCIE1 5

INT0 - External Interrupt Request 0 Enable

#define INT0 6

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also ?External Interrupts.? ? Bits 5..0 - Res: Reserved bits

GIFR - General Interrupt Flag register

sfrb GIFR = $3A;

PCIF0 - Pin Change Interrupt Flag 0

#define PCIF0 4

PCIF1 - Pin Change Interrupt Flag 1

#define PCIF1 5

INTF0 - External Interrupt Flag 0

#define INTF0 6

When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

PCMSK1 - Pin Change Enable Mask 1

sfrb PCMSK1 = $20;

PCINT8 - Pin Change Enable Mask Bit 8

#define PCINT8 0

PCINT9 - Pin Change Enable Mask Bit 9

#define PCINT9 1

PCINT10 - Pin Change Enable Mask Bit 10

#define PCINT10 2

PCINT11 - Pin Change Enable Mask Bit 11

#define PCINT11 3

PCMSK0 - Pin Change Enable Mask 0

sfrb PCMSK0 = $12;

PCINT0 - Pin Change Enable Mask Bit 0

#define PCINT0 0

PCINT1 - Pin Change Enable Mask Bit 1

#define PCINT1 1

PCINT2 - Pin Change Enable Mask Bit 2

#define PCINT2 2

PCINT3 - Pin Change Enable Mask Bit 3

#define PCINT3 3

PCINT4 - Pin Change Enable Mask Bit 4

#define PCINT4 4

PCINT5 - Pin Change Enable Mask Bit 5

#define PCINT5 5

PCINT6 - Pin Change Enable Mask Bit 6

#define PCINT6 6

PCINT7 - Pin Change Enable Mask Bit 7

#define PCINT7 7

EEPROM

EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See ?Preventing EEPROM Corruption? on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execut

EEARH - EEPROM Address Register High Byte

sfrb EEARH = $1F;

EEAR8 - EEPROM Read/Write Access Bit 0

#define EEAR8 0

EEARL - EEPROM Address Register Low Byte

sfrb EEARL = $1E;

EEAR0 - EEPROM Read/Write Access Bit 0

#define EEAR0 0

EEAR1 - EEPROM Read/Write Access Bit 1

#define EEAR1 1

EEAR2 - EEPROM Read/Write Access Bit 2

#define EEAR2 2

EEAR3 - EEPROM Read/Write Access Bit 3

#define EEAR3 3

EEAR4 - EEPROM Read/Write Access Bit 4

#define EEAR4 4

EEAR5 - EEPROM Read/Write Access Bit 5

#define EEAR5 5

EEAR6 - EEPROM Read/Write Access Bit 6

#define EEAR6 6

EEAR7 - EEPROM Read/Write Access Bit 7

#define EEAR7 7

EEDR - EEPROM Data Register

sfrb EEDR = $1D;

EEDR0 - EEPROM Data Register bit 0

#define EEDR0 0

EEDR1 - EEPROM Data Register bit 1

#define EEDR1 1

EEDR2 - EEPROM Data Register bit 2

#define EEDR2 2

EEDR3 - EEPROM Data Register bit 3

#define EEDR3 3

EEDR4 - EEPROM Data Register bit 4

#define EEDR4 4

EEDR5 - EEPROM Data Register bit 5

#define EEDR5 5

EEDR6 - EEPROM Data Register bit 6

#define EEDR6 6

EEDR7 - EEPROM Data Register bit 7

#define EEDR7 7

EECR - EEPROM Control Register

sfrb EECR = $1C;

EERE - EEPROM Read Enable

#define EERE 0

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU

EEPE - EEPROM Write Enable

#define EEPE 1

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See ?Boot Loader Support - Read While Write self-programming? on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed

EEMPE - EEPROM Master Write Enable

#define EEMPE 2

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

EERIE - EEPROM Ready Interrupt Enable

#define EERIE 3

EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.

EEPM0 - EEPROM Programming Mode Bit 0

#define EEPM0 4

The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

EEPM1 - EEPROM Programming Mode Bit 1

#define EEPM1 5

WATCHDOG

WDTCSR - Watchdog Timer Control Register

sfrb WDTCSR = $21;

WDP0 - Watch Dog Timer Prescaler bit 0

#define WDP0 0

WDP1 - Watch Dog Timer Prescaler bit 1

#define WDP1 1

WDP2 - Watch Dog Timer Prescaler bit 2

#define WDP2 2

WDE - Watch Dog Enable

#define WDE 3

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog

WDCE - Watchdog Change Enable

#define WDCE 4

WDP3 - Watchdog Timer Prescaler Bit 3

#define WDP3 5

WDIE - Watchdog Timeout Interrupt Enable

#define WDIE 6

WDIF - Watchdog Timeout Interrupt Flag

#define WDIF 7

TIMER COUNTER 0

TIMSK0 - Timer/Counter Interrupt Mask Register

sfrb TIMSK0 = $39;

TOIE0 - Timer/Counter0 Overflow Interrupt Enable

#define TOIE0 0

OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable

#define OCIE0A 1

OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable

#define OCIE0B 2

TIFR0 - Timer/Counter0 Interrupt Flag Register

sfrb TIFR0 = $38;

TOV0 - Timer/Counter0 Overflow Flag

#define TOV0 0

OCF0A - Timer/Counter0 Output Compare Flag A

#define OCF0A 1

OCF0B - Timer/Counter0 Output Compare Flag B

#define OCF0B 2

TCCR0A - Timer/Counter Control Register A

sfrb TCCR0A = $30;

WGM00 - Waveform Generation Mode bit 0

#define WGM00 0

WGM01 - Waveform Generation Mode bit 1

#define WGM01 1

COM0B0 - Compare Match Output B Mode bit 0

#define COM0B0 4

COM0B1 - Compare Match Output B Mode bit 1

#define COM0B1 5

COM0A0 - Compare Match Output A Mode bit 0

#define COM0A0 6

COM0A1 - Compare Match Output A Mode bit 1

#define COM0A1 7

TCCR0B - Timer/Counter Control Register B

sfrb TCCR0B = $33;

CS00 - Clock Select bit 0

#define CS00 0

CS01 - Clock Select bit 1

#define CS01 1

CS02 - Clock Select bit 2

#define CS02 2

WGM02 - Waveform Generation Mode bit 2

#define WGM02 3

FOC0B - Force Output Compare B

#define FOC0B 6

FOC0A - Force Output Compare A

#define FOC0A 7

TCNT0 - Timer/Counter0

sfrb TCNT0 = $32;

TCNT0_0

#define TCNT0_0 0

TCNT0_1

#define TCNT0_1 1

TCNT0_2

#define TCNT0_2 2

TCNT0_3

#define TCNT0_3 3

TCNT0_4

#define TCNT0_4 4

TCNT0_5

#define TCNT0_5 5

TCNT0_6

#define TCNT0_6 6

TCNT0_7

#define TCNT0_7 7

OCR0A - Timer/Counter0 Output Compare Register A

sfrb OCR0A = $36;

OCR0_0

#define OCR0_0 0

OCR0_1

#define OCR0_1 1

OCR0_2

#define OCR0_2 2

OCR0_3

#define OCR0_3 3

OCR0_4

#define OCR0_4 4

OCR0_5

#define OCR0_5 5

OCR0_6

#define OCR0_6 6

OCR0_7

#define OCR0_7 7

OCR0B - Timer/Counter0 Output Compare Register B

sfrb OCR0B = $3C;

OCR0_0

#define OCR0_0 0

OCR0_1

#define OCR0_1 1

OCR0_2

#define OCR0_2 2

OCR0_3

#define OCR0_3 3

OCR0_4

#define OCR0_4 4

OCR0_5

#define OCR0_5 5

OCR0_6

#define OCR0_6 6

OCR0_7

#define OCR0_7 7

GTCCR - General Timer/Counter Control Register

sfrb GTCCR = $23;

PSR0 - Prescaler Reset Timer/Counter0

#define PSR0 0

When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.

TSM - Timer/Counter Synchronization Mode

#define TSM 7

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneousl

TIMER COUNTER 1

TIMSK1 - Timer/Counter1 Interrupt Mask Register

sfrb TIMSK1 = $0C;

TOIE1 - Timer/Counter1 Overflow Interrupt Enable

#define TOIE1 0

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE1A - Timer/Counter1 Output Compare A Match Interrupt Enable

#define OCIE1A 1

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE1B - Timer/Counter1 Output Compare B Match Interrupt Enable

#define OCIE1B 2

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

ICIE1 - Timer/Counter1 Input Capture Interrupt Enable

#define ICIE1 5

When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

TIFR1 - Timer/Counter Interrupt Flag register

sfrb TIFR1 = $0B;

TOV1 - Timer/Counter1 Overflow Flag

#define TOV1 0

The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.

OCF1A - Timer/Counter1 Output Compare A Match Flag

#define OCF1A 1

The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed.

OCF1B - Timer/Counter1 Output Compare B Match Flag

#define OCF1B 2

The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.

ICF1 - Timer/Counter1 Input Capture Flag

#define ICF1 5

The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.

TCCR1A - Timer/Counter1 Control Register A

sfrb TCCR1A = $2F;

WGM10 - Pulse Width Modulator Select Bit 0

#define WGM10 0

WGM11 - Pulse Width Modulator Select Bit 1

#define WGM11 1

COM1B0 - Comparet Ouput Mode 1B, bit 0

#define COM1B0 4

COM1B1 - Compare Output Mode 1B, bit 1

#define COM1B1 5

COM1A0 - Comparet Ouput Mode 1A, bit 0

#define COM1A0 6

The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in the databook.

COM1A1 - Compare Output Mode 1A, bit 1

#define COM1A1 7

TCCR1B - Timer/Counter1 Control Register B

sfrb TCCR1B = $2E;

CS10 - Clock Select bit 0

#define CS10 0

CS11 - Clock Select 1 bit 1

#define CS11 1

CS12 - Clock Select1 bit 2

#define CS12 2

WGM12 - Waveform Generation Mode Bit 2

#define WGM12 3

WGM13 - Waveform Generation Mode Bit 3

#define WGM13 4

ICES1 - Input Capture 1 Edge Select

#define ICES1 6

While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.

ICNC1 - Input Capture 1 Noise Canceler

#define ICNC1 7

When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.

TCCR1C - Timer/Counter1 Control Register C

sfrb TCCR1C = $22;

FOC1B - Force Output Compare for Channel B

#define FOC1B 6

The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero

FOC1A - Force Output Compare for Channel A

#define FOC1A 7

TCNT1H - Timer/Counter1 High Byte

sfrb TCNT1H = $2D;

TCNT1H0 - Timer/Counter1 High Byte bit 0

#define TCNT1H0 0

TCNT1H1 - Timer/Counter1 High Byte bit 1

#define TCNT1H1 1

TCNT1H2 - Timer/Counter1 High Byte bit 2

#define TCNT1H2 2

TCNT1H3 - Timer/Counter1 High Byte bit 3

#define TCNT1H3 3

TCNT1H4 - Timer/Counter1 High Byte bit 4

#define TCNT1H4 4

TCNT1H5 - Timer/Counter1 High Byte bit 5

#define TCNT1H5 5

TCNT1H6 - Timer/Counter1 High Byte bit 6

#define TCNT1H6 6

TCNT1H7 - Timer/Counter1 High Byte bit 7

#define TCNT1H7 7

TCNT1L - Timer/Counter1 Low Byte

sfrb TCNT1L = $2C;

TCNT1L0 - Timer/Counter1 Low Byte bit 0

#define TCNT1L0 0

TCNT1L1 - Timer/Counter1 Low Byte bit 1

#define TCNT1L1 1

TCNT1L2 - Timer/Counter1 Low Byte bit 2

#define TCNT1L2 2

TCNT1L3 - Timer/Counter1 Low Byte bit 3

#define TCNT1L3 3

TCNT1L4 - Timer/Counter1 Low Byte bit 4

#define TCNT1L4 4

TCNT1L5 - Timer/Counter1 Low Byte bit 5

#define TCNT1L5 5

TCNT1L6 - Timer/Counter1 Low Byte bit 6

#define TCNT1L6 6

TCNT1L7 - Timer/Counter1 Low Byte bit 7

#define TCNT1L7 7

OCR1AH - Timer/Counter1 Output Compare Register A High Byte

sfrb OCR1AH = $2B;

OCR1AH0 - Timer/Counter1 Output Compare Register High Byte bit 0

#define OCR1AH0 0

OCR1AH1 - Timer/Counter1 Output Compare Register High Byte bit 1

#define OCR1AH1 1

OCR1AH2 - Timer/Counter1 Output Compare Register High Byte bit 2

#define OCR1AH2 2

OCR1AH3 - Timer/Counter1 Output Compare Register High Byte bit 3

#define OCR1AH3 3

OCR1AH4 - Timer/Counter1 Output Compare Register High Byte bit 4

#define OCR1AH4 4

OCR1AH5 - Timer/Counter1 Output Compare Register High Byte bit 5

#define OCR1AH5 5

OCR1AH6 - Timer/Counter1 Output Compare Register High Byte bit 6

#define OCR1AH6 6

OCR1AH7 - Timer/Counter1 Output Compare Register High Byte bit 7

#define OCR1AH7 7

OCR1AL - Timer/Counter1 Output Compare Register A Low Byte

sfrb OCR1AL = $2A;

OCR1AL0 - Timer/Counter1 Output Compare Register Low Byte Bit 0

#define OCR1AL0 0

OCR1AL1 - Timer/Counter1 Output Compare Register Low Byte Bit 1

#define OCR1AL1 1

OCR1AL2 - Timer/Counter1 Output Compare Register Low Byte Bit 2

#define OCR1AL2 2

OCR1AL3 - Timer/Counter1 Output Compare Register Low Byte Bit 3

#define OCR1AL3 3

OCR1AL4 - Timer/Counter1 Output Compare Register Low Byte Bit 4

#define OCR1AL4 4

OCR1AL5 - Timer/Counter1 Output Compare Register Low Byte Bit 5

#define OCR1AL5 5

OCR1AL6 - Timer/Counter1 Output Compare Register Low Byte Bit 6

#define OCR1AL6 6

OCR1AL7 - Timer/Counter1 Output Compare Register Low Byte Bit 7

#define OCR1AL7 7

OCR1BH - Timer/Counter1 Output Compare Register B High Byte

sfrb OCR1BH = $29;

OCR1AH0 - Timer/Counter1 Output Compare Register High Byte bit 0

#define OCR1AH0 0

OCR1AH1 - Timer/Counter1 Output Compare Register High Byte bit 1

#define OCR1AH1 1

OCR1AH2 - Timer/Counter1 Output Compare Register High Byte bit 2

#define OCR1AH2 2

OCR1AH3 - Timer/Counter1 Output Compare Register High Byte bit 3

#define OCR1AH3 3

OCR1AH4 - Timer/Counter1 Output Compare Register High Byte bit 4

#define OCR1AH4 4

OCR1AH5 - Timer/Counter1 Output Compare Register High Byte bit 5

#define OCR1AH5 5

OCR1AH6 - Timer/Counter1 Output Compare Register High Byte bit 6

#define OCR1AH6 6

OCR1AH7 - Timer/Counter1 Output Compare Register High Byte bit 7

#define OCR1AH7 7

OCR1BL - Timer/Counter1 Output Compare Register B Low Byte

sfrb OCR1BL = $28;

OCR1AL0 - Timer/Counter1 Output Compare Register Low Byte Bit 0

#define OCR1AL0 0

OCR1AL1 - Timer/Counter1 Output Compare Register Low Byte Bit 1

#define OCR1AL1 1

OCR1AL2 - Timer/Counter1 Output Compare Register Low Byte Bit 2

#define OCR1AL2 2

OCR1AL3 - Timer/Counter1 Output Compare Register Low Byte Bit 3

#define OCR1AL3 3

OCR1AL4 - Timer/Counter1 Output Compare Register Low Byte Bit 4

#define OCR1AL4 4

OCR1AL5 - Timer/Counter1 Output Compare Register Low Byte Bit 5

#define OCR1AL5 5

OCR1AL6 - Timer/Counter1 Output Compare Register Low Byte Bit 6

#define OCR1AL6 6

OCR1AL7 - Timer/Counter1 Output Compare Register Low Byte Bit 7

#define OCR1AL7 7

ICR1H - Timer/Counter1 Input Capture Register High Byte

sfrb ICR1H = $25;

ICR1H0 - Timer/Counter1 Input Capture Register High Byte bit 0

#define ICR1H0 0

ICR1H1 - Timer/Counter1 Input Capture Register High Byte bit 1

#define ICR1H1 1

ICR1H2 - Timer/Counter1 Input Capture Register High Byte bit 2

#define ICR1H2 2

ICR1H3 - Timer/Counter1 Input Capture Register High Byte bit 3

#define ICR1H3 3

ICR1H4 - Timer/Counter1 Input Capture Register High Byte bit 4

#define ICR1H4 4

ICR1H5 - Timer/Counter1 Input Capture Register High Byte bit 5

#define ICR1H5 5

ICR1H6 - Timer/Counter1 Input Capture Register High Byte bit 6

#define ICR1H6 6

ICR1H7 - Timer/Counter1 Input Capture Register High Byte bit 7

#define ICR1H7 7

ICR1L - Timer/Counter1 Input Capture Register Low Byte

sfrb ICR1L = $24;

ICR1L0 - Timer/Counter1 Input Capture Register Low Byte bit 0

#define ICR1L0 0

ICR1L1 - Timer/Counter1 Input Capture Register Low Byte bit 1

#define ICR1L1 1

ICR1L2 - Timer/Counter1 Input Capture Register Low Byte bit 2

#define ICR1L2 2

ICR1L3 - Timer/Counter1 Input Capture Register Low Byte bit 3

#define ICR1L3 3

ICR1L4 - Timer/Counter1 Input Capture Register Low Byte bit 4

#define ICR1L4 4

ICR1L5 - Timer/Counter1 Input Capture Register Low Byte bit 5

#define ICR1L5 5

ICR1L6 - Timer/Counter1 Input Capture Register Low Byte bit 6

#define ICR1L6 6

ICR1L7 - Timer/Counter1 Input Capture Register Low Byte bit 7

#define ICR1L7 7

CPU

PRR - Power Reduction Register

sfrb PRR = $00;

PRADC - Power Reduction ADC

#define PRADC 0

PRUSI - Power Reduction USI

#define PRUSI 1

PRTIM0 - Power Reduction Timer/Counter0

#define PRTIM0 2

PRTIM1 - Power Reduction Timer/Counter1

#define PRTIM1 3

OSCCAL - Oscillator Calibration Value

sfrb OSCCAL = $31;

CAL0 - Oscillator Calibration Value Bit0

#define CAL0 0

CAL1 - Oscillator Calibration Value Bit1

#define CAL1 1

CAL2 - Oscillator Calibration Value Bit2

#define CAL2 2

CAL3 - Oscillator Calibration Value Bit3

#define CAL3 3

CAL4 - Oscillator Calibration Value Bit4

#define CAL4 4

CAL5 - Oscillator Calibration Value Bit5

#define CAL5 5

CAL6 - Oscillator Calibration Value Bit6

#define CAL6 6

CAL7 - Oscillator Calibration Value Bit7

#define CAL7 7

CLKPR - Clock Prescale Register

sfrb CLKPR = ;

CLKPS0 - Clock Prescaler Select Bit 0

#define CLKPS0 0

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.

CLKPS1 - Clock Prescaler Select Bit 1

#define CLKPS1 1

CLKPS2 - Clock Prescaler Select Bit 2

#define CLKPS2 2

CLKPS3 - Clock Prescaler Select Bit 3

#define CLKPS3 3

CLKPCE - Clock Prescaler Change Enable

#define CLKPCE 7

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.

SREG - Status Register

sfrb SREG = $3F;

SPH - Stack Pointer High

sfrb SPH = $3E;

SP8 - Stack pointer bit 8

#define SP8 0

SP9 - Stack pointer bit 9

#define SP9 1

SPL - Stack Pointer Low

sfrb SPL = $3D;

SP0 - Stack pointer bit 0

#define SP0 0

SP1 - Stack pointer bit 1

#define SP1 1

SP2 - Stack pointer bit 2

#define SP2 2

SP3 - Stack pointer bit 3

#define SP3 3

SP4

#define SP4 4

SP5 - Stack pointer bit 5

#define SP5 5

SP6 - Stack pointer bit 6

#define SP6 6

SP7 - Stack pointer bit 7

#define SP7 7

MCUCR - MCU Control Register

sfrb MCUCR = $35;

SM0 - Sleep Mode Select Bit 0

#define SM0 3

SM1 - Sleep Mode Select Bit 1

#define SM1 4

SE - Sleep Enable

#define SE 5

PUD

#define PUD 6

MCUSR - MCU Status Register

sfrb MCUSR = $34;

PORF - Power-on reset flag

#define PORF 0

This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.

EXTRF - External Reset Flag

#define EXTRF 1

This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

BORF - Brown-out Reset Flag

#define BORF 2

This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

WDRF - Watchdog Reset Flag

#define WDRF 3

This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

GPIOR2 - General Purpose I/O Register 2

sfrb GPIOR2 = $15;

GPIOR20

#define GPIOR20 0

GPIOR21

#define GPIOR21 1

GPIOR22

#define GPIOR22 2

GPIOR23

#define GPIOR23 3

GPIOR24

#define GPIOR24 4

GPIOR25

#define GPIOR25 5

GPIOR26

#define GPIOR26 6

GPIOR27

#define GPIOR27 7

GPIOR1 - General Purpose I/O Register 1

sfrb GPIOR1 = $14;

GPIOR10

#define GPIOR10 0

GPIOR11

#define GPIOR11 1

GPIOR12

#define GPIOR12 2

GPIOR13

#define GPIOR13 3

GPIOR14

#define GPIOR14 4

GPIOR15

#define GPIOR15 5

GPIOR16

#define GPIOR16 6

GPIOR17

#define GPIOR17 7

GPIOR0 - General Purpose I/O Register 0

sfrb GPIOR0 = $13;

GPIOR00

#define GPIOR00 0

GPIOR01

#define GPIOR01 1

GPIOR02

#define GPIOR02 2

GPIOR03

#define GPIOR03 3

GPIOR04

#define GPIOR04 4

GPIOR05

#define GPIOR05 5

GPIOR06

#define GPIOR06 6

GPIOR07

#define GPIOR07 7