This documentation was generated automatically from the AVR Studio part description file ATmega406.pdf.
12-bit resolution Sigmal-Delta ADC with +/-1 LSB Accuracy. 512 us conversion time.
sfrb VADMUX = 0x7C;
#define VADMUX0 0
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
#define VADMUX1 1
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
#define VADMUX2 2
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
#define VADMUX3 3
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
sfrb VADCH = 0x79;
#define VADCH0 0
#define VADCH1 1
#define VADCH2 2
#define VADCH3 3
sfrb VADCL = 0x78;
#define VADCL0 0
#define VADCL1 1
#define VADCL2 2
#define VADCL3 3
#define VADCL4 4
#define VADCL5 5
#define VADCL6 6
#define VADCL7 7
sfrb VADCSR = 0x7A;
#define VADCCIE 0
When this bit is written to one and the I-Bit in SREG is set, the V-ADC Conversion Complete Interrupt is activated
#define VADCCIF 1
This bit is set when a V-ADC conversion completes and the data registers are updated.V-ADC Conversion complete Interrupt is executed if the VADCCIE bit and the I-bit in S-REG are set. VADCCIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, VADCCIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on VADCSR, a pending interrupt can be disabled.
#define VADSC 2
Write this bit to one to start a new conversion of the selected channel. VADSC will read as one as long as the conversion is not finished. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect.
#define VADEN 3
Writing this bit to one enables V-ADC Conversion. By writing it to zero, the V-ADC is turned off. Turning the V-ADC off while a conversion is in progress will terminate this conversion
The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in ?Clock Systems and their Distribution? on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in ?Clock Systems and their Distribution? on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interru
sfrb EICRA = 0x69;
#define ISC00 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt.
#define ISC01 1
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt.
#define ISC10 2
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt.
#define ISC11 3
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt.
#define ISC20 4
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt.
#define ISC21 5
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt.
#define ISC30 6
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt.
#define ISC31 7
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt.
sfrb EIMSK = 0x1D;
#define INT0 0
When the INT0 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed.Activity on the pin will cause an interrupt request even if INT0 is configured as an output.The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 interrupt vector.
#define INT1 1
When the INT1 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector.
#define INT2 2
When the INT2 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector.
#define INT3 3
When the INT3 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector.
sfrb EIFR = 0x1C;
#define INTF0 0
When an edge or logic change on the INT0 pin triggers an interrupt request,INTF0 becomes set (one).If the I-bit in SREG and the INT0 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt.
#define INTF1 1
When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt.
#define INTF2 2
When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt.
#define INTF3 3
When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt.
sfrb PCICR = 0x68;
#define PCIE0 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.
#define PCIE1 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register.
sfrb PCIFR = 0x1B;
#define PCIF0 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
#define PCIF1 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
sfrb PCMSK1 = 0x6C;
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCINT15 7
sfrb PCMSK0 = 0x6B;
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
sfrb TCCR1B = 0x81;
#define CS10 0
#define CS11 1
#define CS12 2
#define CTC1 3
sfrb TCNT1H = 0x85;
#define TCNT1H0 0
#define TCNT1H1 1
#define TCNT1H2 2
#define TCNT1H3 3
#define TCNT1H4 4
#define TCNT1H5 5
#define TCNT1H6 6
#define TCNT1H7 7
sfrb TCNT1L = 0x84;
#define TCNT1L0 0
#define TCNT1L1 1
#define TCNT1L2 2
#define TCNT1L3 3
#define TCNT1L4 4
#define TCNT1L5 5
#define TCNT1L6 6
#define TCNT1L7 7
sfrb OCR1AL = 0x88;
#define OCR1AL0 0
#define OCR1AL1 1
#define OCR1AL2 2
#define OCR1AL3 3
#define OCR1AL4 4
#define OCR1AL5 5
#define OCR1AL6 6
#define OCR1AL7 7
sfrb OCR1AH = 0x89;
#define OCR1AH0 0
#define OCR1AH1 1
#define OCR1AH2 2
#define OCR1AH3 3
#define OCR1AH4 4
#define OCR1AH5 5
#define OCR1AH6 6
#define OCR1AH7 7
sfrb TIMSK1 = 0x6F;
#define TOIE1 0
#define OCIE1A 1
sfrb TIFR1 = 0x16;
#define TOV1 0
#define OCF1A 1
sfrb GTCCR = 0x23;
#define PSRSYNC 0
#define PSRASY 1
#define TSM 7
sfrb WUTCSR = 0x62;
#define WUTP0 0
The WUTP2, WUTP1 and WUTP0 bits determine the Wake-up Timer prescaling when the Wake-up Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in the datasheet.
#define WUTP1 1
The WUTP2, WUTP1 and WUTP0 bits determine the Wake-up Timer prescaling when the Wake-up Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in the datasheet.
#define WUTP2 2
The WUTP2, WUTP1 and WUTP0 bits determine the Wake-up Timer prescaling when the Wake-up Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in the datasheet.
#define WUTE 3
When the WUTE is set (one) the Wake-up Timer is enabled, and the WUTE is cleared (zero) the Wake-up Timer function is disabled.
#define WUTR 4
When WUTR is written to one, the Wake-up Timer is reset, and starts counting from zero. The WUTR bit is automatically cleared to zero after the reset has been performed.
#define WUTCF 5
The WUTCF bit is set after every 256 Slow RC OScillator clocks (2 ms @ 131 kHz)
#define WUTIE 6
When the WUTIE bit and the I-bit in the Status Register are set (one), the Wake-up Timer interrupt is enabled. The corresponding interrupt is executed if a Wake-up Timer overflow occurs, i.e., when the WUTIF bit is set .
#define WUTIF 7
The bit WUTIF is set (one) when an overflow occurs in the Wake-up Timer. WUTIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, WUTIE (Wake-up Timer Interrupt Enable), and WUTIF are set (one), the Wake-up Timer interrupt is executed.
sfrb BPPLR = 0xF8;
#define BPPL 0
#define BPPLE 1
sfrb BPCR = 0xF7;
#define CCD 0
#define DCD 1
#define SCD 2
#define DUVD 3
sfrb CBPTR = 0xF6;
#define OCPT0 0
#define OCPT1 1
#define OCPT2 2
#define OCPT3 3
#define SCPT0 4
#define SCPT1 5
#define SCPT2 6
#define SCPT3 7
sfrb BPOCD = 0xF5;
#define CCDL0 0
#define CCDL1 1
#define CCDL2 2
#define CCDL3 3
#define DCDL0 4
#define DCDL1 5
#define DCDL2 6
#define DCDL3 7
sfrb BPSCD = 0xF4;
#define SCDL0 0
#define SCDL1 1
#define SCDL2 2
#define SCDL3 3
sfrb BPDUV = 0xF3;
#define DUDL0 0
#define DUDL1 1
#define DUDL2 2
#define DUDL3 3
#define DUVT0 4
#define DUVT1 5
sfrb BPIR = 0xF2;
#define SCIE 0
#define DOCIE 1
#define COCIE 2
#define DUVIE 3
#define SCIF 4
#define DOCIF 5
#define COCIF 6
#define DUVIF 7
sfrb FCSR = 0xF0;
#define PFD 0
The PFD bit provides complete control of the Precharge FET. When the PFD bit is cleared (zero), the Precharge FET will be enabled. When the PFD bit is set (one), the Precharge FET will be disabled. This bit will be set when CURRENT_PROTECTION is set (one).
#define CFE 1
When the CFE bit is cleared (zero), the Charge FET will be disabled regardless of the state of the Battery Protection circuitry. When this bit is set (one), the Charge FET state is determined by the Battery Protection circuitry. This bit will be cleared when CURRENT_PROTECTION is set (one).
#define DFE 2
When the DFE bit is cleared (zero), the Discharge FET will be disabled regardless of the state of the Battery Protection circuitry. When this bit is set (one), the Discharge FET state is determined by the Battery Protection circuitry. This bit will be cleared when CURRENT_PROTECTION is set (one).
#define CPS 3
The CPTS bit shows the status of the Current Protection. This bit is set (one) when the Current Protection Timer is activated, and is cleared (zero) when the hold-off time has elapsed.
#define PWMOPC 4
When the PWMOPC is cleared (zero), the PFD bit and the battery protection circuitry controls the OPC output. When this bit is set (one), the OC output will be controlled by the PWM output from the 8-bit Timer/Counter0 and the battery protection circuitry.
#define PWMOC 5
When the PWMOC is cleared (zero), the CFE bit and the battery protection circuitry controls the OC output. When this bit is set (one), the OC output will be controlled by the PWM output from the 8-bit Timer/Counter0 and the battery protection circuitry.
sfrb CADCSRA = 0xE4;
#define CADSE 0
#define CADSI0 1
#define CADSI1 2
#define CADAS0 3
The CADAS bits select the conversion time for the Accumulate Current output. Please refer to table 45 in the manual.
#define CADAS1 4
The CADAS bits select the conversion time for the Accumulate Current output. Please refer to table 45 in the manual.
#define CADUB 5
#define CADEN 7
sfrb CADCSRB = 0xE5;
#define CADICIF 0
The CADICIF bit is set (one) when a CC-ADC Instantaneous Current conversion is completed. The CC-ADC Instantaneous Current Interrupt is executed if the CADICIE bit and the I-bit in SREG are set (one). CADICIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADICIF is cleared by writing a logic one to the flag.
#define CADRCIF 1
The CADACIF bit is set (one) after the Accumulate Current conversion has completed. The CC-ADC Accumulate Current Interrupt is executed if the CADAIE bit and the I-bit in SREG are set (one). CADACIF is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, CADACIF is cleared by writing a logic one to the flag. he CADRCIF bit is set (one) when the absolute value of the result of the last CC-ADC conversion is greater than, or equal to, the compare values set by the CC-ADC Regular Charge/Discharge Current Level Registers. A positive value is compared to the Regular Charge Current Level, and a negative value is compared to the Regular Discharge Current Level. The CC-ADC Regular Current Interrupt is executed if the CADRCIE bit and the I-bit in SREG are set (one). CADRCIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADRCIF is cleared by writing a logic one to the flag.
#define CADACIF 2
The CADACIF bit is set (one) after the Accumulate Current conversion has completed. The CC-ADC Accumulate Current Interrupt is executed if the CADAIE bit and the I-bit in SREG are set (one). CADACIF is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, CADACIF is cleared by writing a logic one to the flag. he CADRCIF bit is set (one) when the absolute value of the result of the last CC-ADC conversion is greater than, or equal to, the compare values set by the CC-ADC Regular Charge/Discharge Current Level Registers. A positive value is compared to the Regular Charge Current Level, and a negative value is compared to the Regular Discharge Current Level. The CC-ADC Regular Current Interrupt is executed if the CADRCIE bit and the I-bit in SREG are set (one). CADRCIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADRCIF is cleared by writing a logic one to the flag.
#define CADICIE 4
The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43.
#define CADRCIE 5
When the CADACIE bit is set (one), and the I-bit in the Status Register is set (one), the CC-ADC Accumulate Current Interrupt is enabled.
#define CADACIE 6
CC-ADC Accumulate Current Interrupt Enable
sfrb CADICH = 0xE9;
#define CADICH0 0
#define CADICH1 1
#define CADICH2 2
#define CADICH3 3
#define CADICH4 4
#define CADICH5 5
#define CADICH6 6
#define CADICH7 7
sfrb CADICL = 0xE8;
#define CADICL0 0
#define CADICL1 1
#define CADICL2 2
#define CADICL3 3
#define CADICL4 4
#define CADICL5 5
#define CADICL6 6
#define CADICL7 7
sfrb CADAC3 = 0xE3;
#define CADAC24 0
#define CADAC25 1
#define CADAC26 2
#define CADAC27 3
#define CADAC28 4
#define CADAC29 5
#define CADAC30 6
#define CADAC31 7
sfrb CADAC2 = 0xE2;
#define CADAC16 0
#define CADAC17 1
#define CADAC18 2
#define CADAC19 3
#define CADAC20 4
#define CADAC21 5
#define CADAC22 6
#define CADAC23 7
sfrb CADAC1 = 0xE1;
#define CADAC08 0
#define CADAC09 1
#define CADAC10 2
#define CADAC11 3
#define CADAC12 4
#define CADAC13 5
#define CADAC14 6
#define CADAC15 7
sfrb CADAC0 = 0xE0;
#define CADAC00 0
#define CADAC01 1
#define CADAC02 2
#define CADAC03 3
#define CADAC04 4
#define CADAC05 5
#define CADAC06 6
#define CADAC07 7
sfrb CADRCC = 0xE6;
#define CADRCC0 0
#define CADRCC1 1
#define CADRCC2 2
#define CADRCC3 3
#define CADRCC4 4
#define CADRCC5 5
#define CADRCC6 6
#define CADRCC7 7
sfrb CADRDC = 0xE7;
#define CADRDC0 0
#define CADRDC1 1
#define CADRDC2 2
#define CADRDC3 3
#define CADRDC4 4
#define CADRDC5 5
#define CADRDC6 6
#define CADRDC7 7
sfrb CBCR = 0xF1;
#define CBE1 0
#define CBE2 1
#define CBE3 2
#define CBE4 3
sfrb SREG = 0x3F;
sfrb SPH = 0x3E;
#define SP8 0
#define SP9 1
#define SP10 2
#define SP11 3
#define SP12 4
#define SP13 5
#define SP14 6
#define SP15 7
sfrb SPL = 0x3D;
#define SP0 0
#define SP1 1
#define SP2 2
#define SP3 3
#define SP4 4
#define SP5 5
#define SP6 6
#define SP7 7
sfrb MCUCR = 0x35;
#define IVCE 0
The IVCE bit must be written to logic one to enable change of the IVSEL bit.IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.Setting the IVCE bit will disable interrupts.
#define IVSEL 1
When the IVSEL bit is cleared (zero),the interrupt vectors are placed at the start of the Flash memory.When this bit is set (one),the interrupt vectors are moved to the beginning of the Boot Loader section of the flash.The actual address of the start of the boot flash section is determined by the BOOTSZ fuses.
#define PUD 4
When this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn,PORTxn}=0b01).
#define JTD 7
sfrb MCUSR = 0x34;
#define PORF 0
This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.
#define EXTRF 1
This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
#define BODRF 2
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by
#define WDRF 3
This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
#define JTRF 4
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on reset, or by writing a logic zero to the flag. ? Bit 3 - WDRF: Watchdog Reset Flag
sfrb FOSCCAL = 0x66;
#define FCAL0 0
#define FCAL1 1
#define FCAL2 2
#define FCAL3 3
#define FCAL4 4
#define FCAL5 5
#define FCAL6 6
#define FCAL7 7
sfrb SMCR = 0x33;
#define SE 0
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.To
#define SM0 1
These bits select between the five available sleep modes.
#define SM1 2
These bits select between the five available sleep modes.
#define SM2 3
These bits select between the five available sleep modes.
sfrb GPIOR2 = 0x2B;
#define GPIOR20 0
#define GPIOR21 1
#define GPIOR22 2
#define GPIOR23 3
#define GPIOR24 4
#define GPIOR25 5
#define GPIOR26 6
#define GPIOR27 7
sfrb GPIOR1 = 0x2A;
#define GPIOR10 0
#define GPIOR11 1
#define GPIOR12 2
#define GPIOR13 3
#define GPIOR14 4
#define GPIOR15 5
#define GPIOR16 6
#define GPIOR17 7
sfrb GPIOR0 = 0x1E;
#define GPIOR00 0
#define GPIOR01 1
#define GPIOR02 2
#define GPIOR03 3
#define GPIOR04 4
#define GPIOR05 5
#define GPIOR06 6
#define GPIOR07 7
sfrb CCSR = 0xC0;
#define ACS 0
The ACS bit is used to selected the source of the asynchronous clock for the Coulomb Counter ADC and Wake-up Timer. The Slow RC Oscillator is selected when this bit is cleared (zero). The 32 kHz Crystal Oscillator is selected when this bit is set (one).
#define XOE 1
The XOE bit is used to enable the 32 kHz Crystal Oscillator before it is selected as clock source. This allows the Oscillator clock to stabilize prior to use. The 32 kHz Crystal Oscillator requires approximately two seconds to stabilize, this must be timed by the user software. This bit must remain set as long as the ACS bit is set, otherwise the 32 kHz clock to CC-ADC and Wake-up timer will be stopped.
sfrb DIDR0 = 0x7E;
#define VADC0D 0
#define VADC1D 1
#define VADC2D 2
#define VADC3D 3
sfrb PRR0 = 0x64;
#define PRVADC 0
Writing a logic one to this bit shuts down the V-ADC. The V-ADC must be disabled before shut down.
#define PRTIM0 1
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown.
#define PRTIM1 2
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the, Timer/Counter1 is enabled, operation will continue like before the shutdown.
#define PRTWI 3
Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation.
sfrb WDTCSR = 0x60;
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDE 3
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog
#define WDCE 4
#define WDP3 5
#define WDIE 6
#define WDIF 7
The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in ?Timer/Counter0 Control Register - TCCR0? on page 35. The overflow status flag is found in ?The Timer/Counter Interrupt Flag Register - TIFR? on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in ?The Timer/Counter Interrupt Mask Regis-ter - TIMSK? on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions
sfrb TCCR0A = 0x24;
#define WGM00 0
#define WGM01 1
#define COM0B0 4
#define COM0B1 5
#define COM0A0 6
#define COM0A1 7
sfrb TCCR0B = 0x25;
#define CS00 0
#define CS01 1
#define CS02 2
#define WGM02 3
#define FOC0B 6
#define FOC0A 7
sfrb TCNT0 = 0x26;
#define TCNT00 0
#define TCNT01 1
#define TCNT02 2
#define TCNT03 3
#define TCNT04 4
#define TCNT05 5
#define TCNT06 6
#define TCNT07 7
sfrb OCR0A = 0x27;
#define OCR0A0 0
#define OCR0A1 1
#define OCR0A2 2
#define OCR0A3 3
#define OCR0A4 4
#define OCR0A5 5
#define OCR0A6 6
#define OCR0A7 7
sfrb OCR0B = 0x28;
#define OCR0B0 0
#define OCR0B1 1
#define OCR0B2 2
#define OCR0B3 3
#define OCR0B4 4
#define OCR0B5 5
#define OCR0B6 6
#define OCR0B7 7
sfrb TIMSK0 = 0x6E;
#define TOIE0 0
#define OCIE0A 1
#define OCIE0B 2
sfrb TIFR0 = 0x15;
#define TOV0 0
#define OCF0A 1
#define OCF0B 2
sfrb PORTA = 0x02;
#define PORTA0 0
#define PORTA1 1
#define PORTA2 2
#define PORTA3 3
#define PORTA4 4
#define PORTA5 5
#define PORTA6 6
#define PORTA7 7
sfrb DDRA = 0x01;
#define DDA0 0
#define DDA1 1
#define DDA2 2
#define DDA3 3
#define DDA4 4
#define DDA5 5
#define DDA6 6
#define DDA7 7
sfrb PINA = 0x00;
#define PINA0 0
#define PINA1 1
#define PINA2 2
#define PINA3 3
#define PINA4 4
#define PINA5 5
#define PINA6 6
#define PINA7 7
sfrb PORTB = 0x05;
#define PORTB0 0
#define PORTB1 1
#define PORTB2 2
#define PORTB3 3
#define PORTB4 4
#define PORTB5 5
#define PORTB6 6
#define PORTB7 7
sfrb DDRB = 0x04;
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3
#define DDB4 4
#define DDB5 5
#define DDB6 6
#define DDB7 7
sfrb PINB = 0x03;
#define PINB0 0
#define PINB1 1
#define PINB2 2
#define PINB3 3
#define PINB4 4
#define PINB5 5
#define PINB6 6
#define PINB7 7
sfrb PORTC = 0x08;
#define PORTC0 0
sfrb PORTD = 0x0B;
#define PORTD0 0
#define PORTD1 1
sfrb DDRD = 0x0A;
#define DDD0 0
#define DDD1 1
sfrb PIND = 0x09;
#define PIND0 0
#define PIND1 1
The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppor
sfrb SPMCSR = 0x37;
#define SPMEN 0
This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than ?10001?, "01001", "00101", "00011" or "00001" in the lower five bits will have no effec
#define PGERS 1
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.
#define PGWRT 2
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.
#define BLBSET 3
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See ?Reading the Fuse and Lock Bits from Software? on page 235 for details
#define RWWSRE 4
When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lo
#define SIGRD 5
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read a byte from the signature row into the destination register. see ?Reading the Signature Row from Software? in the datasheet for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. This operation is reserved for future use and should not be used.
#define RWWSB 6
When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated.
#define SPMIE 7
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared.
TWI: Simple yet powerful and flexible communications interface, only two bus lines needed. Both master and slave operation supported. Device can operate as transmitter or receiver. 7-bit address space allows up to 128 different slave addresses. Multi-master arbitration support Up to 400 kHz data transfer speed Slew-rate limited output drivers Noise suppression circuitry rejects spikes on bus lines Fully programmable slave address with general call support Address recognition causes wake-up when AVR is in sleep mode The Two-Wire Serial Interface (TWI) is ideally suited to typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bidirectional bus lines, one for clock (SCL) andone for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI
sfrb TWBCSR = 0xBE;
#define TWBCIP 0
#define TWBDT0 1
#define TWBDT1 2
#define TWBCIE 6
#define TWBCIF 7
sfrb TWAMR = 0xBD;
#define TWAM0 1
#define TWAM1 2
#define TWAM2 3
#define TWAM3 4
#define TWAM4 5
#define TWAM5 6
#define TWAM6 7
sfrb TWBR = 0xB8;
#define TWBR0 0
#define TWBR1 1
#define TWBR2 2
#define TWBR3 3
#define TWBR4 4
#define TWBR5 5
#define TWBR6 6
#define TWBR7 7
sfrb TWCR = 0xBC;
#define TWIE 0
When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT flag is high.
#define TWEN 2
The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation.
#define TWWC 3
The TWWC bit is set when attempting to write to the TWI Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR register when TWINT is high.
#define TWSTO 4
Writing the TWSTO bit to one in master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high impedance state.
#define TWSTA 5
The application writes the TWSTA bit to one when it desires to become a master on the 2-wire Serial Bus. The TWI hard-ware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master sta-tus. TWSTA is cleared by the TWI hardware when the START condition has been transmitted.
#define TWEA 6
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is gener-ated on the TWI bus if the following conditions are met: 1. The device?s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in master receiver or slave receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again
#define TWINT 7
This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag
sfrb TWSR = 0xB9;
#define TWPS0 0
Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See ?Bit Rate Generator Unit? on page 165 for calculating bit rates.
#define TWPS1 1
Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See ?Bit Rate Generator Unit? on page 165 for calculating bit rates.
#define TWS3 3
Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co
#define TWS4 4
Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co
#define TWS5 5
Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c
#define TWS6 6
Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co
#define TWS7 7
Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c
sfrb TWDR = 0xBB;
#define TWD0 0
#define TWD1 1
#define TWD2 2
#define TWD3 3
#define TWD4 4
#define TWD5 5
#define TWD6 6
#define TWD7 7
sfrb TWAR = 0xBA;
#define TWGCE 0
#define TWA0 1
#define TWA1 2
#define TWA2 3
#define TWA3 4
#define TWA4 5
#define TWA5 6
#define TWA6 7
sfrb BGCRR = 0xD1;
#define BGCR0 0
#define BGCR1 1
#define BGCR2 2
#define BGCR3 3
#define BGCR4 4
#define BGCR5 5
#define BGCR6 6
#define BGCR7 7
sfrb BGCCR = 0xD0;
#define BGCC0 0
These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.
#define BGCC1 1
These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.
#define BGCC2 2
These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.
#define BGCC3 3
These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.
#define BGCC4 4
These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.
#define BGCC5 5
#define BGEN 7
EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See ?Preventing EEPROM Corruption? on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execute
sfrb EEARH = 0x22;
#define EEAR8 0
sfrb EEARL = 0x21;
#define EEAR0 0
#define EEAR1 1
#define EEAR2 2
#define EEAR3 3
#define EEAR4 4
#define EEAR5 5
#define EEAR6 6
#define EEAR7 7
sfrb EEDR = 0x20;
#define EEDR0 0
#define EEDR1 1
#define EEDR2 2
#define EEDR3 3
#define EEDR4 4
#define EEDR5 5
#define EEDR6 6
#define EEDR7 7
sfrb EECR = 0x1F;
#define EERE 0
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU
#define EEWE 1
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See ?Boot Loader Support - Read While Write self-programming? on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed
#define EEMWE 2
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.
#define EERIE 3
EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.
#define EEPM0 4
The EEPROM Programming mode bit setting defines which programming action that will
#define EEPM1 5
The EEPROM Programming mode bit setting defines which programming action that will