<ATmega2561.h>

This documentation was generated automatically from the AVR Studio part description file ATmega2561.pdf.

ANALOG COMPARATOR

ADCSRB - ADC Control and Status Register B

sfrb ADCSRB = $7B;

ACME - Analog Comparator Multiplexer Enable

#define ACME 6

When this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see ?Analog Comparator Multiplexed Input? on page 186.

ACSR - Analog Comparator Control And Status Register

sfrb ACSR = $30;

ACIS0 - Analog Comparator Interrupt Mode Select bit 0

#define ACIS0 0

These bits determine which comparator events that trigger the Analog Comparator interrupt.

ACIS1 - Analog Comparator Interrupt Mode Select bit 1

#define ACIS1 1

These bits determine which comparator events that trigger the Analog Comparator interrupt.

ACIC - Analog Comparator Input Capture Enable

#define ACIC 2

When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the analog comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set

ACIE - Analog Comparator Interrupt Enable

#define ACIE 3

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.

ACI - Analog Comparator Interrupt Flag

#define ACI 4

This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

ACO - Analog Compare Output

#define ACO 5

The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.

ACBG - Analog Comparator Bandgap Select

#define ACBG 6

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See ?Internal Voltage Reference? on page 42.

ACD - Analog Comparator Disable

#define ACD 7

When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

DIDR1 - Digital Input Disable Register 1

sfrb DIDR1 = $7F;

AIN0D - AIN0 Digital Input Disable

#define AIN0D 0

When this bit is written logic one,the digital input buffer on the AIN1/0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.

AIN1D - AIN1 Digital Input Disable

#define AIN1D 1

USART0

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: ? Full Duplex Operation (Independent Serial Receive and Transmit Registers) ? Asynchronous or Synchronous Operation ? Master or Slave Clocked Synchronous Operation ? High Resolution Baud Rate Generator ? Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits ? Odd or Even Parity Generation and Parity Check Supported by Hardware ? Data OverRun Detection ? Framing Error Detection ? Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter ? Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete ? Multi-processor Communication Mode ? Double Speed Asynchronous Communica

UDR0 - USART I/O Data Register

sfrb UDR0 = $C6;

UDR0-0 - USART I/O Data Register bit 0

#define UDR0-0 0

UDR0-1 - USART I/O Data Register bit 1

#define UDR0-1 1

UDR0-2 - USART I/O Data Register bit 2

#define UDR0-2 2

UDR0-3 - USART I/O Data Register bit 3

#define UDR0-3 3

UDR0-4 - USART I/O Data Register bit 4

#define UDR0-4 4

UDR0-5 - USART I/O Data Register bit 5

#define UDR0-5 5

UDR0-6 - USART I/O Data Register bit 6

#define UDR0-6 6

UDR0-7 - USART I/O Data Register bit 7

#define UDR0-7 7

UCSR0A - USART Control and Status Register A

sfrb UCSR0A = $C0;

MPCM0 - Multi-processor Communication Mode

#define MPCM0 0

This bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see ?Multi-processor Communication Mode? on page 152.

U2X0 - Double the USART transmission speed

#define U2X0 1

This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.

UPE0 - Parity Error

#define UPE0 2

This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A.

DOR0 - Data overRun

#define DOR0 3

This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0.

FE0 - Framing Error

#define FE0 4

This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.

UDRE0 - USART Data Register Empty

#define UDRE0 5

This bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is re

TXC0 - USART Transmitt Complete

#define TXC0 6

This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the b

RXC0 - USART Receive Complete

#define RXC0 7

This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.

UCSR0B - USART Control and Status Register B

sfrb UCSR0B = $C1;

TXB80 - Transmit Data Bit 8

#define TXB80 0

TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.

RXB80 - Receive Data Bit 8

#define RXB80 1

RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.

UCSZ02 - Character Size

#define UCSZ02 2

The UCSZ2 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use.

TXEN0 - Transmitter Enable

#define TXEN0 3

Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.

RXEN0 - Receiver Enable

#define RXEN0 4

Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.

UDRIE0 - USART Data register Empty Interrupt Enable

#define UDRIE0 5

Writing this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.

TXCIE0 - TX Complete Interrupt Enable

#define TXCIE0 6

Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.

RXCIE0 - RX Complete Interrupt Enable

#define RXCIE0 7

Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.

UCSR0C - USART Control and Status Register C

sfrb UCSR0C = $C2;

UCPOL0 - Clock Polarity

#define UCPOL0 0

This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).

UCSZ00 - Character Size

#define UCSZ00 1

Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.

UCSZ01 - Character Size

#define UCSZ01 2

Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.

USBS0 - Stop Bit Select

#define USBS0 3

0: 1-bit. 1: 2-bit.

UPM00 - Parity Mode Bit 0

#define UPM00 4

This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.

UPM01 - Parity Mode Bit 1

#define UPM01 5

UMSEL00 - USART Mode Select

#define UMSEL00 6

UMSEL01 - USART Mode Select

#define UMSEL01 7

UBRR0H - USART Baud Rate Register High Byte

sfrb UBRR0H = $C5;

UBRR8 - USART Baud Rate Register bit 8

#define UBRR8 0

UBRR9 - USART Baud Rate Register bit 9

#define UBRR9 1

UBRR10 - USART Baud Rate Register bit 10

#define UBRR10 2

UBRR11 - USART Baud Rate Register bit 11

#define UBRR11 3

UBRR0L - USART Baud Rate Register Low Byte

sfrb UBRR0L = $C4;

UBRR0 - USART Baud Rate Register bit 0

#define UBRR0 0

UBRR1 - USART Baud Rate Register bit 1

#define UBRR1 1

UBRR2 - USART Baud Rate Register bit 2

#define UBRR2 2

UBRR3 - USART Baud Rate Register bit 3

#define UBRR3 3

UBRR4 - USART Baud Rate Register bit 4

#define UBRR4 4

UBRR5 - USART Baud Rate Register bit 5

#define UBRR5 5

UBRR6 - USART Baud Rate Register bit 6

#define UBRR6 6

UBRR7 - USART Baud Rate Register bit 7

#define UBRR7 7

TWI

TWI: Simple yet powerful and flexible communications interface, only two bus lines needed. Both master and slave operation supported. Device can operate as transmitter or receiver. 7-bit address space allows up to 128 different slave addresses. Multi-master arbitration support Up to 400 kHz data transfer speed Slew-rate limited output drivers Noise suppression circuitry rejects spikes on bus lines Fully programmable slave address with general call support Address recognition causes wake-up when AVR is in sleep mode The Two-Wire Serial Interface (TWI) is ideally suited to typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bidirectional bus lines, one for clock (SCL) andone for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI pr

TWAMR - TWI (Slave) Address Mask Register

sfrb TWAMR = $BD;

TWAM0

#define TWAM0 1

TWAM1

#define TWAM1 2

TWAM2

#define TWAM2 3

TWAM3

#define TWAM3 4

TWAM4

#define TWAM4 5

TWAM5

#define TWAM5 6

TWAM6

#define TWAM6 7

TWBR - TWI Bit Rate register

sfrb TWBR = $B8;

TWBR0

#define TWBR0 0

TWBR1

#define TWBR1 1

TWBR2

#define TWBR2 2

TWBR3

#define TWBR3 3

TWBR4

#define TWBR4 4

TWBR5

#define TWBR5 5

TWBR6

#define TWBR6 6

TWBR7

#define TWBR7 7

TWCR - TWI Control Register

sfrb TWCR = $BC;

TWIE - TWI Interrupt Enable

#define TWIE 0

When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT flag is high.

TWEN - TWI Enable Bit

#define TWEN 2

The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation.

TWWC - TWI Write Collition Flag

#define TWWC 3

The TWWC bit is set when attempting to write to the TWI Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR register when TWINT is high.

TWSTO - TWI Stop Condition Bit

#define TWSTO 4

Writing the TWSTO bit to one in master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high impedance state.

TWSTA - TWI Start Condition Bit

#define TWSTA 5

The application writes the TWSTA bit to one when it desires to become a master on the 2-wire Serial Bus. The TWI hard-ware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master sta-tus. TWSTA is cleared by the TWI hardware when the START condition has been transmitted.

TWEA - TWI Enable Acknowledge Bit

#define TWEA 6

The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is gener-ated on the TWI bus if the following conditions are met: 1. The device?s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in master receiver or slave receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again

TWINT - TWI Interrupt Flag

#define TWINT 7

This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag

TWSR - TWI Status Register

sfrb TWSR = $B9;

TWPS0 - TWI Prescaler

#define TWPS0 0

Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See ?Bit Rate Generator Unit? on page 165 for calculating bit rates.

TWPS1 - TWI Prescaler

#define TWPS1 1

Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See ?Bit Rate Generator Unit? on page 165 for calculating bit rates.

TWS3 - TWI Status

#define TWS3 3

Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co

TWS4 - TWI Status

#define TWS4 4

TWS5 - TWI Status

#define TWS5 5

TWS6 - TWI Status

#define TWS6 6

TWS7 - TWI Status

#define TWS7 7

TWDR - TWI Data register

sfrb TWDR = $BB;

TWD0 - TWI Data Register Bit 0

#define TWD0 0

TWD1 - TWI Data Register Bit 1

#define TWD1 1

TWD2 - TWI Data Register Bit 2

#define TWD2 2

TWD3 - TWI Data Register Bit 3

#define TWD3 3

TWD4 - TWI Data Register Bit 4

#define TWD4 4

TWD5 - TWI Data Register Bit 5

#define TWD5 5

TWD6 - TWI Data Register Bit 6

#define TWD6 6

TWD7 - TWI Data Register Bit 7

#define TWD7 7

TWAR - TWI (Slave) Address register

sfrb TWAR = $BA;

TWGCE - TWI General Call Recognition Enable Bit

#define TWGCE 0

TWA0 - TWI (Slave) Address register Bit 0

#define TWA0 1

TWA1 - TWI (Slave) Address register Bit 1

#define TWA1 2

TWA2 - TWI (Slave) Address register Bit 2

#define TWA2 3

TWA3 - TWI (Slave) Address register Bit 3

#define TWA3 4

TWA4 - TWI (Slave) Address register Bit 4

#define TWA4 5

TWA5 - TWI (Slave) Address register Bit 5

#define TWA5 6

TWA6 - TWI (Slave) Address register Bit 6

#define TWA6 7

SPI

The Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: ? Full-duplex, 3-wire Synchronous Data Transfer ? Master or Slave Operation ? LSB First or MSB First Data Transfer ? Four Programmable Bit Rates ? End of Transmission Interrupt Flag ? Write Collision Flag Protection ? Wakeup from Idle Mode (Slave Mode Only)

SPCR - SPI Control Register

sfrb SPCR = $2C;

SPR0 - SPI Clock Rate Select 0

#define SPR0 0

These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.

SPR1 - SPI Clock Rate Select 1

#define SPR1 1

These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.

CPHA - Clock Phase

#define CPHA 2

Refer to Figure 36 or Figure 37 for the functionality of this bit.

CPOL - Clock polarity

#define CPOL 3

When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.

MSTR - Master/Slave Select

#define MSTR 4

This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.

DORD - Data Order

#define DORD 5

When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.

SPE - SPI Enable

#define SPE 6

When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.

SPIE - SPI Interrupt Enable

#define SPIE 7

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.

SPSR - SPI Status Register

sfrb SPSR = $2D;

SPI2X - Double SPI Speed Bit

#define SPI2X 0

When this bit is written logic one the SPI speed (SCK Frequency)will be doubled when the SPI is in master mode .This means that the minimum SCK period will be 2 CPU clock periods.When the SPI is configured as Slave,the SPI is only guaranteed to work at f osc /4orlower. The SPI interface on the ATmega162 is also used for program memory and EEPROM downloading or uploading.

WCOL - Write Collision Flag

#define WCOL 6

The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.

SPIF - SPI Interrupt Flag

#define SPIF 7

When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).

SPDR - SPI Data Register

sfrb SPDR = $2E;

SPDR0 - SPI Data Register bit 0

#define SPDR0 0

SPDR1 - SPI Data Register bit 1

#define SPDR1 1

SPDR2 - SPI Data Register bit 2

#define SPDR2 2

SPDR3 - SPI Data Register bit 3

#define SPDR3 3

SPDR4 - SPI Data Register bit 4

#define SPDR4 4

SPDR5 - SPI Data Register bit 5

#define SPDR5 5

SPDR6 - SPI Data Register bit 6

#define SPDR6 6

SPDR7 - SPI Data Register bit 7

#define SPDR7 7

PORTA

PORTA - Port A Data Register

sfrb PORTA = $02;

PORTA0 - Port A Data Register bit 0

#define PORTA0 0

PORTA1 - Port A Data Register bit 1

#define PORTA1 1

PORTA2 - Port A Data Register bit 2

#define PORTA2 2

PORTA3 - Port A Data Register bit 3

#define PORTA3 3

PORTA4 - Port A Data Register bit 4

#define PORTA4 4

PORTA5 - Port A Data Register bit 5

#define PORTA5 5

PORTA6 - Port A Data Register bit 6

#define PORTA6 6

PORTA7 - Port A Data Register bit 7

#define PORTA7 7

DDRA - Port A Data Direction Register

sfrb DDRA = $01;

DDA0 - Data Direction Register, Port A, bit 0

#define DDA0 0

DDA1 - Data Direction Register, Port A, bit 1

#define DDA1 1

DDA2 - Data Direction Register, Port A, bit 2

#define DDA2 2

DDA3 - Data Direction Register, Port A, bit 3

#define DDA3 3

DDA4 - Data Direction Register, Port A, bit 4

#define DDA4 4

DDA5 - Data Direction Register, Port A, bit 5

#define DDA5 5

DDA6 - Data Direction Register, Port A, bit 6

#define DDA6 6

DDA7 - Data Direction Register, Port A, bit 7

#define DDA7 7

PINA - Port A Input Pins

sfrb PINA = $00;

PINA0 - Input Pins, Port A bit 0

#define PINA0 0

PINA1 - Input Pins, Port A bit 1

#define PINA1 1

PINA2 - Input Pins, Port A bit 2

#define PINA2 2

PINA3 - Input Pins, Port A bit 3

#define PINA3 3

PINA4 - Input Pins, Port A bit 4

#define PINA4 4

PINA5 - Input Pins, Port A bit 5

#define PINA5 5

PINA6 - Input Pins, Port A bit 6

#define PINA6 6

PINA7 - Input Pins, Port A bit 7

#define PINA7 7

PORTB

PORTB - Port B Data Register

sfrb PORTB = $05;

PORTB0 - Port B Data Register bit 0

#define PORTB0 0

PORTB1 - Port B Data Register bit 1

#define PORTB1 1

PORTB2 - Port B Data Register bit 2

#define PORTB2 2

PORTB3 - Port B Data Register bit 3

#define PORTB3 3

PORTB4 - Port B Data Register bit 4

#define PORTB4 4

PORTB5 - Port B Data Register bit 5

#define PORTB5 5

PORTB6 - Port B Data Register bit 6

#define PORTB6 6

PORTB7 - Port B Data Register bit 7

#define PORTB7 7

DDRB - Port B Data Direction Register

sfrb DDRB = $04;

DDB0 - Port B Data Direction Register bit 0

#define DDB0 0

DDB1 - Port B Data Direction Register bit 1

#define DDB1 1

DDB2 - Port B Data Direction Register bit 2

#define DDB2 2

DDB3 - Port B Data Direction Register bit 3

#define DDB3 3

DDB4 - Port B Data Direction Register bit 4

#define DDB4 4

DDB5 - Port B Data Direction Register bit 5

#define DDB5 5

DDB6 - Port B Data Direction Register bit 6

#define DDB6 6

DDB7 - Port B Data Direction Register bit 7

#define DDB7 7

PINB - Port B Input Pins

sfrb PINB = $03;

PINB0 - Port B Input Pins bit 0

#define PINB0 0

PINB1 - Port B Input Pins bit 1

#define PINB1 1

PINB2 - Port B Input Pins bit 2

#define PINB2 2

PINB3 - Port B Input Pins bit 3

#define PINB3 3

PINB4 - Port B Input Pins bit 4

#define PINB4 4

PINB5 - Port B Input Pins bit 5

#define PINB5 5

PINB6 - Port B Input Pins bit 6

#define PINB6 6

PINB7 - Port B Input Pins bit 7

#define PINB7 7

PORTC

PORTC - Port C Data Register

sfrb PORTC = $08;

PORTC0 - Port C Data Register bit 0

#define PORTC0 0

PORTC1 - Port C Data Register bit 1

#define PORTC1 1

PORTC2 - Port C Data Register bit 2

#define PORTC2 2

PORTC3 - Port C Data Register bit 3

#define PORTC3 3

PORTC4 - Port C Data Register bit 4

#define PORTC4 4

PORTC5 - Port C Data Register bit 5

#define PORTC5 5

PORTC6 - Port C Data Register bit 6

#define PORTC6 6

PORTC7 - Port C Data Register bit 7

#define PORTC7 7

DDRC - Port C Data Direction Register

sfrb DDRC = $07;

DDC0 - Port C Data Direction Register bit 0

#define DDC0 0

DDC1 - Port C Data Direction Register bit 1

#define DDC1 1

DDC2 - Port C Data Direction Register bit 2

#define DDC2 2

DDC3 - Port C Data Direction Register bit 3

#define DDC3 3

DDC4 - Port C Data Direction Register bit 4

#define DDC4 4

DDC5 - Port C Data Direction Register bit 5

#define DDC5 5

DDC6 - Port C Data Direction Register bit 6

#define DDC6 6

DDC7 - Port C Data Direction Register bit 7

#define DDC7 7

PINC - Port C Input Pins

sfrb PINC = $06;

PINC0 - Port C Input Pins bit 0

#define PINC0 0

PINC1 - Port C Input Pins bit 1

#define PINC1 1

PINC2 - Port C Input Pins bit 2

#define PINC2 2

PINC3 - Port C Input Pins bit 3

#define PINC3 3

PINC4 - Port C Input Pins bit 4

#define PINC4 4

PINC5 - Port C Input Pins bit 5

#define PINC5 5

PINC6 - Port C Input Pins bit 6

#define PINC6 6

PINC7 - Port C Input Pins bit 7

#define PINC7 7

PORTD

PORTD - Port D Data Register

sfrb PORTD = $0B;

PORTD0 - Port D Data Register bit 0

#define PORTD0 0

PORTD1 - Port D Data Register bit 1

#define PORTD1 1

PORTD2 - Port D Data Register bit 2

#define PORTD2 2

PORTD3 - Port D Data Register bit 3

#define PORTD3 3

PORTD4 - Port D Data Register bit 4

#define PORTD4 4

PORTD5 - Port D Data Register bit 5

#define PORTD5 5

PORTD6 - Port D Data Register bit 6

#define PORTD6 6

PORTD7 - Port D Data Register bit 7

#define PORTD7 7

DDRD - Port D Data Direction Register

sfrb DDRD = $0A;

DDD0 - Port D Data Direction Register bit 0

#define DDD0 0

DDD1 - Port D Data Direction Register bit 1

#define DDD1 1

DDD2 - Port D Data Direction Register bit 2

#define DDD2 2

DDD3 - Port D Data Direction Register bit 3

#define DDD3 3

DDD4 - Port D Data Direction Register bit 4

#define DDD4 4

DDD5 - Port D Data Direction Register bit 5

#define DDD5 5

DDD6 - Port D Data Direction Register bit 6

#define DDD6 6

DDD7 - Port D Data Direction Register bit 7

#define DDD7 7

PIND - Port D Input Pins

sfrb PIND = $09;

PIND0 - Port D Input Pins bit 0

#define PIND0 0

PIND1 - Port D Input Pins bit 1

#define PIND1 1

PIND2 - Port D Input Pins bit 2

#define PIND2 2

PIND3 - Port D Input Pins bit 3

#define PIND3 3

PIND4 - Port D Input Pins bit 4

#define PIND4 4

PIND5 - Port D Input Pins bit 5

#define PIND5 5

PIND6 - Port D Input Pins bit 6

#define PIND6 6

PIND7 - Port D Input Pins bit 7

#define PIND7 7

PORTE

PORTE - Data Register, Port E

sfrb PORTE = $0E;

PORTE0

#define PORTE0 0

PORTE1

#define PORTE1 1

PORTE2

#define PORTE2 2

PORTE3

#define PORTE3 3

PORTE4

#define PORTE4 4

PORTE5

#define PORTE5 5

PORTE6

#define PORTE6 6

PORTE7

#define PORTE7 7

DDRE - Data Direction Register, Port E

sfrb DDRE = $0D;

DDE0

#define DDE0 0

DDE1

#define DDE1 1

DDE2

#define DDE2 2

DDE3

#define DDE3 3

DDE4

#define DDE4 4

DDE5

#define DDE5 5

DDE6

#define DDE6 6

DDE7

#define DDE7 7

PINE - Input Pins, Port E

sfrb PINE = $0C;

PINE0

#define PINE0 0

PINE1

#define PINE1 1

PINE2

#define PINE2 2

PINE3

#define PINE3 3

PINE4

#define PINE4 4

PINE5

#define PINE5 5

PINE6

#define PINE6 6

PINE7

#define PINE7 7

PORTF

PORTF - Data Register, Port F

sfrb PORTF = $11;

PORTF0

#define PORTF0 0

PORTF1

#define PORTF1 1

PORTF2

#define PORTF2 2

PORTF3

#define PORTF3 3

PORTF4

#define PORTF4 4

PORTF5

#define PORTF5 5

PORTF6

#define PORTF6 6

PORTF7

#define PORTF7 7

DDRF - Data Direction Register, Port F

sfrb DDRF = $10;

DDF0

#define DDF0 0

DDF1

#define DDF1 1

DDF2

#define DDF2 2

DDF3

#define DDF3 3

DDF4

#define DDF4 4

DDF5

#define DDF5 5

DDF6

#define DDF6 6

DDF7

#define DDF7 7

PINF - Input Pins, Port F

sfrb PINF = $0F;

PINF0

#define PINF0 0

PINF1

#define PINF1 1

PINF2

#define PINF2 2

PINF3

#define PINF3 3

PINF4

#define PINF4 4

PINF5

#define PINF5 5

PINF6

#define PINF6 6

PINF7

#define PINF7 7

PORTG

PORTG - Data Register, Port G

sfrb PORTG = $14;

PORTG0

#define PORTG0 0

PORTG1

#define PORTG1 1

PORTG2

#define PORTG2 2

PORTG3

#define PORTG3 3

PORTG4

#define PORTG4 4

PORTG5

#define PORTG5 5

DDRG -

sfrb DDRG = $13;

DDG0

#define DDG0 0

DDG1

#define DDG1 1

DDG2

#define DDG2 2

DDG3

#define DDG3 3

DDG4

#define DDG4 4

DDG5

#define DDG5 5

PING - Input Pins, Port G

sfrb PING = $12;

PING0

#define PING0 0

PING1

#define PING1 1

PING2

#define PING2 2

PING3

#define PING3 3

PING4

#define PING4 4

PING5

#define PING5 5

TIMER COUNTER 0

OCR0B - Timer/Counter0 Output Compare Register

sfrb OCR0B = $28;

OCR0B_0

#define OCR0B_0 0

OCR0B_1

#define OCR0B_1 1

OCR0B_2

#define OCR0B_2 2

OCR0B_3

#define OCR0B_3 3

OCR0B_4

#define OCR0B_4 4

OCR0B_5

#define OCR0B_5 5

OCR0B_6

#define OCR0B_6 6

OCR0B_7

#define OCR0B_7 7

OCR0A - Timer/Counter0 Output Compare Register

sfrb OCR0A = $27;

OCROA_0

#define OCROA_0 0

OCROA_1

#define OCROA_1 1

OCROA_2

#define OCROA_2 2

OCROA_3

#define OCROA_3 3

OCROA_4

#define OCROA_4 4

OCROA_5

#define OCROA_5 5

OCROA_6

#define OCROA_6 6

OCROA_7

#define OCROA_7 7

TCNT0 - Timer/Counter0

sfrb TCNT0 = $26;

TCNT0_0

#define TCNT0_0 0

TCNT0_1

#define TCNT0_1 1

TCNT0_2

#define TCNT0_2 2

TCNT0_3

#define TCNT0_3 3

TCNT0_4

#define TCNT0_4 4

TCNT0_5

#define TCNT0_5 5

TCNT0_6

#define TCNT0_6 6

TCNT0_7

#define TCNT0_7 7

TCCR0B - Timer/Counter Control Register B

sfrb TCCR0B = $25;

CS00 - Clock Select

#define CS00 0

CS01 - Clock Select

#define CS01 1

CS02 - Clock Select

#define CS02 2

WGM02

#define WGM02 3

FOC0B - Force Output Compare B

#define FOC0B 6

FOC0A - Force Output Compare A

#define FOC0A 7

TCCR0A - Timer/Counter Control Register A

sfrb TCCR0A = $24;

WGM00 - Waveform Generation Mode

#define WGM00 0

WGM01 - Waveform Generation Mode

#define WGM01 1

COM0B0 - Compare Output Mode, Fast PWm

#define COM0B0 4

COM0B1 - Compare Output Mode, Fast PWm

#define COM0B1 5

COM0A0 - Compare Output Mode, Phase Correct PWM Mode

#define COM0A0 6

COM0A1 - Compare Output Mode, Phase Correct PWM Mode

#define COM0A1 7

TIMSK0 - Timer/Counter0 Interrupt Mask Register

sfrb TIMSK0 = $6E;

TOIE0 - Timer/Counter0 Overflow Interrupt Enable

#define TOIE0 0

OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable

#define OCIE0A 1

OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable

#define OCIE0B 2

TIFR0 - Timer/Counter0 Interrupt Flag register

sfrb TIFR0 = $15;

TOV0 - Timer/Counter0 Overflow Flag

#define TOV0 0

OCF0A - Timer/Counter0 Output Compare Flag 0A

#define OCF0A 1

OCF0B - Timer/Counter0 Output Compare Flag 0B

#define OCF0B 2

GTCCR - General Timer/Counter Control Register

sfrb GTCCR = $23;

PSRSYNC - Prescaler Reset Timer/Counter1 and Timer/Counter0

#define PSRSYNC 0

When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.

TSM - Timer/Counter Synchronization Mode

#define TSM 7

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneousl

TIMER COUNTER 2

The 8-bit Timer/Counter2 can select clock source from CK, prescaled CK, or external crystal input TOSC1. It can also be stopped as described in the section ?Timer/Counter2 Control Register - TCCR2?. The status flags (overflow and compare match) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Register TCCR2. The interrupt enable/disable settings are found in ?The Timer/Counter Interrupt Mask Register - TIMSK?. When Timer/Counter2 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. This module features a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. Timer/Counter2 can also be used as an 8-bit Pulse Width Modulator. In this mode, Timer/Counter2 and the output compare register serve as a glitch-free, stand-alone PWM with centered puls

TIMSK2 - Timer/Counter Interrupt Mask register

sfrb TIMSK2 = $70;

TOIE2 - Timer/Counter2 Overflow Interrupt Enable

#define TOIE2 0

When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register ? TIFR2.

OCIE2A - Timer/Counter2 Output Compare Match A Interrupt Enable

#define OCIE2A 1

When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the Timer/Counter 2 Interrupt Flag Register ? TIFR2.

OCIE2B - Timer/Counter2 Output Compare Match B Interrupt Enable

#define OCIE2B 2

When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the Timer/Counter 2 Interrupt Flag Register ? TIFR2.

TIFR2 - Timer/Counter Interrupt Flag Register

sfrb TIFR2 = $17;

TOV2 - Timer/Counter2 Overflow Flag

#define TOV2 0

The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.

OCF2A - Output Compare Flag 2A

#define OCF2A 1

The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A ? Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed.

OCF2B - Output Compare Flag 2B

#define OCF2B 2

The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B ? Output Compare Register2. OCF2B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 Compare match Interrupt Enable), and OCF2B are set (one), the Timer/Counter2 Compare match Interrupt is executed.

TCCR2A - Timer/Counter2 Control Register A

sfrb TCCR2A = $B0;

WGM20 - Waveform Genration Mode

#define WGM20 0

These bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information.

WGM21 - Waveform Genration Mode

#define WGM21 1

COM2B0 - Compare Output Mode bit 0

#define COM2B0 4

The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different functio

COM2B1 - Compare Output Mode bit 1

#define COM2B1 5

COM2A0 - Compare Output Mode bit 1

#define COM2A0 6

COM2A1 - Compare Output Mode bit 1

#define COM2A1 7

TCCR2B - Timer/Counter2 Control Register B

sfrb TCCR2B = $B1;

CS20 - Clock Select bit 0

#define CS20 0

The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.

CS21 - Clock Select bit 1

#define CS21 1

CS22 - Clock Select bit 2

#define CS22 2

WGM22 - Waveform Generation Mode

#define WGM22 3

FOC2B - Force Output Compare B

#define FOC2B 6

Writing a logical one to this bit, forces a change in the compare match output pin PD7 (OC2) according to the values already set in COM21 and COM20. If the COM21 and COM20 bits are written in the same cycle as FOC2, the new settings will not take effect until next compare match or forced output compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM21 and COM20 happens as if a Compare Match had occurred, but no interrupt is generated, and the Timer/Counter will not be cleared even if CTC2 is set. The corresponding I/O pin must be set as an output pin for the FOC2 bit to have effect on the pin. The FOC2 bit will always be read as zero. Setting the FOC2 bit has no effect in PWM mode

FOC2A - Force Output Compare A

#define FOC2A 7

TCNT2 - Timer/Counter2

sfrb TCNT2 = $B2;

TCNT2-0 - Timer/Counter 2 bit 0

#define TCNT2-0 0

TCNT2-1 - Timer/Counter 2 bit 1

#define TCNT2-1 1

TCNT2-2 - Timer/Counter 2 bit 2

#define TCNT2-2 2

TCNT2-3 - Timer/Counter 2 bit 3

#define TCNT2-3 3

TCNT2-4 - Timer/Counter 2 bit 4

#define TCNT2-4 4

TCNT2-5 - Timer/Counter 2 bit 5

#define TCNT2-5 5

TCNT2-6 - Timer/Counter 2 bit 6

#define TCNT2-6 6

TCNT2-7 - Timer/Counter 2 bit 7

#define TCNT2-7 7

OCR2B - Timer/Counter2 Output Compare Register B

sfrb OCR2B = $B4;

OCR2-0 - Timer/Counter2 Output Compare Register Bit 0

#define OCR2-0 0

OCR2-1 - Timer/Counter2 Output Compare Register Bit 1

#define OCR2-1 1

OCR2-2 - Timer/Counter2 Output Compare Register Bit 2

#define OCR2-2 2

OCR2-3 - Timer/Counter2 Output Compare Register Bit 3

#define OCR2-3 3

OCR2-4 - Timer/Counter2 Output Compare Register Bit 4

#define OCR2-4 4

OCR2-5 - Timer/Counter2 Output Compare Register Bit 5

#define OCR2-5 5

OCR2-6 - Timer/Counter2 Output Compare Register Bit 6

#define OCR2-6 6

OCR2-7 - Timer/Counter2 Output Compare Register Bit 7

#define OCR2-7 7

OCR2A - Timer/Counter2 Output Compare Register A

sfrb OCR2A = $B3;

OCR2-0 - Timer/Counter2 Output Compare Register Bit 0

#define OCR2-0 0

OCR2-1 - Timer/Counter2 Output Compare Register Bit 1

#define OCR2-1 1

OCR2-2 - Timer/Counter2 Output Compare Register Bit 2

#define OCR2-2 2

OCR2-3 - Timer/Counter2 Output Compare Register Bit 3

#define OCR2-3 3

OCR2-4 - Timer/Counter2 Output Compare Register Bit 4

#define OCR2-4 4

OCR2-5 - Timer/Counter2 Output Compare Register Bit 5

#define OCR2-5 5

OCR2-6 - Timer/Counter2 Output Compare Register Bit 6

#define OCR2-6 6

OCR2-7 - Timer/Counter2 Output Compare Register Bit 7

#define OCR2-7 7

ASSR - Asynchronous Status Register

sfrb ASSR = $B6;

TCR2BUB - Timer/Counter Control Register2 Update Busy

#define TCR2BUB 0

When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set. When TCCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new value.

TCR2AUB - Timer/Counter Control Register2 Update Busy

#define TCR2AUB 1

When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new value.

OCR2BUB - Output Compare Register 2 Update Busy

#define OCR2BUB 2

When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value.

OCR2AUB - Output Compare Register2 Update Busy

#define OCR2AUB 3

When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value.

TCN2UB - Timer/Counter2 Update Busy

#define TCN2UB 4

When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.

AS2 - Asynchronous Timer/Counter2

#define AS2 5

When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted.

EXCLK - Enable External Clock Input

#define EXCLK 6

When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero.

GTCCR - General Timer Counter Control register

sfrb GTCCR = $23;

PSRASY - Prescaler Reset Timer/Counter2

#define PSRASY 1

When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the ?Bit 7 ? TSM: Timer/Counter Synchronization Mode? on page 107 for a description of the Timer/Counter Synchronization mode.

TSM - Timer/Counter Synchronization Mode

#define TSM 7

WATCHDOG

WDTCSR - Watchdog Timer Control Register

sfrb WDTCSR = $60;

WDP0 - Watch Dog Timer Prescaler bit 0

#define WDP0 0

WDP1 - Watch Dog Timer Prescaler bit 1

#define WDP1 1

WDP2 - Watch Dog Timer Prescaler bit 2

#define WDP2 2

WDE - Watch Dog Enable

#define WDE 3

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog

WDCE - Watchdog Change Enable

#define WDCE 4

WDP3 - Watchdog Timer Prescaler Bit 3

#define WDP3 5

WDIE - Watchdog Timeout Interrupt Enable

#define WDIE 6

WDIF - Watchdog Timeout Interrupt Flag

#define WDIF 7

USART1

UDR1 - USART I/O Data Register

sfrb UDR1 = $CE;

UDR1-0 - USART I/O Data Register bit 0

#define UDR1-0 0

UDR1-1 - USART I/O Data Register bit 1

#define UDR1-1 1

UDR1-2 - USART I/O Data Register bit 2

#define UDR1-2 2

UDR1-3 - USART I/O Data Register bit 3

#define UDR1-3 3

UDR1-4 - USART I/O Data Register bit 4

#define UDR1-4 4

UDR1-5 - USART I/O Data Register bit 5

#define UDR1-5 5

UDR1-6 - USART I/O Data Register bit 6

#define UDR1-6 6

UDR1-7 - USART I/O Data Register bit 7

#define UDR1-7 7

UCSR1A - USART Control and Status Register A

sfrb UCSR1A = $C8;

MPCM1 - Multi-processor Communication Mode

#define MPCM1 0

U2X1 - Double the USART transmission speed

#define U2X1 1

UPE1 - Parity Error

#define UPE1 2

DOR1 - Data overRun

#define DOR1 3

FE1 - Framing Error

#define FE1 4

This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.

UDRE1 - USART Data Register Empty

#define UDRE1 5

TXC1 - USART Transmitt Complete

#define TXC1 6

RXC1 - USART Receive Complete

#define RXC1 7

UCSR1B - USART Control and Status Register B

sfrb UCSR1B = $C9;

TXB81 - Transmit Data Bit 8

#define TXB81 0

TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.

RXB81 - Receive Data Bit 8

#define RXB81 1

RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.

UCSZ12 - Character Size

#define UCSZ12 2

The UCSZ2 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use.

TXEN1 - Transmitter Enable

#define TXEN1 3

RXEN1 - Receiver Enable

#define RXEN1 4

UDRIE1 - USART Data register Empty Interrupt Enable

#define UDRIE1 5

TXCIE1 - TX Complete Interrupt Enable

#define TXCIE1 6

RXCIE1 - RX Complete Interrupt Enable

#define RXCIE1 7

UCSR1C - USART Control and Status Register C

sfrb UCSR1C = $CA;

UCPOL1 - Clock Polarity

#define UCPOL1 0

UCSZ10-UCPHA1 - Character Size

#define UCSZ10-UCPHA1 1

Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.

UCSZ11-UDORD1 - Character Size

#define UCSZ11-UDORD1 2

Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.

USBS1 - Stop Bit Select

#define USBS1 3

0: 1-bit. 1: 2-bit.

UPM10 - Parity Mode Bit 0

#define UPM10 4

UPM11 - Parity Mode Bit 1

#define UPM11 5

UMSEL10 - USART Mode Select

#define UMSEL10 6

UMSEL11 - USART Mode Select

#define UMSEL11 7

UBRR1H - USART Baud Rate Register High Byte

sfrb UBRR1H = $CD;

UBRR8 - USART Baud Rate Register bit 8

#define UBRR8 0

UBRR9 - USART Baud Rate Register bit 9

#define UBRR9 1

UBRR10 - USART Baud Rate Register bit 10

#define UBRR10 2

UBRR11 - USART Baud Rate Register bit 11

#define UBRR11 3

UBRR1L - USART Baud Rate Register Low Byte

sfrb UBRR1L = $CC;

UBRR0 - USART Baud Rate Register bit 0

#define UBRR0 0

UBRR1 - USART Baud Rate Register bit 1

#define UBRR1 1

UBRR2 - USART Baud Rate Register bit 2

#define UBRR2 2

UBRR3 - USART Baud Rate Register bit 3

#define UBRR3 3

UBRR4 - USART Baud Rate Register bit 4

#define UBRR4 4

UBRR5 - USART Baud Rate Register bit 5

#define UBRR5 5

UBRR6 - USART Baud Rate Register bit 6

#define UBRR6 6

UBRR7 - USART Baud Rate Register bit 7

#define UBRR7 7

EEPROM

EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See ?Preventing EEPROM Corruption? on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execute

EEARH - EEPROM Address Register Low Byte

sfrb EEARH = $22;

EEAR8 - EEPROM Read/Write Access Bit 8

#define EEAR8 0

EEAR9 - EEPROM Read/Write Access Bit 9

#define EEAR9 1

EEAR10 - EEPROM Read/Write Access Bit 10

#define EEAR10 2

EEAR11 - EEPROM Read/Write Access Bit 11

#define EEAR11 3

EEARL - EEPROM Address Register Low Byte

sfrb EEARL = $21;

EEAR0 - EEPROM Read/Write Access Bit 0

#define EEAR0 0

EEAR1 - EEPROM Read/Write Access Bit 1

#define EEAR1 1

EEAR2 - EEPROM Read/Write Access Bit 2

#define EEAR2 2

EEAR3 - EEPROM Read/Write Access Bit 3

#define EEAR3 3

EEAR4 - EEPROM Read/Write Access Bit 4

#define EEAR4 4

EEAR5 - EEPROM Read/Write Access Bit 5

#define EEAR5 5

EEAR6 - EEPROM Read/Write Access Bit 6

#define EEAR6 6

EEAR7 - EEPROM Read/Write Access Bit 7

#define EEAR7 7

EEDR - EEPROM Data Register

sfrb EEDR = $20;

EEDR0 - EEPROM Data Register bit 0

#define EEDR0 0

EEDR1 - EEPROM Data Register bit 1

#define EEDR1 1

EEDR2 - EEPROM Data Register bit 2

#define EEDR2 2

EEDR3 - EEPROM Data Register bit 3

#define EEDR3 3

EEDR4 - EEPROM Data Register bit 4

#define EEDR4 4

EEDR5 - EEPROM Data Register bit 5

#define EEDR5 5

EEDR6 - EEPROM Data Register bit 6

#define EEDR6 6

EEDR7 - EEPROM Data Register bit 7

#define EEDR7 7

EECR - EEPROM Control Register

sfrb EECR = $1F;

EERE - EEPROM Read Enable

#define EERE 0

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU

EEPE - EEPROM Write Enable

#define EEPE 1

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See ?Boot Loader Support - Read While Write self-programming? on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed

EEMPE - EEPROM Master Write Enable

#define EEMPE 2

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

EERIE - EEPROM Ready Interrupt Enable

#define EERIE 3

EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.

EEPM0 - EEPROM Programming Mode Bit 0

#define EEPM0 4

The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

EEPM1 - EEPROM Programming Mode Bit 1

#define EEPM1 5

TIMER COUNTER 5

TCCR5A - Timer/Counter5 Control Register A

sfrb TCCR5A = $120;

WGM50 - Waveform Generation Mode

#define WGM50 0

Combined with the WGM53:2 bits found in the TCCR5B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.

WGM51 - Waveform Generation Mode

#define WGM51 1

COM5C0 - Compare Output Mode 5C, bit 0

#define COM5C0 2

The COM5C1 and COM5C0 control bits determine any output pin action following a compare match in Timer/Counter5. Any output pin actions affect pin OC5B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.

COM5C1 - Compare Output Mode 5C, bit 1

#define COM5C1 3

COM5B0 - Compare Output Mode 5B, bit 0

#define COM5B0 4

The COM5B1 and COM5B0 control bits determine any output pin action following a compare match in Timer/Counter5. Any output pin actions affect pin OC5B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.

COM5B1 - Compare Output Mode 5B, bit 1

#define COM5B1 5

COM5A0 - Compare Output Mode 5A, bit 0

#define COM5A0 6

The COM5A1 and COM5A0 control bits determine any output pin action following a compare match in Timer/Counter5. Any output pin actions affect pin OC5A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.

COM5A1 - Compare Output Mode 1A, bit 1

#define COM5A1 7

TCCR5B - Timer/Counter5 Control Register B

sfrb TCCR5B = $121;

CS50 - Prescaler source of Timer/Counter 5

#define CS50 0

Select Prescaling Clock Source of Timer/Counter5. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.

CS51 - Prescaler source of Timer/Counter 5

#define CS51 1

Select Prescaling Clock Source of Timer/Counter5. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T5, falling edge. (1:1:1) = External Pin 1, rising edge.

CS52 - Prescaler source of Timer/Counter 5

#define CS52 2

WGM52 - Waveform Generation Mode

#define WGM52 3

WGM53 - Waveform Generation Mode

#define WGM53 4

ICES5 - Input Capture 5 Edge Select

#define ICES5 6

While the ICES5 bit is cleared (zero), the Timer/Counter5 contents are transferred to the Input Capture Register - ICR5 - on the falling edge of the input capture pin - ICP. While the ICES5 bit is set (one), the Timer/Counter5 contents are transferred to the Input Capture Register - ICR5 - on the rising edge of the input capture pin - ICP.

ICNC5 - Input Capture 5 Noise Canceler

#define ICNC5 7

When the ICNC5 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC5 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES5 bit. The actual sampling frequency is XTAL clock frequency.

TCCR5C - Timer/Counter 5 Control Register C

sfrb TCCR5C = $122;

FOC5C - Force Output Compare 5C

#define FOC5C 5

Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM5B1 and COM5B0.If the COM5B1 and COM5B0 bits are written in the same cycle as FOC5B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM5B1 and COM5B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC5B bit to have effect on the pin. The FOC5B bit will always be read as zero. The setting of the FOC5B bit has no effect in PWM mo

FOC5B - Force Output Compare 5B

#define FOC5B 6

FOC5A - Force Output Compare 5A

#define FOC5A 7

Writing a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM5A1 and COM5A0.If the COM5A1 and COM5A0 bits are written in the same cycle as FOC5A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM5A1 and COM5A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC5 in TCCR5B is set. The corresponding I/O pin must be set as an output pin for the FOC5A bit to have effect on the pin. The FOC5A bit will always be read as zero. The setting of the FOC5A bit has no effect in PWM m

TCNT5H - Timer/Counter5 High Byte

sfrb TCNT5H = $125;

TCNT5H0 - Timer/Counter5 High Byte bit 0

#define TCNT5H0 0

TCNT5H1 - Timer/Counter5 High Byte bit 1

#define TCNT5H1 1

TCNT5H2 - Timer/Counter5 High Byte bit 2

#define TCNT5H2 2

TCNT5H3 - Timer/Counter5 High Byte bit 3

#define TCNT5H3 3

TCNT5H4 - Timer/Counter5 High Byte bit 4

#define TCNT5H4 4

TCNT5H5 - Timer/Counter5 High Byte bit 5

#define TCNT5H5 5

TCNT5H6 - Timer/Counter5 High Byte bit 6

#define TCNT5H6 6

TCNT5H7 - Timer/Counter5 High Byte bit 7

#define TCNT5H7 7

TCNT5L - Timer/Counter5 Low Byte

sfrb TCNT5L = $124;

TCNT5L0 - Timer/Counter5 Low Byte bit 0

#define TCNT5L0 0

TCNT5L1 - Timer/Counter5 Low Byte bit 1

#define TCNT5L1 1

TCNT5L2 - Timer/Counter5 Low Byte bit 2

#define TCNT5L2 2

TCNT5L3 - Timer/Counter5 Low Byte bit 3

#define TCNT5L3 3

TCNT5L4 - Timer/Counter5 Low Byte bit 4

#define TCNT5L4 4

TCNT5L5 - Timer/Counter5 Low Byte bit 5

#define TCNT5L5 5

TCNT5L6 - Timer/Counter5 Low Byte bit 6

#define TCNT5L6 6

TCNT5L7 - Timer/Counter5 Low Byte bit 7

#define TCNT5L7 7

OCR5AH - Timer/Counter5 Outbut Compare Register A High Byte

sfrb OCR5AH = $129;

OCR5AH0 - Timer/Counter5 Outbut Compare Register High Byte bit 0

#define OCR5AH0 0

OCR5AH1 - Timer/Counter5 Outbut Compare Register High Byte bit 1

#define OCR5AH1 1

OCR5AH2 - Timer/Counter5 Outbut Compare Register High Byte bit 2

#define OCR5AH2 2

OCR5AH3 - Timer/Counter5 Outbut Compare Register High Byte bit 3

#define OCR5AH3 3

OCR5AH4 - Timer/Counter5 Outbut Compare Register High Byte bit 4

#define OCR5AH4 4

OCR5AH5 - Timer/Counter5 Outbut Compare Register High Byte bit 5

#define OCR5AH5 5

OCR5AH6 - Timer/Counter5 Outbut Compare Register High Byte bit 6

#define OCR5AH6 6

OCR5AH7 - Timer/Counter5 Outbut Compare Register High Byte bit 7

#define OCR5AH7 7

OCR5AL - Timer/Counter5 Outbut Compare Register A Low Byte

sfrb OCR5AL = $128;

OCR5AL0 - Timer/Counter5 Outbut Compare Register Low Byte Bit 0

#define OCR5AL0 0

OCR5AL1 - Timer/Counter5 Outbut Compare Register Low Byte Bit 1

#define OCR5AL1 1

OCR5AL2 - Timer/Counter5 Outbut Compare Register Low Byte Bit 2

#define OCR5AL2 2

OCR5AL3 - Timer/Counter5 Outbut Compare Register Low Byte Bit 3

#define OCR5AL3 3

OCR5AL4 - Timer/Counter5 Outbut Compare Register Low Byte Bit 4

#define OCR5AL4 4

OCR5AL5 - Timer/Counter5 Outbut Compare Register Low Byte Bit 5

#define OCR5AL5 5

OCR5AL6 - Timer/Counter5 Outbut Compare Register Low Byte Bit 6

#define OCR5AL6 6

OCR5AL7 - Timer/Counter5 Outbut Compare Register Low Byte Bit 7

#define OCR5AL7 7

OCR5BH - Timer/Counter5 Output Compare Register B High Byte

sfrb OCR5BH = $12B;

OCR5BH0 - Timer/Counter5 Output Compare Register High Byte bit 0

#define OCR5BH0 0

OCR5BH1 - Timer/Counter5 Output Compare Register High Byte bit 1

#define OCR5BH1 1

OCR5BH2 - Timer/Counter5 Output Compare Register High Byte bit 2

#define OCR5BH2 2

OCR5BH3 - Timer/Counter5 Output Compare Register High Byte bit 3

#define OCR5BH3 3

OCR5BH4 - Timer/Counter5 Output Compare Register High Byte bit 4

#define OCR5BH4 4

OCR5BH5 - Timer/Counter5 Output Compare Register High Byte bit 5

#define OCR5BH5 5

OCR5BH6 - Timer/Counter5 Output Compare Register High Byte bit 6

#define OCR5BH6 6

OCR5BH7 - Timer/Counter5 Output Compare Register High Byte bit 7

#define OCR5BH7 7

OCR5BL - Timer/Counter5 Output Compare Register B Low Byte

sfrb OCR5BL = $12A;

OCR5BL0 - Timer/Counter5 Output Compare Register Low Byte bit 0

#define OCR5BL0 0

OCR5BL1 - Timer/Counter5 Output Compare Register Low Byte bit 1

#define OCR5BL1 1

OCR5BL2 - Timer/Counter5 Output Compare Register Low Byte bit 2

#define OCR5BL2 2

OCR5BL3 - Timer/Counter5 Output Compare Register Low Byte bit 3

#define OCR5BL3 3

OCR5BL4 - Timer/Counter5 Output Compare Register Low Byte bit 4

#define OCR5BL4 4

OCR5BL5 - Timer/Counter5 Output Compare Register Low Byte bit 5

#define OCR5BL5 5

OCR5BL6 - Timer/Counter5 Output Compare Register Low Byte bit 6

#define OCR5BL6 6

OCR5BL7 - Timer/Counter5 Output Compare Register Low Byte bit 7

#define OCR5BL7 7

OCR5CH - Timer/Counter5 Output Compare Register B High Byte

sfrb OCR5CH = $12D;

OCR5CH0 - Timer/Counter5 Output Compare Register High Byte bit 0

#define OCR5CH0 0

OCR5CH1 - Timer/Counter5 Output Compare Register High Byte bit 1

#define OCR5CH1 1

OCR5CH2 - Timer/Counter5 Output Compare Register High Byte bit 2

#define OCR5CH2 2

OCR5CH3 - Timer/Counter5 Output Compare Register High Byte bit 3

#define OCR5CH3 3

OCR5CH4 - Timer/Counter5 Output Compare Register High Byte bit 4

#define OCR5CH4 4

OCR5CH5 - Timer/Counter5 Output Compare Register High Byte bit 5

#define OCR5CH5 5

OCR5CH6 - Timer/Counter5 Output Compare Register High Byte bit 6

#define OCR5CH6 6

OCR5CH7 - Timer/Counter5 Output Compare Register High Byte bit 7

#define OCR5CH7 7

OCR5CL - Timer/Counter5 Output Compare Register B Low Byte

sfrb OCR5CL = $12C;

OCR5CL0 - Timer/Counter5 Output Compare Register Low Byte bit 0

#define OCR5CL0 0

OCR5CL1 - Timer/Counter5 Output Compare Register Low Byte bit 1

#define OCR5CL1 1

OCR5CL2 - Timer/Counter5 Output Compare Register Low Byte bit 2

#define OCR5CL2 2

OCR5CL3 - Timer/Counter5 Output Compare Register Low Byte bit 3

#define OCR5CL3 3

OCR5CL4 - Timer/Counter5 Output Compare Register Low Byte bit 4

#define OCR5CL4 4

OCR5CL5 - Timer/Counter5 Output Compare Register Low Byte bit 5

#define OCR5CL5 5

OCR5CL6 - Timer/Counter5 Output Compare Register Low Byte bit 6

#define OCR5CL6 6

OCR5CL7 - Timer/Counter5 Output Compare Register Low Byte bit 7

#define OCR5CL7 7

ICR5H - Timer/Counter5 Input Capture Register High Byte

sfrb ICR5H = $127;

ICR5H0 - Timer/Counter5 Input Capture Register High Byte bit 0

#define ICR5H0 0

ICR5H1 - Timer/Counter5 Input Capture Register High Byte bit 1

#define ICR5H1 1

ICR5H2 - Timer/Counter5 Input Capture Register High Byte bit 2

#define ICR5H2 2

ICR5H3 - Timer/Counter5 Input Capture Register High Byte bit 3

#define ICR5H3 3

ICR5H4 - Timer/Counter5 Input Capture Register High Byte bit 4

#define ICR5H4 4

ICR5H5 - Timer/Counter5 Input Capture Register High Byte bit 5

#define ICR5H5 5

ICR5H6 - Timer/Counter5 Input Capture Register High Byte bit 6

#define ICR5H6 6

ICR5H7 - Timer/Counter5 Input Capture Register High Byte bit 7

#define ICR5H7 7

ICR5L - Timer/Counter5 Input Capture Register Low Byte

sfrb ICR5L = $126;

ICR5L0 - Timer/Counter5 Input Capture Register Low Byte bit 0

#define ICR5L0 0

ICR5L1 - Timer/Counter5 Input Capture Register Low Byte bit 1

#define ICR5L1 1

ICR5L2 - Timer/Counter5 Input Capture Register Low Byte bit 2

#define ICR5L2 2

ICR5L3 - Timer/Counter5 Input Capture Register Low Byte bit 3

#define ICR5L3 3

ICR5L4 - Timer/Counter5 Input Capture Register Low Byte bit 4

#define ICR5L4 4

ICR5L5 - Timer/Counter5 Input Capture Register Low Byte bit 5

#define ICR5L5 5

ICR5L6 - Timer/Counter5 Input Capture Register Low Byte bit 6

#define ICR5L6 6

ICR5L7 - Timer/Counter5 Input Capture Register Low Byte bit 7

#define ICR5L7 7

TIMSK5 - Timer/Counter5 Interrupt Mask Register

sfrb TIMSK5 = $73;

TOIE5 - Timer/Counter5 Overflow Interrupt Enable

#define TOIE5 0

When the TOIE5 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter5 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter5 occurs, i.e., when the TOV5 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE5A - Timer/Counter5 Output Compare A Match Interrupt Enable

#define OCIE5A 1

When the OCIE5A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter5 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter5 occurs, i.e., when the OCF5A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE5B - Timer/Counter5 Output Compare B Match Interrupt Enable

#define OCIE5B 2

When the OCIE5B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter5 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter5 occurs, i.e., when the OCF5B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE5C - Timer/Counter5 Output Compare C Match Interrupt Enable

#define OCIE5C 3

When the OCIE5C bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter5 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter5 occurs, i.e., when the OCF5B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

ICIE5 - Timer/Counter5 Input Capture Interrupt Enable

#define ICIE5 5

When the TICIE5 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter5 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF5 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

TIFR5 - Timer/Counter5 Interrupt Flag register

sfrb TIFR5 = $1A;

TOV5 - Timer/Counter5 Overflow Flag

#define TOV5 0

The TOV5 is set (one) when an overflow occurs in Timer/Counter5. TOV5 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV5 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE5 (Timer/Counter5 Overflow Interrupt Enable), and TOV5 are set (one), the Timer/Counter5 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter5 changes counting direction at $0000.

OCF5A - Output Compare Flag 5A

#define OCF5A 1

The OCF5A bit is set (one) when compare match occurs between the Timer/Counter5 and the data in OCR5A - Output Compare Register 5A. OCF5A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF5A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE5A (Timer/Counter5 Compare match InterruptA Enable), and the OCF5A are set (one), the Timer/Counter5 Compare A match Interrupt is executed.

OCF5B - Output Compare Flag 5B

#define OCF5B 2

The OCF5B bit is set (one) when compare match occurs between the Timer/Counter5 and the data in OCR5B - Output Compare Register 5B. OCF5B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF5B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE5B (Timer/Counter5 Compare match InterruptB Enable), and the OCF5B are set (one), the Timer/Counter5 Compare B match Interrupt is executed.

OCF5C - Output Compare Flag 5C

#define OCF5C 3

The OCF5C bit is set (one) when compare match occurs between the Timer/Counter5 and the data in OCR5B - Output Compare Register 5B. OCF5B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF5B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE5B (Timer/Counter5 Compare match InterruptB Enable), and the OCF5B are set (one), the Timer/Counter5 Compare B match Interrupt is executed.

ICF5 - Input Capture Flag 5

#define ICF5 5

The ICF5 bit is set (one) to flag an input capture event, indicating that the Timer/Counter5 value has been transferred to the input capture register - ICR5. ICF5 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF5 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE5 (Timer/Counter5 Input Capture Interrupt Enable), and ICF5 are set (one), the Timer/Counter5 Capture Interrupt is executed.

TIMER COUNTER 4

TCCR4A - Timer/Counter4 Control Register A

sfrb TCCR4A = $A0;

WGM40 - Waveform Generation Mode

#define WGM40 0

Combined with the WGM43:2 bits found in the TCCR4B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.

WGM41 - Waveform Generation Mode

#define WGM41 1

COM4C0 - Compare Output Mode 4C, bit 0

#define COM4C0 2

The COM4C1 and COM4C0 control bits determine any output pin action following a compare match in Timer/Counter4. Any output pin actions affect pin OC4B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.

COM4C1 - Compare Output Mode 4C, bit 1

#define COM4C1 3

COM4B0 - Compare Output Mode 4B, bit 0

#define COM4B0 4

The COM4B1 and COM4B0 control bits determine any output pin action following a compare match in Timer/Counter4. Any output pin actions affect pin OC4B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.

COM4B1 - Compare Output Mode 4B, bit 1

#define COM4B1 5

COM4A0 - Compare Output Mode 4A, bit 0

#define COM4A0 6

The COM4A1 and COM4A0 control bits determine any output pin action following a compare match in Timer/Counter4. Any output pin actions affect pin OC4A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.

COM4A1 - Compare Output Mode 1A, bit 1

#define COM4A1 7

TCCR4B - Timer/Counter4 Control Register B

sfrb TCCR4B = $A1;

CS40 - Prescaler source of Timer/Counter 4

#define CS40 0

Select Prescaling Clock Source of Timer/Counter4. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.

CS41 - Prescaler source of Timer/Counter 4

#define CS41 1

Select Prescaling Clock Source of Timer/Counter4. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T4, falling edge. (1:1:1) = External Pin 1, rising edge.

CS42 - Prescaler source of Timer/Counter 4

#define CS42 2

WGM42 - Waveform Generation Mode

#define WGM42 3

WGM43 - Waveform Generation Mode

#define WGM43 4

ICES4 - Input Capture 4 Edge Select

#define ICES4 6

While the ICES4 bit is cleared (zero), the Timer/Counter4 contents are transferred to the Input Capture Register - ICR4 - on the falling edge of the input capture pin - ICP. While the ICES4 bit is set (one), the Timer/Counter4 contents are transferred to the Input Capture Register - ICR4 - on the rising edge of the input capture pin - ICP.

ICNC4 - Input Capture 4 Noise Canceler

#define ICNC4 7

When the ICNC4 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC4 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES4 bit. The actual sampling frequency is XTAL clock frequency.

TCCR4C - Timer/Counter 4 Control Register C

sfrb TCCR4C = $A2;

FOC4C - Force Output Compare 4C

#define FOC4C 5

Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM4B1 and COM4B0.If the COM4B1 and COM4B0 bits are written in the same cycle as FOC4B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM4B1 and COM4B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC4B bit to have effect on the pin. The FOC4B bit will always be read as zero. The setting of the FOC4B bit has no effect in PWM mo

FOC4B - Force Output Compare 4B

#define FOC4B 6

FOC4A - Force Output Compare 4A

#define FOC4A 7

Writing a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM4A1 and COM4A0.If the COM4A1 and COM4A0 bits are written in the same cycle as FOC4A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM4A1 and COM4A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC4 in TCCR4B is set. The corresponding I/O pin must be set as an output pin for the FOC4A bit to have effect on the pin. The FOC4A bit will always be read as zero. The setting of the FOC4A bit has no effect in PWM m

TCNT4H - Timer/Counter4 High Byte

sfrb TCNT4H = $A5;

TCNT4H0 - Timer/Counter4 High Byte bit 0

#define TCNT4H0 0

TCNT4H1 - Timer/Counter4 High Byte bit 1

#define TCNT4H1 1

TCNT4H2 - Timer/Counter4 High Byte bit 2

#define TCNT4H2 2

TCNT4H3 - Timer/Counter4 High Byte bit 3

#define TCNT4H3 3

TCNT4H4 - Timer/Counter4 High Byte bit 4

#define TCNT4H4 4

TCNT4H5 - Timer/Counter4 High Byte bit 5

#define TCNT4H5 5

TCNT4H6 - Timer/Counter4 High Byte bit 6

#define TCNT4H6 6

TCNT4H7 - Timer/Counter4 High Byte bit 7

#define TCNT4H7 7

TCNT4L - Timer/Counter4 Low Byte

sfrb TCNT4L = $A4;

TCNT4L0 - Timer/Counter4 Low Byte bit 0

#define TCNT4L0 0

TCNT4L1 - Timer/Counter4 Low Byte bit 1

#define TCNT4L1 1

TCNT4L2 - Timer/Counter4 Low Byte bit 2

#define TCNT4L2 2

TCNT4L3 - Timer/Counter4 Low Byte bit 3

#define TCNT4L3 3

TCNT4L4 - Timer/Counter4 Low Byte bit 4

#define TCNT4L4 4

TCNT4L5 - Timer/Counter4 Low Byte bit 5

#define TCNT4L5 5

TCNT4L6 - Timer/Counter4 Low Byte bit 6

#define TCNT4L6 6

TCNT4L7 - Timer/Counter4 Low Byte bit 7

#define TCNT4L7 7

OCR4AH - Timer/Counter4 Outbut Compare Register A High Byte

sfrb OCR4AH = $A9;

OCR4AH0 - Timer/Counter4 Outbut Compare Register High Byte bit 0

#define OCR4AH0 0

OCR4AH1 - Timer/Counter4 Outbut Compare Register High Byte bit 1

#define OCR4AH1 1

OCR4AH2 - Timer/Counter4 Outbut Compare Register High Byte bit 2

#define OCR4AH2 2

OCR4AH3 - Timer/Counter4 Outbut Compare Register High Byte bit 3

#define OCR4AH3 3

OCR4AH4 - Timer/Counter4 Outbut Compare Register High Byte bit 4

#define OCR4AH4 4

OCR4AH5 - Timer/Counter4 Outbut Compare Register High Byte bit 5

#define OCR4AH5 5

OCR4AH6 - Timer/Counter4 Outbut Compare Register High Byte bit 6

#define OCR4AH6 6

OCR4AH7 - Timer/Counter4 Outbut Compare Register High Byte bit 7

#define OCR4AH7 7

OCR4AL - Timer/Counter4 Outbut Compare Register A Low Byte

sfrb OCR4AL = $A8;

OCR4AL0 - Timer/Counter4 Outbut Compare Register Low Byte Bit 0

#define OCR4AL0 0

OCR4AL1 - Timer/Counter4 Outbut Compare Register Low Byte Bit 1

#define OCR4AL1 1

OCR4AL2 - Timer/Counter4 Outbut Compare Register Low Byte Bit 2

#define OCR4AL2 2

OCR4AL3 - Timer/Counter4 Outbut Compare Register Low Byte Bit 3

#define OCR4AL3 3

OCR4AL4 - Timer/Counter4 Outbut Compare Register Low Byte Bit 4

#define OCR4AL4 4

OCR4AL5 - Timer/Counter4 Outbut Compare Register Low Byte Bit 5

#define OCR4AL5 5

OCR4AL6 - Timer/Counter4 Outbut Compare Register Low Byte Bit 6

#define OCR4AL6 6

OCR4AL7 - Timer/Counter4 Outbut Compare Register Low Byte Bit 7

#define OCR4AL7 7

OCR4BH - Timer/Counter4 Output Compare Register B High Byte

sfrb OCR4BH = $AB;

OCR4BH0 - Timer/Counter4 Output Compare Register High Byte bit 0

#define OCR4BH0 0

OCR4BH1 - Timer/Counter4 Output Compare Register High Byte bit 1

#define OCR4BH1 1

OCR4BH2 - Timer/Counter4 Output Compare Register High Byte bit 2

#define OCR4BH2 2

OCR4BH3 - Timer/Counter4 Output Compare Register High Byte bit 3

#define OCR4BH3 3

OCR4BH4 - Timer/Counter4 Output Compare Register High Byte bit 4

#define OCR4BH4 4

OCR4BH5 - Timer/Counter4 Output Compare Register High Byte bit 5

#define OCR4BH5 5

OCR4BH6 - Timer/Counter4 Output Compare Register High Byte bit 6

#define OCR4BH6 6

OCR4BH7 - Timer/Counter4 Output Compare Register High Byte bit 7

#define OCR4BH7 7

OCR4BL - Timer/Counter4 Output Compare Register B Low Byte

sfrb OCR4BL = $AA;

OCR4BL0 - Timer/Counter4 Output Compare Register Low Byte bit 0

#define OCR4BL0 0

OCR4BL1 - Timer/Counter4 Output Compare Register Low Byte bit 1

#define OCR4BL1 1

OCR4BL2 - Timer/Counter4 Output Compare Register Low Byte bit 2

#define OCR4BL2 2

OCR4BL3 - Timer/Counter4 Output Compare Register Low Byte bit 3

#define OCR4BL3 3

OCR4BL4 - Timer/Counter4 Output Compare Register Low Byte bit 4

#define OCR4BL4 4

OCR4BL5 - Timer/Counter4 Output Compare Register Low Byte bit 5

#define OCR4BL5 5

OCR4BL6 - Timer/Counter4 Output Compare Register Low Byte bit 6

#define OCR4BL6 6

OCR4BL7 - Timer/Counter4 Output Compare Register Low Byte bit 7

#define OCR4BL7 7

OCR4CH - Timer/Counter4 Output Compare Register B High Byte

sfrb OCR4CH = $AD;

OCR4CH0 - Timer/Counter4 Output Compare Register High Byte bit 0

#define OCR4CH0 0

OCR4CH1 - Timer/Counter4 Output Compare Register High Byte bit 1

#define OCR4CH1 1

OCR4CH2 - Timer/Counter4 Output Compare Register High Byte bit 2

#define OCR4CH2 2

OCR4CH3 - Timer/Counter4 Output Compare Register High Byte bit 3

#define OCR4CH3 3

OCR4CH4 - Timer/Counter4 Output Compare Register High Byte bit 4

#define OCR4CH4 4

OCR4CH5 - Timer/Counter4 Output Compare Register High Byte bit 5

#define OCR4CH5 5

OCR4CH6 - Timer/Counter4 Output Compare Register High Byte bit 6

#define OCR4CH6 6

OCR4CH7 - Timer/Counter4 Output Compare Register High Byte bit 7

#define OCR4CH7 7

OCR4CL - Timer/Counter4 Output Compare Register B Low Byte

sfrb OCR4CL = $AC;

OCR4CL0 - Timer/Counter4 Output Compare Register Low Byte bit 0

#define OCR4CL0 0

OCR4CL1 - Timer/Counter4 Output Compare Register Low Byte bit 1

#define OCR4CL1 1

OCR4CL2 - Timer/Counter4 Output Compare Register Low Byte bit 2

#define OCR4CL2 2

OCR4CL3 - Timer/Counter4 Output Compare Register Low Byte bit 3

#define OCR4CL3 3

OCR4CL4 - Timer/Counter4 Output Compare Register Low Byte bit 4

#define OCR4CL4 4

OCR4CL5 - Timer/Counter4 Output Compare Register Low Byte bit 5

#define OCR4CL5 5

OCR4CL6 - Timer/Counter4 Output Compare Register Low Byte bit 6

#define OCR4CL6 6

OCR4CL7 - Timer/Counter4 Output Compare Register Low Byte bit 7

#define OCR4CL7 7

ICR4H - Timer/Counter4 Input Capture Register High Byte

sfrb ICR4H = $A7;

ICR4H0 - Timer/Counter4 Input Capture Register High Byte bit 0

#define ICR4H0 0

ICR4H1 - Timer/Counter4 Input Capture Register High Byte bit 1

#define ICR4H1 1

ICR4H2 - Timer/Counter4 Input Capture Register High Byte bit 2

#define ICR4H2 2

ICR4H3 - Timer/Counter4 Input Capture Register High Byte bit 3

#define ICR4H3 3

ICR4H4 - Timer/Counter4 Input Capture Register High Byte bit 4

#define ICR4H4 4

ICR4H5 - Timer/Counter4 Input Capture Register High Byte bit 5

#define ICR4H5 5

ICR4H6 - Timer/Counter4 Input Capture Register High Byte bit 6

#define ICR4H6 6

ICR4H7 - Timer/Counter4 Input Capture Register High Byte bit 7

#define ICR4H7 7

ICR4L - Timer/Counter4 Input Capture Register Low Byte

sfrb ICR4L = $A6;

ICR4L0 - Timer/Counter4 Input Capture Register Low Byte bit 0

#define ICR4L0 0

ICR4L1 - Timer/Counter4 Input Capture Register Low Byte bit 1

#define ICR4L1 1

ICR4L2 - Timer/Counter4 Input Capture Register Low Byte bit 2

#define ICR4L2 2

ICR4L3 - Timer/Counter4 Input Capture Register Low Byte bit 3

#define ICR4L3 3

ICR4L4 - Timer/Counter4 Input Capture Register Low Byte bit 4

#define ICR4L4 4

ICR4L5 - Timer/Counter4 Input Capture Register Low Byte bit 5

#define ICR4L5 5

ICR4L6 - Timer/Counter4 Input Capture Register Low Byte bit 6

#define ICR4L6 6

ICR4L7 - Timer/Counter4 Input Capture Register Low Byte bit 7

#define ICR4L7 7

TIMSK4 - Timer/Counter4 Interrupt Mask Register

sfrb TIMSK4 = $72;

TOIE4 - Timer/Counter4 Overflow Interrupt Enable

#define TOIE4 0

When the TOIE4 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter4 occurs, i.e., when the TOV4 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE4A - Timer/Counter4 Output Compare A Match Interrupt Enable

#define OCIE4A 1

When the OCIE4A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter4 occurs, i.e., when the OCF4A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE4B - Timer/Counter4 Output Compare B Match Interrupt Enable

#define OCIE4B 2

When the OCIE4B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter4 occurs, i.e., when the OCF4B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE4C - Timer/Counter4 Output Compare C Match Interrupt Enable

#define OCIE4C 3

When the OCIE4C bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter4 occurs, i.e., when the OCF4B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

ICIE4 - Timer/Counter4 Input Capture Interrupt Enable

#define ICIE4 5

When the TICIE4 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF4 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

TIFR4 - Timer/Counter4 Interrupt Flag register

sfrb TIFR4 = $19;

TOV4 - Timer/Counter4 Overflow Flag

#define TOV4 0

The TOV4 is set (one) when an overflow occurs in Timer/Counter4. TOV4 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV4 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE4 (Timer/Counter4 Overflow Interrupt Enable), and TOV4 are set (one), the Timer/Counter4 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter4 changes counting direction at $0000.

OCF4A - Output Compare Flag 4A

#define OCF4A 1

The OCF4A bit is set (one) when compare match occurs between the Timer/Counter4 and the data in OCR4A - Output Compare Register 4A. OCF4A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF4A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE4A (Timer/Counter4 Compare match InterruptA Enable), and the OCF4A are set (one), the Timer/Counter4 Compare A match Interrupt is executed.

OCF4B - Output Compare Flag 4B

#define OCF4B 2

The OCF4B bit is set (one) when compare match occurs between the Timer/Counter4 and the data in OCR4B - Output Compare Register 4B. OCF4B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF4B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE4B (Timer/Counter4 Compare match InterruptB Enable), and the OCF4B are set (one), the Timer/Counter4 Compare B match Interrupt is executed.

OCF4C - Output Compare Flag 4C

#define OCF4C 3

The OCF4C bit is set (one) when compare match occurs between the Timer/Counter4 and the data in OCR4B - Output Compare Register 4B. OCF4B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF4B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE4B (Timer/Counter4 Compare match InterruptB Enable), and the OCF4B are set (one), the Timer/Counter4 Compare B match Interrupt is executed.

ICF4 - Input Capture Flag 4

#define ICF4 5

The ICF4 bit is set (one) to flag an input capture event, indicating that the Timer/Counter4 value has been transferred to the input capture register - ICR4. ICF4 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF4 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE4 (Timer/Counter4 Input Capture Interrupt Enable), and ICF4 are set (one), the Timer/Counter4 Capture Interrupt is executed.

TIMER COUNTER 3

TCCR3A - Timer/Counter3 Control Register A

sfrb TCCR3A = $90;

WGM30 - Waveform Generation Mode

#define WGM30 0

Combined with the WGM33:2 bits found in the TCCR3B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.

WGM31 - Waveform Generation Mode

#define WGM31 1

COM3C0 - Compare Output Mode 3C, bit 0

#define COM3C0 2

The COM3C1 and COM3C0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.

COM3C1 - Compare Output Mode 3C, bit 1

#define COM3C1 3

COM3B0 - Compare Output Mode 3B, bit 0

#define COM3B0 4

The COM3B1 and COM3B0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.

COM3B1 - Compare Output Mode 3B, bit 1

#define COM3B1 5

COM3A0 - Compare Output Mode 3A, bit 0

#define COM3A0 6

The COM3A1 and COM3A0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.

COM3A1 - Compare Output Mode 1A, bit 1

#define COM3A1 7

TCCR3B - Timer/Counter3 Control Register B

sfrb TCCR3B = $91;

CS30 - Prescaler source of Timer/Counter 3

#define CS30 0

Select Prescaling Clock Source of Timer/Counter3. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.

CS31 - Prescaler source of Timer/Counter 3

#define CS31 1

Select Prescaling Clock Source of Timer/Counter3. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T3, falling edge. (1:1:1) = External Pin 1, rising edge.

CS32 - Prescaler source of Timer/Counter 3

#define CS32 2

WGM32 - Waveform Generation Mode

#define WGM32 3

WGM33 - Waveform Generation Mode

#define WGM33 4

ICES3 - Input Capture 3 Edge Select

#define ICES3 6

While the ICES3 bit is cleared (zero), the Timer/Counter3 contents are transferred to the Input Capture Register - ICR3 - on the falling edge of the input capture pin - ICP. While the ICES3 bit is set (one), the Timer/Counter3 contents are transferred to the Input Capture Register - ICR3 - on the rising edge of the input capture pin - ICP.

ICNC3 - Input Capture 3 Noise Canceler

#define ICNC3 7

When the ICNC3 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC3 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES3 bit. The actual sampling frequency is XTAL clock frequency.

TCCR3C - Timer/Counter 3 Control Register C

sfrb TCCR3C = $92;

FOC3C - Force Output Compare 3C

#define FOC3C 5

Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM3B1 and COM3B0.If the COM3B1 and COM3B0 bits are written in the same cycle as FOC3B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM3B1 and COM3B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC3B bit to have effect on the pin. The FOC3B bit will always be read as zero. The setting of the FOC3B bit has no effect in PWM mo

FOC3B - Force Output Compare 3B

#define FOC3B 6

FOC3A - Force Output Compare 3A

#define FOC3A 7

Writing a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM3A1 and COM3A0.If the COM3A1 and COM3A0 bits are written in the same cycle as FOC3A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM3A1 and COM3A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC3 in TCCR3B is set. The corresponding I/O pin must be set as an output pin for the FOC3A bit to have effect on the pin. The FOC3A bit will always be read as zero. The setting of the FOC3A bit has no effect in PWM m

TCNT3H - Timer/Counter3 High Byte

sfrb TCNT3H = $95;

TCNT3H0 - Timer/Counter3 High Byte bit 0

#define TCNT3H0 0

TCNT3H1 - Timer/Counter3 High Byte bit 1

#define TCNT3H1 1

TCNT3H2 - Timer/Counter3 High Byte bit 2

#define TCNT3H2 2

TCNT3H3 - Timer/Counter3 High Byte bit 3

#define TCNT3H3 3

TCNT3H4 - Timer/Counter3 High Byte bit 4

#define TCNT3H4 4

TCNT3H5 - Timer/Counter3 High Byte bit 5

#define TCNT3H5 5

TCNT3H6 - Timer/Counter3 High Byte bit 6

#define TCNT3H6 6

TCNT3H7 - Timer/Counter3 High Byte bit 7

#define TCNT3H7 7

TCNT3L - Timer/Counter3 Low Byte

sfrb TCNT3L = $94;

TCNT3L0 - Timer/Counter3 Low Byte bit 0

#define TCNT3L0 0

TCNT3L1 - Timer/Counter3 Low Byte bit 1

#define TCNT3L1 1

TCNT3L2 - Timer/Counter3 Low Byte bit 2

#define TCNT3L2 2

TCNT3L3 - Timer/Counter3 Low Byte bit 3

#define TCNT3L3 3

TCNT3L4 - Timer/Counter3 Low Byte bit 4

#define TCNT3L4 4

TCNT3L5 - Timer/Counter3 Low Byte bit 5

#define TCNT3L5 5

TCNT3L6 - Timer/Counter3 Low Byte bit 6

#define TCNT3L6 6

TCNT3L7 - Timer/Counter3 Low Byte bit 7

#define TCNT3L7 7

OCR3AH - Timer/Counter3 Outbut Compare Register A High Byte

sfrb OCR3AH = $99;

OCR3AH0 - Timer/Counter3 Outbut Compare Register High Byte bit 0

#define OCR3AH0 0

OCR3AH1 - Timer/Counter3 Outbut Compare Register High Byte bit 1

#define OCR3AH1 1

OCR3AH2 - Timer/Counter3 Outbut Compare Register High Byte bit 2

#define OCR3AH2 2

OCR3AH3 - Timer/Counter3 Outbut Compare Register High Byte bit 3

#define OCR3AH3 3

OCR3AH4 - Timer/Counter3 Outbut Compare Register High Byte bit 4

#define OCR3AH4 4

OCR3AH5 - Timer/Counter3 Outbut Compare Register High Byte bit 5

#define OCR3AH5 5

OCR3AH6 - Timer/Counter3 Outbut Compare Register High Byte bit 6

#define OCR3AH6 6

OCR3AH7 - Timer/Counter3 Outbut Compare Register High Byte bit 7

#define OCR3AH7 7

OCR3AL - Timer/Counter3 Outbut Compare Register A Low Byte

sfrb OCR3AL = $98;

OCR3AL0 - Timer/Counter3 Outbut Compare Register Low Byte Bit 0

#define OCR3AL0 0

OCR3AL1 - Timer/Counter3 Outbut Compare Register Low Byte Bit 1

#define OCR3AL1 1

OCR3AL2 - Timer/Counter3 Outbut Compare Register Low Byte Bit 2

#define OCR3AL2 2

OCR3AL3 - Timer/Counter3 Outbut Compare Register Low Byte Bit 3

#define OCR3AL3 3

OCR3AL4 - Timer/Counter3 Outbut Compare Register Low Byte Bit 4

#define OCR3AL4 4

OCR3AL5 - Timer/Counter3 Outbut Compare Register Low Byte Bit 5

#define OCR3AL5 5

OCR3AL6 - Timer/Counter3 Outbut Compare Register Low Byte Bit 6

#define OCR3AL6 6

OCR3AL7 - Timer/Counter3 Outbut Compare Register Low Byte Bit 7

#define OCR3AL7 7

OCR3BH - Timer/Counter3 Output Compare Register B High Byte

sfrb OCR3BH = $9B;

OCR3BH0 - Timer/Counter3 Output Compare Register High Byte bit 0

#define OCR3BH0 0

OCR3BH1 - Timer/Counter3 Output Compare Register High Byte bit 1

#define OCR3BH1 1

OCR3BH2 - Timer/Counter3 Output Compare Register High Byte bit 2

#define OCR3BH2 2

OCR3BH3 - Timer/Counter3 Output Compare Register High Byte bit 3

#define OCR3BH3 3

OCR3BH4 - Timer/Counter3 Output Compare Register High Byte bit 4

#define OCR3BH4 4

OCR3BH5 - Timer/Counter3 Output Compare Register High Byte bit 5

#define OCR3BH5 5

OCR3BH6 - Timer/Counter3 Output Compare Register High Byte bit 6

#define OCR3BH6 6

OCR3BH7 - Timer/Counter3 Output Compare Register High Byte bit 7

#define OCR3BH7 7

OCR3BL - Timer/Counter3 Output Compare Register B Low Byte

sfrb OCR3BL = $9A;

OCR3BL0 - Timer/Counter3 Output Compare Register Low Byte bit 0

#define OCR3BL0 0

OCR3BL1 - Timer/Counter3 Output Compare Register Low Byte bit 1

#define OCR3BL1 1

OCR3BL2 - Timer/Counter3 Output Compare Register Low Byte bit 2

#define OCR3BL2 2

OCR3BL3 - Timer/Counter3 Output Compare Register Low Byte bit 3

#define OCR3BL3 3

OCR3BL4 - Timer/Counter3 Output Compare Register Low Byte bit 4

#define OCR3BL4 4

OCR3BL5 - Timer/Counter3 Output Compare Register Low Byte bit 5

#define OCR3BL5 5

OCR3BL6 - Timer/Counter3 Output Compare Register Low Byte bit 6

#define OCR3BL6 6

OCR3BL7 - Timer/Counter3 Output Compare Register Low Byte bit 7

#define OCR3BL7 7

OCR3CH - Timer/Counter3 Output Compare Register B High Byte

sfrb OCR3CH = $9D;

OCR3CH0 - Timer/Counter3 Output Compare Register High Byte bit 0

#define OCR3CH0 0

OCR3CH1 - Timer/Counter3 Output Compare Register High Byte bit 1

#define OCR3CH1 1

OCR3CH2 - Timer/Counter3 Output Compare Register High Byte bit 2

#define OCR3CH2 2

OCR3CH3 - Timer/Counter3 Output Compare Register High Byte bit 3

#define OCR3CH3 3

OCR3CH4 - Timer/Counter3 Output Compare Register High Byte bit 4

#define OCR3CH4 4

OCR3CH5 - Timer/Counter3 Output Compare Register High Byte bit 5

#define OCR3CH5 5

OCR3CH6 - Timer/Counter3 Output Compare Register High Byte bit 6

#define OCR3CH6 6

OCR3CH7 - Timer/Counter3 Output Compare Register High Byte bit 7

#define OCR3CH7 7

OCR3CL - Timer/Counter3 Output Compare Register B Low Byte

sfrb OCR3CL = $9C;

OCR3CL0 - Timer/Counter3 Output Compare Register Low Byte bit 0

#define OCR3CL0 0

OCR3CL1 - Timer/Counter3 Output Compare Register Low Byte bit 1

#define OCR3CL1 1

OCR3CL2 - Timer/Counter3 Output Compare Register Low Byte bit 2

#define OCR3CL2 2

OCR3CL3 - Timer/Counter3 Output Compare Register Low Byte bit 3

#define OCR3CL3 3

OCR3CL4 - Timer/Counter3 Output Compare Register Low Byte bit 4

#define OCR3CL4 4

OCR3CL5 - Timer/Counter3 Output Compare Register Low Byte bit 5

#define OCR3CL5 5

OCR3CL6 - Timer/Counter3 Output Compare Register Low Byte bit 6

#define OCR3CL6 6

OCR3CL7 - Timer/Counter3 Output Compare Register Low Byte bit 7

#define OCR3CL7 7

ICR3H - Timer/Counter3 Input Capture Register High Byte

sfrb ICR3H = $97;

ICR3H0 - Timer/Counter3 Input Capture Register High Byte bit 0

#define ICR3H0 0

ICR3H1 - Timer/Counter3 Input Capture Register High Byte bit 1

#define ICR3H1 1

ICR3H2 - Timer/Counter3 Input Capture Register High Byte bit 2

#define ICR3H2 2

ICR3H3 - Timer/Counter3 Input Capture Register High Byte bit 3

#define ICR3H3 3

ICR3H4 - Timer/Counter3 Input Capture Register High Byte bit 4

#define ICR3H4 4

ICR3H5 - Timer/Counter3 Input Capture Register High Byte bit 5

#define ICR3H5 5

ICR3H6 - Timer/Counter3 Input Capture Register High Byte bit 6

#define ICR3H6 6

ICR3H7 - Timer/Counter3 Input Capture Register High Byte bit 7

#define ICR3H7 7

ICR3L - Timer/Counter3 Input Capture Register Low Byte

sfrb ICR3L = $96;

ICR3L0 - Timer/Counter3 Input Capture Register Low Byte bit 0

#define ICR3L0 0

ICR3L1 - Timer/Counter3 Input Capture Register Low Byte bit 1

#define ICR3L1 1

ICR3L2 - Timer/Counter3 Input Capture Register Low Byte bit 2

#define ICR3L2 2

ICR3L3 - Timer/Counter3 Input Capture Register Low Byte bit 3

#define ICR3L3 3

ICR3L4 - Timer/Counter3 Input Capture Register Low Byte bit 4

#define ICR3L4 4

ICR3L5 - Timer/Counter3 Input Capture Register Low Byte bit 5

#define ICR3L5 5

ICR3L6 - Timer/Counter3 Input Capture Register Low Byte bit 6

#define ICR3L6 6

ICR3L7 - Timer/Counter3 Input Capture Register Low Byte bit 7

#define ICR3L7 7

TIMSK3 - Timer/Counter3 Interrupt Mask Register

sfrb TIMSK3 = $71;

TOIE3 - Timer/Counter3 Overflow Interrupt Enable

#define TOIE3 0

When the TOIE3 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter3 occurs, i.e., when the TOV3 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE3A - Timer/Counter3 Output Compare A Match Interrupt Enable

#define OCIE3A 1

When the OCIE3A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter3 occurs, i.e., when the OCF3A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE3B - Timer/Counter3 Output Compare B Match Interrupt Enable

#define OCIE3B 2

When the OCIE3B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter3 occurs, i.e., when the OCF3B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE3C - Timer/Counter3 Output Compare C Match Interrupt Enable

#define OCIE3C 3

When the OCIE3C bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter3 occurs, i.e., when the OCF3B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

ICIE3 - Timer/Counter3 Input Capture Interrupt Enable

#define ICIE3 5

When the TICIE3 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF3 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

TIFR3 - Timer/Counter3 Interrupt Flag register

sfrb TIFR3 = $18;

TOV3 - Timer/Counter3 Overflow Flag

#define TOV3 0

The TOV3 is set (one) when an overflow occurs in Timer/Counter3. TOV3 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV3 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE3 (Timer/Counter3 Overflow Interrupt Enable), and TOV3 are set (one), the Timer/Counter3 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter3 changes counting direction at $0000.

OCF3A - Output Compare Flag 3A

#define OCF3A 1

The OCF3A bit is set (one) when compare match occurs between the Timer/Counter3 and the data in OCR3A - Output Compare Register 3A. OCF3A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF3A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE3A (Timer/Counter3 Compare match InterruptA Enable), and the OCF3A are set (one), the Timer/Counter3 Compare A match Interrupt is executed.

OCF3B - Output Compare Flag 3B

#define OCF3B 2

The OCF3B bit is set (one) when compare match occurs between the Timer/Counter3 and the data in OCR3B - Output Compare Register 3B. OCF3B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF3B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE3B (Timer/Counter3 Compare match InterruptB Enable), and the OCF3B are set (one), the Timer/Counter3 Compare B match Interrupt is executed.

OCF3C - Output Compare Flag 3C

#define OCF3C 3

The OCF3C bit is set (one) when compare match occurs between the Timer/Counter3 and the data in OCR3B - Output Compare Register 3B. OCF3B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF3B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE3B (Timer/Counter3 Compare match InterruptB Enable), and the OCF3B are set (one), the Timer/Counter3 Compare B match Interrupt is executed.

ICF3 - Input Capture Flag 3

#define ICF3 5

The ICF3 bit is set (one) to flag an input capture event, indicating that the Timer/Counter3 value has been transferred to the input capture register - ICR3. ICF3 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF3 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE3 (Timer/Counter3 Input Capture Interrupt Enable), and ICF3 are set (one), the Timer/Counter3 Capture Interrupt is executed.

TIMER COUNTER 1

TCCR1A - Timer/Counter1 Control Register A

sfrb TCCR1A = $80;

WGM10 - Waveform Generation Mode

#define WGM10 0

Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.

WGM11 - Waveform Generation Mode

#define WGM11 1

COM1C0 - Compare Output Mode 1C, bit 0

#define COM1C0 2

The COM1C1 and COM1C0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.

COM1C1 - Compare Output Mode 1C, bit 1

#define COM1C1 3

COM1B0 - Compare Output Mode 1B, bit 0

#define COM1B0 4

The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.

COM1B1 - Compare Output Mode 1B, bit 1

#define COM1B1 5

COM1A0 - Compare Output Mode 1A, bit 0

#define COM1A0 6

The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.

COM1A1 - Compare Output Mode 1A, bit 1

#define COM1A1 7

TCCR1B - Timer/Counter1 Control Register B

sfrb TCCR1B = $81;

CS10 - Prescaler source of Timer/Counter 1

#define CS10 0

Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.

CS11 - Prescaler source of Timer/Counter 1

#define CS11 1

CS12 - Prescaler source of Timer/Counter 1

#define CS12 2

WGM12 - Waveform Generation Mode

#define WGM12 3

WGM13 - Waveform Generation Mode

#define WGM13 4

ICES1 - Input Capture 1 Edge Select

#define ICES1 6

While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.

ICNC1 - Input Capture 1 Noise Canceler

#define ICNC1 7

When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.

TCCR1C - Timer/Counter 1 Control Register C

sfrb TCCR1C = $82;

FOC1C - Force Output Compare 1C

#define FOC1C 5

Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM1B1 and COM1B0.If the COM1B1 and COM1B0 bits are written in the same cycle as FOC1B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1B1 and COM1B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC1B bit to have effect on the pin. The FOC1B bit will always be read as zero. The setting of the FOC1B bit has no effect in PWM mo

FOC1B - Force Output Compare 1B

#define FOC1B 6

FOC1A - Force Output Compare 1A

#define FOC1A 7

Writing a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM1A1 and COM1A0.If the COM1A1 and COM1A0 bits are written in the same cycle as FOC1A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1A1 and COM1A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC1 in TCCR1B is set. The corresponding I/O pin must be set as an output pin for the FOC1A bit to have effect on the pin. The FOC1A bit will always be read as zero. The setting of the FOC1A bit has no effect in PWM m

TCNT1H - Timer/Counter1 High Byte

sfrb TCNT1H = $85;

TCNT1H0 - Timer/Counter1 High Byte bit 0

#define TCNT1H0 0

TCNT1H1 - Timer/Counter1 High Byte bit 1

#define TCNT1H1 1

TCNT1H2 - Timer/Counter1 High Byte bit 2

#define TCNT1H2 2

TCNT1H3 - Timer/Counter1 High Byte bit 3

#define TCNT1H3 3

TCNT1H4 - Timer/Counter1 High Byte bit 4

#define TCNT1H4 4

TCNT1H5 - Timer/Counter1 High Byte bit 5

#define TCNT1H5 5

TCNT1H6 - Timer/Counter1 High Byte bit 6

#define TCNT1H6 6

TCNT1H7 - Timer/Counter1 High Byte bit 7

#define TCNT1H7 7

TCNT1L - Timer/Counter1 Low Byte

sfrb TCNT1L = $84;

TCNT1L0 - Timer/Counter1 Low Byte bit 0

#define TCNT1L0 0

TCNT1L1 - Timer/Counter1 Low Byte bit 1

#define TCNT1L1 1

TCNT1L2 - Timer/Counter1 Low Byte bit 2

#define TCNT1L2 2

TCNT1L3 - Timer/Counter1 Low Byte bit 3

#define TCNT1L3 3

TCNT1L4 - Timer/Counter1 Low Byte bit 4

#define TCNT1L4 4

TCNT1L5 - Timer/Counter1 Low Byte bit 5

#define TCNT1L5 5

TCNT1L6 - Timer/Counter1 Low Byte bit 6

#define TCNT1L6 6

TCNT1L7 - Timer/Counter1 Low Byte bit 7

#define TCNT1L7 7

OCR1AH - Timer/Counter1 Outbut Compare Register A High Byte

sfrb OCR1AH = $89;

OCR1AH0 - Timer/Counter1 Outbut Compare Register High Byte bit 0

#define OCR1AH0 0

OCR1AH1 - Timer/Counter1 Outbut Compare Register High Byte bit 1

#define OCR1AH1 1

OCR1AH2 - Timer/Counter1 Outbut Compare Register High Byte bit 2

#define OCR1AH2 2

OCR1AH3 - Timer/Counter1 Outbut Compare Register High Byte bit 3

#define OCR1AH3 3

OCR1AH4 - Timer/Counter1 Outbut Compare Register High Byte bit 4

#define OCR1AH4 4

OCR1AH5 - Timer/Counter1 Outbut Compare Register High Byte bit 5

#define OCR1AH5 5

OCR1AH6 - Timer/Counter1 Outbut Compare Register High Byte bit 6

#define OCR1AH6 6

OCR1AH7 - Timer/Counter1 Outbut Compare Register High Byte bit 7

#define OCR1AH7 7

OCR1AL - Timer/Counter1 Outbut Compare Register A Low Byte

sfrb OCR1AL = $88;

OCR1AL0 - Timer/Counter1 Outbut Compare Register Low Byte Bit 0

#define OCR1AL0 0

OCR1AL1 - Timer/Counter1 Outbut Compare Register Low Byte Bit 1

#define OCR1AL1 1

OCR1AL2 - Timer/Counter1 Outbut Compare Register Low Byte Bit 2

#define OCR1AL2 2

OCR1AL3 - Timer/Counter1 Outbut Compare Register Low Byte Bit 3

#define OCR1AL3 3

OCR1AL4 - Timer/Counter1 Outbut Compare Register Low Byte Bit 4

#define OCR1AL4 4

OCR1AL5 - Timer/Counter1 Outbut Compare Register Low Byte Bit 5

#define OCR1AL5 5

OCR1AL6 - Timer/Counter1 Outbut Compare Register Low Byte Bit 6

#define OCR1AL6 6

OCR1AL7 - Timer/Counter1 Outbut Compare Register Low Byte Bit 7

#define OCR1AL7 7

OCR1BH - Timer/Counter1 Output Compare Register B High Byte

sfrb OCR1BH = $8B;

OCR1BH0 - Timer/Counter1 Output Compare Register High Byte bit 0

#define OCR1BH0 0

OCR1BH1 - Timer/Counter1 Output Compare Register High Byte bit 1

#define OCR1BH1 1

OCR1BH2 - Timer/Counter1 Output Compare Register High Byte bit 2

#define OCR1BH2 2

OCR1BH3 - Timer/Counter1 Output Compare Register High Byte bit 3

#define OCR1BH3 3

OCR1BH4 - Timer/Counter1 Output Compare Register High Byte bit 4

#define OCR1BH4 4

OCR1BH5 - Timer/Counter1 Output Compare Register High Byte bit 5

#define OCR1BH5 5

OCR1BH6 - Timer/Counter1 Output Compare Register High Byte bit 6

#define OCR1BH6 6

OCR1BH7 - Timer/Counter1 Output Compare Register High Byte bit 7

#define OCR1BH7 7

OCR1BL - Timer/Counter1 Output Compare Register B Low Byte

sfrb OCR1BL = $8A;

OCR1BL0 - Timer/Counter1 Output Compare Register Low Byte bit 0

#define OCR1BL0 0

OCR1BL1 - Timer/Counter1 Output Compare Register Low Byte bit 1

#define OCR1BL1 1

OCR1BL2 - Timer/Counter1 Output Compare Register Low Byte bit 2

#define OCR1BL2 2

OCR1BL3 - Timer/Counter1 Output Compare Register Low Byte bit 3

#define OCR1BL3 3

OCR1BL4 - Timer/Counter1 Output Compare Register Low Byte bit 4

#define OCR1BL4 4

OCR1BL5 - Timer/Counter1 Output Compare Register Low Byte bit 5

#define OCR1BL5 5

OCR1BL6 - Timer/Counter1 Output Compare Register Low Byte bit 6

#define OCR1BL6 6

OCR1BL7 - Timer/Counter1 Output Compare Register Low Byte bit 7

#define OCR1BL7 7

OCR1CH - Timer/Counter1 Output Compare Register B High Byte

sfrb OCR1CH = $8D;

OCR1CH0 - Timer/Counter1 Output Compare Register High Byte bit 0

#define OCR1CH0 0

OCR1CH1 - Timer/Counter1 Output Compare Register High Byte bit 1

#define OCR1CH1 1

OCR1CH2 - Timer/Counter1 Output Compare Register High Byte bit 2

#define OCR1CH2 2

OCR1CH3 - Timer/Counter1 Output Compare Register High Byte bit 3

#define OCR1CH3 3

OCR1CH4 - Timer/Counter1 Output Compare Register High Byte bit 4

#define OCR1CH4 4

OCR1CH5 - Timer/Counter1 Output Compare Register High Byte bit 5

#define OCR1CH5 5

OCR1CH6 - Timer/Counter1 Output Compare Register High Byte bit 6

#define OCR1CH6 6

OCR1CH7 - Timer/Counter1 Output Compare Register High Byte bit 7

#define OCR1CH7 7

OCR1CL - Timer/Counter1 Output Compare Register B Low Byte

sfrb OCR1CL = $8C;

OCR1CL0 - Timer/Counter1 Output Compare Register Low Byte bit 0

#define OCR1CL0 0

OCR1CL1 - Timer/Counter1 Output Compare Register Low Byte bit 1

#define OCR1CL1 1

OCR1CL2 - Timer/Counter1 Output Compare Register Low Byte bit 2

#define OCR1CL2 2

OCR1CL3 - Timer/Counter1 Output Compare Register Low Byte bit 3

#define OCR1CL3 3

OCR1CL4 - Timer/Counter1 Output Compare Register Low Byte bit 4

#define OCR1CL4 4

OCR1CL5 - Timer/Counter1 Output Compare Register Low Byte bit 5

#define OCR1CL5 5

OCR1CL6 - Timer/Counter1 Output Compare Register Low Byte bit 6

#define OCR1CL6 6

OCR1CL7 - Timer/Counter1 Output Compare Register Low Byte bit 7

#define OCR1CL7 7

ICR1H - Timer/Counter1 Input Capture Register High Byte

sfrb ICR1H = $87;

ICR1H0 - Timer/Counter1 Input Capture Register High Byte bit 0

#define ICR1H0 0

ICR1H1 - Timer/Counter1 Input Capture Register High Byte bit 1

#define ICR1H1 1

ICR1H2 - Timer/Counter1 Input Capture Register High Byte bit 2

#define ICR1H2 2

ICR1H3 - Timer/Counter1 Input Capture Register High Byte bit 3

#define ICR1H3 3

ICR1H4 - Timer/Counter1 Input Capture Register High Byte bit 4

#define ICR1H4 4

ICR1H5 - Timer/Counter1 Input Capture Register High Byte bit 5

#define ICR1H5 5

ICR1H6 - Timer/Counter1 Input Capture Register High Byte bit 6

#define ICR1H6 6

ICR1H7 - Timer/Counter1 Input Capture Register High Byte bit 7

#define ICR1H7 7

ICR1L - Timer/Counter1 Input Capture Register Low Byte

sfrb ICR1L = $86;

ICR1L0 - Timer/Counter1 Input Capture Register Low Byte bit 0

#define ICR1L0 0

ICR1L1 - Timer/Counter1 Input Capture Register Low Byte bit 1

#define ICR1L1 1

ICR1L2 - Timer/Counter1 Input Capture Register Low Byte bit 2

#define ICR1L2 2

ICR1L3 - Timer/Counter1 Input Capture Register Low Byte bit 3

#define ICR1L3 3

ICR1L4 - Timer/Counter1 Input Capture Register Low Byte bit 4

#define ICR1L4 4

ICR1L5 - Timer/Counter1 Input Capture Register Low Byte bit 5

#define ICR1L5 5

ICR1L6 - Timer/Counter1 Input Capture Register Low Byte bit 6

#define ICR1L6 6

ICR1L7 - Timer/Counter1 Input Capture Register Low Byte bit 7

#define ICR1L7 7

TIMSK1 - Timer/Counter1 Interrupt Mask Register

sfrb TIMSK1 = $6F;

TOIE1 - Timer/Counter1 Overflow Interrupt Enable

#define TOIE1 0

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE1A - Timer/Counter1 Output Compare A Match Interrupt Enable

#define OCIE1A 1

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE1B - Timer/Counter1 Output Compare B Match Interrupt Enable

#define OCIE1B 2

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE1C - Timer/Counter1 Output Compare C Match Interrupt Enable

#define OCIE1C 3

When the OCIE1C bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

ICIE1 - Timer/Counter1 Input Capture Interrupt Enable

#define ICIE1 5

When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

TIFR1 - Timer/Counter1 Interrupt Flag register

sfrb TIFR1 = $16;

TOV1 - Timer/Counter1 Overflow Flag

#define TOV1 0

The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.

OCF1A - Output Compare Flag 1A

#define OCF1A 1

The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed.

OCF1B - Output Compare Flag 1B

#define OCF1B 2

The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.

OCF1C - Output Compare Flag 1C

#define OCF1C 3

The OCF1C bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.

ICF1 - Input Capture Flag 1

#define ICF1 5

The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.

JTAG

JTAG Features: JTAG (IEEE std. 1149.1 compliant) Interface. Boundary-Scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard. Debugger Access to: ? All Internal Peripheral Units ? Internal and External RAM ? The Internal Register File ?Program Counter ? EEPROM and Flash Memories. Extensive On-Chip Debug Support for Break Conditions, Including: ?AVR Break Instruction ? Break on Change of Program Memory Flow ?Single Step Break ?Program Memory Breakpoints on Single Address or Address Range ? Data Memory Breakpoints on Single Address or Address Range. Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface. On-Chip Debugging Supported by AVR Stu

OCDR - On-Chip Debug Related Register in I/O Memory

sfrb OCDR = $31;

OCDR0 - On-Chip Debug Register Bit 0

#define OCDR0 0

OCDR1 - On-Chip Debug Register Bit 1

#define OCDR1 1

OCDR2 - On-Chip Debug Register Bit 2

#define OCDR2 2

OCDR3 - On-Chip Debug Register Bit 3

#define OCDR3 3

OCDR4 - On-Chip Debug Register Bit 4

#define OCDR4 4

OCDR5 - On-Chip Debug Register Bit 5

#define OCDR5 5

OCDR6 - On-Chip Debug Register Bit 6

#define OCDR6 6

OCDR7 - On-Chip Debug Register Bit 7

#define OCDR7 7

MCUCR - MCU Control Register

sfrb MCUCR = $35;

JTD - JTAG Interface Disable

#define JTD 7

When this bit is written to zero, the JTAG interface is enabled if the JTAGEN fuse is programmed. If this bit is written to one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface, a timed sequence must be followed: The application software must write this to the desired value twice within four cycles to change the bit.

MCUSR - MCU Status Register

sfrb MCUSR = $34;

JTRF - JTAG Reset Flag

#define JTRF 4

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET.This bit is reset by a Power-on reset,or by writing a logic zero to the flag.

EXTERNAL INTERRUPT

The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in ?Clock Systems and their Distribution? on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 �s (nominal) at 5.0V and 25�C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in ?Clock Systems and their Distribution? on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt

EICRA - External Interrupt Control Register A

sfrb EICRA = $69;

ISC00 - External Interrupt Sense Control Bit

#define ISC00 0

ISC01 - External Interrupt Sense Control Bit

#define ISC01 1

ISC10 - External Interrupt Sense Control Bit

#define ISC10 2

ISC11 - External Interrupt Sense Control Bit

#define ISC11 3

ISC20 - External Interrupt Sense Control Bit

#define ISC20 4

ISC21 - External Interrupt Sense Control Bit

#define ISC21 5

ISC30 - External Interrupt Sense Control Bit

#define ISC30 6

ISC31 - External Interrupt Sense Control Bit

#define ISC31 7

EICRB - External Interrupt Control Register B

sfrb EICRB = $6A;

ISC40 - External Interrupt 7-4 Sense Control Bit

#define ISC40 0

ISC41 - External Interrupt 7-4 Sense Control Bit

#define ISC41 1

ISC50 - External Interrupt 7-4 Sense Control Bit

#define ISC50 2

ISC51 - External Interrupt 7-4 Sense Control Bit

#define ISC51 3

ISC60 - External Interrupt 7-4 Sense Control Bit

#define ISC60 4

ISC61 - External Interrupt 7-4 Sense Control Bit

#define ISC61 5

ISC70 - External Interrupt 7-4 Sense Control Bit

#define ISC70 6

ISC71 - External Interrupt 7-4 Sense Control Bit

#define ISC71 7

EIMSK - External Interrupt Mask Register

sfrb EIMSK = $1D;

INT0 - External Interrupt Request 0 Enable

#define INT0 0

INT1 - External Interrupt Request 1 Enable

#define INT1 1

INT2 - External Interrupt Request 2 Enable

#define INT2 2

INT3 - External Interrupt Request 3 Enable

#define INT3 3

INT4 - External Interrupt Request 4 Enable

#define INT4 4

INT5 - External Interrupt Request 5 Enable

#define INT5 5

INT6 - External Interrupt Request 6 Enable

#define INT6 6

INT7 - External Interrupt Request 7 Enable

#define INT7 7

EIFR - External Interrupt Flag Register

sfrb EIFR = $1C;

INTF0 - External Interrupt Flag 0

#define INTF0 0

INTF1 - External Interrupt Flag 1

#define INTF1 1

INTF2 - External Interrupt Flag 2

#define INTF2 2

INTF3 - External Interrupt Flag 3

#define INTF3 3

INTF4 - External Interrupt Flag 4

#define INTF4 4

INTF5 - External Interrupt Flag 5

#define INTF5 5

INTF6 - External Interrupt Flag 6

#define INTF6 6

INTF7 - External Interrupt Flag 7

#define INTF7 7

PCMSK2 - Pin Change Mask Register 2

sfrb PCMSK2 = $6D;

PCINT16 - Pin Change Enable Mask 16

#define PCINT16 0

PCINT17 - Pin Change Enable Mask 17

#define PCINT17 1

PCINT18 - Pin Change Enable Mask 18

#define PCINT18 2

PCINT19 - Pin Change Enable Mask 19

#define PCINT19 3

PCINT20 - Pin Change Enable Mask 20

#define PCINT20 4

PCINT21 - Pin Change Enable Mask 21

#define PCINT21 5

PCINT22 - Pin Change Enable Mask 22

#define PCINT22 6

PCINT23 - Pin Change Enable Mask 23

#define PCINT23 7

PCMSK1 - Pin Change Mask Register 1

sfrb PCMSK1 = $6C;

PCINT8 - Pin Change Enable Mask 8

#define PCINT8 0

PCINT9 - Pin Change Enable Mask 9

#define PCINT9 1

PCINT10 - Pin Change Enable Mask 10

#define PCINT10 2

PCINT11 - Pin Change Enable Mask 11

#define PCINT11 3

PCINT12 - Pin Change Enable Mask 12

#define PCINT12 4

PCINT13 - Pin Change Enable Mask 13

#define PCINT13 5

PCINT14 - Pin Change Enable Mask 14

#define PCINT14 6

PCINT15 - Pin Change Enable Mask 15

#define PCINT15 7

PCMSK0 - Pin Change Mask Register 0

sfrb PCMSK0 = $6B;

PCINT0 - Pin Change Enable Mask 0

#define PCINT0 0

PCINT1 - Pin Change Enable Mask 1

#define PCINT1 1

PCINT2 - Pin Change Enable Mask 2

#define PCINT2 2

PCINT3 - Pin Change Enable Mask 3

#define PCINT3 3

PCINT4 - Pin Change Enable Mask 4

#define PCINT4 4

PCINT5 - Pin Change Enable Mask 5

#define PCINT5 5

PCINT6 - Pin Change Enable Mask 6

#define PCINT6 6

PCINT7 - Pin Change Enable Mask 7

#define PCINT7 7

PCIFR - Pin Change Interrupt Flag Register

sfrb PCIFR = $1B;

PCIF0 - Pin Change Interrupt Flag 0

#define PCIF0 0

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

PCIF1 - Pin Change Interrupt Flag 1

#define PCIF1 1

When a logic change on any PCINT14..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

PCIF2 - Pin Change Interrupt Flag 2

#define PCIF2 2

When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

PCICR - Pin Change Interrupt Control Register

sfrb PCICR = $68;

PCIE0 - Pin Change Interrupt Enable 0

#define PCIE0 0

PCIE1 - Pin Change Interrupt Enable 1

#define PCIE1 1

PCIE2 - Pin Change Interrupt Enable 2

#define PCIE2 2

CPU

SREG - Status Register

sfrb SREG = $3F;

SPH - Stack Pointer High

sfrb SPH = $3E;

SP8 - Stack pointer bit 8

#define SP8 0

SP9 - Stack pointer bit 9

#define SP9 1

SP10 - Stack pointer bit 10

#define SP10 2

SP11 - Stack pointer bit 11

#define SP11 3

SP12

#define SP12 4

SP13 - Stack pointer bit 13

#define SP13 5

SP14 - Stack pointer bit 14

#define SP14 6

SP15 - Stack pointer bit 15

#define SP15 7

SPL - Stack Pointer Low

sfrb SPL = $3D;

SP0 - Stack pointer bit 0

#define SP0 0

SP1 - Stack pointer bit 1

#define SP1 1

SP2 - Stack pointer bit 2

#define SP2 2

SP3 - Stack pointer bit 3

#define SP3 3

SP4

#define SP4 4

SP5 - Stack pointer bit 5

#define SP5 5

SP6 - Stack pointer bit 6

#define SP6 6

SP7 - Stack pointer bit 7

#define SP7 7

MCUCR - MCU Control Register

sfrb MCUCR = $35;

IVCE - Interrupt Vector Change Enable

#define IVCE 0

The IVCE bit must be written to logic one to enable change of the IVSEL bit.IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.Setting the IVCE bit will disable interrupts.

IVSEL - Interrupt Vector Select

#define IVSEL 1

When the IVSEL bit is cleared (zero),the interrupt vectors are placed at the start of the Flash memory.When this bit is set (one),the interrupt vectors are moved to the beginning of the Boot Loader section of the flash.The actual address of the start of the boot flash section is determined by the BOOTSZ fuses.

PUD - Pull-up disable

#define PUD 4

When this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn,PORTxn}=0b01).

JTD - JTAG Interface Disable

#define JTD 7

When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed.

MCUSR - MCU Status Register

sfrb MCUSR = $34;

PORF - Power-on reset flag

#define PORF 0

This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.

EXTRF - External Reset Flag

#define EXTRF 1

This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

BORF - Brown-out Reset Flag

#define BORF 2

This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

WDRF - Watchdog Reset Flag

#define WDRF 3

This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

JTRF - JTAG Reset Flag

#define JTRF 4

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on reset, or by writing a logic zero to the flag. ? Bit 3 - WDRF: Watchdog Reset Flag

XMCRA - External Memory Control Register A

sfrb XMCRA = $74;

SRW00 - Wait state select bit lower page

#define SRW00 0

SRW01 - Wait state select bit lower page

#define SRW01 1

SRW10 - Wait state select bit upper page

#define SRW10 2

SRW11 - Wait state select bit upper page

#define SRW11 3

SRL0 - Wait state page limit

#define SRL0 4

It is possible to configure different wait-states for different external memory addresses.

SRL1 - Wait state page limit

#define SRL1 5

It is possible to configure different wait-states for different external memory addresses.

SRL2 - Wait state page limit

#define SRL2 6

It is possible to configure different wait-states for different external memory addresses.

SRE - External SRAM Enable

#define SRE 7

Writing SRE to one enables the External Memory Interface.

XMCRB - External Memory Control Register B

sfrb XMCRB = $75;

XMM0 - External Memory High Mask

#define XMM0 0

Port C pins released.

XMM1 - External Memory High Mask

#define XMM1 1

Port C pins released.

XMM2 - External Memory High Mask

#define XMM2 2

Port C pins released.

XMBK - External Memory Bus Keeper Enable

#define XMBK 7

Port C pins release command.

OSCCAL - Oscillator Calibration Value

sfrb OSCCAL = $66;

CAL0 - Oscillator Calibration Value Bit0

#define CAL0 0

CAL1 - Oscillator Calibration Value Bit1

#define CAL1 1

CAL2 - Oscillator Calibration Value Bit2

#define CAL2 2

CAL3 - Oscillator Calibration Value Bit3

#define CAL3 3

CAL4 - Oscillator Calibration Value Bit4

#define CAL4 4

CAL5 - Oscillator Calibration Value Bit5

#define CAL5 5

CAL6 - Oscillator Calibration Value Bit6

#define CAL6 6

CAL7 - Oscillator Calibration Value Bit7

#define CAL7 7

CLKPR -

sfrb CLKPR = $61;

CLKPS0

#define CLKPS0 0

CLKPS1

#define CLKPS1 1

CLKPS2

#define CLKPS2 2

CLKPS3

#define CLKPS3 3

CPKPCE

#define CPKPCE 7

SMCR - Sleep Mode Control Register

sfrb SMCR = $33;

SE - Sleep Enable

#define SE 0

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.To

SM0 - Sleep Mode Select bit 0

#define SM0 1

These bits select between the five available sleep modes.

SM1 - Sleep Mode Select bit 1

#define SM1 2

These bits select between the five available sleep modes.

SM2 - Sleep Mode Select bit 2

#define SM2 3

These bits select between the five available sleep modes.

EIND - Extended Indirect Register

sfrb EIND = $3C;

EIND0 - Bit 0

#define EIND0 0

For EICALL/EIJMP instructions.

RAMPZ - RAM Page Z Select Register

sfrb RAMPZ = $3B;

RAMPZ0 - RAM Page Z Select Register Bit 0

#define RAMPZ0 0

The RAMPZ register is normally used to select which 64K RAM Page is accessed by the Z pointer.

RAMPZ1 - RAM Page Z Select Register Bit 1

#define RAMPZ1 1

The RAMPZ register is normally used to select which 64K RAM Page is accessed by the Z pointer.

GPIOR2 - General Purpose IO Register 2

sfrb GPIOR2 = $2B;

GPIOR20 - General Purpose IO Register 2 bit 0

#define GPIOR20 0

GPIOR21 - General Purpose IO Register 2 bit 1

#define GPIOR21 1

GPIOR22 - General Purpose IO Register 2 bit 2

#define GPIOR22 2

GPIOR23 - General Purpose IO Register 2 bit 3

#define GPIOR23 3

GPIOR24 - General Purpose IO Register 2 bit 4

#define GPIOR24 4

GPIOR25 - General Purpose IO Register 2 bit 5

#define GPIOR25 5

GPIOR26 - General Purpose IO Register 2 bit 6

#define GPIOR26 6

GPIOR27 - General Purpose IO Register 2 bit 7

#define GPIOR27 7

GPIOR1 - General Purpose IO Register 1

sfrb GPIOR1 = $2A;

GPIOR10 - General Purpose IO Register 1 bit 0

#define GPIOR10 0

GPIOR11 - General Purpose IO Register 1 bit 1

#define GPIOR11 1

GPIOR12 - General Purpose IO Register 1 bit 2

#define GPIOR12 2

GPIOR13 - General Purpose IO Register 1 bit 3

#define GPIOR13 3

GPIOR14 - General Purpose IO Register 1 bit 4

#define GPIOR14 4

GPIOR15 - General Purpose IO Register 1 bit 5

#define GPIOR15 5

GPIOR16 - General Purpose IO Register 1 bit 6

#define GPIOR16 6

GPIOR17 - General Purpose IO Register 1 bit 7

#define GPIOR17 7

GPIOR0 - General Purpose IO Register 0

sfrb GPIOR0 = $1E;

GPIOR00 - General Purpose IO Register 0 bit 0

#define GPIOR00 0

GPIOR01 - General Purpose IO Register 0 bit 1

#define GPIOR01 1

GPIOR02 - General Purpose IO Register 0 bit 2

#define GPIOR02 2

GPIOR03 - General Purpose IO Register 0 bit 3

#define GPIOR03 3

GPIOR04 - General Purpose IO Register 0 bit 4

#define GPIOR04 4

GPIOR05 - General Purpose IO Register 0 bit 5

#define GPIOR05 5

GPIOR06 - General Purpose IO Register 0 bit 6

#define GPIOR06 6

GPIOR07 - General Purpose IO Register 0 bit 7

#define GPIOR07 7

PRR1 - Power Reduction Register1

sfrb PRR1 = $65;

PRUSART1 - Power Reduction USART1

#define PRUSART1 0

PRUSART2 - Power Reduction USART2

#define PRUSART2 1

PRUSART3 - Power Reduction USART3

#define PRUSART3 2

PRTIM3 - Power Reduction Timer/Counter3

#define PRTIM3 3

PRTIM4 - Power Reduction Timer/Counter4

#define PRTIM4 4

PRTIM5 - Power Reduction Timer/Counter5

#define PRTIM5 5

PRR0 - Power Reduction Register0

sfrb PRR0 = $64;

PRADC - Power Reduction ADC

#define PRADC 0

PRUSART0 - Power Reduction USART

#define PRUSART0 1

PRSPI - Power Reduction Serial Peripheral Interface

#define PRSPI 2

PRTIM1 - Power Reduction Timer/Counter1

#define PRTIM1 3

PRTIM0 - Power Reduction Timer/Counter0

#define PRTIM0 5

PRTIM2 - Power Reduction Timer/Counter2

#define PRTIM2 6

PRTWI - Power Reduction TWI

#define PRTWI 7

AD CONVERTER

AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 �s Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode No

ADMUX - The ADC multiplexer Selection Register

sfrb ADMUX = $7C;

MUX0 - Analog Channel and Gain Selection Bits

#define MUX0 0

The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).

MUX1 - Analog Channel and Gain Selection Bits

#define MUX1 1

MUX2 - Analog Channel and Gain Selection Bits

#define MUX2 2

MUX3 - Analog Channel and Gain Selection Bits

#define MUX3 3

MUX4 - Analog Channel and Gain Selection Bits

#define MUX4 4

ADLAR - Left Adjust Result

#define ADLAR 5

The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see ?The ADC Data Register -ADCL and ADCH? on page 198.

REFS0 - Reference Selection Bit 0

#define REFS0 6

These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.

REFS1 - Reference Selection Bit 1

#define REFS1 7

ADCH - ADC Data Register High Byte

sfrb ADCH = $79;

ADCH0 - ADC Data Register High Byte Bit 0

#define ADCH0 0

ADCH1 - ADC Data Register High Byte Bit 1

#define ADCH1 1

ADCH2 - ADC Data Register High Byte Bit 2

#define ADCH2 2

ADCH3 - ADC Data Register High Byte Bit 3

#define ADCH3 3

ADCH4 - ADC Data Register High Byte Bit 4

#define ADCH4 4

ADCH5 - ADC Data Register High Byte Bit 5

#define ADCH5 5

ADCH6 - ADC Data Register High Byte Bit 6

#define ADCH6 6

ADCH7 - ADC Data Register High Byte Bit 7

#define ADCH7 7

ADCL - ADC Data Register Low Byte

sfrb ADCL = $78;

ADCL0 - ADC Data Register Low Byte Bit 0

#define ADCL0 0

ADCL1 - ADC Data Register Low Byte Bit 1

#define ADCL1 1

ADCL2 - ADC Data Register Low Byte Bit 2

#define ADCL2 2

ADCL3 - ADC Data Register Low Byte Bit 3

#define ADCL3 3

ADCL4 - ADC Data Register Low Byte Bit 4

#define ADCL4 4

ADCL5 - ADC Data Register Low Byte Bit 5

#define ADCL5 5

ADCL6 - ADC Data Register Low Byte Bit 6

#define ADCL6 6

ADCL7 - ADC Data Register Low Byte Bit 7

#define ADCL7 7

ADCSRA - The ADC Control and Status register A

sfrb ADCSRA = $7A;

ADPS0 - ADC Prescaler Select Bits

#define ADPS0 0

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

ADPS1 - ADC Prescaler Select Bits

#define ADPS1 1

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

ADPS2 - ADC Prescaler Select Bits

#define ADPS2 2

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

ADIE - ADC Interrupt Enable

#define ADIE 3

When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.

ADIF - ADC Interrupt Flag

#define ADIF 4

This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.

ADATE - ADC Auto Trigger Enable

#define ADATE 5

When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB.

ADSC - ADC Start Conversion

#define ADSC 6

In Single Conversion Mode, a logical ?1? must be written to this bit to start each conversion. In Free Running Mode, a logical ?1? must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect

ADEN - ADC Enable

#define ADEN 7

Writing a logical ?1? to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.

ADCSRB - The ADC Control and Status register B

sfrb ADCSRB = $7B;

ADTS0 - ADC Auto Trigger Source bit 0

#define ADTS0 0

Please refer to table on page 240 in datasheet for trigger selection.

ADTS1 - ADC Auto Trigger Source bit 1

#define ADTS1 1

Please refer to table on page 240 in datasheet for trigger selection.

ADTS2 - ADC Auto Trigger Source bit 2

#define ADTS2 2

Please refer to table on page 240 in datasheet for trigger selection.

MUX5 - Analog Channel and Gain Selection Bits

#define MUX5 3

ACME

#define ACME 6

DIDR2 - Digital Input Disable Register

sfrb DIDR2 = $7D;

ADC8D

#define ADC8D 0

ADC9D

#define ADC9D 1

ADC10D

#define ADC10D 2

ADC11D

#define ADC11D 3

ADC12D

#define ADC12D 4

ADC13D

#define ADC13D 5

ADC14D

#define ADC14D 6

ADC15D

#define ADC15D 7

DIDR0 - Digital Input Disable Register

sfrb DIDR0 = $7E;

ADC0D

#define ADC0D 0

ADC1D

#define ADC1D 1

ADC2D

#define ADC2D 2

ADC3D

#define ADC3D 3

ADC4D

#define ADC4D 4

ADC5D

#define ADC5D 5

ADC6D

#define ADC6D 6

ADC7D

#define ADC7D 7

BOOT LOAD

The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppor

SPMCSR - Store Program Memory Control Register

sfrb SPMCSR = $37;

SPMEN - Store Program Memory Enable

#define SPMEN 0

This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than ?10001?, "01001", "00101", "00011" or "00001" in the lower five bits will have no effec

PGERS - Page Erase

#define PGERS 1

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.

PGWRT - Page Write

#define PGWRT 2

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.

BLBSET - Boot Lock Bit Set

#define BLBSET 3

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See ?Reading the Fuse and Lock Bits from Software? on page 235 for details

RWWSRE - Read While Write section read enable

#define RWWSRE 4

When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lo

SIGRD - Signature Row Read

#define SIGRD 5

If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read a byte from the signature row into the destination register. see ?Reading the Signature Row from Software? in the datasheet for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. This operation is reserved for future use and should not be used.

RWWSB - Read While Write Section Busy

#define RWWSB 6

When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated.

SPMIE - SPM Interrupt Enable

#define SPMIE 7

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared.