<ATmega162.h>

This documentation was generated automatically from the AVR Studio part description file ATmega162.pdf.

TIMER COUNTER 1

The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in the specification for the Timer/Counter1 Control Registers - TCCR1A and TCCR1B. The different status flags (overflow, compare match and capture event) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter1 Control Registers - TCCR1A and TCCR1B. The interrupt enable/disable settings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register - TIM

TIMSK - Timer/Counter Interrupt Mask Register

sfrb TIMSK = $39;

TICIE1 - Timer/Counter1 Input Capture Interrupt Enable

#define TICIE1 3

When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE1B - Timer/Counter1 Output CompareB Match Interrupt Enable

#define OCIE1B 5

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE1A - Timer/Counter1 Output CompareA Match Interrupt Enable

#define OCIE1A 6

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

TOIE1 - Timer/Counter1 Overflow Interrupt Enable

#define TOIE1 7

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

TIFR - Timer/Counter Interrupt Flag register

sfrb TIFR = $38;

ICF1 - Input Capture Flag 1

#define ICF1 3

The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.

OCF1B - Output Compare Flag 1B

#define OCF1B 5

The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.

OCF1A - Output Compare Flag 1A

#define OCF1A 6

The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed.

TOV1 - Timer/Counter1 Overflow Flag

#define TOV1 7

The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.

TCCR1A - Timer/Counter1 Control Register A

sfrb TCCR1A = $2F;

WGM10 - Pulse Width Modulator Select Bit 0

#define WGM10 0

Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter,the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the Timer/Counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes.

WGM11 - Pulse Width Modulator Select Bit 1

#define WGM11 1

FOC1B - Force Output Compare for Channel B

#define FOC1B 2

The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode.However,for ensuring compatibility with future devices,these bits must be set to zero when TCCR1A is written when operating in a PWM mode.When writing a logical one to the FOC1A/FOC1Bbit,an immediate compare match is forced on the waveform generation unit.The OC1A/OC1B output is changed according to its COM1x1:0 bits setting.Note that the FOC1A/FOC1Bbits are implemented as strobes.Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (CTC)mode using OCR1A as TOP. The FOC1A/FOC1Bbits are always read as zero.

FOC1A - Force Output Compare for Channel A

#define FOC1A 3

COM1B0 - Compare Output Mode 1B, bit 0

#define COM1B0 4

The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB.

COM1B1 - Compare Output Mode 1B, bit 1

#define COM1B1 5

The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB.

COM1A0 - Compare Ouput Mode 1A, bit 0

#define COM1A0 6

The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in Table 9.

COM1A1 - Compare Output Mode 1A, bit 1

#define COM1A1 7

TCCR1B - Timer/Counter1 Control Register B

sfrb TCCR1B = $2E;

CS10 - Clock Select1 bit 0

#define CS10 0

CS11 - Clock Select1 bit 1

#define CS11 1

CS12 - Clock Select1 bit 2

#define CS12 2

WGM12 - Pulse Width Modulator Select Bit 2

#define WGM12 3

Combined with the WGM11:0 bits found in the TCCR1B register,these bits control the counting sequence of the counter,the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the Timer/Counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes.

WGM13 - Pulse Width Modulator Select Bit 3

#define WGM13 4

ICES1 - Input Capture 1 Edge Select

#define ICES1 6

While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.

ICNC1 - Input Capture 1 Noise Canceler

#define ICNC1 7

When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.

TCNT1H - Timer/Counter1 High Byte

sfrb TCNT1H = $2D;

TCNT1H0 - Timer/Counter1 High Byte bit 0

#define TCNT1H0 0

TCNT1H1 - Timer/Counter1 High Byte bit 1

#define TCNT1H1 1

TCNT1H2 - Timer/Counter1 High Byte bit 2

#define TCNT1H2 2

TCNT1H3 - Timer/Counter1 High Byte bit 3

#define TCNT1H3 3

TCNT1H4 - Timer/Counter1 High Byte bit 4

#define TCNT1H4 4

TCNT1H5 - Timer/Counter1 High Byte bit 5

#define TCNT1H5 5

TCNT1H6 - Timer/Counter1 High Byte bit 6

#define TCNT1H6 6

TCNT1H7 - Timer/Counter1 High Byte bit 7

#define TCNT1H7 7

TCNT1L - Timer/Counter1 Low Byte

sfrb TCNT1L = $2C;

TCNT1L0 - Timer/Counter1 Low Byte bit 0

#define TCNT1L0 0

TCNT1L1 - Timer/Counter1 Low Byte bit 1

#define TCNT1L1 1

TCNT1L2 - Timer/Counter1 Low Byte bit 2

#define TCNT1L2 2

TCNT1L3 - Timer/Counter1 Low Byte bit 3

#define TCNT1L3 3

TCNT1L4 - Timer/Counter1 Low Byte bit 4

#define TCNT1L4 4

TCNT1L5 - Timer/Counter1 Low Byte bit 5

#define TCNT1L5 5

TCNT1L6 - Timer/Counter1 Low Byte bit 6

#define TCNT1L6 6

TCNT1L7 - Timer/Counter1 Low Byte bit 7

#define TCNT1L7 7

OCR1AH - Timer/Counter1 Outbut Compare Register A High Byte

sfrb OCR1AH = $2B;

OCR1AH0 - Timer/Counter1 Outbut Compare Register High Byte bit 0

#define OCR1AH0 0

OCR1AH1 - Timer/Counter1 Outbut Compare Register High Byte bit 1

#define OCR1AH1 1

OCR1AH2 - Timer/Counter1 Outbut Compare Register High Byte bit 2

#define OCR1AH2 2

OCR1AH3 - Timer/Counter1 Outbut Compare Register High Byte bit 3

#define OCR1AH3 3

OCR1AH4 - Timer/Counter1 Outbut Compare Register High Byte bit 4

#define OCR1AH4 4

OCR1AH5 - Timer/Counter1 Outbut Compare Register High Byte bit 5

#define OCR1AH5 5

OCR1AH6 - Timer/Counter1 Outbut Compare Register High Byte bit 6

#define OCR1AH6 6

OCR1AH7 - Timer/Counter1 Outbut Compare Register High Byte bit 7

#define OCR1AH7 7

OCR1AL - Timer/Counter1 Output Compare Register A Low Byte

sfrb OCR1AL = $2A;

OCR1AL0 - Timer/Counter1 Output Compare Register Low Byte Bit 0

#define OCR1AL0 0

OCR1AL1 - Timer/Counter1 Output Compare Register Low Byte Bit 1

#define OCR1AL1 1

OCR1AL2 - Timer/Counter1 Output Compare Register Low Byte Bit 2

#define OCR1AL2 2

OCR1AL3 - Timer/Counter1 Output Compare Register Low Byte Bit 3

#define OCR1AL3 3

OCR1AL4 - Timer/Counter1 Output Compare Register Low Byte Bit 4

#define OCR1AL4 4

OCR1AL5 - Timer/Counter1 Output Compare Register Low Byte Bit 5

#define OCR1AL5 5

OCR1AL6 - Timer/Counter1 Output Compare Register Low Byte Bit 6

#define OCR1AL6 6

OCR1AL7 - Timer/Counter1 Output Compare Register Low Byte Bit 7

#define OCR1AL7 7

OCR1BH - Timer/Counter1 Output Compare Register B High Byte

sfrb OCR1BH = $29;

OCR1BH0 - Timer/Counter1 Output Compare Register High Byte bit 0

#define OCR1BH0 0

OCR1BH1 - Timer/Counter1 Output Compare Register High Byte bit 1

#define OCR1BH1 1

OCR1BH2 - Timer/Counter1 Output Compare Register High Byte bit 2

#define OCR1BH2 2

OCR1BH3 - Timer/Counter1 Output Compare Register High Byte bit 3

#define OCR1BH3 3

OCR1BH4 - Timer/Counter1 Output Compare Register High Byte bit 4

#define OCR1BH4 4

OCR1BH5 - Timer/Counter1 Output Compare Register High Byte bit 5

#define OCR1BH5 5

OCR1BH6 - Timer/Counter1 Output Compare Register High Byte bit 6

#define OCR1BH6 6

OCR1BH7 - Timer/Counter1 Output Compare Register High Byte bit 7

#define OCR1BH7 7

OCR1BL - Timer/Counter1 Output Compare Register B Low Byte

sfrb OCR1BL = $28;

OCR1BL0 - Timer/Counter1 Output Compare Register Low Byte bit 0

#define OCR1BL0 0

OCR1BL1 - Timer/Counter1 Output Compare Register Low Byte bit 1

#define OCR1BL1 1

OCR1BL2 - Timer/Counter1 Output Compare Register Low Byte bit 2

#define OCR1BL2 2

OCR1BL3 - Timer/Counter1 Output Compare Register Low Byte bit 3

#define OCR1BL3 3

OCR1BL4 - Timer/Counter1 Output Compare Register Low Byte bit 4

#define OCR1BL4 4

OCR1BL5 - Timer/Counter1 Output Compare Register Low Byte bit 5

#define OCR1BL5 5

OCR1BL6 - Timer/Counter1 Output Compare Register Low Byte bit 6

#define OCR1BL6 6

OCR1BL7 - Timer/Counter1 Output Compare Register Low Byte bit 7

#define OCR1BL7 7

ICR1H - Timer/Counter1 Input Capture Register High Byte

sfrb ICR1H = $25;

ICR1H0 - Timer/Counter1 Input Capture Register High Byte bit 0

#define ICR1H0 0

ICR1H1 - Timer/Counter1 Input Capture Register High Byte bit 1

#define ICR1H1 1

ICR1H2 - Timer/Counter1 Input Capture Register High Byte bit 2

#define ICR1H2 2

ICR1H3 - Timer/Counter1 Input Capture Register High Byte bit 3

#define ICR1H3 3

ICR1H4 - Timer/Counter1 Input Capture Register High Byte bit 4

#define ICR1H4 4

ICR1H5 - Timer/Counter1 Input Capture Register High Byte bit 5

#define ICR1H5 5

ICR1H6 - Timer/Counter1 Input Capture Register High Byte bit 6

#define ICR1H6 6

ICR1H7 - Timer/Counter1 Input Capture Register High Byte bit 7

#define ICR1H7 7

ICR1L - Timer/Counter1 Input Capture Register Low Byte

sfrb ICR1L = $24;

ICR1L0 - Timer/Counter1 Input Capture Register Low Byte bit 0

#define ICR1L0 0

ICR1L1 - Timer/Counter1 Input Capture Register Low Byte bit 1

#define ICR1L1 1

ICR1L2 - Timer/Counter1 Input Capture Register Low Byte bit 2

#define ICR1L2 2

ICR1L3 - Timer/Counter1 Input Capture Register Low Byte bit 3

#define ICR1L3 3

ICR1L4 - Timer/Counter1 Input Capture Register Low Byte bit 4

#define ICR1L4 4

ICR1L5 - Timer/Counter1 Input Capture Register Low Byte bit 5

#define ICR1L5 5

ICR1L6 - Timer/Counter1 Input Capture Register Low Byte bit 6

#define ICR1L6 6

ICR1L7 - Timer/Counter1 Input Capture Register Low Byte bit 7

#define ICR1L7 7

TIMER COUNTER 2

TCCR2 - Timer/Counter Control Register

sfrb TCCR2 = $27;

CS20 - Clock Select

#define CS20 0

The three clock select bits select the clock source to be used by the Timer/Counter.

CS21 - Clock Select

#define CS21 1

The three clock select bits select the clock source to be used by the Timer/Counter.

CS22 - Clock Select

#define CS22 2

The three clock select bits select the clock source to be used by the Timer/Counter.

WGM21 - Pulse Width Modulator Select Bit 1

#define WGM21 3

These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes.

COM20 - Compare Match Output Mode

#define COM20 4

These bits control the output compare pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 64 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PW

COM21 - Compare Match Output Mode

#define COM21 5

WGM20 - Pulse Width Modulator Select Bit 0

#define WGM20 6

These bits control the counting sequence of the counter,the source for the maximum (TOP)counter value,and what type of waveform generation to be used.Modes of oper-ation supported by the Timer/Counter unit are:Normal mode,Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes.

FOC2 - Forde Output Compare

#define FOC2 7

The FOC2 bit is only active when the WGM bits specify a non-PWM mode.However,for ensuring compatibility with future devices,this bit must be set to zero when TCCR2 is written when operating in PWM mode.When writing a logical one to the FOC2 bit,an immediate compare match is forced on the waveform generation unit.The OC2 output is changed according to its COM21:0 bits setting.Note that the FOC2 bit is implemented as a strobe.Therefore it is the value present in the COM21:0 bits that determines the effect of the forced compare.

TCNT2 - Timer/Counter Register

sfrb TCNT2 = $23;

TCNT2_0 - Timer/Counter Register Bit 0

#define TCNT2_0 0

TCNT2_1 - Timer/Counter Register Bit 1

#define TCNT2_1 1

TCNT2_2 - Timer/Counter Register Bit 2

#define TCNT2_2 2

TCNT2_3 - Timer/Counter Register Bit 3

#define TCNT2_3 3

TCNT2_4 - Timer/Counter Register Bit 4

#define TCNT2_4 4

TCNT2_5 - Timer/Counter Register Bit 5

#define TCNT2_5 5

TCNT2_6 - Timer/Counter Register Bit 6

#define TCNT2_6 6

TCNT2_7 - Timer/Counter Register Bit 7

#define TCNT2_7 7

OCR2 - Output Compare Register

sfrb OCR2 = $22;

OCR2_0 - Output Compare Register Bit 0

#define OCR2_0 0

OCR2_1 - Output Compare Register Bit 1

#define OCR2_1 1

OCR2_2 - Output Compare Register Bit 2

#define OCR2_2 2

OCR2_3 - Output Compare Register Bit 3

#define OCR2_3 3

OCR2_4 - Output Compare Register Bit 4

#define OCR2_4 4

OCR2_5 - Output Compare Register Bit 5

#define OCR2_5 5

OCR2_6 - Output Compare Register Bit 6

#define OCR2_6 6

OCR2_7 - Output Compare Register Bit 7

#define OCR2_7 7

TIMSK - Timer/Counter Interrupt Mask Register

sfrb TIMSK = $39;

TOIE2 - Timer/Counter2 Overflow Interrupt Enable

#define TOIE2 2

When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter2 occurs (i.e., when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).

OCIE2 - Timer/Counter2 Output Compare Match Interrupt Enable

#define OCIE2 4

When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match inter-rupt is enabled. The corresponding interrupt (at vector $003) is executed if a compare match in Timer/Counter2 occurs (i.e., when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).

TIFR - Timer/Counter Interrupt Flag Register

sfrb TIFR = $38;

TOV2 - Timer/Counter2 Overflow Flag

#define TOV2 2

The TOV2 bit is set (one)when an overflow occurs in Timer/Counter2.TOV2 is cleared by hardware when executing the corresponding interrupt handling vector.Alternatively, TOV2 is cleared by writing a logic one to the flag.When the SREG I-bit,TOIE2 (Timer/Counter2 Overflow Interrupt Enable),and TOV2 are set (one),the Timer/Counter2 Overflow interrupt is executed.In PWM mode,this bit is set when Timer/Counter2 changes counting direction at $00.

OCF2 - Output Compare Flag 2

#define OCF2 4

The OCF2 bit is set (one)when a compare match occurs between the Timer/Counter2 and the data in OCR2 -Output Compare Register2.OCF2 is cleared by hardware when executing the corresponding interrupt handling vector.Alternatively,OCF2 is cleared by writing a logic one to the flag.When the I-bit in SREG,OCIE2 (Timer/Counter2 Compare match Interrupt Enable),and OCF2 are set (one),the Timer/Counter2 Compare match Interrupt is executed.

ASSR - Asynchronous Status Register

sfrb ASSR = $26;

TCR2UB - Timer/Counter Control Register2 Update Busy

#define TCR2UB 0

When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set (one). When TCCR2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical ?0? in this bit indicates that TCCR2 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter2 registers while its Update Busy flag is set (one), the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2 and TCCR2 are different. When reading TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary storage register is rea

OCR2UB - Output Compare Register2 Update Busy

#define OCR2UB 1

When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set (one). When OCR2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical ?0? in this bit indicates that OCR2 is ready to be updated with a new value.

TCN2UB - Timer/Counter2 Update Busy

#define TCN2UB 2

When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set (one). When TCNT2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical ?0? in this bit indicates that TCNT2 is ready to be updated with a new value.

AS2 - Asynchronous Timer 2

#define AS2 3

When AS2 is set (one), Timer/Counter2 is clocked from the TOSC1 pin. Pins PC6 and PC7 become connected to a crystal oscillator and cannot be used as general I/O pins. When cleared (zero), Timer/Counter2 is clocked from the internal system clock, CK. When the value of this bit is changed, the contents of TCNT2, OCR2 and TCCR2 might get corrupted.

TIMER COUNTER 3

The 16-bit Timer/Counter3 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in the specification for the Timer/Counter3 Control Registers - TCCR3A and TCCR3B. The different status flags (overflow, compare match and capture event) are found in the Extended Timer/Counter Interrupt Flag Register - ETIFR. Control signals are found in the Timer/Counter3 Control Registers - TCCR3A and TCCR3B. The interrupt enable/disable settings for Timer/Counter3 are found in the Exteded Timer/Counter Interrupt Mask Register - ETIMSK.

ETIMSK - Extended Timer/Counter Interrupt Mask Register

sfrb ETIMSK = $7D;

TOIE3 - Timer/Counter3 Overflow Interrupt Enable

#define TOIE3 2

When the TOIE3 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter3 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE3B - Timer/Counter3 Output CompareB Match Interrupt Enable

#define OCIE3B 3

When the OCIE3B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter3 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE3A - Timer/Counter3 Output CompareA Match Interrupt Enable

#define OCIE3A 4

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF3A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

TICIE3 - Timer/Counter3 Input Capture Interrupt Enable

#define TICIE3 5

When the TICIE3 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF3 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

ETIFR - Extended Timer/Counter Interrupt Flag register

sfrb ETIFR = $7C;

TOV3 - Timer/Counter3 Overflow Flag

#define TOV3 2

The TOV3 is set (one) when an overflow occurs in Timer/Counter3. TOV3 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV3 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE3 (Timer/Counter3 Overflow Interrupt Enable), and TOV3 are set (one), the Timer/Counter3 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter3 changes counting direction at $0000.

OCF3B - Output Compare Flag 3B

#define OCF3B 3

The OCF1B bit is set (one) when compare match occurs between the Timer/Counter3 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE3B (Timer/Counter3 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter3 Compare B match Interrupt is executed.

OCF3A - Output Compare Flag 3A

#define OCF3A 4

The OCF3A bit is set (one) when compare match occurs between the Timer/Counter3 and the data in OCR1A - Output Compare Register 1A. OCF3A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF3A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter3 Compare match InterruptA Enable), and the OCF3A are set (one), the Timer/Counter3 Compare A match Interrupt is executed.

ICF3 - Input Capture Flag 3

#define ICF3 5

The ICF3 bit is set (one) to flag an input capture event, indicating that the Timer/Counter3 value has been transferred to the input capture register - ICR1. ICF3 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF3 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE3 (Timer/Counter3 Input Capture Interrupt Enable), and ICF3 are set (one), the Timer/Counter3 Capture Interrupt is executed.

TCCR3A - Timer/Counter3 Control Register A

sfrb TCCR3A = $8B;

WGM30 - Pulse Width Modulator Select Bit 0

#define WGM30 0

Combined with the WGM33:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter,the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the Timer/Counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes.

WGM31 - Pulse Width Modulator Select Bit 1

#define WGM31 1

FOC3B - Force Output Compare for Channel B

#define FOC3B 2

The FOC3A/FOC3B bits are only active when the WGM33:0 bits specifies a non-PWM mode.However,for ensuring compatibility with future devices,these bits must be set to zero when TCCR3A is written when operating in a PWM mode.When writing a logical one to the FOC3A/FOC3B bit,an immediate compare match is forced on the waveform generation unit.The OC3A/OC3B output is changed according to its COM3x1:0 bits setting.Note that the FOC3A/FOC3B bits are implemented as strobes.Therefore it is the value present in the COM3x1:0 bits that determine the effect of the forced compare. A FOC3A/FOC3B strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (CTC)mode using OCR3A as TOP. The FOC3A/FOC3Bbits are always read as ze

FOC3A - Force Output Compare for Channel A

#define FOC3A 3

COM3B0 - Compare Output Mode 3B, bit 0

#define COM3B0 4

The COM3B1 and COM3B0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3B - Output CompareB.

COM3B1 - Compare Output Mode 3B, bit 1

#define COM3B1 5

The COM3B1 and COM3B0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3B - Output CompareB.

COM3A0 - Compare Ouput Mode 3A, bit 0

#define COM3A0 6

The COM3A1 and COM3A0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin.

COM3A1 - Compare Output Mode 3A, bit 1

#define COM3A1 7

TCCR3B - Timer/Counter3 Control Register B

sfrb TCCR3B = $8A;

CS30 - Clock Select3 bit 0

#define CS30 0

CS31 - Clock Select3 bit 1

#define CS31 1

CS32 - Clock Select3 bit 2

#define CS32 2

WGM32 - Pulse Width Modulator Select Bit 2

#define WGM32 3

Combined with the WGM31:0 bits found in the TCCR3B register,these bits control the counting sequence of the counter,the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the Timer/Counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes.

WGM33 - Pulse Width Modulator Select Bit 3

#define WGM33 4

ICES3 - Input Capture 3 Edge Select

#define ICES3 6

While the ICES3 bit is cleared (zero), the Timer/Counter3 contents are transferred to the Input Capture Register - ICR3 - on the falling edge of the input capture pin - ICP. While the ICES3 bit is set (one), the Timer/Counter3 contents are transferred to the Input Capture Register - ICR3 - on the rising edge of the input capture pin - ICP.

ICNC3 - Input Capture 3 Noise Canceler

#define ICNC3 7

When the ICNC3 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC3 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES3 bit. The actual sampling frequency is XTAL clock frequency.

TCNT3H - Timer/Counter3 High Byte

sfrb TCNT3H = $89;

TCNT3H0 - Timer/Counter3 High Byte bit 0

#define TCNT3H0 0

TCNT3H1 - Timer/Counter3 High Byte bit 1

#define TCNT3H1 1

TCNT3H2 - Timer/Counter3 High Byte bit 2

#define TCNT3H2 2

TCNT3H3 - Timer/Counter3 High Byte bit 3

#define TCNT3H3 3

TCNT3H4 - Timer/Counter3 High Byte bit 4

#define TCNT3H4 4

TCNT3H5 - Timer/Counter3 High Byte bit 5

#define TCNT3H5 5

TCNT3H6 - Timer/Counter3 High Byte bit 6

#define TCNT3H6 6

TCNT3H7 - Timer/Counter3 High Byte bit 7

#define TCNT3H7 7

TCNT3L - Timer/Counter3 Low Byte

sfrb TCNT3L = $88;

TCNT3L0 - Timer/Counter3 Low Byte bit 0

#define TCNT3L0 0

TCNT3L1 - Timer/Counter3 Low Byte bit 1

#define TCNT3L1 1

TCNT3L2 - Timer/Counter3 Low Byte bit 2

#define TCNT3L2 2

TCNT3L3 - Timer/Counter3 Low Byte bit 3

#define TCNT3L3 3

TCNT3L4 - Timer/Counter3 Low Byte bit 4

#define TCNT3L4 4

TCNT3L5 - Timer/Counter3 Low Byte bit 5

#define TCNT3L5 5

TCNT3L6 - Timer/Counter3 Low Byte bit 6

#define TCNT3L6 6

TCNT3L7 - Timer/Counter3 Low Byte bit 7

#define TCNT3L7 7

OCR3AH - Timer/Counter3 Outbut Compare Register A High Byte

sfrb OCR3AH = $87;

OCR3AH0 - Timer/Counter3 Outbut Compare Register High Byte bit 0

#define OCR3AH0 0

OCR3AH1 - Timer/Counter3 Outbut Compare Register High Byte bit 1

#define OCR3AH1 1

OCR3AH2 - Timer/Counter3 Outbut Compare Register High Byte bit 2

#define OCR3AH2 2

OCR3AH3 - Timer/Counter3 Outbut Compare Register High Byte bit 3

#define OCR3AH3 3

OCR3AH4 - Timer/Counter3 Outbut Compare Register High Byte bit 4

#define OCR3AH4 4

OCR3AH5 - Timer/Counter3 Outbut Compare Register High Byte bit 5

#define OCR3AH5 5

OCR3AH6 - Timer/Counter3 Outbut Compare Register High Byte bit 6

#define OCR3AH6 6

OCR3AH7 - Timer/Counter3 Outbut Compare Register High Byte bit 7

#define OCR3AH7 7

OCR3AL - Timer/Counter3 Output Compare Register A Low Byte

sfrb OCR3AL = $86;

OCR3AL0 - Timer/Counter3 Output Compare Register Low Byte Bit 0

#define OCR3AL0 0

OCR3AL1 - Timer/Counter3 Output Compare Register Low Byte Bit 1

#define OCR3AL1 1

OCR3AL2 - Timer/Counter3 Output Compare Register Low Byte Bit 2

#define OCR3AL2 2

OCR3AL3 - Timer/Counter3 Output Compare Register Low Byte Bit 3

#define OCR3AL3 3

OCR3AL4 - Timer/Counter3 Output Compare Register Low Byte Bit 4

#define OCR3AL4 4

OCR3AL5 - Timer/Counter3 Output Compare Register Low Byte Bit 5

#define OCR3AL5 5

OCR3AL6 - Timer/Counter3 Output Compare Register Low Byte Bit 6

#define OCR3AL6 6

OCR3AL7 - Timer/Counter3 Output Compare Register Low Byte Bit 7

#define OCR3AL7 7

OCR3BH - Timer/Counte3 Output Compare Register B High Byte

sfrb OCR3BH = $85;

OCR3BH0 - Timer/Counter3 Output Compare Register High Byte bit 0

#define OCR3BH0 0

OCR3BH1 - Timer/Counter3 Output Compare Register High Byte bit 1

#define OCR3BH1 1

OCR3BH2 - Timer/Counter3 Output Compare Register High Byte bit 2

#define OCR3BH2 2

OCR3BH3 - Timer/Counter3 Output Compare Register High Byte bit 3

#define OCR3BH3 3

OCR3BH4 - Timer/Counter3 Output Compare Register High Byte bit 4

#define OCR3BH4 4

OCR3BH5 - Timer/Counter3 Output Compare Register High Byte bit 5

#define OCR3BH5 5

OCR3BH6 - Timer/Counter3 Output Compare Register High Byte bit 6

#define OCR3BH6 6

OCR3BH7 - Timer/Counter3 Output Compare Register High Byte bit 7

#define OCR3BH7 7

OCR3BL - Timer/Counter3 Output Compare Register Low Byte

sfrb OCR3BL = $84;

OCR3BL0 - Timer/Counter3 Output Compare Register Low Byte bit 0

#define OCR3BL0 0

OCR3BL1 - Timer/Counter3 Output Compare Register Low Byte bit 1

#define OCR3BL1 1

OCR3BL2 - Timer/Counter3 Output Compare Register Low Byte bit 2

#define OCR3BL2 2

OCR3BL3 - Timer/Counter3 Output Compare Register Low Byte bit 3

#define OCR3BL3 3

OCR3BL4 - Timer/Counter3 Output Compare Register Low Byte bit 4

#define OCR3BL4 4

OCR3BL5 - Timer/Counter3 Output Compare Register Low Byte bit 5

#define OCR3BL5 5

OCR3BL6 - Timer/Counter3 Output Compare Register Low Byte bit 6

#define OCR3BL6 6

OCR3BL7 - Timer/Counter3 Output Compare Register Low Byte bit 7

#define OCR3BL7 7

ICR3H - Timer/Counter3 Input Capture Register High Byte

sfrb ICR3H = $81;

ICR3H0 - Timer/Counter3 Input Capture Register High Byte bit 0

#define ICR3H0 0

ICR3H1 - Timer/Counter3 Input Capture Register High Byte bit 1

#define ICR3H1 1

ICR3H2 - Timer/Counter3 Input Capture Register High Byte bit 2

#define ICR3H2 2

ICR3H3 - Timer/Counter3 Input Capture Register High Byte bit 3

#define ICR3H3 3

ICR3H4 - Timer/Counter3 Input Capture Register High Byte bit 4

#define ICR3H4 4

ICR3H5 - Timer/Counter3 Input Capture Register High Byte bit 5

#define ICR3H5 5

ICR3H6 - Timer/Counter3 Input Capture Register High Byte bit 6

#define ICR3H6 6

ICR3H7 - Timer/Counter3 Input Capture Register High Byte bit 7

#define ICR3H7 7

ICR3L - Timer/Counter3 Input Capture Register Low Byte

sfrb ICR3L = $80;

ICR3L0 - Timer/Counter3 Input Capture Register Low Byte bit 0

#define ICR3L0 0

ICR3L1 - Timer/Counter3 Input Capture Register Low Byte bit 1

#define ICR3L1 1

ICR3L2 - Timer/Counter3 Input Capture Register Low Byte bit 2

#define ICR3L2 2

ICR3L3 - Timer/Counter3 Input Capture Register Low Byte bit 3

#define ICR3L3 3

ICR3L4 - Timer/Counter3 Input Capture Register Low Byte bit 4

#define ICR3L4 4

ICR3L5 - Timer/Counter3 Input Capture Register Low Byte bit 5

#define ICR3L5 5

ICR3L6 - Timer/Counter3 Input Capture Register Low Byte bit 6

#define ICR3L6 6

ICR3L7 - Timer/Counter3 Input Capture Register Low Byte bit 7

#define ICR3L7 7

ANALOG COMPARATOR

ACSR - Analog Comparator Control And Status Register

sfrb ACSR = $08;

ACIS0 - Analog Comparator Interrupt Mode Select bit 0

#define ACIS0 0

These bits determine which comparator events that trigger the Analog Comparator interrupt.

ACIS1 - Analog Comparator Interrupt Mode Select bit 1

#define ACIS1 1

These bits determine which comparator events that trigger the Analog Comparator interrupt.

ACIC - Analog Comparator Input Capture Enable

#define ACIC 2

When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the analog comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set

ACIE - Analog Comparator Interrupt Enable

#define ACIE 3

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.

ACI - Analog Comparator Interrupt Flag

#define ACI 4

This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

ACO - Analog Compare Output

#define ACO 5

The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.

ACBG - Analog Comparator Bandgap Select

#define ACBG 6

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See ?Internal Voltage Reference? on page 42.

ACD - Analog Comparator Disable

#define ACD 7

When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

USART0

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: ? Full Duplex Operation (Independent Serial Receive and Transmit Registers) ? Asynchronous or Synchronous Operation ? Master or Slave Clocked Synchronous Operation ? High Resolution Baud Rate Generator ? Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits ? Odd or Even Parity Generation and Parity Check Supported by Hardware ? Data OverRun Detection ? Framing Error Detection ? Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter ? Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete ? Multi-processor Communication Mode ? Double Speed Asynchronous Communica

UDR0 - USART I/O Data Register

sfrb UDR0 = $0C;

UDR0-0 - USART I/O Data Register bit 0

#define UDR0-0 0

UDR0-1 - USART I/O Data Register bit 1

#define UDR0-1 1

UDR0-2 - USART I/O Data Register bit 2

#define UDR0-2 2

UDR0-3 - USART I/O Data Register bit 3

#define UDR0-3 3

UDR0-4 - USART I/O Data Register bit 4

#define UDR0-4 4

UDR0-5 - USART I/O Data Register bit 5

#define UDR0-5 5

UDR0-6 - USART I/O Data Register bit 6

#define UDR0-6 6

UDR0-7 - USART I/O Data Register bit 7

#define UDR0-7 7

UCSR0A - USART Control and Status Register A

sfrb UCSR0A = $0B;

MPCM0 - Multi-processor Communication Mode

#define MPCM0 0

This bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see ?Multi-processor Communication Mode? on page 152.

U2X0 - Double the USART transmission speed

#define U2X0 1

This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.

UPE0 - Parity Error

#define UPE0 2

This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A.

DOR0 - Data overRun

#define DOR0 3

This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0.

FE0 - Framing Error

#define FE0 4

This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.

UDRE0 - USART Data Register Empty

#define UDRE0 5

This bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is re

TXC0 - USART Transmitt Complete

#define TXC0 6

This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the b

RXC0 - USART Receive Complete

#define RXC0 7

This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.

UCSR0B - USART Control and Status Register B

sfrb UCSR0B = $0A;

TXB80 - Transmit Data Bit 8

#define TXB80 0

TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.

RXB80 - Receive Data Bit 8

#define RXB80 1

RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.

UCSZ02 - Character Size

#define UCSZ02 2

The UCSZ2 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use.

TXEN0 - Transmitter Enable

#define TXEN0 3

Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.

RXEN0 - Receiver Enable

#define RXEN0 4

Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.

UDRIE0 - USART Data register Empty Interrupt Enable

#define UDRIE0 5

Writing this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.

TXCIE0 - TX Complete Interrupt Enable

#define TXCIE0 6

Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.

RXCIE0 - RX Complete Interrupt Enable

#define RXCIE0 7

Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.

UCSR0C - USART Control and Status Register C

sfrb UCSR0C = $20;

UCPOL0 - Clock Polarity

#define UCPOL0 0

This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).

UCSZ00 - Character Size

#define UCSZ00 1

Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.

UCSZ01 - Character Size

#define UCSZ01 2

Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.

USBS0 - Stop Bit Select

#define USBS0 3

0: 1-bit. 1: 2-bit.

UPM00 - Parity Mode Bit 0

#define UPM00 4

This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.

UPM01 - Parity Mode Bit 1

#define UPM01 5

UMSEL0 - USART Mode Select

#define UMSEL0 6

0: Asynchronous Operation. 1: Synchronous Operation

URSEL - Register Select

#define URSEL 7

This bit selects between accessing the UCSRC or the UBRRH register.It is read as one when reading UCSRC.The URSEL must be one when writing the UCSRC.

UBRR0H - USART Baud Rate Register Hight Byte

sfrb UBRR0H = $20;

UBRR8 - USART Baud Rate Register bit 8

#define UBRR8 0

UBRR9 - USART Baud Rate Register bit 9

#define UBRR9 1

UBRR10 - USART Baud Rate Register bit 10

#define UBRR10 2

UBRR11 - USART Baud Rate Register bit 11

#define UBRR11 3

URSEL - Register Select

#define URSEL 7

This bit selects between accessing the UCSRC or the UBRRH register.It is read as one when reading UCSRC.The URSEL must be one when writing the UCSRC.

UBRR0L - USART Baud Rate Register Low Byte

sfrb UBRR0L = $09;

UBRR0 - USART Baud Rate Register bit 0

#define UBRR0 0

UBRR1 - USART Baud Rate Register bit 1

#define UBRR1 1

UBRR2 - USART Baud Rate Register bit 2

#define UBRR2 2

UBRR3 - USART Baud Rate Register bit 3

#define UBRR3 3

UBRR4 - USART Baud Rate Register bit 4

#define UBRR4 4

UBRR5 - USART Baud Rate Register bit 5

#define UBRR5 5

UBRR6 - USART Baud Rate Register bit 6

#define UBRR6 6

UBRR7 - USART Baud Rate Register bit 7

#define UBRR7 7

USART1

UDR - USART I/O Data Register

sfrb UDR = $03;

UDR1-0 - USART1 I/O Data Register bit 0

#define UDR1-0 0

UDR1-1 - USART1 I/O Data Register bit 1

#define UDR1-1 1

UDR1-2 - USART1 I/O Data Register bit 2

#define UDR1-2 2

UDR1-3 - USART1 I/O Data Register bit 3

#define UDR1-3 3

UDR1-4 - USART1 I/O Data Register bit 4

#define UDR1-4 4

UDR1-5 - USART1 I/O Data Register bit 5

#define UDR1-5 5

UDR1-6 - USART1 I/O Data Register bit 6

#define UDR1-6 6

UDR1-7 - USART1 I/O Data Register bit 7

#define UDR1-7 7

UCSR1A - USART Control and Status Register A

sfrb UCSR1A = $02;

MPCM1 - Multi-processor Communication Mode

#define MPCM1 0

U2X1 - Double the USART transmission speed

#define U2X1 1

UPE1 - Parity Error

#define UPE1 2

DOR1 - Data overRun

#define DOR1 3

FE1 - Framing Error

#define FE1 4

This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.

UDRE1 - USART Data Register Empty

#define UDRE1 5

TXC1 - USART Transmitt Complete

#define TXC1 6

RXC1 - USART Receive Complete

#define RXC1 7

UCSR1B - USART Control and Status Register B

sfrb UCSR1B = $01;

TXB81 - Transmit Data Bit 8

#define TXB81 0

TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.

RXB81 - Receive Data Bit 8

#define RXB81 1

RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.

UCSZ12 - Character Size

#define UCSZ12 2

The UCSZ2 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use.

TXEN1 - Transmitter Enable

#define TXEN1 3

RXEN1 - Receiver Enable

#define RXEN1 4

UDRIE1 - USART Data register Empty Interrupt Enable

#define UDRIE1 5

TXCIE1 - TX Complete Interrupt Enable

#define TXCIE1 6

RXCIE1 - RX Complete Interrupt Enable

#define RXCIE1 7

UCSR1C - USART Control and Status Register C

sfrb UCSR1C = $3C;

UCPOL - Clock Polarity

#define UCPOL 0

UCSZ0 - Character Size

#define UCSZ0 1

Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.

UCSZ1 - Character Size

#define UCSZ1 2

Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.

USBS - Stop Bit Select

#define USBS 3

0: 1-bit. 1: 2-bit.

UPM0 - Parity Mode Bit 0

#define UPM0 4

UPM1 - Parity Mode Bit 1

#define UPM1 5

UMSEL - USART Mode Select

#define UMSEL 6

0: Asynchronous Operation. 1: Synchronous Operation

URSEL - Register Select

#define URSEL 7

This bit selects between accessing the UCSRC or the UBRRH register.It is read as one when reading UCSRC.The URSELmust be one when writing the UCSRC.

UBRR0H - USART Baud Rate Register Hight Byte

sfrb UBRR0H = $3C;

UBRR8 - USART Baud Rate Register bit 8

#define UBRR8 0

UBRR9 - USART Baud Rate Register bit 9

#define UBRR9 1

UBRR10 - USART Baud Rate Register bit 10

#define UBRR10 2

UBRR11 - USART Baud Rate Register bit 11

#define UBRR11 3

UBRR1L - USART Baud Rate Register Low Byte

sfrb UBRR1L = $00;

UBRR1L0 - USART Baud Rate Register bit 0

#define UBRR1L0 0

UBRR1L1 - USART Baud Rate Register bit 1

#define UBRR1L1 1

UBRR1L2 - USART Baud Rate Register bit 2

#define UBRR1L2 2

UBRR1L3 - USART Baud Rate Register bit 3

#define UBRR1L3 3

UBRR1L4 - USART Baud Rate Register bit 4

#define UBRR1L4 4

UBRR1L5 - USART Baud Rate Register bit 5

#define UBRR1L5 5

UBRR1L6 - USART Baud Rate Register bit 6

#define UBRR1L6 6

UBRR1L7 - USART Baud Rate Register bit 7

#define UBRR1L7 7

SPI

The Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: ? Full-duplex, 3-wire Synchronous Data Transfer ? Master or Slave Operation ? LSB First or MSB First Data Transfer ? Four Programmable Bit Rates ? End of Transmission Interrupt Flag ? Write Collision Flag Protection ? Wakeup from Idle Mode (Slave Mode Only)

SPCR - SPI Control Register

sfrb SPCR = $0D;

SPR0 - SPI Clock Rate Select 0

#define SPR0 0

These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.

SPR1 - SPI Clock Rate Select 1

#define SPR1 1

These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.

CPHA - Clock Phase

#define CPHA 2

Refer to Figure 36 or Figure 37 for the functionality of this bit.

CPOL - Clock polarity

#define CPOL 3

When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.

MSTR - Master/Slave Select

#define MSTR 4

This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.

DORD - Data Order

#define DORD 5

When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.

SPE - SPI Enable

#define SPE 6

When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.

SPIE - SPI Interrupt Enable

#define SPIE 7

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.

SPSR - SPI Status Register

sfrb SPSR = $0E;

SPI2X - Double SPI Speed Bit

#define SPI2X 0

When this bit is written logic one the SPI speed (SCK Frequency)will be doubled when the SPI is in master mode .This means that the minimum SCK period will be 2 CPU clock periods.When the SPI is configured as Slave,the SPI is only guaranteed to work at f osc /4orlower. The SPI interface on the ATmega162 is also used for program memory and EEPROM downloading or uploading.

WCOL - Write Collision Flag

#define WCOL 6

The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.

SPIF - SPI Interrupt Flag

#define SPIF 7

When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).

SPDR - SPI Data Register

sfrb SPDR = $0F;

SPDR0 - SPI Data Register bit 0

#define SPDR0 0

SPDR1 - SPI Data Register bit 1

#define SPDR1 1

SPDR2 - SPI Data Register bit 2

#define SPDR2 2

SPDR3 - SPI Data Register bit 3

#define SPDR3 3

SPDR4 - SPI Data Register bit 4

#define SPDR4 4

SPDR5 - SPI Data Register bit 5

#define SPDR5 5

SPDR6 - SPI Data Register bit 6

#define SPDR6 6

SPDR7 - SPI Data Register bit 7

#define SPDR7 7

CPU

SREG - Status Register

sfrb SREG = $3F;

SPH - Stack Pointer High

sfrb SPH = $3E;

SP8 - Stack pointer bit 8

#define SP8 0

SP9 - Stack pointer bit 9

#define SP9 1

SP10 - Stack pointer bit 10

#define SP10 2

SP11 - Stack pointer bit 11

#define SP11 3

SP12

#define SP12 4

SP13 - Stack pointer bit 13

#define SP13 5

SP14 - Stack pointer bit 14

#define SP14 6

SP15 - Stack pointer bit 15

#define SP15 7

SPL - Stack Pointer Low

sfrb SPL = $3D;

SP0 - Stack pointer bit 0

#define SP0 0

SP1 - Stack pointer bit 1

#define SP1 1

SP2 - Stack pointer bit 2

#define SP2 2

SP3 - Stack pointer bit 3

#define SP3 3

SP4

#define SP4 4

SP5 - Stack pointer bit 5

#define SP5 5

SP6 - Stack pointer bit 6

#define SP6 6

SP7 - Stack pointer bit 7

#define SP7 7

MCUCR - MCU Control Register

sfrb MCUCR = $35;

ISC00 - Interrupt Sense Control 0 bit 0

#define ISC00 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt.

ISC01 - Interrupt Sense Control 0 bit 1

#define ISC01 1

ISC10 - Interrupt Sense Control 1 bit 1

#define ISC10 2

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-bit and the corresponding interrupt mask in the GICR are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt.

ISC11 - Interrupt Sense Control 1 bit 1

#define ISC11 3

SM1 - Sleep Mode Select

#define SM1 4

The description is to long for the tooltip help, please refer to the manual

SE - Sleep Enable

#define SE 5

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.To avoid the MCU entering the sleep mode unless it is the programmers purpose,it is recommended to write the Sleep Enable (SE)bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up.

SRW10 - External SRAM Wait State Select

#define SRW10 6

For a detailed description in non ATmega103 Compatibility mode, see common description for the SRWn bits below (XMRA description). In ATmega103 Compatibility mode, writing SRW10 to one enables the wait state and one extra cycle is added during read/write strobe as shown in Figure 14.

SRE - External SRAM Enable

#define SRE 7

Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are acti-vated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction regis-ters. Writing SRE to zero, disables the External Memory Interface and the normal pin and data direction settings are used.

MCUCSR - MCU Control And Status Register

sfrb MCUCSR = $34;

PORF - Power-on reset flag

#define PORF 0

This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.

EXTRF - External Reset Flag

#define EXTRF 1

This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

BORF - Brown-out Reset Flag

#define BORF 2

This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

WDRF - Watchdog Reset Flag

#define WDRF 3

This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

JTRF - JTAG Reset Flag

#define JTRF 4

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on reset, or by writing a logic zero to the flag. ? Bit 3 - WDRF: Watchdog Reset Flag

SM2 - Sleep Mode Select Bit 2

#define SM2 5

The Sleep Mode Select bits select between the five available sleep modes. See Datasheet.

JDT - JTAG Interface Disable

#define JDT 7

When this bit is zero,the JTAG interface is enabled if the JTAGEN fuse is programmed. If this bit is one,the JTAG interface is disabled.In order to avoid unintentional disabling or enabling of the JTAG interface,a timed sequence must be followed when changing this bit:The application software must write this bit to the desired value twice within four cycles to change its value.

EMCUCR - Extended MCU Control Register

sfrb EMCUCR = $36;

ISC2 - Interrupt Sense Control 2

#define ISC2 0

The asynchronous external interrupt 2 is activated by the external pin INT2 if the SREG I-bit and the corresponding interrupt mask in GICR are set.If ISC2 is written to zero,a falling edge on INT2 activates the interrupt.If ISC2 is written to one,a rising edge on INT2 activates the interrupt.Edges on INT2 are registered asynchronously.Pulses on INT2 wider than the minimum pulse given width will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.When changing the ISC2 bit,an interrupt can occur.Therefore,it is recommended to first disable INT2 by clearing its Interrupt Enable bit in the GICR register.Then,the ISC2 bit can be changed.Finally, the INT2 interruptflag should becleared by writing a logical one to its Interrupt Flagbit (INTF2)in the GIFR register before the interrupt is re-enabled.

SRW11 - Wait State Select Bit 1 for Upper Sector

#define SRW11 1

The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the external memory address space.

SRW00 - Wait State Select Bit 0 for Lower Sector

#define SRW00 2

The SRW00 and SRW01 bits control the number of wait-states for the upper sector of the external memory address space.

SRW01 - Wait State Select Bit 1 for Lower Sector

#define SRW01 3

The SRW00 and SRW01 bits control the number of wait-states for the upper sector of the external memory address space.

SRL0 - Wait State Sector Limit Bit 0

#define SRL0 4

It is possible to configure different wait-states for different external memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits.The SRL2,SRL1,and SRL0 bits select the splitting of these sectors. By default,the SRL2,SRL1,and SRL0 bits are set to zero and the entire external memory address space is treated as one sector.When the entire SRAM address space is configured as one sector,the wait-states are configured by the SRW11 and SRW10 bits.

SRL1 - Wait State Sector Limit Bit 1

#define SRL1 5

SRL2 - Wait State Sector Limit Bit 2

#define SRL2 6

SM0 - Sleep mode Select Bit 0

#define SM0 7

The Sleep Mode Select bits select between the five available sleep modes. See Datasheet.

OSCCAL - Oscillator Calibration Value

sfrb OSCCAL = $04;

CAL0 - Oscillator Calibration Value Bit0

#define CAL0 0

CAL1 - Oscillator Calibration Value Bit1

#define CAL1 1

CAL2 - Oscillator Calibration Value Bit2

#define CAL2 2

CAL3 - Oscillator Calibration Value Bit3

#define CAL3 3

CAL4 - Oscillator Calibration Value Bit4

#define CAL4 4

CAL5 - Oscillator Calibration Value Bit5

#define CAL5 5

CAL6 - Oscillator Calibration Value Bit6

#define CAL6 6

CLKPR - Oscillator Calibration Value

sfrb CLKPR = $61;

CLKPS0 - Clock Prescaler Select Bit 0

#define CLKPS0 0

CLKPS1 - Clock Prescaler Select Bit 1

#define CLKPS1 1

CLKPS2 - Clock Prescaler Select Bit 2

#define CLKPS2 2

CLKPS3 - Clock Prescaler Select Bit 3

#define CLKPS3 3

CLKPCE - Clock Prescaler Change Enable

#define CLKPCE 7

SFIOR - Special Function IO Register

sfrb SFIOR = $30;

PSR310 - Prescaler Reset Timer/Counter3, Timer/Counter1 and Timer/Counter0

#define PSR310 0

When this bit is written to one,the Timer/Counter3,Timer/Counter1,and Timer/Counter0 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.Note that Timer/Counter3,Timer/Counter1,and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect all 3 timers.This bit will always be read as zero.

PSR2 - Prescaler Reset Timer/Counter2

#define PSR2 1

When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.

PUD - Pull-up Disable

#define PUD 2

When this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn

XMM0 - External Memory High Mask Bit 0

#define XMM0 3

Please refer to the datasheet for a full description of the usage.

XMM1 - External Memory High Mask Bit 1

#define XMM1 4

Please refer to the datasheet for a full description of the usage.

XMM2 - External Memory High Mask Bit 2

#define XMM2 5

Please refer to the datasheet for a full description of the usage.

XMBK - External Memory Bus Keeper Enable

#define XMBK 6

Writing XMBK to one enables the bus keeper on the AD7:0 lines.When the bus keeper

TSM - Timer/Counter Synchronization Mode

#define TSM 7

Writing TSM to one,PSR0 and PSR321 becomes registers that hold their value until rewritten,or the TSM bit is written zero.This mode is useful for synchronizing timer/counters.By setting both TSM and the appropriate PSR bit(s),the appropriate timer/counters are halted,and can be configured to same value without the risk of one of them advancing during configuration.When the TSM bit is written zero,the Timer/Counters start counting simultaneously.

JTAG

JTAG Features: JTAG (IEEE std. 1149.1 compliant) Interface. Boundary-Scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard. Debugger Access to: ? All Internal Peripheral Units ? Internal and External RAM ? The Internal Register File ?Program Counter ? EEPROM and Flash Memories. Extensive On-Chip Debug Support for Break Conditions, Including: ?AVR Break Instruction ? Break on Change of Program Memory Flow ?Single Step Break ?Program Memory Breakpoints on Single Address or Address Range ? Data Memory Breakpoints on Single Address or Address Range. Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface. On-Chip Debugging Supported by AVR S

OCDR - On-Chip Debug Related Register in I/O Memory

sfrb OCDR = $04;

OCDR0 - On-Chip Debug Register Bit 0

#define OCDR0 0

OCDR1 - On-Chip Debug Register Bit 1

#define OCDR1 1

OCDR2 - On-Chip Debug Register Bit 2

#define OCDR2 2

OCDR3 - On-Chip Debug Register Bit 3

#define OCDR3 3

OCDR4 - On-Chip Debug Register Bit 4

#define OCDR4 4

OCDR5 - On-Chip Debug Register Bit 5

#define OCDR5 5

OCDR6 - On-Chip Debug Register Bit 6

#define OCDR6 6

OCDR7 - On-Chip Debug Register Bit 7

#define OCDR7 7

MCUCSR - MCU Control And Status Register

sfrb MCUCSR = $34;

JTRF - JTAG Reset Flag

#define JTRF 4

JTD - JTAG Interface Disable

#define JTD 7

When this bit is written to zero, the JTAG interface is enabled if the JTAGEN fuse is programmed. If this bit is written to one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface, a timed sequence must be followed: The application software must write this to the desired value twice within four cycles to change the bit.

BOOT LOAD

The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppo

SPMCR - Store Program Memory Control Register

sfrb SPMCR = $37;

SPMEN - Store Program Memory Enable

#define SPMEN 0

This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than ?10001?, "01001", "00101", "00011" or "00001" in the lower five bits will have no effec

PGERS - Page Erase

#define PGERS 1

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.

PGWRT - Page Write

#define PGWRT 2

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.

BLBSET - Boot Lock Bit Set

#define BLBSET 3

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See ?Reading the Fuse and Lock Bits from Software? on page 235 for details

RWWSRE - Read While Write secion read enable

#define RWWSRE 4

When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lo

RWWSB - Read While Write Section Busy

#define RWWSB 6

When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated.

SPMIE - SPM Interrupt Enable

#define SPMIE 7

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared.

EEPROM

EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See ?Preventing EEPROM Corruption? on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execute

EEARH - EEPROM Address Register High Byte

sfrb EEARH = $1F;

EEAR8 - EEPROM Read/Write Access Bit 8

#define EEAR8 0

EEARL - EEPROM Address Register Low Byte

sfrb EEARL = $1E;

EEAR0 - EEPROM Read/Write Access Bit 0

#define EEAR0 0

EEAR1 - EEPROM Read/Write Access Bit 1

#define EEAR1 1

EEAR2 - EEPROM Read/Write Access Bit 2

#define EEAR2 2

EEAR3 - EEPROM Read/Write Access Bit 3

#define EEAR3 3

EEAR4 - EEPROM Read/Write Access Bit 4

#define EEAR4 4

EEAR5 - EEPROM Read/Write Access Bit 5

#define EEAR5 5

EEAR6 - EEPROM Read/Write Access Bit 6

#define EEAR6 6

EEAR7 - EEPROM Read/Write Access Bit 7

#define EEAR7 7

EEDR - EEPROM Data Register

sfrb EEDR = $1D;

EEDR0 - EEPROM Data Register bit 0

#define EEDR0 0

EEDR1 - EEPROM Data Register bit 1

#define EEDR1 1

EEDR2 - EEPROM Data Register bit 2

#define EEDR2 2

EEDR3 - EEPROM Data Register bit 3

#define EEDR3 3

EEDR4 - EEPROM Data Register bit 4

#define EEDR4 4

EEDR5 - EEPROM Data Register bit 5

#define EEDR5 5

EEDR6 - EEPROM Data Register bit 6

#define EEDR6 6

EEDR7 - EEPROM Data Register bit 7

#define EEDR7 7

EECR - EEPROM Control Register

sfrb EECR = $1C;

EERE - EEPROM Read Enable

#define EERE 0

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU

EEWE - EEPROM Write Enable

#define EEWE 1

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See ?Boot Loader Support - Read While Write self-programming? on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed

EEMWE - EEPROM Master Write Enable

#define EEMWE 2

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

EERIE - EEPROM Ready Interrupt Enable

#define EERIE 3

EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.

PORTA

PORTA - Port A Data Register

sfrb PORTA = $1B;

PORTA0 - Port A Data Register bit 0

#define PORTA0 0

PORTA1 - Port A Data Register bit 1

#define PORTA1 1

PORTA2 - Port A Data Register bit 2

#define PORTA2 2

PORTA3 - Port A Data Register bit 3

#define PORTA3 3

PORTA4 - Port A Data Register bit 4

#define PORTA4 4

PORTA5 - Port A Data Register bit 5

#define PORTA5 5

PORTA6 - Port A Data Register bit 6

#define PORTA6 6

PORTA7 - Port A Data Register bit 7

#define PORTA7 7

DDRA - Port A Data Direction Register

sfrb DDRA = $1A;

DDA0 - Data Direction Register, Port A, bit 0

#define DDA0 0

DDA1 - Data Direction Register, Port A, bit 1

#define DDA1 1

DDA2 - Data Direction Register, Port A, bit 2

#define DDA2 2

DDA3 - Data Direction Register, Port A, bit 3

#define DDA3 3

DDA4 - Data Direction Register, Port A, bit 4

#define DDA4 4

DDA5 - Data Direction Register, Port A, bit 5

#define DDA5 5

DDA6 - Data Direction Register, Port A, bit 6

#define DDA6 6

DDA7 - Data Direction Register, Port A, bit 7

#define DDA7 7

PINA - Port A Input Pins

sfrb PINA = $19;

PINA0 - Input Pins, Port A bit 0

#define PINA0 0

PINA1 - Input Pins, Port A bit 1

#define PINA1 1

PINA2 - Input Pins, Port A bit 2

#define PINA2 2

PINA3 - Input Pins, Port A bit 3

#define PINA3 3

PINA4 - Input Pins, Port A bit 4

#define PINA4 4

PINA5 - Input Pins, Port A bit 5

#define PINA5 5

PINA6 - Input Pins, Port A bit 6

#define PINA6 6

PINA7 - Input Pins, Port A bit 7

#define PINA7 7

PORTB

PORTB - Port B Data Register

sfrb PORTB = $18;

PORTB0 - Port B Data Register bit 0

#define PORTB0 0

PORTB1 - Port B Data Register bit 1

#define PORTB1 1

PORTB2 - Port B Data Register bit 2

#define PORTB2 2

PORTB3 - Port B Data Register bit 3

#define PORTB3 3

PORTB4 - Port B Data Register bit 4

#define PORTB4 4

PORTB5 - Port B Data Register bit 5

#define PORTB5 5

PORTB6 - Port B Data Register bit 6

#define PORTB6 6

PORTB7 - Port B Data Register bit 7

#define PORTB7 7

DDRB - Port B Data Direction Register

sfrb DDRB = $17;

DDB0 - Port B Data Direction Register bit 0

#define DDB0 0

DDB1 - Port B Data Direction Register bit 1

#define DDB1 1

DDB2 - Port B Data Direction Register bit 2

#define DDB2 2

DDB3 - Port B Data Direction Register bit 3

#define DDB3 3

DDB4 - Port B Data Direction Register bit 4

#define DDB4 4

DDB5 - Port B Data Direction Register bit 5

#define DDB5 5

DDB6 - Port B Data Direction Register bit 6

#define DDB6 6

DDB7 - Port B Data Direction Register bit 7

#define DDB7 7

PINB - Port B Input Pins

sfrb PINB = $16;

PINB0 - Port B Input Pins bit 0

#define PINB0 0

PINB1 - Port B Input Pins bit 1

#define PINB1 1

PINB2 - Port B Input Pins bit 2

#define PINB2 2

PINB3 - Port B Input Pins bit 3

#define PINB3 3

PINB4 - Port B Input Pins bit 4

#define PINB4 4

PINB5 - Port B Input Pins bit 5

#define PINB5 5

PINB6 - Port B Input Pins bit 6

#define PINB6 6

PINB7 - Port B Input Pins bit 7

#define PINB7 7

PORTC

PORTC - Port C Data Register

sfrb PORTC = $15;

PORTC0 - Port C Data Register bit 0

#define PORTC0 0

PORTC1 - Port C Data Register bit 1

#define PORTC1 1

PORTC2 - Port C Data Register bit 2

#define PORTC2 2

PORTC3 - Port C Data Register bit 3

#define PORTC3 3

PORTC4 - Port C Data Register bit 4

#define PORTC4 4

PORTC5 - Port C Data Register bit 5

#define PORTC5 5

PORTC6 - Port C Data Register bit 6

#define PORTC6 6

PORTC7 - Port C Data Register bit 7

#define PORTC7 7

DDRC - Port C Data Direction Register

sfrb DDRC = $14;

DDC0 - Port C Data Direction Register bit 0

#define DDC0 0

DDC1 - Port C Data Direction Register bit 1

#define DDC1 1

DDC2 - Port C Data Direction Register bit 2

#define DDC2 2

DDC3 - Port C Data Direction Register bit 3

#define DDC3 3

DDC4 - Port C Data Direction Register bit 4

#define DDC4 4

DDC5 - Port C Data Direction Register bit 5

#define DDC5 5

DDC6 - Port C Data Direction Register bit 6

#define DDC6 6

DDC7 - Port C Data Direction Register bit 7

#define DDC7 7

PINC - Port C Input Pins

sfrb PINC = $13;

PINC0 - Port C Input Pins bit 0

#define PINC0 0

PINC1 - Port C Input Pins bit 1

#define PINC1 1

PINC2 - Port C Input Pins bit 2

#define PINC2 2

PINC3 - Port C Input Pins bit 3

#define PINC3 3

PINC4 - Port C Input Pins bit 4

#define PINC4 4

PINC5 - Port C Input Pins bit 5

#define PINC5 5

PINC6 - Port C Input Pins bit 6

#define PINC6 6

PINC7 - Port C Input Pins bit 7

#define PINC7 7

PORTD

PORTD - Port D Data Register

sfrb PORTD = $12;

PORTD0 - Port D Data Register bit 0

#define PORTD0 0

PORTD1 - Port D Data Register bit 1

#define PORTD1 1

PORTD2 - Port D Data Register bit 2

#define PORTD2 2

PORTD3 - Port D Data Register bit 3

#define PORTD3 3

PORTD4 - Port D Data Register bit 4

#define PORTD4 4

PORTD5 - Port D Data Register bit 5

#define PORTD5 5

PORTD6 - Port D Data Register bit 6

#define PORTD6 6

PORTD7 - Port D Data Register bit 7

#define PORTD7 7

DDRD - Port D Data Direction Register

sfrb DDRD = $11;

DDD0 - Port D Data Direction Register bit 0

#define DDD0 0

DDD1 - Port D Data Direction Register bit 1

#define DDD1 1

DDD2 - Port D Data Direction Register bit 2

#define DDD2 2

DDD3 - Port D Data Direction Register bit 3

#define DDD3 3

DDD4 - Port D Data Direction Register bit 4

#define DDD4 4

DDD5 - Port D Data Direction Register bit 5

#define DDD5 5

DDD6 - Port D Data Direction Register bit 6

#define DDD6 6

DDD7 - Port D Data Direction Register bit 7

#define DDD7 7

PIND - Port D Input Pins

sfrb PIND = $10;

PIND0 - Port D Input Pins bit 0

#define PIND0 0

PIND1 - Port D Input Pins bit 1

#define PIND1 1

PIND2 - Port D Input Pins bit 2

#define PIND2 2

PIND3 - Port D Input Pins bit 3

#define PIND3 3

PIND4 - Port D Input Pins bit 4

#define PIND4 4

PIND5 - Port D Input Pins bit 5

#define PIND5 5

PIND6 - Port D Input Pins bit 6

#define PIND6 6

PIND7 - Port D Input Pins bit 7

#define PIND7 7

TIMER COUNTER 0

TCCR0 - Timer/Counter 0 Control Register

sfrb TCCR0 = $33;

CS00 - Clock Select 1

#define CS00 0

The three clock select bits select the clock source to be used by the Timer/Counter,

CS01 - Clock Select 1

#define CS01 1

The three clock select bits select the clock source to be used by the Timer/Counter,

CS02 - Clock Select 2

#define CS02 2

The three clock select bits select the clock source to be used by the Timer/Counter,

WGM01 - Waveform Generation Mode 1

#define WGM01 3

COM00 - Compare match Output Mode 0

#define COM00 4

These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set in order to enable the output driver. When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 52 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM)

COM01 - Compare Match Output Mode 1

#define COM01 5

WGM00 - Waveform Generation Mode 0

#define WGM00 6

FOC0 - Force Output Compare

#define FOC0 7

The FOC0 bit is only active when the WGM bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode. When writing a logical one to the FOC0 bit, an immediate compare match is forced on the waveform generation unit. The OC0 output is changed accord-ing to its COM01:0 bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the value present in the COM01:0 bits that determines the effect of the forced compare. A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0 as TOP. The FOC0 bit is always read as zero.

TCNT0 - Timer/Counter 0 Register

sfrb TCNT0 = $32;

TCNT0_0

#define TCNT0_0 0

TCNT0_1

#define TCNT0_1 1

TCNT0_2

#define TCNT0_2 2

TCNT0_3

#define TCNT0_3 3

TCNT0_4

#define TCNT0_4 4

TCNT0_5

#define TCNT0_5 5

TCNT0_6

#define TCNT0_6 6

TCNT0_7

#define TCNT0_7 7

OCR0 - Timer/Counter 0 Output Compare Register

sfrb OCR0 = $31;

OCR0_0

#define OCR0_0 0

OCR0_1

#define OCR0_1 1

OCR0_2

#define OCR0_2 2

OCR0_3

#define OCR0_3 3

OCR0_4

#define OCR0_4 4

OCR0_5

#define OCR0_5 5

OCR0_6

#define OCR0_6 6

OCR0_7

#define OCR0_7 7

TIMSK - Timer/Counter Interrupt Mask Register

sfrb TIMSK = $39;

OCIE0 - Timer/Counter0 Output Compare Match Interrupt register

#define OCIE0 0

When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, i.e. when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

TOIE0 - Timer/Counter0 Overflow Interrupt Enable

#define TOIE0 1

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e. when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

TIFR - Timer/Counter Interrupt Flag register

sfrb TIFR = $38;

OCF0 - Output Compare Flag 0

#define OCF0 0

The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0 and the data in OCR0 - Output Compare Register0. OCF0 is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF0 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare match Interrupt Enable), and OCF0 are set (one), the Timer/Counter0 Compare match Interrupt is executed.

TOV0 - Timer/Counter0 Overflow Flag

#define TOV0 1

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter0 changes counting direction at $00.

WATCHDOG

WDTCR - Watchdog Timer Control Register

sfrb WDTCR = $21;

WDP0 - Watch Dog Timer Prescaler bit 0

#define WDP0 0

The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.

WDP1 - Watch Dog Timer Prescaler bit 1

#define WDP1 1

The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.

WDP2 - Watch Dog Timer Prescaler bit 2

#define WDP2 2

The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.

WDE - Watch Dog Enable

#define WDE 3

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog

WDCE - Watchdog Change Enable

#define WDCE 4

This bit must be set when the WDE bit is written to logic zero.Otherwise,the watchdog will not be disabled.Once written to one,hardware will clear this bit after four clock cycles.Refer to the description of the WDE bit for a watchdog disable procedure.This bit must also be set when changing the prescaler bits.

PORTE

PORTE - Data Register, Port E

sfrb PORTE = $07;

PORTE0

#define PORTE0 0

PORTE1

#define PORTE1 1

PORTE2

#define PORTE2 2

DDRE -

sfrb DDRE = $06;

DDE0

#define DDE0 0

DDE1

#define DDE1 1

DDE2

#define DDE2 2

PINE - Input Pins, Port E

sfrb PINE = $05;

PINE0

#define PINE0 0

PINE1

#define PINE1 1

PINE2

#define PINE2 2

PINE3

#define PINE3 3

EXTERNAL INTERRUPT

MCUCR - MCU Control Register

sfrb MCUCR = $35;

ISC00 - Interrupt Sense Control 0 Bit 0

#define ISC00 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I flag and the corresponding interrupt mask are set.The level and edges on the external INT0 pin that activate the interrupt are defined below. The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt. (ISC01:ISC00) Description: (0:0) The low level of INT0 generates an interrupt request. (0:1) Any logical change on INT0 generates an interrupt request. (1:0) The falling edge of INT0 generates an interrupt request. (1:1) The rising edge of INT0 generates an interrupt request

ISC01 - Interrupt Sense Control 0 Bit 1

#define ISC01 1

ISC10 - Interrupt Sense Control 1 Bit 0

#define ISC10 2

The External Interrupt 1 is activated by the external pin INT1 if the SREG I bit and the corresponding interrupt mask in the GICR are set.The level and edges on the external INT1 pin that activate the interrupt are defined below.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt. (ISC11:ISC10) Description: (0:0) The low level of INT1 generates an interrupt request. (0:1) Any logical change on INT1 generates an interrupt request. (1:0) The falling edge of INT1 generates an interrupt request. (1:1) The rising edge of INT1 generates an interrupt reques

ISC11 - Interrupt Sense Control 1 Bit 1

#define ISC11 3

EMCUCR - Extended MCU Control Register

sfrb EMCUCR = $36;

ISC2 - Interrupt Sense Control 2

#define ISC2 0

The asynchronous external interrupt 2 is activated by the external pin INT2 if the SREG I-bit and the corresponding interrupt mask in GICR are set.If ISC2 is written to zero,a falling edge on INT2 activates the interrupt.If ISC2 is written to one,a rising edge on INT2 activates the interrupt.Edges on INT2 are registered asynchronously.Pulses on INT2 wider than the minimum pulse width given in Table 41 will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.When changing the ISC2 bit,an interrupt can occur.Therefore,it is recommended to first disable INT2 by clearing its Interrupt Enable bit in the GICR register.Then,the ISC2 bit can be changed.Finally, the INT2 interruptflag should be cleared by writing a logical one to its Interrupt Flag bit (INTF2)in the GIFR register before the interrupt is re-enabled.

GICR - General Interrupt Control Register

sfrb GICR = $3B;

IVCE - Interrupt Vector Change Enable

#define IVCE 0

The IVCE bit must be written to logic one to enable change of the IVSEL bit.IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.Setting the IVCE bit will disable interrupts.

IVSEL - Interrupt Vector Select

#define IVSEL 1

When the IVSEL bit is cleared (zero),the interrupt vectors are placed at the start of the Flash memory.When this bit is set (one),the interrupt vectors are moved to the beginning of the Boot Loader section of the flash.The actual address of the start of the boot flash section is determined by the BOOTSZ fuses.Refer to the section ?Boot Loader Support Read While Write self-programming ?on page 203 for details.To avoid unintentional changes of interrupt vector tables,a special write procedure must be followed to change the IVSEL bit: 1.Write the Interrupt Vector Change Enable (IVCE)bit to one. 2.Within four cycles,write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed.Interrupts are disabled in the cycle IVCE is set,and they remain disabled until after the instruction following the write to IVSEL.If IVSEL is not written,interrupts remain disabled for four cycles.The I-bit in the Status Register is unaffected by the automatic disabling. Note:If interrupt vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,interrupts are disabled while executing from the Application section.If interrupt vectors are placed in the Application section and Boot Lock bit BLB12 is programed,interrupts are disabled while executing from the Boot Loader section.Refer to the section ?Boot Loader Support -Read While Write self-programming ?on page 203 for details on Boot Lock bits

PCIE0 - Pin Change Interrupt Enable 0

#define PCIE0 3

When the PCIE0 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),

PCIE1 - Pin Change Interrupt Enable 1

#define PCIE1 4

When the PCIE1 bit is set (one)and the I-bit in the Status Register (SREG)is set (one), pin change interrupt 1 is enabled.Any change on any enabled PCINT15..8 pin will cause an interrupt.The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 interrupt vector.PCINT15..8 pins are enabled individually by the PCMSK1 register.

INT2 - External Interrupt Request 2 Enable

#define INT2 5

INT0 - External Interrupt Request 0 Enable

#define INT0 6

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also ?External Interrupts.? ? Bits 5..0 - Res: Reserved bits

INT1 - External Interrupt Request 1 Enable

#define INT1 7

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory address $002. See also ?External Interrupts?.

GIFR - General Interrupt Flag Register

sfrb GIFR = $3A;

PCIF0 - Pin Change Interrupt Flag 0

#define PCIF0 3

When a logic change on any PCINT7..0 pin triggers an interrupt request,PCIF0 becomes set (one).If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.

PCIF1 - Pin Change Interrupt Flag 1

#define PCIF1 4

When a logic change on any PCINT15..8 pin triggers an interrupt request,PCIF1 becomes set (one).If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.

INTF2 - External Interrupt Flag 2

#define INTF2 5

When an event on the INT2 pin triggers an interrupt request,INTF2 becomes set (one).If the I bit in SREG and the INT2 bit in GICR are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt rou tine is executed.Alternatively,the flag can be cleared by writing a logical one to it.Note that when entering some sleep modes with the INT2 interrupt disabled,the input buffer on this pin will be disabled.This may cause a logic change in inter nal signals which will set the INTF2 flag

INTF0 - External Interrupt Flag 0

#define INTF0 6

When an event on the INT0 pin triggers an interrupt request,INTF0 becomes set (one).If the I bit in SREG and the INT0 bit in GICR are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt rou tine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt.

INTF1 - External Interrupt Flag 1

#define INTF1 7

When an event on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I bit in SREG and the INT1 bit in GICR are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT1 is configured as a level interrupt.

PCMSK1 - Pin Change Mask Register 1

sfrb PCMSK1 = $6C;

PCINT8 - Pin Change Enable Mask 8

#define PCINT8 0

PCINT9 - Pin Change Enable Mask 9

#define PCINT9 1

PCINT10 - Pin Change Enable Mask 10

#define PCINT10 2

PCINT11 - Pin Change Enable Mask 11

#define PCINT11 3

PCINT12 - Pin Change Enable Mask 12

#define PCINT12 4

PCINT13 - Pin Change Enable Mask 13

#define PCINT13 5

PCINT14 - Pin Change Enable Mask 14

#define PCINT14 6

PCINT15 - Pin Change Enable Mask 15

#define PCINT15 7

PCMSK0 - Pin Change Enable Mask

sfrb PCMSK0 = $6B;

PCINT0 - Pin Change Enable Mask 0

#define PCINT0 0

PCINT1 - Pin Change Enable Mask 1

#define PCINT1 1

PCINT2 - Pin Change Enable Mask 2

#define PCINT2 2

PCINT3 - Pin Change Enable Mask 3

#define PCINT3 3

PCINT4 - Pin Change Enable Mask 4

#define PCINT4 4

PCINT5 - Pin Change Enable Mask 5

#define PCINT5 5

PCINT6 - Pin Change Enable Mask 6

#define PCINT6 6

PCINT7 - Pin Change Enable Mask 7

#define PCINT7 7