<ATmega161.h>

This documentation was generated automatically from the AVR Studio part description file ATmega161.pdf.

ANALOG COMPARATOR

ACSR - Analog Comparator Control And Status Register

sfrb ACSR = $08;

ACIS0 - Analog Comparator Interrupt Mode Select bit 0

#define ACIS0 0

These bits determine which comparator events that trigger the Analog Comparator interrupt.

ACIS1 - Analog Comparator Interrupt Mode Select bit 1

#define ACIS1 1

These bits determine which comparator events that trigger the Analog Comparator interrupt.

ACIC - Analog Comparator Input Capture Enable

#define ACIC 2

When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the analog comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set

ACIE - Analog Comparator Interrupt Enable

#define ACIE 3

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.

ACI - Analog Comparator Interrupt Flag

#define ACI 4

This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

ACO - Analog Compare Output

#define ACO 5

The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.

AINBG - Analog Comparator Bandgap Select

#define AINBG 6

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See ?Internal Voltage Reference? on page 42.

ACD - Analog Comparator Disable

#define ACD 7

When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

SPI

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the device and peripheral devices or between several AVR devices. The SPI includes the following features: ? Full-duplex, 3-wire Synchronous Data Transfer ? Master or Slave Operation ? LSB First or MSB First Data Transfer ? Seven Programmable Bit Rates ? End of Transmission Interrupt Flag ? Write Collision Flag Protection ? Wake-up from Idle Mode ? Double Speed (CK/2) Master SPI Mode

SPDR - SPI Data Register

sfrb SPDR = $0F;

SPDR0 - SPI Data Register bit 0

#define SPDR0 0

SPDR1 - SPI Data Register bit 1

#define SPDR1 1

SPDR2 - SPI Data Register bit 2

#define SPDR2 2

SPDR3 - SPI Data Register bit 3

#define SPDR3 3

SPDR4 - SPI Data Register bit 4

#define SPDR4 4

SPDR5 - SPI Data Register bit 5

#define SPDR5 5

SPDR6 - SPI Data Register bit 6

#define SPDR6 6

SPDR7 - SPI Data Register bit 7

#define SPDR7 7

SPSR - SPI Status Register

sfrb SPSR = $0E;

SPI2X - Double SPI Speed Bit

#define SPI2X 0

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in master mode (see Table 71). This means that the minimum SCK period will be 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f ck / 4 or lower. The SPI interface on the ATmega104 is also used for program memory and EEPROM downloading or uploading. See page 253 for serial programming and verification.

WCOL - Write Collision Flag

#define WCOL 6

The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.

SPIF - SPI Interrupt Flag

#define SPIF 7

When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).

SPCR - SPI Control Register

sfrb SPCR = $0D;

SPR0 - SPI Clock Rate Select 0

#define SPR0 0

SPR1 - SPI Clock Rate Select 1

#define SPR1 1

CPHA - Clock Phase

#define CPHA 2

Refer to Figure 36 or Figure 37 for the functionality of this bit.

CPOL - Clock polarity

#define CPOL 3

When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.

MSTR - Master/Slave Select

#define MSTR 4

This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.

DORD - Data Order

#define DORD 5

When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.

SPE - SPI Enable

#define SPE 6

When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.

SPIE - SPI Interrupt Enable

#define SPIE 7

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.

USART0

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: ? Full Duplex Operation (Independent Serial Receive and Transmit Registers) ? Asynchronous or Synchronous Operation ? Master or Slave Clocked Synchronous Operation ? High Resolution Baud Rate Generator ? Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits ? Odd or Even Parity Generation and Parity Check Supported by Hardware ? Data OverRun Detection ? Framing Error Detection ? Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter ? Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete ? Multi-processor Communication Mode ? Double Speed Asynchronous Com

UDR0 - USART I/O Data Register

sfrb UDR0 = $0C;

UDR00 - USART I/O Data Register bit 0

#define UDR00 0

UDR01 - USART I/O Data Register bit 1

#define UDR01 1

UDR02 - USART I/O Data Register bit 2

#define UDR02 2

UDR03 - USART I/O Data Register bit 3

#define UDR03 3

UDR04 - USART I/O Data Register bit 4

#define UDR04 4

UDR05 - USART I/O Data Register bit 5

#define UDR05 5

UDR06 - USART I/O Data Register bit 6

#define UDR06 6

UDR07 - USART I/O Data Register bit 7

#define UDR07 7

UCSR0A - USART Control and Status Register A

sfrb UCSR0A = $0B;

MPCM0 - Multi-processor Communication Mode

#define MPCM0 0

This bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see ?Multi-processor Communication Mode? on page 152.

U2X0 - Double the USART transmission speed

#define U2X0 1

This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.

OR0 - Data overRun

#define OR0 3

This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR0 register is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0.

FE0 - Framing Error

#define FE0 4

This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.

UDRE0 - USART Data Register Empty

#define UDRE0 5

This bit is set (one) when a character written to UDR0 is transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDR0 in order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is r

TXC0 - USART Transmitt Complete

#define TXC0 6

This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to t

RXC0 - USART Receive Complete

#define RXC0 7

This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regardless of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDR0 in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.

UCSR0B - USART Control and Status Register B

sfrb UCSR0B = $0A;

TXB80 - Transmit Data Bit 8

#define TXB80 0

TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.

RXB80 - Receive Data Bit 8

#define RXB80 1

RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.

CHR90 - 9-Bit Character

#define CHR90 2

TXEN0 - Transmitter Enable

#define TXEN0 3

Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.

RXEN0 - Receiver Enable

#define RXEN0 4

Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.

UDR0IE0 - USART Data register Empty Interrupt Enable

#define UDR0IE0 5

Writing this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.

TXCIE0 - TX Complete Interrupt Enable

#define TXCIE0 6

Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.

RXCIE0 - RX Complete Interrupt Enable

#define RXCIE0 7

Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.

UBRR0 - USART Baud Rate Register Byte

sfrb UBRR0 = $09;

UBRR00 - USART Baud Rate Register bit 0

#define UBRR00 0

UBRR01 - USART Baud Rate Register bit 1

#define UBRR01 1

UBRR02 - USART Baud Rate Register bit 2

#define UBRR02 2

UBRR03 - USART Baud Rate Register bit 3

#define UBRR03 3

UBRR04 - USART Baud Rate Register bit 4

#define UBRR04 4

UBRR05 - USART Baud Rate Register bit 5

#define UBRR05 5

UBRR06 - USART Baud Rate Register bit 6

#define UBRR06 6

UBRR07 - USART Baud Rate Register bit 7

#define UBRR07 7

UBRRHI - High Byte Baud Rate Register

sfrb UBRRHI = $20;

UBRRHI00 - High Byte Baud Rate Register Port 0 Bit 0

#define UBRRHI00 0

UBRRHI01 - High Byte Baud Rate Register Port 0 Bit 1

#define UBRRHI01 1

UBRRHI02 - High Byte Baud Rate Register Port 0 Bit 2

#define UBRRHI02 2

UBRRHI03 - High Byte Baud Rate Register Port 0 Bit 3

#define UBRRHI03 3

USART1

UDR1 - USART I/O Data Register

sfrb UDR1 = $03;

UDR10 - USART I/O Data Register bit 0

#define UDR10 0

UDR11 - USART I/O Data Register bit 1

#define UDR11 1

UDR12 - USART I/O Data Register bit 2

#define UDR12 2

UDR13 - USART I/O Data Register bit 3

#define UDR13 3

UDR14 - USART I/O Data Register bit 4

#define UDR14 4

UDR15 - USART I/O Data Register bit 5

#define UDR15 5

UDR16 - USART I/O Data Register bit 6

#define UDR16 6

UDR17 - USART I/O Data Register bit 7

#define UDR17 7

UCSR1A - USART Control and Status Register A

sfrb UCSR1A = $02;

MPCM1 - Multi-processor Communication Mode

#define MPCM1 0

U2X1 - Double the USART transmission speed

#define U2X1 1

OR1 - Data overRun

#define OR1 3

This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR1 register is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR1E is read. The OR bit is cleared (zero) when data is received and transferred to UDR1.

FE1 - Framing Error

#define FE1 4

This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.

UDRE1 - USART Data Register Empty

#define UDRE1 5

This bit is set (one) when a character written to UDR1 is transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR1IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR1E is set. UDR1E is cleared by writing UDR1. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDR1 in order to clear UDR1E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR1E is set (one) during reset to indicate that the transmitter is

TXC1 - USART Transmitt Complete

#define TXC1 6

This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR1. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to

RXC1 - USART Receive Complete

#define RXC1 7

This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR1. The bit is set regardless of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR1. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDR1 in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.

UCSR1B - USART Control and Status Register B

sfrb UCSR1B = $01;

TXB81 - Transmit Data Bit 8

#define TXB81 0

TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR1.

RXB81 - Receive Data Bit 8

#define RXB81 1

RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR1.

CHR91 - 9-Bit Character

#define CHR91 2

TXEN1 - Transmitter Enable

#define TXEN1 3

RXEN1 - Receiver Enable

#define RXEN1 4

UDR1IE1 - USART Data register Empty Interrupt Enable

#define UDR1IE1 5

Writing this bit to one enables interrupt on the UDR1E flag. A Data Register Empty interrupt will be generated only if the UDR1IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR1E bit in UCSR1A is set.

TXCIE1 - TX Complete Interrupt Enable

#define TXCIE1 6

RXCIE1 - RX Complete Interrupt Enable

#define RXCIE1 7

UBRR1 - USART Baud Rate Register Byte

sfrb UBRR1 = $00;

UBRR10 - USART Baud Rate Register bit 0

#define UBRR10 0

UBRR11 - USART Baud Rate Register bit 1

#define UBRR11 1

UBRR12 - USART Baud Rate Register bit 2

#define UBRR12 2

UBRR13 - USART Baud Rate Register bit 3

#define UBRR13 3

UBRR14 - USART Baud Rate Register bit 4

#define UBRR14 4

UBRR15 - USART Baud Rate Register bit 5

#define UBRR15 5

UBRR16 - USART Baud Rate Register bit 6

#define UBRR16 6

UBRR17 - USART Baud Rate Register bit 7

#define UBRR17 7

UBRRHI - high Byte Baud Rate Register

sfrb UBRRHI = $20;

UBRRHI10 - High Byte Baud Rate Register Port 0 Bit 0

#define UBRRHI10 4

UBRRHI11 - High Byte Baud Rate Register Port 0 Bit 1

#define UBRRHI11 5

UBRRHI12 - High Byte Baud Rate Register Port 0 Bit 2

#define UBRRHI12 6

UBRRHI13 - High Byte Baud Rate Register Port 0 Bit 3

#define UBRRHI13 7

PORTA

PORTA - Port A Data Register

sfrb PORTA = $1B;

PORTA0 - Port A Data Register bit 0

#define PORTA0 0

PORTA1 - Port A Data Register bit 1

#define PORTA1 1

PORTA2 - Port A Data Register bit 2

#define PORTA2 2

PORTA3 - Port A Data Register bit 3

#define PORTA3 3

PORTA4 - Port A Data Register bit 4

#define PORTA4 4

PORTA5 - Port A Data Register bit 5

#define PORTA5 5

PORTA6 - Port A Data Register bit 6

#define PORTA6 6

PORTA7 - Port A Data Register bit 7

#define PORTA7 7

DDRA - Port A Data Direction Register

sfrb DDRA = $1A;

DDA0 - Data Direction Register, Port A, bit 0

#define DDA0 0

DDA1 - Data Direction Register, Port A, bit 1

#define DDA1 1

DDA2 - Data Direction Register, Port A, bit 2

#define DDA2 2

DDA3 - Data Direction Register, Port A, bit 3

#define DDA3 3

DDA4 - Data Direction Register, Port A, bit 4

#define DDA4 4

DDA5 - Data Direction Register, Port A, bit 5

#define DDA5 5

DDA6 - Data Direction Register, Port A, bit 6

#define DDA6 6

DDA7 - Data Direction Register, Port A, bit 7

#define DDA7 7

PINA - Port A Input Pins

sfrb PINA = $19;

PINA0 - Input Pins, Port A bit 0

#define PINA0 0

PINA1 - Input Pins, Port A bit 1

#define PINA1 1

PINA2 - Input Pins, Port A bit 2

#define PINA2 2

PINA3 - Input Pins, Port A bit 3

#define PINA3 3

PINA4 - Input Pins, Port A bit 4

#define PINA4 4

PINA5 - Input Pins, Port A bit 5

#define PINA5 5

PINA6 - Input Pins, Port A bit 6

#define PINA6 6

PINA7 - Input Pins, Port A bit 7

#define PINA7 7

PORTB

PORTB - Port B Data Register

sfrb PORTB = $18;

PORTB0 - Port B Data Register bit 0

#define PORTB0 0

PORTB1 - Port B Data Register bit 1

#define PORTB1 1

PORTB2 - Port B Data Register bit 2

#define PORTB2 2

PORTB3 - Port B Data Register bit 3

#define PORTB3 3

PORTB4 - Port B Data Register bit 4

#define PORTB4 4

PORTB5 - Port B Data Register bit 5

#define PORTB5 5

PORTB6 - Port B Data Register bit 6

#define PORTB6 6

PORTB7 - Port B Data Register bit 7

#define PORTB7 7

DDRB - Port B Data Direction Register

sfrb DDRB = $17;

DDB0 - Port B Data Direction Register bit 0

#define DDB0 0

DDB1 - Port B Data Direction Register bit 1

#define DDB1 1

DDB2 - Port B Data Direction Register bit 2

#define DDB2 2

DDB3 - Port B Data Direction Register bit 3

#define DDB3 3

DDB4 - Port B Data Direction Register bit 4

#define DDB4 4

DDB5 - Port B Data Direction Register bit 5

#define DDB5 5

DDB6 - Port B Data Direction Register bit 6

#define DDB6 6

DDB7 - Port B Data Direction Register bit 7

#define DDB7 7

PINB - Port B Input Pins

sfrb PINB = $16;

PINB0 - Port B Input Pins bit 0

#define PINB0 0

PINB1 - Port B Input Pins bit 1

#define PINB1 1

PINB2 - Port B Input Pins bit 2

#define PINB2 2

PINB3 - Port B Input Pins bit 3

#define PINB3 3

PINB4 - Port B Input Pins bit 4

#define PINB4 4

PINB5 - Port B Input Pins bit 5

#define PINB5 5

PINB6 - Port B Input Pins bit 6

#define PINB6 6

PINB7 - Port B Input Pins bit 7

#define PINB7 7

PORTC

PORTC - Port C Data Register

sfrb PORTC = $15;

PORTC0 - Port C Data Register bit 0

#define PORTC0 0

PORTC1 - Port C Data Register bit 1

#define PORTC1 1

PORTC2 - Port C Data Register bit 2

#define PORTC2 2

PORTC3 - Port C Data Register bit 3

#define PORTC3 3

PORTC4 - Port C Data Register bit 4

#define PORTC4 4

PORTC5 - Port C Data Register bit 5

#define PORTC5 5

PORTC6 - Port C Data Register bit 6

#define PORTC6 6

PORTC7 - Port C Data Register bit 7

#define PORTC7 7

DDRC - Port C Data Direction Register

sfrb DDRC = $14;

DDC0 - Port C Data Direction Register bit 0

#define DDC0 0

DDC1 - Port C Data Direction Register bit 1

#define DDC1 1

DDC2 - Port C Data Direction Register bit 2

#define DDC2 2

DDC3 - Port C Data Direction Register bit 3

#define DDC3 3

DDC4 - Port C Data Direction Register bit 4

#define DDC4 4

DDC5 - Port C Data Direction Register bit 5

#define DDC5 5

DDC6 - Port C Data Direction Register bit 6

#define DDC6 6

DDC7 - Port C Data Direction Register bit 7

#define DDC7 7

PINC - Port C Input Pins

sfrb PINC = $13;

PINC0 - Port C Input Pins bit 0

#define PINC0 0

PINC1 - Port C Input Pins bit 1

#define PINC1 1

PINC2 - Port C Input Pins bit 2

#define PINC2 2

PINC3 - Port C Input Pins bit 3

#define PINC3 3

PINC4 - Port C Input Pins bit 4

#define PINC4 4

PINC5 - Port C Input Pins bit 5

#define PINC5 5

PINC6 - Port C Input Pins bit 6

#define PINC6 6

PINC7 - Port C Input Pins bit 7

#define PINC7 7

PORTD

PORTD - Port D Data Register

sfrb PORTD = $12;

PORTD0 - Port D Data Register bit 0

#define PORTD0 0

PORTD1 - Port D Data Register bit 1

#define PORTD1 1

PORTD2 - Port D Data Register bit 2

#define PORTD2 2

PORTD3 - Port D Data Register bit 3

#define PORTD3 3

PORTD4 - Port D Data Register bit 4

#define PORTD4 4

PORTD5 - Port D Data Register bit 5

#define PORTD5 5

PORTD6 - Port D Data Register bit 6

#define PORTD6 6

PORTD7 - Port D Data Register bit 7

#define PORTD7 7

DDRD - Port D Data Direction Register

sfrb DDRD = $11;

DDD0 - Port D Data Direction Register bit 0

#define DDD0 0

DDD1 - Port D Data Direction Register bit 1

#define DDD1 1

DDD2 - Port D Data Direction Register bit 2

#define DDD2 2

DDD3 - Port D Data Direction Register bit 3

#define DDD3 3

DDD4 - Port D Data Direction Register bit 4

#define DDD4 4

DDD5 - Port D Data Direction Register bit 5

#define DDD5 5

DDD6 - Port D Data Direction Register bit 6

#define DDD6 6

DDD7 - Port D Data Direction Register bit 7

#define DDD7 7

PIND - Port D Input Pins

sfrb PIND = $10;

PIND0 - Port D Input Pins bit 0

#define PIND0 0

PIND1 - Port D Input Pins bit 1

#define PIND1 1

PIND2 - Port D Input Pins bit 2

#define PIND2 2

PIND3 - Port D Input Pins bit 3

#define PIND3 3

PIND4 - Port D Input Pins bit 4

#define PIND4 4

PIND5 - Port D Input Pins bit 5

#define PIND5 5

PIND6 - Port D Input Pins bit 6

#define PIND6 6

PIND7 - Port D Input Pins bit 7

#define PIND7 7

PORTE

PORTE - Port E Data Register

sfrb PORTE = $07;

PORTE0

#define PORTE0 0

PORTE1

#define PORTE1 1

PORTE2

#define PORTE2 2

DDRE - Port E Data Direction Register

sfrb DDRE = $06;

DDE0

#define DDE0 0

DDE1

#define DDE1 1

DDE2

#define DDE2 2

PINE - Port E Input Pins

sfrb PINE = $05;

PINE0

#define PINE0 0

PINE1

#define PINE1 1

PINE2

#define PINE2 2

EEPROM

EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See ?Preventing EEPROM Corruption? on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execute

EEARH - EEPROM Address Register High Byte

sfrb EEARH = $1F;

EEAR8 - EEPROM Read/Write Access Bit 8

#define EEAR8 0

EEARL - EEPROM Address Register Low Byte

sfrb EEARL = $1E;

EEAR0 - EEPROM Read/Write Access Bit 0

#define EEAR0 0

EEAR1 - EEPROM Read/Write Access Bit 1

#define EEAR1 1

EEAR2 - EEPROM Read/Write Access Bit 2

#define EEAR2 2

EEAR3 - EEPROM Read/Write Access Bit 3

#define EEAR3 3

EEAR4 - EEPROM Read/Write Access Bit 4

#define EEAR4 4

EEAR5 - EEPROM Read/Write Access Bit 5

#define EEAR5 5

EEAR6 - EEPROM Read/Write Access Bit 6

#define EEAR6 6

EEAR7 - EEPROM Read/Write Access Bit 7

#define EEAR7 7

EEDR - EEPROM Data Register

sfrb EEDR = $1D;

EEDR0 - EEPROM Data Register bit 0

#define EEDR0 0

EEDR1 - EEPROM Data Register bit 1

#define EEDR1 1

EEDR2 - EEPROM Data Register bit 2

#define EEDR2 2

EEDR3 - EEPROM Data Register bit 3

#define EEDR3 3

EEDR4 - EEPROM Data Register bit 4

#define EEDR4 4

EEDR5 - EEPROM Data Register bit 5

#define EEDR5 5

EEDR6 - EEPROM Data Register bit 6

#define EEDR6 6

EEDR7 - EEPROM Data Register bit 7

#define EEDR7 7

EECR - EEPROM Control Register

sfrb EECR = $1C;

EERE - EEPROM Read Enable

#define EERE 0

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU

EEWE - EEPROM Write Enable

#define EEWE 1

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See ?Boot Loader Support - Read While Write self-programming? on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed

EEMWE - EEPROM Master Write Enable

#define EEMWE 2

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

EERIE - EEPROM Ready Interrupt Enable

#define EERIE 3

EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.

EXTERNAL INTERRUPT

GIMSK - General Interrupt Mask Register

sfrb GIMSK = $3B;

INT2 - External Interrupt Request 2 Enable

#define INT2 5

INT0 - External Interrupt Request 0 Enable

#define INT0 6

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also ?External Interrupts.? ? Bits 5..0 - Res: Reserved bits

INT1 - External Interrupt Request 1 Enable

#define INT1 7

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory address $002. See also ?External Interrupts?.

GIFR - General Interrupt Flag Register

sfrb GIFR = $3A;

INTF2 - External Interrupt Flag 2

#define INTF2 5

When an event on the INT2 pin triggers an interrupt request,INTF2 becomes set (one).If the I bit in SREG and the INT2 bit in GICR are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt rou tine is executed.Alternatively,the flag can be cleared by writing a logical one to it.Note that when entering some sleep modes with the INT2 interrupt disabled,the input buffer on this pin will be disabled.This may cause a logic change in inter nal signals which will set the INTF2 flag

INTF0 - External Interrupt Flag 0

#define INTF0 6

When an event on the INT0 pin triggers an interrupt request,INTF0 becomes set (one).If the I bit in SREG and the INT0 bit in GICR are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt rou tine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt.

INTF1 - External Interrupt Flag 1

#define INTF1 7

When an event on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I bit in SREG and the INT1 bit in GICR are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT1 is configured as a level interrupt.

CPU

SREG - Status Register

sfrb SREG = $3F;

SPH - Stack Pointer High

sfrb SPH = $3E;

SP8 - Stack pointer bit 8

#define SP8 0

SP9 - Stack pointer bit 9

#define SP9 1

SP10 - Stack pointer bit 10

#define SP10 2

SP11 - Stack pointer bit 11

#define SP11 3

SP12

#define SP12 4

SP13 - Stack pointer bit 13

#define SP13 5

SP14 - Stack pointer bit 14

#define SP14 6

SP15 - Stack pointer bit 15

#define SP15 7

SPL - Stack Pointer Low

sfrb SPL = $3D;

SP0 - Stack pointer bit 0

#define SP0 0

SP1 - Stack pointer bit 1

#define SP1 1

SP2 - Stack pointer bit 2

#define SP2 2

SP3 - Stack pointer bit 3

#define SP3 3

SP4

#define SP4 4

SP5 - Stack pointer bit 5

#define SP5 5

SP6 - Stack pointer bit 6

#define SP6 6

SP7 - Stack pointer bit 7

#define SP7 7

MCUCR - MCU Control Register

sfrb MCUCR = $35;

ISC00 - Interrupt Sense Control 0 bit 0

#define ISC00 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt.

ISC01 - Interrupt Sense Control 0 bit 1

#define ISC01 1

ISC10 - Interrupt Sense Control 1 bit 1

#define ISC10 2

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-bit and the corresponding interrupt mask in the GICR are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt.

ISC11 - Interrupt Sense Control 1 bit 1

#define ISC11 3

SM1 - Sleep Mode Select

#define SM1 4

The description is to long for the tooltip help, please refer to the manual

SE - Sleep Enable

#define SE 5

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.To avoid the MCU entering the sleep mode unless it is the programmers purpose,it is recommended to write the Sleep Enable (SE)bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up.

SRW10 - External SRAM Wait State Select

#define SRW10 6

For a detailed description in non ATmega103 Compatibility mode, see common description for the SRWn bits below (XMRA description). In ATmega103 Compatibility mode, writing SRW10 to one enables the wait state and one extra cycle is added during read/write strobe as shown in Figure 14.

SRE - External SRAM Enable

#define SRE 7

Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are acti-vated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction regis-ters. Writing SRE to zero, disables the External Memory Interface and the normal pin and data direction settings are used.

MCUSR - MCU Status Register

sfrb MCUSR = $34;

PORF - Power-on reset flag

#define PORF 0

This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.

EXTRF - External Reset Flag

#define EXTRF 1

This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

BORF - Brown-out Reset Flag

#define BORF 2

This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

WDRF - Watchdog Reset Flag

#define WDRF 3

This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

EMCUCR - Extended MCU Control Register

sfrb EMCUCR = $36;

ISC2 - Interrupt Sense Control 2

#define ISC2 0

The asynchronous external interrupt 2 is activated by the external pin INT2 if the SREG I-bit and the corresponding interrupt mask in GICR are set.If ISC2 is written to zero,a falling edge on INT2 activates the interrupt.If ISC2 is written to one,a rising edge on INT2 activates the interrupt.Edges on INT2 are registered asynchronously.Pulses on INT2 wider than the minimum pulse given width will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.When changing the ISC2 bit,an interrupt can occur.Therefore,it is recommended to first disable INT2 by clearing its Interrupt Enable bit in the GICR register.Then,the ISC2 bit can be changed.Finally, the INT2 interruptflag should becleared by writing a logical one to its Interrupt Flagbit (INTF2)in the GIFR register before the interrupt is re-enabled.

SRW11 - Wait State Select Bit 1 for Upper Sector

#define SRW11 1

The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the external memory address space.

SRW00 - Wait State Select Bit 0 for Lower Sector

#define SRW00 2

The SRW00 and SRW01 bits control the number of wait-states for the upper sector of the external memory address space.

SRW01 - Wait State Select Bit 1 for Lower Sector

#define SRW01 3

The SRW00 and SRW01 bits control the number of wait-states for the upper sector of the external memory address space.

SRL0 - Wait State Sector Limit Bit 0

#define SRL0 4

It is possible to configure different wait-states for different external memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits.The SRL2,SRL1,and SRL0 bits select the splitting of these sectors. By default,the SRL2,SRL1,and SRL0 bits are set to zero and the entire external memory address space is treated as one sector.When the entire SRAM address space is configured as one sector,the wait-states are configured by the SRW11 and SRW10 bits.

SRL1 - Wait State Sector Limit Bit 1

#define SRL1 5

SRL2 - Wait State Sector Limit Bit 2

#define SRL2 6

SM0 - Sleep mode Select Bit 0

#define SM0 7

The Sleep Mode Select bits select between the five available sleep modes. See Datasheet.

SPMCR - Store Program Memory Control Register

sfrb SPMCR = $37;

SPMEN - Store Program Memory Enable

#define SPMEN 0

PGERS - Page Erase

#define PGERS 1

PGWRT - Page Write

#define PGWRT 2

BLBSET - Boot Lock Bit Set

#define BLBSET 3

TIMER COUNTER 0

TCCR0 - Timer/Counter Control Register

sfrb TCCR0 = $33;

CS00 - Clock Select 1

#define CS00 0

The three clock select bits select the clock source to be used by the Timer/Counter,

CS01 - Clock Select 1

#define CS01 1

The three clock select bits select the clock source to be used by the Timer/Counter,

CS02 - Clock Select 2

#define CS02 2

The three clock select bits select the clock source to be used by the Timer/Counter,

WGM01 - Waveform Generation Mode 1

#define WGM01 3

These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 51 and ?Modes of Operation? on page 80.

COM00 - Compare match Output Mode 0

#define COM00 4

These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set in order to enable the output driver. When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 52 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM)

COM01 - Compare Match Output Mode 1

#define COM01 5

WGM00 - Waveform Generation Mode 0

#define WGM00 6

FOC0 - Force Output Compare

#define FOC0 7

The FOC0 bit is only active when the WGM bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode. When writing a logical one to the FOC0 bit, an immediate compare match is forced on the waveform generation unit. The OC0 output is changed accord-ing to its COM01:0 bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the value present in the COM01:0 bits that determines the effect of the forced compare. A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0 as TOP. The FOC0 bit is always read as zero.

TCNT0 - Timer/Counter Register

sfrb TCNT0 = $32;

TCNT0_0

#define TCNT0_0 0

TCNT0_1

#define TCNT0_1 1

TCNT0_2

#define TCNT0_2 2

TCNT0_3

#define TCNT0_3 3

TCNT0_4

#define TCNT0_4 4

TCNT0_5

#define TCNT0_5 5

TCNT0_6

#define TCNT0_6 6

TCNT0_7

#define TCNT0_7 7

OCR0 - Output Compare Register

sfrb OCR0 = $31;

OCR0_0

#define OCR0_0 0

OCR0_1

#define OCR0_1 1

OCR0_2

#define OCR0_2 2

OCR0_3

#define OCR0_3 3

OCR0_4

#define OCR0_4 4

OCR0_5

#define OCR0_5 5

OCR0_6

#define OCR0_6 6

OCR0_7

#define OCR0_7 7

TIMSK - Timer/Counter Interrupt Mask Register

sfrb TIMSK = $39;

OCIE0 - Timer/Counter0 Output Compare Match Interrupt register

#define OCIE0 0

When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, i.e. when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

TOIE0 - Timer/Counter0 Overflow Interrupt Enable

#define TOIE0 1

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e. when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

TIFR - Timer/Counter Interrupt Flag register

sfrb TIFR = $38;

OCF0 - Output Compare Flag 0

#define OCF0 0

The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0 and the data in OCR0 - Output Compare Register0. OCF0 is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF0 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare match Interrupt Enable), and OCF0 are set (one), the Timer/Counter0 Compare match Interrupt is executed.

TOV0 - Timer/Counter0 Overflow Flag

#define TOV0 1

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter0 changes counting direction at $00.

SFIOR - Special Function IO Register

sfrb SFIOR = $30;

PSR10 - Prescaler Reset Timer/Counter1 and Timer/Counter0

#define PSR10 0

When this bit is set (one)the Timer/Counter1 and Timer/Counter0 prescaler will be reset.The bit will be cleared by hard ware after the operation is performed.Writing a zero to this bit will have no effect.Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.This bit will always be read as zero.

TIMER COUNTER 2

The 8-bit Timer/Counter2 can select clock source from CK, prescaled CK, or external crystal input TOSC1. It can also be stopped as described in the section ?Timer/Counter2 Control Register - TCCR2?. The status flags (overflow and compare match) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Register TCCR2. The interrupt enable/disable settings are found in ?The Timer/Counter Interrupt Mask Register - TIMSK?. When Timer/Counter2 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. This module features a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. Timer/Counter2 can also be used as an 8-bit Pulse Width Modulator. In this mode, Timer/Counter2 and the output compare register serve as a glitch-free, stand-alone PWM with centered puls

TIMSK - Timer/Counter Interrupt Mask register

sfrb TIMSK = $39;

OCIE2 - Timer/Counter2 Output Compare Match Interrupt Enable

#define OCIE2 2

When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt (at vector $006) is executed if a compare match in Timer/Counter2 occurs, i.e. when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

TOIE2 - Timer/Counter2 Overflow Interrupt Enable

#define TOIE2 4

When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is

TIFR - Timer/Counter Interrupt Flag Register

sfrb TIFR = $38;

OCF2 - Output Compare Flag 2

#define OCF2 2

The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2 - Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2 Compare match Interrupt Enable), and the OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed.

TOV2 - Timer/Counter2 Overflow Flag

#define TOV2 4

The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In up/down PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00.

TCCR2 - Timer/Counter2 Control Register

sfrb TCCR2 = $27;

CS20 - Clock Select bit 0

#define CS20 0

The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.

CS21 - Clock Select bit 1

#define CS21 1

CS22 - Clock Select bit 2

#define CS22 2

CTC2 - Clear Timer/Counter2 on Compare Match

#define CTC2 3

These bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information.

COM20 - Compare Output Mode bit 0

#define COM20 4

The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function

COM21 - Compare Output Mode bit 1

#define COM21 5

PWM2 - Pulse Width Modulator Enable

#define PWM2 6

FOC2 - Force Output Compare

#define FOC2 7

Writing a logical one to this bit, forces a change in the compare match output pin PD7 (OC2) according to the values already set in COM21 and COM20. If the COM21 and COM20 bits are written in the same cycle as FOC2, the new settings will not take effect until next compare match or forced output compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM21 and COM20 happens as if a Compare Match had occurred, but no interrupt is generated, and the Timer/Counter will not be cleared even if CTC2 is set. The corresponding I/O pin must be set as an output pin for the FOC2 bit to have effect on the pin. The FOC2 bit will always be read as zero. Setting the FOC2 bit has no effect in PWM mode

TCNT2 - Timer/Counter2

sfrb TCNT2 = $23;

TCNT2-0 - Timer/Counter 2 bit 0

#define TCNT2-0 0

TCNT2-1 - Timer/Counter 2 bit 1

#define TCNT2-1 1

TCNT2-2 - Timer/Counter 2 bit 2

#define TCNT2-2 2

TCNT2-3 - Timer/Counter 2 bit 3

#define TCNT2-3 3

TCNT2-4 - Timer/Counter 2 bit 4

#define TCNT2-4 4

TCNT2-5 - Timer/Counter 2 bit 5

#define TCNT2-5 5

TCNT2-6 - Timer/Counter 2 bit 6

#define TCNT2-6 6

TCNT2-7 - Timer/Counter 2 bit 7

#define TCNT2-7 7

OCR2 - Timer/Counter2 Output Compare Register

sfrb OCR2 = $22;

OCR2-0 - Timer/Counter2 Output Compare Register Bit 0

#define OCR2-0 0

OCR2-1 - Timer/Counter2 Output Compare Register Bit 1

#define OCR2-1 1

OCR2-2 - Timer/Counter2 Output Compare Register Bit 2

#define OCR2-2 2

OCR2-3 - Timer/Counter2 Output Compare Register Bit 3

#define OCR2-3 3

OCR2-4 - Timer/Counter2 Output Compare Register Bit 4

#define OCR2-4 4

OCR2-5 - Timer/Counter2 Output Compare Register Bit 5

#define OCR2-5 5

OCR2-6 - Timer/Counter2 Output Compare Register Bit 6

#define OCR2-6 6

OCR2-7 - Timer/Counter2 Output Compare Register Bit 7

#define OCR2-7 7

ASSR - Asynchronous Status Register

sfrb ASSR = $26;

TCR2UB - Timer/counter Control Register2 Update Busy

#define TCR2UB 0

When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set (one). When TCCR2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that TCCR2 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter2 registers while its update busy flag is set (one), the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary storage register is rea

OCR2UB - Output Compare Register2 Update Busy

#define OCR2UB 1

When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set (one). When OCR2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that OCR2 is ready to be updated with a new value.

TCN2UB - Timer/Counter2 Update Busy

#define TCN2UB 2

When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set (one). When TCNT2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.

AS2 - Asynchronous Timer/counter2

#define AS2 3

When AS2 is cleared (zero), Timer/Counter2 is clocked from the internal system clock, CK. When AS2 is set (one), Timer/Counter2 is clocked from the PC6(TOSC1) pin. Pins PC6 and PC7 are connected to a crystal oscillator and cannot be used as general I/O pins. When the value of this bit is changed, the contents of TCNT2, OCR2, and TCCR2 might be corrupted.

SFIOR - Specil Function IO Register

sfrb SFIOR = $30;

PSR2 - Prescaler Reset Timer/Counter2

#define PSR2 1

When this bit is set (one)the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.

TIMER COUNTER 1

TIMSK - Timer/Counter Interrupt Mask Register

sfrb TIMSK = $39;

TICIE1 - Timer/Counter1 Input Capture Interrupt Enable

#define TICIE1 3

When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE1B - Timer/Counter1 Output CompareB Match Interrupt Enable

#define OCIE1B 5

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

OCIE1A - Timer/Counter1 Output CompareA Match Interrupt Enable

#define OCIE1A 6

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

TOIE1 - Timer/Counter1 Overflow Interrupt Enable

#define TOIE1 7

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

TIFR - Timer/Counter Interrupt Flag register

sfrb TIFR = $38;

ICF1 - Input Capture Flag 1

#define ICF1 3

The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.

OCF1B - Output Compare Flag 1B

#define OCF1B 5

The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.

OCF1A - Output Compare Flag 1A

#define OCF1A 6

The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed.

TOV1 - Timer/Counter1 Overflow Flag

#define TOV1 7

The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.

TCCR1A - Timer/Counter1 Control Register A

sfrb TCCR1A = $2F;

WGM10 - Waveform Generation Mode

#define WGM10 0

Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.

WGM11 - Waveform Generation Mode

#define WGM11 1

FOC1B - Force Output Compare 1B

#define FOC1B 2

Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM1B1 and COM1B0.If the COM1B1 and COM1B0 bits are written in the same cycle as FOC1B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1B1 and COM1B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC1B bit to have effect on the pin. The FOC1B bit will always be read as zero. The setting of the FOC1B bit has no effect in PWM mode

FOC1A - Force Output Compare 1A

#define FOC1A 3

Writing a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM1A1 and COM1A0.If the COM1A1 and COM1A0 bits are written in the same cycle as FOC1A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1A1 and COM1A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC1 in TCCR1B is set. The corresponding I/O pin must be set as an output pin for the FOC1A bit to have effect on the pin. The FOC1A bit will always be read as zero. The setting of the FOC1A bit has no effect in PWM mod

COM1B0 - Compare Output Mode 1B, bit 0

#define COM1B0 4

The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.

COM1B1 - Compare Output Mode 1B, bit 1

#define COM1B1 5

COM1A0 - Comparet Ouput Mode 1A, bit 0

#define COM1A0 6

The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.

COM1A1 - Compare Output Mode 1A, bit 1

#define COM1A1 7

TCCR1B - Timer/Counter1 Control Register B

sfrb TCCR1B = $2E;

CS10 - Prescaler source of Timer/Counter 1

#define CS10 0

Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.

CS11 - Prescaler source of Timer/Counter 1

#define CS11 1

CS12 - Prescaler source of Timer/Counter 1

#define CS12 2

CTC1 - Clear Timer/Counter1 on Compare Match

#define CTC1 3

ICES1 - Input Capture 1 Edge Select

#define ICES1 6

While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.

ICNC1 - Input Capture 1 Noise Canceler

#define ICNC1 7

When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.

TCNT1H - Timer/Counter1 High Byte

sfrb TCNT1H = $2D;

TCNT1H0 - Timer/Counter1 High Byte bit 0

#define TCNT1H0 0

TCNT1H1 - Timer/Counter1 High Byte bit 1

#define TCNT1H1 1

TCNT1H2 - Timer/Counter1 High Byte bit 2

#define TCNT1H2 2

TCNT1H3 - Timer/Counter1 High Byte bit 3

#define TCNT1H3 3

TCNT1H4 - Timer/Counter1 High Byte bit 4

#define TCNT1H4 4

TCNT1H5 - Timer/Counter1 High Byte bit 5

#define TCNT1H5 5

TCNT1H6 - Timer/Counter1 High Byte bit 6

#define TCNT1H6 6

TCNT1H7 - Timer/Counter1 High Byte bit 7

#define TCNT1H7 7

TCNT1L - Timer/Counter1 Low Byte

sfrb TCNT1L = $2C;

TCNT1L0 - Timer/Counter1 Low Byte bit 0

#define TCNT1L0 0

TCNT1L1 - Timer/Counter1 Low Byte bit 1

#define TCNT1L1 1

TCNT1L2 - Timer/Counter1 Low Byte bit 2

#define TCNT1L2 2

TCNT1L3 - Timer/Counter1 Low Byte bit 3

#define TCNT1L3 3

TCNT1L4 - Timer/Counter1 Low Byte bit 4

#define TCNT1L4 4

TCNT1L5 - Timer/Counter1 Low Byte bit 5

#define TCNT1L5 5

TCNT1L6 - Timer/Counter1 Low Byte bit 6

#define TCNT1L6 6

TCNT1L7 - Timer/Counter1 Low Byte bit 7

#define TCNT1L7 7

OCR1AH - Timer/Counter1 Outbut Compare Register High Byte

sfrb OCR1AH = $2B;

OCR1AH0 - Timer/Counter1 Outbut Compare Register High Byte bit 0

#define OCR1AH0 0

OCR1AH1 - Timer/Counter1 Outbut Compare Register High Byte bit 1

#define OCR1AH1 1

OCR1AH2 - Timer/Counter1 Outbut Compare Register High Byte bit 2

#define OCR1AH2 2

OCR1AH3 - Timer/Counter1 Outbut Compare Register High Byte bit 3

#define OCR1AH3 3

OCR1AH4 - Timer/Counter1 Outbut Compare Register High Byte bit 4

#define OCR1AH4 4

OCR1AH5 - Timer/Counter1 Outbut Compare Register High Byte bit 5

#define OCR1AH5 5

OCR1AH6 - Timer/Counter1 Outbut Compare Register High Byte bit 6

#define OCR1AH6 6

OCR1AH7 - Timer/Counter1 Outbut Compare Register High Byte bit 7

#define OCR1AH7 7

OCR1AL - Timer/Counter1 Outbut Compare Register Low Byte

sfrb OCR1AL = $2A;

OCR1AL0 - Timer/Counter1 Outbut Compare Register Low Byte Bit 0

#define OCR1AL0 0

OCR1AL1 - Timer/Counter1 Outbut Compare Register Low Byte Bit 1

#define OCR1AL1 1

OCR1AL2 - Timer/Counter1 Outbut Compare Register Low Byte Bit 2

#define OCR1AL2 2

OCR1AL3 - Timer/Counter1 Outbut Compare Register Low Byte Bit 3

#define OCR1AL3 3

OCR1AL4 - Timer/Counter1 Outbut Compare Register Low Byte Bit 4

#define OCR1AL4 4

OCR1AL5 - Timer/Counter1 Outbut Compare Register Low Byte Bit 5

#define OCR1AL5 5

OCR1AL6 - Timer/Counter1 Outbut Compare Register Low Byte Bit 6

#define OCR1AL6 6

OCR1AL7 - Timer/Counter1 Outbut Compare Register Low Byte Bit 7

#define OCR1AL7 7

OCR1BH - Timer/Counter1 Output Compare Register High Byte

sfrb OCR1BH = $29;

OCR1BH0 - Timer/Counter1 Output Compare Register High Byte bit 0

#define OCR1BH0 0

OCR1BH1 - Timer/Counter1 Output Compare Register High Byte bit 1

#define OCR1BH1 1

OCR1BH2 - Timer/Counter1 Output Compare Register High Byte bit 2

#define OCR1BH2 2

OCR1BH3 - Timer/Counter1 Output Compare Register High Byte bit 3

#define OCR1BH3 3

OCR1BH4 - Timer/Counter1 Output Compare Register High Byte bit 4

#define OCR1BH4 4

OCR1BH5 - Timer/Counter1 Output Compare Register High Byte bit 5

#define OCR1BH5 5

OCR1BH6 - Timer/Counter1 Output Compare Register High Byte bit 6

#define OCR1BH6 6

OCR1BH7 - Timer/Counter1 Output Compare Register High Byte bit 7

#define OCR1BH7 7

OCR1BL - Timer/Counter1 Output Compare Register Low Byte

sfrb OCR1BL = $28;

OCR1BL0 - Timer/Counter1 Output Compare Register Low Byte bit 0

#define OCR1BL0 0

OCR1BL1 - Timer/Counter1 Output Compare Register Low Byte bit 1

#define OCR1BL1 1

OCR1BL2 - Timer/Counter1 Output Compare Register Low Byte bit 2

#define OCR1BL2 2

OCR1BL3 - Timer/Counter1 Output Compare Register Low Byte bit 3

#define OCR1BL3 3

OCR1BL4 - Timer/Counter1 Output Compare Register Low Byte bit 4

#define OCR1BL4 4

OCR1BL5 - Timer/Counter1 Output Compare Register Low Byte bit 5

#define OCR1BL5 5

OCR1BL6 - Timer/Counter1 Output Compare Register Low Byte bit 6

#define OCR1BL6 6

OCR1BL7 - Timer/Counter1 Output Compare Register Low Byte bit 7

#define OCR1BL7 7

ICR1H - Timer/Counter1 Input Capture Register High Byte

sfrb ICR1H = $25;

ICR1H0 - Timer/Counter1 Input Capture Register High Byte bit 0

#define ICR1H0 0

ICR1H1 - Timer/Counter1 Input Capture Register High Byte bit 1

#define ICR1H1 1

ICR1H2 - Timer/Counter1 Input Capture Register High Byte bit 2

#define ICR1H2 2

ICR1H3 - Timer/Counter1 Input Capture Register High Byte bit 3

#define ICR1H3 3

ICR1H4 - Timer/Counter1 Input Capture Register High Byte bit 4

#define ICR1H4 4

ICR1H5 - Timer/Counter1 Input Capture Register High Byte bit 5

#define ICR1H5 5

ICR1H6 - Timer/Counter1 Input Capture Register High Byte bit 6

#define ICR1H6 6

ICR1H7 - Timer/Counter1 Input Capture Register High Byte bit 7

#define ICR1H7 7

ICR1L - Timer/Counter1 Input Capture Register Low Byte

sfrb ICR1L = $24;

ICR1L0 - Timer/Counter1 Input Capture Register Low Byte bit 0

#define ICR1L0 0

ICR1L1 - Timer/Counter1 Input Capture Register Low Byte bit 1

#define ICR1L1 1

ICR1L2 - Timer/Counter1 Input Capture Register Low Byte bit 2

#define ICR1L2 2

ICR1L3 - Timer/Counter1 Input Capture Register Low Byte bit 3

#define ICR1L3 3

ICR1L4 - Timer/Counter1 Input Capture Register Low Byte bit 4

#define ICR1L4 4

ICR1L5 - Timer/Counter1 Input Capture Register Low Byte bit 5

#define ICR1L5 5

ICR1L6 - Timer/Counter1 Input Capture Register Low Byte bit 6

#define ICR1L6 6

ICR1L7 - Timer/Counter1 Input Capture Register Low Byte bit 7

#define ICR1L7 7

WATCHDOG

WDTCR - Watchdog Timer Control Register

sfrb WDTCR = $21;

WDP0 - Watch Dog Timer Prescaler bit 0

#define WDP0 0

WDP1 - Watch Dog Timer Prescaler bit 1

#define WDP1 1

WDP2 - Watch Dog Timer Prescaler bit 2

#define WDP2 2

WDE - Watch Dog Enable

#define WDE 3

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog

WDTOE - RW

#define WDTOE 4

This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.