This documentation was generated automatically from the AVR Studio part description file ATmega128.pdf.
sfrb SFIOR = 0x20;
#define ACME 3
When this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see ?Analog Comparator Multiplexed Input? on page 186.
sfrb ACSR = 0x08;
#define ACIS0 0
These bits determine which comparator events that trigger the Analog Comparator interrupt.
#define ACIS1 1
These bits determine which comparator events that trigger the Analog Comparator interrupt.
#define ACIC 2
When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the analog comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set
#define ACIE 3
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.
#define ACI 4
This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
#define ACO 5
The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.
#define ACBG 6
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See ?Internal Voltage Reference? on page 42.
#define ACD 7
When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode Noise
sfrb ADMUX = 0x07;
#define MUX0 0
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
#define MUX1 1
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
#define MUX2 2
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
#define MUX3 3
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
#define MUX4 4
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
#define ADLAR 5
The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see ?The ADC Data Register -ADCL and ADCH? on page 198.
#define REFS0 6
These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.
#define REFS1 7
These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.
sfrb ADCSRA = 0x06;
#define ADPS0 0
These bits determine the division factor between the XTAL frequency and the input clock to the ADC.
#define ADPS1 1
These bits determine the division factor between the XTAL frequency and the input clock to the ADC.
#define ADPS2 2
These bits determine the division factor between the XTAL frequency and the input clock to the ADC.
#define ADIE 3
When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.
#define ADIF 4
This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.
#define ADFR 5
When this bit is set (one) the ADC operates in Free Running Mode. In this mode, the ADC samples and updates the data registers continuously. Clearing this bit (zero) will terminate Free Running Mode.
#define ADSC 6
In Single Conversion Mode, a logical ?1? must be written to this bit to start each conversion. In Free Running Mode, a logical ?1? must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect
#define ADEN 7
Writing a logical ?1? to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
sfrb ADCH = 0x05;
#define ADCH0 0
#define ADCH1 1
#define ADCH2 2
#define ADCH3 3
#define ADCH4 4
#define ADCH5 5
#define ADCH6 6
#define ADCH7 7
sfrb ADCL = 0x04;
#define ADCL0 0
#define ADCL1 1
#define ADCL2 2
#define ADCL3 3
#define ADCL4 4
#define ADCL5 5
#define ADCL6 6
#define ADCL7 7
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the device and peripheral devices or between several AVR devices. The SPI includes the following features: ? Full-duplex, 3-wire Synchronous Data Transfer ? Master or Slave Operation ? LSB First or MSB First Data Transfer ? Seven Programmable Bit Rates ? End of Transmission Interrupt Flag ? Write Collision Flag Protection ? Wake-up from Idle Mode ? Double Speed (CK/2) Master SPI Mode
sfrb SPDR = 0x0F;
#define SPDR0 0
#define SPDR1 1
#define SPDR2 2
#define SPDR3 3
#define SPDR4 4
#define SPDR5 5
#define SPDR6 6
#define SPDR7 7
sfrb SPSR = 0x0E;
#define SPI2X 0
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in master mode (see Table 71). This means that the minimum SCK period will be 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f ck / 4 or lower. The SPI interface on the ATmega104 is also used for program memory and EEPROM downloading or uploading. See page 253 for serial programming and verification.
#define WCOL 6
The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.
#define SPIF 7
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).
sfrb SPCR = 0x0D;
#define SPR0 0
#define SPR1 1
#define CPHA 2
Refer to Figure 36 or Figure 37 for the functionality of this bit.
#define CPOL 3
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.
#define MSTR 4
This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.
#define DORD 5
When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.
#define SPE 6
When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.
#define SPIE 7
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.
TWI: Simple yet powerful and flexible communications interface, only two bus lines needed. Both master and slave operation supported. Device can operate as transmitter or receiver. 7-bit address space allows up to 128 different slave addresses. Multi-master arbitration support Up to 400 kHz data transfer speed Slew-rate limited output drivers Noise suppression circuitry rejects spikes on bus lines Fully programmable slave address with general call support Address recognition causes wake-up when AVR is in sleep mode The Two-Wire Serial Interface (TWI) is ideally suited to typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bidirectional bus lines, one for clock (SCL) andone for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI pr
sfrb TWBR = 0x70;
#define TWBR0 0
#define TWBR1 1
#define TWBR2 2
#define TWBR3 3
#define TWBR4 4
#define TWBR5 5
#define TWBR6 6
#define TWBR7 7
sfrb TWCR = 0x74;
#define TWIE 0
When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT flag is high.
#define TWEN 2
The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation.
#define TWWC 3
The TWWC bit is set when attempting to write to the TWI Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR register when TWINT is high.
#define TWSTO 4
Writing the TWSTO bit to one in master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high impedance state.
#define TWSTA 5
The application writes the TWSTA bit to one when it desires to become a master on the 2-wire Serial Bus. The TWI hard-ware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master sta-tus. TWSTA is cleared by the TWI hardware when the START condition has been transmitted.
#define TWEA 6
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is gener-ated on the TWI bus if the following conditions are met: 1. The device?s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in master receiver or slave receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again
#define TWINT 7
This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag
sfrb TWSR = 0x71;
#define TWPS0 0
Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See ?Bit Rate Generator Unit? on page 165 for calculating bit rates.
#define TWPS1 1
Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See ?Bit Rate Generator Unit? on page 165 for calculating bit rates.
#define TWS3 3
Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co
#define TWS4 4
Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co
#define TWS5 5
Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c
#define TWS6 6
Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co
#define TWS7 7
Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c
sfrb TWDR = 0x73;
#define TWD0 0
#define TWD1 1
#define TWD2 2
#define TWD3 3
#define TWD4 4
#define TWD5 5
#define TWD6 6
#define TWD7 7
sfrb TWAR = 0x72;
#define TWGCE 0
#define TWA0 1
#define TWA1 2
#define TWA2 3
#define TWA3 4
#define TWA4 5
#define TWA5 6
#define TWA6 7
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: ? Full Duplex Operation (Independent Serial Receive and Transmit Registers) ? Asynchronous or Synchronous Operation ? Master or Slave Clocked Synchronous Operation ? High Resolution Baud Rate Generator ? Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits ? Odd or Even Parity Generation and Parity Check Supported by Hardware ? Data OverRun Detection ? Framing Error Detection ? Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter ? Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete ? Multi-processor Communication Mode ? Double Speed Asynchronous Commu
sfrb UDR0 = 0x0C;
#define UDR00 0
#define UDR01 1
#define UDR02 2
#define UDR03 3
#define UDR04 4
#define UDR05 5
#define UDR06 6
#define UDR07 7
sfrb UCSR0A = 0x0B;
#define MPCM0 0
This bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see ?Multi-processor Communication Mode? on page 152.
#define U2X0 1
This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.
#define UPE0 2
This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A.
#define DOR0 3
This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR0 register is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0.
#define FE0 4
This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.
#define UDRE0 5
This bit is set (one) when a character written to UDR0 is transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDR0 in order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is re
#define TXC0 6
This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to th
#define RXC0 7
This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDR0 in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.
sfrb UCSR0B = 0x0A;
#define TXB80 0
TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.
#define RXB80 1
RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.
#define UCSZ02 2
The UCSZ2 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use.
#define TXEN0 3
Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.
#define RXEN0 4
Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.
#define UDRIE0 5
Writing this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.
#define TXCIE0 6
Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.
#define RXCIE0 7
Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.
sfrb UCSR0C = 0x95;
#define UCPOL0 0
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).
#define UCSZ00 1
Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.
#define UCSZ01 2
Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.
#define USBS0 3
0: 1-bit. 1: 2-bit.
#define UPM00 4
This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.
#define UPM01 5
This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.
#define UMSEL0 6
0: Asynchronous Operation. 1: Synchronous Operation
sfrb UBRR0H = 0x90;
#define UBRR8 0
#define UBRR9 1
#define UBRR10 2
#define UBRR11 3
sfrb UBRR0L = 0x09;
#define UBRR0 0
#define UBRR1 1
#define UBRR2 2
#define UBRR3 3
#define UBRR4 4
#define UBRR5 5
#define UBRR6 6
#define UBRR7 7
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: ? Full Duplex Operation (Independent Serial Receive and Transmit Registers) ? Asynchronous or Synchronous Operation ? Master or Slave Clocked Synchronous Operation ? High Resolution Baud Rate Generator ? Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits ? Odd or Even Parity Generation and Parity Check Supported by Hardware ? Data OverRun Detection ? Framing Error Detection ? Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter ? Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete ? Multi-processor Communication Mode ? Double Speed Asynchronous Communicat
sfrb UDR1 = 0x9C;
#define UDR10 0
#define UDR11 1
#define UDR12 2
#define UDR13 3
#define UDR14 4
#define UDR15 5
#define UDR16 6
#define UDR17 7
sfrb UCSR1A = 0x9B;
#define MPCM1 0
This bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see ?Multi-processor Communication Mode? on page 152.
#define U2X1 1
This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.
#define UPE1 2
This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR1) is read. Always set this bit to zero when writing to UCSR1A.
#define DOR1 3
This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR1 register is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR1E is read. The OR bit is cleared (zero) when data is received and transferred to UDR1.
#define FE1 4
This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.
#define UDRE1 5
This bit is set (one) when a character written to UDR1 is transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR1IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR1E is set. UDR1E is cleared by writing UDR1. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDR1 in order to clear UDR1E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR1E is set (one) during reset to indicate that the transmitter is read
#define TXC1 6
This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR1. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bi
#define RXC1 7
This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR1. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR1. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDR1 in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.
sfrb UCSR1B = 0x9A;
#define TXB81 0
TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR1.
#define RXB81 1
RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR1.
#define UCSZ12 2
The UCSZ2 bits combined with the UCSZ1:0 bit in UCSR1C sets the number of data bits (character size) in a frame the receiver and transmitter use.
#define TXEN1 3
Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.
#define RXEN1 4
Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.
#define UDRIE1 5
Writing this bit to one enables interrupt on the UDR1E flag. A Data Register Empty interrupt will be generated only if the UDR1IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR1E bit in UCSR1A is set.
#define TXCIE1 6
Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR1A is set.
#define RXCIE1 7
Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR1A is set.
sfrb UCSR1C = 0x9D;
#define UCPOL1 0
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).
#define UCSZ10 1
Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.
#define UCSZ11 2
Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.
#define USBS1 3
0: 1-bit. 1: 2-bit.
#define UPM10 4
This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR1A will be set.
#define UPM11 5
This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR1A will be set.
#define UMSEL1 6
0: Asynchronous Operation. 1: Synchronous Operation
sfrb UBRR1H = 0x98;
#define UBRR8 0
#define UBRR9 1
#define UBRR10 2
#define UBRR11 3
sfrb UBRR1L = 0x99;
#define UBRR0 0
#define UBRR1 1
#define UBRR2 2
#define UBRR3 3
#define UBRR4 4
#define UBRR5 5
#define UBRR6 6
#define UBRR7 7
sfrb SREG = 0x3F;
sfrb SPH = 0x3E;
#define SP8 0
#define SP9 1
#define SP10 2
#define SP11 3
#define SP12 4
#define SP13 5
#define SP14 6
#define SP15 7
sfrb SPL = 0x3D;
#define SP0 0
#define SP1 1
#define SP2 2
#define SP3 3
#define SP4 4
#define SP5 5
#define SP6 6
#define SP7 7
sfrb MCUCR = 0x35;
#define IVCE 0
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above.
#define IVSEL 1
When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the Flash memory. When this bit is set (one), the interrupt vectors are moved to the beginning of the Boot Loader section of the flash. The actual address of the start of the boot flash section is determined by the BOOTSZ fuses. Refer to the section ?Boot Loader Support - Read While Write self-programming? on page 228 for details. To avoid unintentional changes of interrupt vector tables, a special write procedure must be followed to change the IVSEL bit: 1. Write the Interrupt Vector Change Enable (IVCE) bit to one. 2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain dis-abled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: Note: If interrupt vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If interrupt vectors are placed in the Application section and Boot Lock bit BLB01 is pro-gramed, interrupts are disabled while executing from the Boot Loader section. Refer to the section ?Boot Loader Support - Read While Write self-programming? on page 228 for details on Boot Lock bits
#define SM2 2
The description is to long for the tooltip help, please refer to the manual
#define SM0 3
The description is to long for the tooltip help, please refer to the manual
#define SM1 4
The description is to long for the tooltip help, please refer to the manual
#define SE 5
#define SRW10 6
For a detailed description in non ATmega103 Compatibility mode, see common description for the SRWn bits below (XMRA description). In ATmega103 Compatibility mode, writing SRW10 to one enables the wait state and one extra cycle is added during read/write strobe as shown in Figure 14.
#define SRE 7
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are acti-vated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction regis-ters. Writing SRE to zero, disables the External Memory Interface and the normal pin and data direction settings are used.
sfrb MCUCSR = 0x34;
#define PORF 0
This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.
#define EXTRF 1
This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
#define BORF 2
This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
#define WDRF 3
This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
#define JTRF 4
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on reset, or by writing a logic zero to the flag. ? Bit 3 - WDRF: Watchdog Reset Flag
#define JTD 7
When this bit is zero, the JTAG interface is enabled if the JTAGEN fuse is programmed.
sfrb XMCRA = 0x6D;
#define SRW11 1
Wait state select bits for upper page. The SRW11 and SRW10 bits control the number of wait-states for the upper page of the external memory address space, see Table 3.
#define SRW00 2
Note: n = 0 or 1 (lower/upper page). For further details of the timing and wait-states of the External Memory Interface, see Figure 13 to Figure 16 how the setting of the SRW bits affects the timing. Wait-states SRWn1 SRWn0 Wait-states 0 0 No wait states 0 1 Wait one cycle during read/write strobe 1 0 Wait two cycles during read/write strobe 1 1 Wait two cycles during read/write and wait one cycle before driving out new address
#define SRW01 3
Note: n = 0 or 1 (lower/upper page). For further details of the timing and wait-states of the External Memory Interface, see Figure 13 to Figure 16 how the setting of the SRW bits affects the timing. Wait-states SRWn1 SRWn0 Wait-states 0 0 No wait states 0 1 Wait one cycle during read/write strobe 1 0 Wait two cycles during read/write strobe 1 1 Wait two cycles during read/write and wait one cycle before driving out new address
#define SRL0 4
It is possible to configure different wait-states for different external memory addresses. The external memory address space can be divided in two pages that have separate wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the pages, see Table 2 and Figure 11. As default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external mem-ory address space is treated as one page. When the entire SRAM address space is configured as one page, the wait-states are configured by the SRW11 and SRW10 bits
#define SRL1 5
It is possible to configure different wait-states for different external memory addresses. The external memory address space can be divided in two pages that have separate wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the pages, see Table 2 and Figure 11. As default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external mem-ory address space is treated as one page. When the entire SRAM address space is configured as one page, the wait-states are configured by the SRW11 and SRW10 bits
#define SRL2 6
It is possible to configure different wait-states for different external memory addresses. The external memory address space can be divided in two pages that have separate wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the pages, see Table 2 and Figure 11. As default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external mem-ory address space is treated as one page. When the entire SRAM address space is configured as one page, the wait-states are configured by the SRW11 and SRW10 bits
sfrb XMCRB = 0x6C;
#define XMM0 0
When the External Memory is enabled, all Port C pins are default used for the high address byte. If the full 60KB address space is not required to access the external memory, some, or all, Port C pins can be released for normal Port Pin function as described in Table 4. As described in ?Using all 64KB locations of external memory? on page 27, it is possible to use the XMMn bits to access all 64KB locations of the external memory.
#define XMM1 1
When the External Memory is enabled, all Port C pins are default used for the high address byte. If the full 60KB address space is not required to access the external memory, some, or all, Port C pins can be released for normal Port Pin function as described in Table 4. As described in ?Using all 64KB locations of external memory? on page 27, it is possible to use the XMMn bits to access all 64KB locations of the external memory.
#define XMM2 2
When the External Memory is enabled, all Port C pins are default used for the high address byte. If the full 60KB address space is not required to access the external memory, some, or all, Port C pins can be released for normal Port Pin function as described in Table 4. As described in ?Using all 64KB locations of external memory? on page 27, it is possible to use the XMMn bits to access all 64KB locations of the external memory.
#define XMBK 7
Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface has tri-stated the lines. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE, so even if the XMEM interface is disabled, the bus keepers are still activiated as long as XMBK is one.
sfrb OSCCAL = 0x6F;
#define CAL0 0
#define CAL1 1
#define CAL2 2
#define CAL3 3
#define CAL4 4
#define CAL5 5
#define CAL6 6
#define CAL7 7
sfrb XDIV = 0x3C;
#define XDIV0 0
These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas.
#define XDIV1 1
These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas.
#define XDIV2 2
These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas.
#define XDIV3 3
These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas.
#define XDIV4 4
These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas.
#define XDIV5 5
These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas.
#define XDIV6 6
These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas.
#define XDIVEN 7
When the XDIVEN bit is written one, the clock frequency of the CPU and all peripherals (clk I/O , clk ADC , clk CPU , clk FLASH ) is divided by the factor defined by the setting of XDIV6 - XDIV0. This bit can be written run-time to vary the clock frequency as suitable to the application.
sfrb RAMPZ = 0x3B;
#define RAMPZ0 0
The RAMPZ register is normally used to select which 64K RAM Page is accessed by the Z pointer. As the ATmega104 does not support more than 64K of SRAM memory, this register is used only to select which page in the program memory is accessed when the ELPM/SPM instruction is used. The different settings of the RAMPZ0 bit have the following effects: Note that LPM is not affected by the RAMPZ setting. RAMPZ0 = 0: Program memory address $0000- $7FFF (lower 64K bytes) is accessed by ELPM/SPM RAMPZ0 = 1: Program memory address $8000- $FFFF (higher 64K bytes) is accessed by ELPM/
The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppor
sfrb SPMCSR = 0x68;
#define SPMEN 0
This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than ?10001?, "01001", "00101", "00011" or "00001" in the lower five bits will have no effec
#define PGERS 1
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.
#define PGWRT 2
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.
#define BLBSET 3
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See ?Reading the Fuse and Lock Bits from Software? on page 235 for details
#define RWWSRE 4
When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lo
#define RWWSB 6
When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated.
#define SPMIE 7
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared.
JTAG Features: JTAG (IEEE std. 1149.1 compliant) Interface. Boundary-Scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard. Debugger Access to: ? All Internal Peripheral Units ? Internal and External RAM ? The Internal Register File ?Program Counter ? EEPROM and Flash Memories. Extensive On-Chip Debug Support for Break Conditions, Including: ?AVR Break Instruction ? Break on Change of Program Memory Flow ?Single Step Break ?Program Memory Breakpoints on Single Address or Address Range ? Data Memory Breakpoints on Single Address or Address Range. Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface. On-Chip Debugging Supported by AVR S
sfrb OCDR = 0x22;
#define OCDR0 0
#define OCDR1 1
#define OCDR2 2
#define OCDR3 3
#define OCDR4 4
#define OCDR5 5
#define OCDR6 6
#define OCDR7 7
sfrb MCUCSR = 0x34;
#define JTRF 4
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on reset, or by writing a logic zero to the flag.
#define JTD 7
When this bit is written to zero, the JTAG interface is enabled if the JTAGEN fuse is programmed. If this bit is written to one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface, a timed sequence must be followed: The application software must write this to the desired value twice within four cycles to change the bit.
sfrb SFIOR = 0x20;
#define PSR321 0
#define PSR0 1
#define PUD 2
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are config-ured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See ?Configuring the Pin? on page 52 for more details about this fea-ture.
#define ACME 3
#define TSM 7
The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in ?Clock Systems and their Distribution? on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in ?Clock Systems and their Distribution? on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt
sfrb EICRA = 0x6A;
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
#define ISC20 4
#define ISC21 5
#define ISC30 6
#define ISC31 7
sfrb EICRB = 0x3A;
#define ISC40 0
#define ISC41 1
#define ISC50 2
#define ISC51 3
#define ISC60 4
#define ISC61 5
#define ISC70 6
#define ISC71 7
sfrb EIMSK = 0x39;
#define INT0 0
#define INT1 1
#define INT2 2
#define INT3 3
#define INT4 4
#define INT5 5
#define INT6 6
#define INT7 7
sfrb EIFR = 0x38;
#define INTF0 0
#define INTF1 1
#define INTF2 2
#define INTF3 3
#define INTF4 4
#define INTF5 5
#define INTF6 6
#define INTF7 7
EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See ?Preventing EEPROM Corruption? on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execute
sfrb EEARH = 0x1F;
#define EEAR8 0
#define EEAR9 1
#define EEAR10 2
#define EEAR11 3
sfrb EEARL = 0x1E;
#define EEARL0 0
#define EEARL1 1
#define EEARL2 2
#define EEARL3 3
#define EEARL4 4
#define EEARL5 5
#define EEARL6 6
#define EEARL7 7
sfrb EEDR = 0x1D;
#define EEDR0 0
#define EEDR1 1
#define EEDR2 2
#define EEDR3 3
#define EEDR4 4
#define EEDR5 5
#define EEDR6 6
#define EEDR7 7
sfrb EECR = 0x1C;
#define EERE 0
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU
#define EEWE 1
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See ?Boot Loader Support - Read While Write self-programming? on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed
#define EEMWE 2
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.
#define EERIE 3
EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.
sfrb PORTA = 0x1B;
#define PORTA0 0
#define PORTA1 1
#define PORTA2 2
#define PORTA3 3
#define PORTA4 4
#define PORTA5 5
#define PORTA6 6
#define PORTA7 7
sfrb DDRA = 0x1A;
#define DDA0 0
#define DDA1 1
#define DDA2 2
#define DDA3 3
#define DDA4 4
#define DDA5 5
#define DDA6 6
#define DDA7 7
sfrb PINA = 0x19;
#define PINA0 0
#define PINA1 1
#define PINA2 2
#define PINA3 3
#define PINA4 4
#define PINA5 5
#define PINA6 6
#define PINA7 7
sfrb PORTB = 0x18;
#define PORTB0 0
#define PORTB1 1
#define PORTB2 2
#define PORTB3 3
#define PORTB4 4
#define PORTB5 5
#define PORTB6 6
#define PORTB7 7
sfrb DDRB = 0x17;
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3
#define DDB4 4
#define DDB5 5
#define DDB6 6
#define DDB7 7
sfrb PINB = 0x16;
#define PINB0 0
#define PINB1 1
#define PINB2 2
#define PINB3 3
#define PINB4 4
#define PINB5 5
#define PINB6 6
#define PINB7 7
sfrb PORTC = 0x15;
#define PORTC0 0
#define PORTC1 1
#define PORTC2 2
#define PORTC3 3
#define PORTC4 4
#define PORTC5 5
#define PORTC6 6
#define PORTC7 7
sfrb DDRC = 0x14;
#define DDC0 0
#define DDC1 1
#define DDC2 2
#define DDC3 3
#define DDC4 4
#define DDC5 5
#define DDC6 6
#define DDC7 7
sfrb PINC = 0x13;
#define PINC0 0
#define PINC1 1
#define PINC2 2
#define PINC3 3
#define PINC4 4
#define PINC5 5
#define PINC6 6
#define PINC7 7
sfrb PORTD = 0x12;
#define PORTD0 0
#define PORTD1 1
#define PORTD2 2
#define PORTD3 3
#define PORTD4 4
#define PORTD5 5
#define PORTD6 6
#define PORTD7 7
sfrb DDRD = 0x11;
#define DDD0 0
#define DDD1 1
#define DDD2 2
#define DDD3 3
#define DDD4 4
#define DDD5 5
#define DDD6 6
#define DDD7 7
sfrb PIND = 0x10;
#define PIND0 0
#define PIND1 1
#define PIND2 2
#define PIND3 3
#define PIND4 4
#define PIND5 5
#define PIND6 6
#define PIND7 7
sfrb PORTE = 0x03;
#define PORTE0 0
#define PORTE1 1
#define PORTE2 2
#define PORTE3 3
#define PORTE4 4
#define PORTE5 5
#define PORTE6 6
#define PORTE7 7
sfrb DDRE = 0x02;
#define DDE0 0
#define DDE1 1
#define DDE2 2
#define DDE3 3
#define DDE4 4
#define DDE5 5
#define DDE6 6
#define DDE7 7
sfrb PINE = 0x01;
#define PINE0 0
#define PINE1 1
#define PINE2 2
#define PINE3 3
#define PINE4 4
#define PINE5 5
#define PINE6 6
#define PINE7 7
sfrb PORTF = 0x62;
#define PORTF0 0
#define PORTF1 1
#define PORTF2 2
#define PORTF3 3
#define PORTF4 4
#define PORTF5 5
#define PORTF6 6
#define PORTF7 7
sfrb DDRF = 0x61;
#define DDF0 0
#define DDF1 1
#define DDF2 2
#define DDF3 3
#define DDF4 4
#define DDF5 5
#define DDF6 6
#define DDF7 7
sfrb PINF = 0x00;
#define PINF0 0
#define PINF1 1
#define PINF2 2
#define PINF3 3
#define PINF4 4
#define PINF5 5
#define PINF6 6
#define PINF7 7
sfrb PORTG = 0x65;
#define PORTG0 0
#define PORTG1 1
#define PORTG2 2
#define PORTG3 3
#define PORTG4 4
sfrb DDRG = 0x64;
#define DDG0 0
#define DDG1 1
#define DDG2 2
#define DDG3 3
#define DDG4 4
sfrb PING = 0x63;
#define PING0 0
#define PING1 1
#define PING2 2
#define PING3 3
#define PING4 4
sfrb TCCR0 = 0x33;
#define CS00 0
The three clock select bits select the clock source to be used by the Timer/Counter,
#define CS01 1
The three clock select bits select the clock source to be used by the Timer/Counter,
#define CS02 2
The three clock select bits select the clock source to be used by the Timer/Counter,
#define WGM01 3
These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 51 and ?Modes of Operation? on page 80.
#define COM00 4
These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set in order to enable the output driver. When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 52 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM)
#define COM01 5
These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set in order to enable the output driver. When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 52 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM)
#define WGM00 6
These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 51 and ?Modes of Operation? on page 80.
#define FOC0 7
The FOC0 bit is only active when the WGM bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode. When writing a logical one to the FOC0 bit, an immediate compare match is forced on the waveform generation unit. The OC0 output is changed accord-ing to its COM01:0 bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the value present in the COM01:0 bits that determines the effect of the forced compare. A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0 as TOP. The FOC0 bit is always read as zero.
sfrb TCNT0 = 0x32;
#define TCNT0_0 0
#define TCNT0_1 1
#define TCNT0_2 2
#define TCNT0_3 3
#define TCNT0_4 4
#define TCNT0_5 5
#define TCNT0_6 6
#define TCNT0_7 7
sfrb OCR0 = 0x31;
#define OCR0_0 0
#define OCR0_1 1
#define OCR0_2 2
#define OCR0_3 3
#define OCR0_4 4
#define OCR0_5 5
#define OCR0_6 6
#define OCR0_7 7
sfrb ASSR = 0x30;
#define TCR0UB 0
When Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomes set. When TCCR0 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR0 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter0 registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur.The mechanisms for reading TCNT0, OCR0, and TCCR0 are different. When reading TCNT0, the actual timer value is read. When reading OCR0 or TCCR0, the value in the temporary storage register is read
#define OCR0UB 1
When Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes set. When OCR0 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR0 is ready to be updated with a new value.
#define TCN0UB 2
When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set. When TCNT0 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT0 is ready to be updated with a new value.
#define AS0 3
When AS0 is cleared, Timer/Counter 0 is clocked from the I/O clock, clk I/O . When AS0 is set, Timer/Counter 0 is clocked from a crystal oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS0 is changed, the contents of TCNT0, OCR0, and TCCR0 might be corrupted.
sfrb TIMSK = 0x37;
#define TOIE0 0
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e. when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define OCIE0 1
When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, i.e. when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
sfrb TIFR = 0x36;
#define TOV0 0
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter0 changes counting direction at $00.
#define OCF0 1
The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0 and the data in OCR0 - Output Compare Register0. OCF0 is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF0 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare match Interrupt Enable), and OCF0 are set (one), the Timer/Counter0 Compare match Interrupt is executed.
sfrb SFIOR = 0x20;
#define PSR0 1
When this bit is written to one, the Timer/Counter0 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always be read as zero if Timer/Counter0 is clocked by the internal CPU clock. If this bit is written when Timer/Counter0 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset.
#define TSM 7
Writing TSM to one, PSR0 and PSR321 becomes registers that hold their value until rewritten, or the TSM bit is written zero. This mode is useful for synchronizing timer/counters. By setting both TSM and the appropriate PSR bit(s), the appro-priate timer/counters are halted, and can be configured to same value without the risk of one of them advancing during con-figuration. When the TSM bit written zero, the Timer/Counters start counting simultaneously.
sfrb TIMSK = 0x37;
#define TOIE1 2
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define OCIE1B 3
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define OCIE1A 4
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define TICIE1 5
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
sfrb ETIMSK = 0x7D;
#define OCIE1C 0
When this bit is written to one, and the I-flag in the status register is set (interrupts globally enabled), the timer/counter 1 output compare C match interrupt is enabled. The corresponding interrupt vector (See ?Interrupts? on page 46.) is executed when the OCF1C flag, located in ETIFR, is set.
sfrb TIFR = 0x36;
#define TOV1 2
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.
#define OCF1B 3
The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.
#define OCF1A 4
The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed.
#define ICF1 5
The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.
sfrb ETIFR = 0x7C;
#define OCF1C 0
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register C (OCR1C). Note that a forced output compare (FOC1C) strobe will not set the OCF1C flag. OCF1C is automatically cleared when the Output Compare Match 1 C interrupt vector is executed. Alternatively, OCF1C can be cleared by writing a logic one to its bit location.
sfrb SFIOR = 0x20;
#define PSR321 0
? Bit 0 - PSR321: Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1 Writing PSR321 to one resets the prescalter for Timer/Counter3, Timer/Counter2, and Timer/Counter1. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter3 Timer/Counter2, and Timer/Counter1 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero.
#define TSM 7
? Bit 7 - TSM: Timer/Counter Synchronization Mode Writing TSM to one, PSR0 and PSR321 becomes registers that hold their value until rewritten, or the TSM bit is written zero. This mode is useful for synchronizing timer/counters. By setting both TSM and the appropriate PSR bit(s), the appro-priate timer/counters are halted, and can be configured to same value without the risk of one of them advancing during con-figuration. When the TSM bit written zero, the Timer/Counters start counting simultaneously.
sfrb TCCR1A = 0x2F;
#define WGM10 0
Combined with the WGMn3:2 bits found in the TCCRnB register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 60. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See ?Modes of Operation? on page 101.)
#define WGM11 1
Combined with the WGMn3:2 bits found in the TCCRnB register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 60. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See ?Modes of Operation? on page 101.)
#define COM1C0 2
#define COM1C1 3
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7
sfrb TCCR1B = 0x2E;
#define CS10 0
Select clock source
#define CS11 1
Select clock source
#define CS12 2
Select clock source
#define WGM12 3
See description found for TCCR1A
#define WGM13 4
See description found for TCCR1A
#define ICES1 6
While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.
#define ICNC1 7
When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.
sfrb TCCR1C = 0x7A;
#define FOC1C 5
? Bit 7- FOCnA: Force Output Compare for channel A ? Bit 6- FOCnB: Force Output Compare for channel B ? Bit 5- FOCnC: Force Output Compare for channel C The FOCnA/FOCnB//FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode. When writing a log-icalone to the FOCnA/FOCnB//FOCnC bit, an immediate compare match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB//FOCnB bits are always read as zero
#define FOC1B 6
? Bit 7- FOCnA: Force Output Compare for channel A ? Bit 6- FOCnB: Force Output Compare for channel B ? Bit 5- FOCnC: Force Output Compare for channel C The FOCnA/FOCnB//FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode. When writing a log-icalone to the FOCnA/FOCnB//FOCnC bit, an immediate compare match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB//FOCnB bits are always read as zero
#define FOC1A 7
? Bit 7- FOCnA: Force Output Compare for channel A ? Bit 6- FOCnB: Force Output Compare for channel B ? Bit 5- FOCnC: Force Output Compare for channel C The FOCnA/FOCnB//FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode. When writing a log-icalone to the FOCnA/FOCnB//FOCnC bit, an immediate compare match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB//FOCnB bits are always read as zero
sfrb TCNT1H = 0x2D;
#define TCNT1H0 0
#define TCNT1H1 1
#define TCNT1H2 2
#define TCNT1H3 3
#define TCNT1H4 4
#define TCNT1H5 5
#define TCNT1H6 6
#define TCNT1H7 7
sfrb TCNT1L = 0x2C;
#define TCNT1L0 0
#define TCNT1L1 1
#define TCNT1L2 2
#define TCNT1L3 3
#define TCNT1L4 4
#define TCNT1L5 5
#define TCNT1L6 6
#define TCNT1L7 7
sfrb OCR1AH = 0x2B;
#define OCR1AH0 0
#define OCR1AH1 1
#define OCR1AH2 2
#define OCR1AH3 3
#define OCR1AH4 4
#define OCR1AH5 5
#define OCR1AH6 6
#define OCR1AH7 7
sfrb OCR1AL = 0x2A;
#define OCR1AL0 0
#define OCR1AL1 1
#define OCR1AL2 2
#define OCR1AL3 3
#define OCR1AL4 4
#define OCR1AL5 5
#define OCR1AL6 6
#define OCR1AL7 7
sfrb OCR1BH = 0x29;
#define OCR1BH0 0
#define OCR1BH1 1
#define OCR1BH2 2
#define OCR1BH3 3
#define OCR1BH4 4
#define OCR1BH5 5
#define OCR1BH6 6
#define OCR1BH7 7
sfrb OCR1BL = 0x28;
#define OCR1BL0 0
#define OCR1BL1 1
#define OCR1BL2 2
#define OCR1BL3 3
#define OCR1BL4 4
#define OCR1BL5 5
#define OCR1BL6 6
#define OCR1BL7 7
sfrb OCR1CH = 0x79;
#define OCR1CH0 0
#define OCR1CH1 1
#define OCR1CH2 2
#define OCR1CH3 3
#define OCR1CH4 4
#define OCR1CH5 5
#define OCR1CH6 6
#define OCR1CH7 7
sfrb OCR1CL = 0x78;
#define OCR1CL0 0
#define OCR1CL1 1
#define OCR1CL2 2
#define OCR1CL3 3
#define OCR1CL4 4
#define OCR1CL5 5
#define OCR1CL6 6
#define OCR1CL7 7
sfrb ICR1H = 0x27;
#define ICR1H0 0
#define ICR1H1 1
#define ICR1H2 2
#define ICR1H3 3
#define ICR1H4 4
#define ICR1H5 5
#define ICR1H6 6
#define ICR1H7 7
sfrb ICR1L = 0x26;
#define ICR1L0 0
#define ICR1L1 1
#define ICR1L2 2
#define ICR1L3 3
#define ICR1L4 4
#define ICR1L5 5
#define ICR1L6 6
#define ICR1L7 7
sfrb TCCR2 = 0x25;
#define CS20 0
The three clock select bits select the clock source to be used by the Timer/Counter.
#define CS21 1
The three clock select bits select the clock source to be used by the Timer/Counter.
#define CS22 2
The three clock select bits select the clock source to be used by the Timer/Counter.
#define WGM21 3
These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes.
#define COM20 4
These bits control the output compare pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 64 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM)
#define COM21 5
These bits control the output compare pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 64 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM).
#define WGM20 6
These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes.
#define FOC2 7
The FOC2 bit is only active when the WGM20 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written when operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate compare match is forced on the waveform generation unit. The OC2 output is changed according to its COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the value present in the COM21:0 bits that determines the effect of the forced compare. A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2 as TOP. The FOC2 bit is always read as zero.
sfrb TCNT2 = 0x24;
#define TCNT2_0 0
#define TCNT2_1 1
#define TCNT2_2 2
#define TCNT2_3 3
#define TCNT2_4 4
#define TCNT2_5 5
#define TCNT2_6 6
#define TCNT2_7 7
sfrb OCR2 = 0x23;
#define OCR2_0 0
#define OCR2_1 1
#define OCR2_2 2
#define OCR2_3 3
#define OCR2_4 4
#define OCR2_5 5
#define OCR2_6 6
#define OCR2_7 7
sfrb TIFR = 0x36;
#define TOV2 6
The bit TOV2 is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00.
#define OCF2 7
The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2 - Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare match Interrupt Enable), and OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed.
sfrb TIMSK = 0x37;
#define TOIE2 6
#define OCIE2 7
sfrb ETIMSK = 0x7D;
#define OCIE3C 1
When this bit is written to one, and the I-flag status register is set (interrupts globally enabled), the timer/counter3 output compare C match interrupt is enabled. The corresponding interrupt vector is executed when the OCF3C flag, located in ETIFR is set.
#define TOIE3 2
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter3 occurs, i.e., when the TOV3bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define OCIE3B 3
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter3 occurs, i.e., when the OCF3Bbit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define OCIE3A 4
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter3 occurs, i.e., when the OCF3Abit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define TICIE3 5
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
sfrb ETIFR = 0x7C;
#define OCF3C 1
This flag is set in the timer clock sycle after the counter (TCNT3) value matches the Output Compare Register C (OCR3C)
#define TOV3 2
The TOV3is set (one) when an overflow occurs in Timer/Counter3. TOV3is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV3is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter3 Overflow Interrupt Enable), and TOV3are set (one), the Timer/Counter3 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter3 changes counting direction at $0000.
#define OCF3B 3
The OCF3Bbit is set (one) when compare match occurs between the Timer/Counter3 and the data in OCR3B- Output Compare Register 1B. OCF3Bis cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF3Bis cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter3 Compare match InterruptB Enable), and the OCF3Bare set (one), the Timer/Counter3 Compare B match Interrupt is executed.
#define OCF3A 4
The OCF3Abit is set (one) when compare match occurs between the Timer/Counter3 and the data in OCR1A - Output Compare Register 1A. OCF3Ais cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF3Ais cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter3 Compare match InterruptA Enable), and the OCF3Aare set (one), the Timer/Counter3 Compare A match Interrupt is executed.
#define ICF3 5
The ICF3 bit is set (one) to flag an input capture event, indicating that the Timer/Counter3 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF3 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE3 (Timer/Counter3 Input Capture Interrupt Enable), and ICF3 are set (one), the Timer/Counter3 Capture Interrupt is executed.
sfrb SFIOR = 0x20;
#define PSR321 0
? Bit 0 - PSR321: Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter3 Writing PSR321 to one resets the prescalter for Timer/Counter3, Timer/Counter2, and Timer/Counter3. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter3 Timer/Counter2, and Timer/Counter3 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero.
#define TSM 7
? Bit 7 - TSM: Timer/Counter Synchronization Mode Writing TSM to one, PSR0 and PSR321 becomes registers that hold their value until rewritten, or the TSM bit is written zero. This mode is useful for synchronizing timer/counters. By setting both TSM and the appropriate PSR bit(s), the appro-priate timer/counters are halted, and can be configured to same value without the risk of one of them advancing during con-figuration. When the TSM bit written zero, the Timer/Counters start counting simultaneously.
sfrb TCCR3A = 0x8B;
#define WGM30 0
Combined with the WGMn3:2 bits found in the TCCRnB register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 60. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See ?Modes of Operation? on page 101.)
#define WGM31 1
Combined with the WGMn3:2 bits found in the TCCRnB register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 60. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See ?Modes of Operation? on page 101.)
#define COM3C0 2
#define COM3C1 3
#define COM3B0 4
#define COM3B1 5
#define COM3A0 6
#define COM3A1 7
sfrb TCCR3B = 0x8A;
#define CS30 0
Select clock source
#define CS31 1
Select clock source
#define CS32 2
Select clock source
#define WGM32 3
See description found for TCCR3A
#define WGM33 4
See description found for TCCR3A
#define ICES3 6
While the ICES3 bit is cleared (zero), the Timer/Counter3 contents are transferred to the Input Capture Register - ICR3 - on the falling edge of the input capture pin - ICP. While the ICES3 bit is set (one), the Timer/Counter3 contents are transferred to the Input Capture Register - ICR3 - on the rising edge of the input capture pin - ICP.
#define ICNC3 7
When the ICNC3 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC3 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES3 bit. The actual sampling frequency is XTAL clock frequency.
sfrb TCCR3C = 0x8C;
#define FOC3C 5
? Bit 7- FOCnA: Force Output Compare for channel A ? Bit 6- FOCnB: Force Output Compare for channel B ? Bit 5- FOCnC: Force Output Compare for channel C The FOCnA/FOCnB//FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode. When writing a log-icalone to the FOCnA/FOCnB//FOCnC bit, an immediate compare match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB//FOCnB bits are always read as zero
#define FOC3B 6
? Bit 7- FOCnA: Force Output Compare for channel A ? Bit 6- FOCnB: Force Output Compare for channel B ? Bit 5- FOCnC: Force Output Compare for channel C The FOCnA/FOCnB//FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode. When writing a log-icalone to the FOCnA/FOCnB//FOCnC bit, an immediate compare match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB//FOCnB bits are always read as zer
#define FOC3A 7
? Bit 7- FOCnA: Force Output Compare for channel A ? Bit 6- FOCnB: Force Output Compare for channel B ? Bit 5- FOCnC: Force Output Compare for channel C The FOCnA/FOCnB//FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode. When writing a log-icalone to the FOCnA/FOCnB//FOCnC bit, an immediate compare match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB//FOCnB bits are always read as zer
sfrb TCNT3H = 0x89;
#define TCNT3H0 0
#define TCNT3H1 1
#define TCNT3H2 2
#define TCNT3H3 3
#define TCNT3H4 4
#define TCNT3H5 5
#define TCNT3H6 6
#define TCNT3H7 7
sfrb TCNT3L = 0x88;
#define TCN3L0 0
#define TCN3L1 1
#define TCN3L2 2
#define TCN3L3 3
#define TCN3L4 4
#define TCN3L5 5
#define TCN3L6 6
#define TCN3L7 7
sfrb OCR3AH = 0x87;
#define OCR3AH0 0
#define OCR3AH1 1
#define OCR3AH2 2
#define OCR3AH3 3
#define OCR3AH4 4
#define OCR3AH5 5
#define OCR3AH6 6
#define OCR3AH7 7
sfrb OCR3AL = 0x86;
#define OCR3AL0 0
#define OCR3AL1 1
#define OCR3AL2 2
#define OCR3AL3 3
#define OCR3AL4 4
#define OCR3AL5 5
#define OCR3AL6 6
#define OCR3AL7 7
sfrb OCR3BH = 0x85;
#define OCR3BH0 0
#define OCR3BH1 1
#define OCR3BH2 2
#define OCR3BH3 3
#define OCR3BH4 4
#define OCR3BH5 5
#define OCR3BH6 6
#define OCR3BH7 7
sfrb OCR3BL = 0x84;
#define OCR3BL0 0
#define OCR3BL1 1
#define OCR3BL2 2
#define OCR3BL3 3
#define OCR3BL4 4
#define OCR3BL5 5
#define OCR3BL6 6
#define OCR3BL7 7
sfrb OCR3CH = 0x83;
#define OCR3CH0 0
#define OCR3CH1 1
#define OCR3CH2 2
#define OCR3CH3 3
#define OCR3CH4 4
#define OCR3CH5 5
#define OCR3CH6 6
#define OCR3CH7 7
sfrb OCR3CL = 0x82;
#define OCR3CL0 0
#define OCR3CL1 1
#define OCR3CL2 2
#define OCR3CL3 3
#define OCR3CL4 4
#define OCR3CL5 5
#define OCR3CL6 6
#define OCR3CL7 7
sfrb ICR3H = 0x81;
#define ICR3H0 0
#define ICR3H1 1
#define ICR3H2 2
#define ICR3H3 3
#define ICR3H4 4
#define ICR3H5 5
#define ICR3H6 6
#define ICR3H7 7
sfrb ICR3L = 0x80;
#define ICR3L0 0
#define ICR3L1 1
#define ICR3L2 2
#define ICR3L3 3
#define ICR3L4 4
#define ICR3L5 5
#define ICR3L6 6
#define ICR3L7 7
sfrb WDTCR = 0x21;
#define WDP0 0
The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.
#define WDP1 1
The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.
#define WDP2 2
The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.
#define WDE 3
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog
#define WDCE 4
This bit must be set when the WDE bit is written to logic zero.Otherwise,the watchdog will not be disabled.Once written to one,hardware will clear this bit after four clock cycles.Refer to the description of the WDE bit for a watchdog disable procedure.This bit must also be set when changing the prescaler bits.