The ARM Simulator target interface provides access to CrossStudio's ARM instruction set simulator (ISS). The ISS simulates the ARM V5TE instruction set as defined in Part A of the ARM Architecure Reference Manual (ARM DDI 0100E). The ISS supports exception vectors at address zero - high vectors are not supported. The ISS implements a 3 word instruction pre-fetch buffer.

The ISS supports MCR and MRC access to the 16 primary registers of the System Control coprocessor (CP15) as defined in Part B of the ARM DDI 0100E, however the cache and MMU functionality is not supported. The ISS supports MCR and MRC access to the Debug Communication Channel (CP14) as defined in ARM7TDMI Technical Reference Manual (ARM DDI 0210B).

The memory system simulated by the ISS is specified by a dynamic link library and associated parameter defined in the simulator properties help..

The ISS supports program loading and debugging with an unlimited number of breakpoints. The ISS supports instruction tracing, execution counts, exception vector trapping and exception vector triggering.