8.13.4 i860 Opcodes
All of the Intel i860XR and i860XP machine instructions are supported. Please see either i860 Microprocessor Programmer's Reference Manual or i860 Microprocessor Architecture for more information.
8.13.4.1 Other instruction support (pseudo-instructions)
For compatibility with some other i860 assemblers, a number of pseudo-instructions are supported. While these are supported, they are a very undesirable feature that should be avoided – in particular, when they result in an expansion to multiple actual i860 instructions. Below are the pseudo-instructions that result in expansions.
- Load large immediate into general register:
The pseudo-instruction
mov imm,%rn
(where the immediate does not fit within a signed 16-bit field) will be expanded into:orh large_imm@h,%r0,%rn or large_imm@l,%rn,%rn
- Load/store with relocatable address expression:
For example, the pseudo-instruction
ld.b addr_exp(%rx),%rn
will be expanded into:orh addr_exp@ha,%rx,%r31 ld.l addr_exp@l(%r31),%rn
The analogous expansions apply to
ld.x, st.x, fld.x, pfld.x, fst.x
, andpst.x
as well. - Signed large immediate with add/subtract:
If any of the arithmetic operations
adds, addu, subs, subu
are used with an immediate larger than 16-bits (signed), then they will be expanded. For instance, the pseudo-instructionadds large_imm,%rx,%rn
expands to:orh large_imm@h,%r0,%r31 or large_imm@l,%r31,%r31 adds %r31,%rx,%rn
- Unsigned large immediate with logical operations:
Logical operations (
or, andnot, or, xor
) also result in expansions. The pseudo-instructionor large_imm,%rx,%rn
results in:orh large_imm@h,%rx,%r31 or large_imm@l,%r31,%rn
Similarly for the others, except for
and
which expands to:andnot (-1 - large_imm)@h,%rx,%r31 andnot (-1 - large_imm)@l,%r31,%rn