// AT91SAM7S128 register and bit definitions.
//
// Copyright (c) 2005 Rowley Associates Limited.
//
// This file may be distributed under the terms of the License Agreement
// provided with this software.
//
// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE
// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.

#ifndef AT91SAM7S128_h
#define AT91SAM7S128_h

#define AIC_BASE 0xFFFFF000

#define AIC_SMR0 (*(volatile unsigned long *)0xFFFFF000)
#define AIC_SMR0_OFFSET 0x0
#define AIC_SMR0_PRIOR_MASK 0x7U
#define AIC_SMR0_PRIOR_BIT 0
#define AIC_SMR0_SRCTYPE_MASK 0x60U
#define AIC_SMR0_SRCTYPE_BIT 5

#define AIC_SMR1 (*(volatile unsigned long *)0xFFFFF004)
#define AIC_SMR1_OFFSET 0x4
#define AIC_SMR1_PRIOR_MASK 0x7U
#define AIC_SMR1_PRIOR_BIT 0
#define AIC_SMR1_SRCTYPE_MASK 0x60U
#define AIC_SMR1_SRCTYPE_BIT 5

#define AIC_SMR2 (*(volatile unsigned long *)0xFFFFF008)
#define AIC_SMR2_OFFSET 0x8
#define AIC_SMR2_PRIOR_MASK 0x7U
#define AIC_SMR2_PRIOR_BIT 0
#define AIC_SMR2_SRCTYPE_MASK 0x60U
#define AIC_SMR2_SRCTYPE_BIT 5

#define AIC_SMR3 (*(volatile unsigned long *)0xFFFFF00C)
#define AIC_SMR3_OFFSET 0xC
#define AIC_SMR3_PRIOR_MASK 0x7U
#define AIC_SMR3_PRIOR_BIT 0
#define AIC_SMR3_SRCTYPE_MASK 0x60U
#define AIC_SMR3_SRCTYPE_BIT 5

#define AIC_SMR4 (*(volatile unsigned long *)0xFFFFF010)
#define AIC_SMR4_OFFSET 0x10
#define AIC_SMR4_PRIOR_MASK 0x7U
#define AIC_SMR4_PRIOR_BIT 0
#define AIC_SMR4_SRCTYPE_MASK 0x60U
#define AIC_SMR4_SRCTYPE_BIT 5

#define AIC_SMR5 (*(volatile unsigned long *)0xFFFFF014)
#define AIC_SMR5_OFFSET 0x14
#define AIC_SMR5_PRIOR_MASK 0x7U
#define AIC_SMR5_PRIOR_BIT 0
#define AIC_SMR5_SRCTYPE_MASK 0x60U
#define AIC_SMR5_SRCTYPE_BIT 5

#define AIC_SMR6 (*(volatile unsigned long *)0xFFFFF018)
#define AIC_SMR6_OFFSET 0x18
#define AIC_SMR6_PRIOR_MASK 0x7U
#define AIC_SMR6_PRIOR_BIT 0
#define AIC_SMR6_SRCTYPE_MASK 0x60U
#define AIC_SMR6_SRCTYPE_BIT 5

#define AIC_SMR7 (*(volatile unsigned long *)0xFFFFF01C)
#define AIC_SMR7_OFFSET 0x1C
#define AIC_SMR7_PRIOR_MASK 0x7U
#define AIC_SMR7_PRIOR_BIT 0
#define AIC_SMR7_SRCTYPE_MASK 0x60U
#define AIC_SMR7_SRCTYPE_BIT 5

#define AIC_SMR8 (*(volatile unsigned long *)0xFFFFF020)
#define AIC_SMR8_OFFSET 0x20
#define AIC_SMR8_PRIOR_MASK 0x7U
#define AIC_SMR8_PRIOR_BIT 0
#define AIC_SMR8_SRCTYPE_MASK 0x60U
#define AIC_SMR8_SRCTYPE_BIT 5

#define AIC_SMR9 (*(volatile unsigned long *)0xFFFFF024)
#define AIC_SMR9_OFFSET 0x24
#define AIC_SMR9_PRIOR_MASK 0x7U
#define AIC_SMR9_PRIOR_BIT 0
#define AIC_SMR9_SRCTYPE_MASK 0x60U
#define AIC_SMR9_SRCTYPE_BIT 5

#define AIC_SMR10 (*(volatile unsigned long *)0xFFFFF028)
#define AIC_SMR10_OFFSET 0x28
#define AIC_SMR10_PRIOR_MASK 0x7U
#define AIC_SMR10_PRIOR_BIT 0
#define AIC_SMR10_SRCTYPE_MASK 0x60U
#define AIC_SMR10_SRCTYPE_BIT 5

#define AIC_SMR11 (*(volatile unsigned long *)0xFFFFF02C)
#define AIC_SMR11_OFFSET 0x2C
#define AIC_SMR11_PRIOR_MASK 0x7U
#define AIC_SMR11_PRIOR_BIT 0
#define AIC_SMR11_SRCTYPE_MASK 0x60U
#define AIC_SMR11_SRCTYPE_BIT 5

#define AIC_SMR12 (*(volatile unsigned long *)0xFFFFF030)
#define AIC_SMR12_OFFSET 0x30
#define AIC_SMR12_PRIOR_MASK 0x7U
#define AIC_SMR12_PRIOR_BIT 0
#define AIC_SMR12_SRCTYPE_MASK 0x60U
#define AIC_SMR12_SRCTYPE_BIT 5

#define AIC_SMR13 (*(volatile unsigned long *)0xFFFFF034)
#define AIC_SMR13_OFFSET 0x34
#define AIC_SMR13_PRIOR_MASK 0x7U
#define AIC_SMR13_PRIOR_BIT 0
#define AIC_SMR13_SRCTYPE_MASK 0x60U
#define AIC_SMR13_SRCTYPE_BIT 5

#define AIC_SMR14 (*(volatile unsigned long *)0xFFFFF038)
#define AIC_SMR14_OFFSET 0x38
#define AIC_SMR14_PRIOR_MASK 0x7U
#define AIC_SMR14_PRIOR_BIT 0
#define AIC_SMR14_SRCTYPE_MASK 0x60U
#define AIC_SMR14_SRCTYPE_BIT 5

#define AIC_SMR15 (*(volatile unsigned long *)0xFFFFF03C)
#define AIC_SMR15_OFFSET 0x3C
#define AIC_SMR15_PRIOR_MASK 0x7U
#define AIC_SMR15_PRIOR_BIT 0
#define AIC_SMR15_SRCTYPE_MASK 0x60U
#define AIC_SMR15_SRCTYPE_BIT 5

#define AIC_SMR16 (*(volatile unsigned long *)0xFFFFF040)
#define AIC_SMR16_OFFSET 0x40
#define AIC_SMR16_PRIOR_MASK 0x7U
#define AIC_SMR16_PRIOR_BIT 0
#define AIC_SMR16_SRCTYPE_MASK 0x60U
#define AIC_SMR16_SRCTYPE_BIT 5

#define AIC_SMR17 (*(volatile unsigned long *)0xFFFFF044)
#define AIC_SMR17_OFFSET 0x44
#define AIC_SMR17_PRIOR_MASK 0x7U
#define AIC_SMR17_PRIOR_BIT 0
#define AIC_SMR17_SRCTYPE_MASK 0x60U
#define AIC_SMR17_SRCTYPE_BIT 5

#define AIC_SMR18 (*(volatile unsigned long *)0xFFFFF048)
#define AIC_SMR18_OFFSET 0x48
#define AIC_SMR18_PRIOR_MASK 0x7U
#define AIC_SMR18_PRIOR_BIT 0
#define AIC_SMR18_SRCTYPE_MASK 0x60U
#define AIC_SMR18_SRCTYPE_BIT 5

#define AIC_SMR19 (*(volatile unsigned long *)0xFFFFF04C)
#define AIC_SMR19_OFFSET 0x4C
#define AIC_SMR19_PRIOR_MASK 0x7U
#define AIC_SMR19_PRIOR_BIT 0
#define AIC_SMR19_SRCTYPE_MASK 0x60U
#define AIC_SMR19_SRCTYPE_BIT 5

#define AIC_SMR20 (*(volatile unsigned long *)0xFFFFF050)
#define AIC_SMR20_OFFSET 0x50
#define AIC_SMR20_PRIOR_MASK 0x7U
#define AIC_SMR20_PRIOR_BIT 0
#define AIC_SMR20_SRCTYPE_MASK 0x60U
#define AIC_SMR20_SRCTYPE_BIT 5

#define AIC_SMR21 (*(volatile unsigned long *)0xFFFFF054)
#define AIC_SMR21_OFFSET 0x54
#define AIC_SMR21_PRIOR_MASK 0x7U
#define AIC_SMR21_PRIOR_BIT 0
#define AIC_SMR21_SRCTYPE_MASK 0x60U
#define AIC_SMR21_SRCTYPE_BIT 5

#define AIC_SMR22 (*(volatile unsigned long *)0xFFFFF058)
#define AIC_SMR22_OFFSET 0x58
#define AIC_SMR22_PRIOR_MASK 0x7U
#define AIC_SMR22_PRIOR_BIT 0
#define AIC_SMR22_SRCTYPE_MASK 0x60U
#define AIC_SMR22_SRCTYPE_BIT 5

#define AIC_SMR23 (*(volatile unsigned long *)0xFFFFF05C)
#define AIC_SMR23_OFFSET 0x5C
#define AIC_SMR23_PRIOR_MASK 0x7U
#define AIC_SMR23_PRIOR_BIT 0
#define AIC_SMR23_SRCTYPE_MASK 0x60U
#define AIC_SMR23_SRCTYPE_BIT 5

#define AIC_SMR24 (*(volatile unsigned long *)0xFFFFF060)
#define AIC_SMR24_OFFSET 0x60
#define AIC_SMR24_PRIOR_MASK 0x7U
#define AIC_SMR24_PRIOR_BIT 0
#define AIC_SMR24_SRCTYPE_MASK 0x60U
#define AIC_SMR24_SRCTYPE_BIT 5

#define AIC_SMR25 (*(volatile unsigned long *)0xFFFFF064)
#define AIC_SMR25_OFFSET 0x64
#define AIC_SMR25_PRIOR_MASK 0x7U
#define AIC_SMR25_PRIOR_BIT 0
#define AIC_SMR25_SRCTYPE_MASK 0x60U
#define AIC_SMR25_SRCTYPE_BIT 5

#define AIC_SMR26 (*(volatile unsigned long *)0xFFFFF068)
#define AIC_SMR26_OFFSET 0x68
#define AIC_SMR26_PRIOR_MASK 0x7U
#define AIC_SMR26_PRIOR_BIT 0
#define AIC_SMR26_SRCTYPE_MASK 0x60U
#define AIC_SMR26_SRCTYPE_BIT 5

#define AIC_SMR27 (*(volatile unsigned long *)0xFFFFF06C)
#define AIC_SMR27_OFFSET 0x6C
#define AIC_SMR27_PRIOR_MASK 0x7U
#define AIC_SMR27_PRIOR_BIT 0
#define AIC_SMR27_SRCTYPE_MASK 0x60U
#define AIC_SMR27_SRCTYPE_BIT 5

#define AIC_SMR28 (*(volatile unsigned long *)0xFFFFF070)
#define AIC_SMR28_OFFSET 0x70
#define AIC_SMR28_PRIOR_MASK 0x7U
#define AIC_SMR28_PRIOR_BIT 0
#define AIC_SMR28_SRCTYPE_MASK 0x60U
#define AIC_SMR28_SRCTYPE_BIT 5

#define AIC_SMR29 (*(volatile unsigned long *)0xFFFFF074)
#define AIC_SMR29_OFFSET 0x74
#define AIC_SMR29_PRIOR_MASK 0x7U
#define AIC_SMR29_PRIOR_BIT 0
#define AIC_SMR29_SRCTYPE_MASK 0x60U
#define AIC_SMR29_SRCTYPE_BIT 5

#define AIC_SMR30 (*(volatile unsigned long *)0xFFFFF078)
#define AIC_SMR30_OFFSET 0x78
#define AIC_SMR30_PRIOR_MASK 0x7U
#define AIC_SMR30_PRIOR_BIT 0
#define AIC_SMR30_SRCTYPE_MASK 0x60U
#define AIC_SMR30_SRCTYPE_BIT 5

#define AIC_SMR31 (*(volatile unsigned long *)0xFFFFF07C)
#define AIC_SMR31_OFFSET 0x7C
#define AIC_SMR31_PRIOR_MASK 0x7U
#define AIC_SMR31_PRIOR_BIT 0
#define AIC_SMR31_SRCTYPE_MASK 0x60U
#define AIC_SMR31_SRCTYPE_BIT 5

#define AIC_SVR0 (*(volatile unsigned long *)0xFFFFF080)
#define AIC_SVR0_OFFSET 0x80

#define AIC_SVR1 (*(volatile unsigned long *)0xFFFFF084)
#define AIC_SVR1_OFFSET 0x84

#define AIC_SVR2 (*(volatile unsigned long *)0xFFFFF088)
#define AIC_SVR2_OFFSET 0x88

#define AIC_SVR3 (*(volatile unsigned long *)0xFFFFF08C)
#define AIC_SVR3_OFFSET 0x8C

#define AIC_SVR4 (*(volatile unsigned long *)0xFFFFF090)
#define AIC_SVR4_OFFSET 0x90

#define AIC_SVR5 (*(volatile unsigned long *)0xFFFFF094)
#define AIC_SVR5_OFFSET 0x94

#define AIC_SVR6 (*(volatile unsigned long *)0xFFFFF098)
#define AIC_SVR6_OFFSET 0x98

#define AIC_SVR7 (*(volatile unsigned long *)0xFFFFF09C)
#define AIC_SVR7_OFFSET 0x9C

#define AIC_SVR8 (*(volatile unsigned long *)0xFFFFF0A0)
#define AIC_SVR8_OFFSET 0xA0

#define AIC_SVR9 (*(volatile unsigned long *)0xFFFFF0A4)
#define AIC_SVR9_OFFSET 0xA4

#define AIC_SVR10 (*(volatile unsigned long *)0xFFFFF0A8)
#define AIC_SVR10_OFFSET 0xA8

#define AIC_SVR11 (*(volatile unsigned long *)0xFFFFF0AC)
#define AIC_SVR11_OFFSET 0xAC

#define AIC_SVR12 (*(volatile unsigned long *)0xFFFFF0B0)
#define AIC_SVR12_OFFSET 0xB0

#define AIC_SVR13 (*(volatile unsigned long *)0xFFFFF0B4)
#define AIC_SVR13_OFFSET 0xB4

#define AIC_SVR14 (*(volatile unsigned long *)0xFFFFF0B8)
#define AIC_SVR14_OFFSET 0xB8

#define AIC_SVR15 (*(volatile unsigned long *)0xFFFFF0BC)
#define AIC_SVR15_OFFSET 0xBC

#define AIC_SVR16 (*(volatile unsigned long *)0xFFFFF0C0)
#define AIC_SVR16_OFFSET 0xC0

#define AIC_SVR17 (*(volatile unsigned long *)0xFFFFF0C4)
#define AIC_SVR17_OFFSET 0xC4

#define AIC_SVR18 (*(volatile unsigned long *)0xFFFFF0C8)
#define AIC_SVR18_OFFSET 0xC8

#define AIC_SVR19 (*(volatile unsigned long *)0xFFFFF0CC)
#define AIC_SVR19_OFFSET 0xCC

#define AIC_SVR20 (*(volatile unsigned long *)0xFFFFF0D0)
#define AIC_SVR20_OFFSET 0xD0

#define AIC_SVR21 (*(volatile unsigned long *)0xFFFFF0D4)
#define AIC_SVR21_OFFSET 0xD4

#define AIC_SVR22 (*(volatile unsigned long *)0xFFFFF0D8)
#define AIC_SVR22_OFFSET 0xD8

#define AIC_SVR23 (*(volatile unsigned long *)0xFFFFF0DC)
#define AIC_SVR23_OFFSET 0xDC

#define AIC_SVR24 (*(volatile unsigned long *)0xFFFFF0E0)
#define AIC_SVR24_OFFSET 0xE0

#define AIC_SVR25 (*(volatile unsigned long *)0xFFFFF0E4)
#define AIC_SVR25_OFFSET 0xE4

#define AIC_SVR26 (*(volatile unsigned long *)0xFFFFF0E8)
#define AIC_SVR26_OFFSET 0xE8

#define AIC_SVR27 (*(volatile unsigned long *)0xFFFFF0EC)
#define AIC_SVR27_OFFSET 0xEC

#define AIC_SVR28 (*(volatile unsigned long *)0xFFFFF0F0)
#define AIC_SVR28_OFFSET 0xF0

#define AIC_SVR29 (*(volatile unsigned long *)0xFFFFF0F4)
#define AIC_SVR29_OFFSET 0xF4

#define AIC_SVR30 (*(volatile unsigned long *)0xFFFFF0F8)
#define AIC_SVR30_OFFSET 0xF8

#define AIC_SVR31 (*(volatile unsigned long *)0xFFFFF0FC)
#define AIC_SVR31_OFFSET 0xFC

#define AIC_IVR (*(volatile unsigned long *)0xFFFFF100)
#define AIC_IVR_OFFSET 0x100

#define AIC_FVR (*(volatile unsigned long *)0xFFFFF104)
#define AIC_FVR_OFFSET 0x104

#define AIC_ISR (*(volatile unsigned long *)0xFFFFF108)
#define AIC_ISR_OFFSET 0x108

#define AIC_IPR (*(volatile unsigned long *)0xFFFFF10C)
#define AIC_IPR_OFFSET 0x10C
#define AIC_IPR_FIQ_MASK 0x1U
#define AIC_IPR_FIQ 0x1U
#define AIC_IPR_FIQ_BIT 0
#define AIC_IPR_SYS_MASK 0x2U
#define AIC_IPR_SYS 0x2U
#define AIC_IPR_SYS_BIT 1
#define AIC_IPR_PID2_MASK 0x4U
#define AIC_IPR_PID2 0x4U
#define AIC_IPR_PID2_BIT 2
#define AIC_IPR_PID3_MASK 0x8U
#define AIC_IPR_PID3 0x8U
#define AIC_IPR_PID3_BIT 3
#define AIC_IPR_PID4_MASK 0x10U
#define AIC_IPR_PID4 0x10U
#define AIC_IPR_PID4_BIT 4
#define AIC_IPR_PID5_MASK 0x20U
#define AIC_IPR_PID5 0x20U
#define AIC_IPR_PID5_BIT 5
#define AIC_IPR_PID6_MASK 0x40U
#define AIC_IPR_PID6 0x40U
#define AIC_IPR_PID6_BIT 6
#define AIC_IPR_PID7_MASK 0x80U
#define AIC_IPR_PID7 0x80U
#define AIC_IPR_PID7_BIT 7
#define AIC_IPR_PID8_MASK 0x100U
#define AIC_IPR_PID8 0x100U
#define AIC_IPR_PID8_BIT 8
#define AIC_IPR_PID9_MASK 0x200U
#define AIC_IPR_PID9 0x200U
#define AIC_IPR_PID9_BIT 9
#define AIC_IPR_PID10_MASK 0x400U
#define AIC_IPR_PID10 0x400U
#define AIC_IPR_PID10_BIT 10
#define AIC_IPR_PID11_MASK 0x800U
#define AIC_IPR_PID11 0x800U
#define AIC_IPR_PID11_BIT 11
#define AIC_IPR_PID12_MASK 0x1000U
#define AIC_IPR_PID12 0x1000U
#define AIC_IPR_PID12_BIT 12
#define AIC_IPR_PID13_MASK 0x2000U
#define AIC_IPR_PID13 0x2000U
#define AIC_IPR_PID13_BIT 13
#define AIC_IPR_PID14_MASK 0x4000U
#define AIC_IPR_PID14 0x4000U
#define AIC_IPR_PID14_BIT 14
#define AIC_IPR_PID15_MASK 0x8000U
#define AIC_IPR_PID15 0x8000U
#define AIC_IPR_PID15_BIT 15
#define AIC_IPR_PID16_MASK 0x10000U
#define AIC_IPR_PID16 0x10000U
#define AIC_IPR_PID16_BIT 16
#define AIC_IPR_PID17_MASK 0x20000U
#define AIC_IPR_PID17 0x20000U
#define AIC_IPR_PID17_BIT 17
#define AIC_IPR_PID18_MASK 0x40000U
#define AIC_IPR_PID18 0x40000U
#define AIC_IPR_PID18_BIT 18
#define AIC_IPR_PID19_MASK 0x80000U
#define AIC_IPR_PID19 0x80000U
#define AIC_IPR_PID19_BIT 19
#define AIC_IPR_PID20_MASK 0x100000U
#define AIC_IPR_PID20 0x100000U
#define AIC_IPR_PID20_BIT 20
#define AIC_IPR_PID21_MASK 0x200000U
#define AIC_IPR_PID21 0x200000U
#define AIC_IPR_PID21_BIT 21
#define AIC_IPR_PID22_MASK 0x400000U
#define AIC_IPR_PID22 0x400000U
#define AIC_IPR_PID22_BIT 22
#define AIC_IPR_PID23_MASK 0x800000U
#define AIC_IPR_PID23 0x800000U
#define AIC_IPR_PID23_BIT 23
#define AIC_IPR_PID24_MASK 0x1000000U
#define AIC_IPR_PID24 0x1000000U
#define AIC_IPR_PID24_BIT 24
#define AIC_IPR_PID25_MASK 0x2000000U
#define AIC_IPR_PID25 0x2000000U
#define AIC_IPR_PID25_BIT 25
#define AIC_IPR_PID26_MASK 0x4000000U
#define AIC_IPR_PID26 0x4000000U
#define AIC_IPR_PID26_BIT 26
#define AIC_IPR_PID27_MASK 0x8000000U
#define AIC_IPR_PID27 0x8000000U
#define AIC_IPR_PID27_BIT 27
#define AIC_IPR_PID28_MASK 0x10000000U
#define AIC_IPR_PID28 0x10000000U
#define AIC_IPR_PID28_BIT 28
#define AIC_IPR_PID29_MASK 0x20000000U
#define AIC_IPR_PID29 0x20000000U
#define AIC_IPR_PID29_BIT 29
#define AIC_IPR_PID30_MASK 0x40000000U
#define AIC_IPR_PID30 0x40000000U
#define AIC_IPR_PID30_BIT 30
#define AIC_IPR_PID31_MASK 0x80000000U
#define AIC_IPR_PID31 0x80000000U
#define AIC_IPR_PID31_BIT 31

#define AIC_IMR (*(volatile unsigned long *)0xFFFFF110)
#define AIC_IMR_OFFSET 0x110
#define AIC_IMR_FIQ_MASK 0x1U
#define AIC_IMR_FIQ 0x1U
#define AIC_IMR_FIQ_BIT 0
#define AIC_IMR_SYS_MASK 0x2U
#define AIC_IMR_SYS 0x2U
#define AIC_IMR_SYS_BIT 1
#define AIC_IMR_PID2_MASK 0x4U
#define AIC_IMR_PID2 0x4U
#define AIC_IMR_PID2_BIT 2
#define AIC_IMR_PID3_MASK 0x8U
#define AIC_IMR_PID3 0x8U
#define AIC_IMR_PID3_BIT 3
#define AIC_IMR_PID4_MASK 0x10U
#define AIC_IMR_PID4 0x10U
#define AIC_IMR_PID4_BIT 4
#define AIC_IMR_PID5_MASK 0x20U
#define AIC_IMR_PID5 0x20U
#define AIC_IMR_PID5_BIT 5
#define AIC_IMR_PID6_MASK 0x40U
#define AIC_IMR_PID6 0x40U
#define AIC_IMR_PID6_BIT 6
#define AIC_IMR_PID7_MASK 0x80U
#define AIC_IMR_PID7 0x80U
#define AIC_IMR_PID7_BIT 7
#define AIC_IMR_PID8_MASK 0x100U
#define AIC_IMR_PID8 0x100U
#define AIC_IMR_PID8_BIT 8
#define AIC_IMR_PID9_MASK 0x200U
#define AIC_IMR_PID9 0x200U
#define AIC_IMR_PID9_BIT 9
#define AIC_IMR_PID10_MASK 0x400U
#define AIC_IMR_PID10 0x400U
#define AIC_IMR_PID10_BIT 10
#define AIC_IMR_PID11_MASK 0x800U
#define AIC_IMR_PID11 0x800U
#define AIC_IMR_PID11_BIT 11
#define AIC_IMR_PID12_MASK 0x1000U
#define AIC_IMR_PID12 0x1000U
#define AIC_IMR_PID12_BIT 12
#define AIC_IMR_PID13_MASK 0x2000U
#define AIC_IMR_PID13 0x2000U
#define AIC_IMR_PID13_BIT 13
#define AIC_IMR_PID14_MASK 0x4000U
#define AIC_IMR_PID14 0x4000U
#define AIC_IMR_PID14_BIT 14
#define AIC_IMR_PID15_MASK 0x8000U
#define AIC_IMR_PID15 0x8000U
#define AIC_IMR_PID15_BIT 15
#define AIC_IMR_PID16_MASK 0x10000U
#define AIC_IMR_PID16 0x10000U
#define AIC_IMR_PID16_BIT 16
#define AIC_IMR_PID17_MASK 0x20000U
#define AIC_IMR_PID17 0x20000U
#define AIC_IMR_PID17_BIT 17
#define AIC_IMR_PID18_MASK 0x40000U
#define AIC_IMR_PID18 0x40000U
#define AIC_IMR_PID18_BIT 18
#define AIC_IMR_PID19_MASK 0x80000U
#define AIC_IMR_PID19 0x80000U
#define AIC_IMR_PID19_BIT 19
#define AIC_IMR_PID20_MASK 0x100000U
#define AIC_IMR_PID20 0x100000U
#define AIC_IMR_PID20_BIT 20
#define AIC_IMR_PID21_MASK 0x200000U
#define AIC_IMR_PID21 0x200000U
#define AIC_IMR_PID21_BIT 21
#define AIC_IMR_PID22_MASK 0x400000U
#define AIC_IMR_PID22 0x400000U
#define AIC_IMR_PID22_BIT 22
#define AIC_IMR_PID23_MASK 0x800000U
#define AIC_IMR_PID23 0x800000U
#define AIC_IMR_PID23_BIT 23
#define AIC_IMR_PID24_MASK 0x1000000U
#define AIC_IMR_PID24 0x1000000U
#define AIC_IMR_PID24_BIT 24
#define AIC_IMR_PID25_MASK 0x2000000U
#define AIC_IMR_PID25 0x2000000U
#define AIC_IMR_PID25_BIT 25
#define AIC_IMR_PID26_MASK 0x4000000U
#define AIC_IMR_PID26 0x4000000U
#define AIC_IMR_PID26_BIT 26
#define AIC_IMR_PID27_MASK 0x8000000U
#define AIC_IMR_PID27 0x8000000U
#define AIC_IMR_PID27_BIT 27
#define AIC_IMR_PID28_MASK 0x10000000U
#define AIC_IMR_PID28 0x10000000U
#define AIC_IMR_PID28_BIT 28
#define AIC_IMR_PID29_MASK 0x20000000U
#define AIC_IMR_PID29 0x20000000U
#define AIC_IMR_PID29_BIT 29
#define AIC_IMR_PID30_MASK 0x40000000U
#define AIC_IMR_PID30 0x40000000U
#define AIC_IMR_PID30_BIT 30
#define AIC_IMR_PID31_MASK 0x80000000U
#define AIC_IMR_PID31 0x80000000U
#define AIC_IMR_PID31_BIT 31

#define AIC_CISR (*(volatile unsigned long *)0xFFFFF114)
#define AIC_CISR_OFFSET 0x114
#define AIC_CISR_NFIQ_MASK 0x1U
#define AIC_CISR_NFIQ 0x1U
#define AIC_CISR_NFIQ_BIT 0
#define AIC_CISR_NIRQ_MASK 0x2U
#define AIC_CISR_NIRQ 0x2U
#define AIC_CISR_NIRQ_BIT 1

#define AIC_IECR (*(volatile unsigned long *)0xFFFFF120)
#define AIC_IECR_OFFSET 0x120
#define AIC_IECR_FIQ_MASK 0x1U
#define AIC_IECR_FIQ 0x1U
#define AIC_IECR_FIQ_BIT 0
#define AIC_IECR_SYS_MASK 0x2U
#define AIC_IECR_SYS 0x2U
#define AIC_IECR_SYS_BIT 1
#define AIC_IECR_PID2_MASK 0x4U
#define AIC_IECR_PID2 0x4U
#define AIC_IECR_PID2_BIT 2
#define AIC_IECR_PID3_MASK 0x8U
#define AIC_IECR_PID3 0x8U
#define AIC_IECR_PID3_BIT 3
#define AIC_IECR_PID4_MASK 0x10U
#define AIC_IECR_PID4 0x10U
#define AIC_IECR_PID4_BIT 4
#define AIC_IECR_PID5_MASK 0x20U
#define AIC_IECR_PID5 0x20U
#define AIC_IECR_PID5_BIT 5
#define AIC_IECR_PID6_MASK 0x40U
#define AIC_IECR_PID6 0x40U
#define AIC_IECR_PID6_BIT 6
#define AIC_IECR_PID7_MASK 0x80U
#define AIC_IECR_PID7 0x80U
#define AIC_IECR_PID7_BIT 7
#define AIC_IECR_PID8_MASK 0x100U
#define AIC_IECR_PID8 0x100U
#define AIC_IECR_PID8_BIT 8
#define AIC_IECR_PID9_MASK 0x200U
#define AIC_IECR_PID9 0x200U
#define AIC_IECR_PID9_BIT 9
#define AIC_IECR_PID10_MASK 0x400U
#define AIC_IECR_PID10 0x400U
#define AIC_IECR_PID10_BIT 10
#define AIC_IECR_PID11_MASK 0x800U
#define AIC_IECR_PID11 0x800U
#define AIC_IECR_PID11_BIT 11
#define AIC_IECR_PID12_MASK 0x1000U
#define AIC_IECR_PID12 0x1000U
#define AIC_IECR_PID12_BIT 12
#define AIC_IECR_PID13_MASK 0x2000U
#define AIC_IECR_PID13 0x2000U
#define AIC_IECR_PID13_BIT 13
#define AIC_IECR_PID14_MASK 0x4000U
#define AIC_IECR_PID14 0x4000U
#define AIC_IECR_PID14_BIT 14
#define AIC_IECR_PID15_MASK 0x8000U
#define AIC_IECR_PID15 0x8000U
#define AIC_IECR_PID15_BIT 15
#define AIC_IECR_PID16_MASK 0x10000U
#define AIC_IECR_PID16 0x10000U
#define AIC_IECR_PID16_BIT 16
#define AIC_IECR_PID17_MASK 0x20000U
#define AIC_IECR_PID17 0x20000U
#define AIC_IECR_PID17_BIT 17
#define AIC_IECR_PID18_MASK 0x40000U
#define AIC_IECR_PID18 0x40000U
#define AIC_IECR_PID18_BIT 18
#define AIC_IECR_PID19_MASK 0x80000U
#define AIC_IECR_PID19 0x80000U
#define AIC_IECR_PID19_BIT 19
#define AIC_IECR_PID20_MASK 0x100000U
#define AIC_IECR_PID20 0x100000U
#define AIC_IECR_PID20_BIT 20
#define AIC_IECR_PID21_MASK 0x200000U
#define AIC_IECR_PID21 0x200000U
#define AIC_IECR_PID21_BIT 21
#define AIC_IECR_PID22_MASK 0x400000U
#define AIC_IECR_PID22 0x400000U
#define AIC_IECR_PID22_BIT 22
#define AIC_IECR_PID23_MASK 0x800000U
#define AIC_IECR_PID23 0x800000U
#define AIC_IECR_PID23_BIT 23
#define AIC_IECR_PID24_MASK 0x1000000U
#define AIC_IECR_PID24 0x1000000U
#define AIC_IECR_PID24_BIT 24
#define AIC_IECR_PID25_MASK 0x2000000U
#define AIC_IECR_PID25 0x2000000U
#define AIC_IECR_PID25_BIT 25
#define AIC_IECR_PID26_MASK 0x4000000U
#define AIC_IECR_PID26 0x4000000U
#define AIC_IECR_PID26_BIT 26
#define AIC_IECR_PID27_MASK 0x8000000U
#define AIC_IECR_PID27 0x8000000U
#define AIC_IECR_PID27_BIT 27
#define AIC_IECR_PID28_MASK 0x10000000U
#define AIC_IECR_PID28 0x10000000U
#define AIC_IECR_PID28_BIT 28
#define AIC_IECR_PID29_MASK 0x20000000U
#define AIC_IECR_PID29 0x20000000U
#define AIC_IECR_PID29_BIT 29
#define AIC_IECR_PID30_MASK 0x40000000U
#define AIC_IECR_PID30 0x40000000U
#define AIC_IECR_PID30_BIT 30
#define AIC_IECR_PID31_MASK 0x80000000U
#define AIC_IECR_PID31 0x80000000U
#define AIC_IECR_PID31_BIT 31

#define AIC_IDCR (*(volatile unsigned long *)0xFFFFF124)
#define AIC_IDCR_OFFSET 0x124
#define AIC_IDCR_FIQ_MASK 0x1U
#define AIC_IDCR_FIQ 0x1U
#define AIC_IDCR_FIQ_BIT 0
#define AIC_IDCR_SYS_MASK 0x2U
#define AIC_IDCR_SYS 0x2U
#define AIC_IDCR_SYS_BIT 1
#define AIC_IDCR_PID2_MASK 0x4U
#define AIC_IDCR_PID2 0x4U
#define AIC_IDCR_PID2_BIT 2
#define AIC_IDCR_PID3_MASK 0x8U
#define AIC_IDCR_PID3 0x8U
#define AIC_IDCR_PID3_BIT 3
#define AIC_IDCR_PID4_MASK 0x10U
#define AIC_IDCR_PID4 0x10U
#define AIC_IDCR_PID4_BIT 4
#define AIC_IDCR_PID5_MASK 0x20U
#define AIC_IDCR_PID5 0x20U
#define AIC_IDCR_PID5_BIT 5
#define AIC_IDCR_PID6_MASK 0x40U
#define AIC_IDCR_PID6 0x40U
#define AIC_IDCR_PID6_BIT 6
#define AIC_IDCR_PID7_MASK 0x80U
#define AIC_IDCR_PID7 0x80U
#define AIC_IDCR_PID7_BIT 7
#define AIC_IDCR_PID8_MASK 0x100U
#define AIC_IDCR_PID8 0x100U
#define AIC_IDCR_PID8_BIT 8
#define AIC_IDCR_PID9_MASK 0x200U
#define AIC_IDCR_PID9 0x200U
#define AIC_IDCR_PID9_BIT 9
#define AIC_IDCR_PID10_MASK 0x400U
#define AIC_IDCR_PID10 0x400U
#define AIC_IDCR_PID10_BIT 10
#define AIC_IDCR_PID11_MASK 0x800U
#define AIC_IDCR_PID11 0x800U
#define AIC_IDCR_PID11_BIT 11
#define AIC_IDCR_PID12_MASK 0x1000U
#define AIC_IDCR_PID12 0x1000U
#define AIC_IDCR_PID12_BIT 12
#define AIC_IDCR_PID13_MASK 0x2000U
#define AIC_IDCR_PID13 0x2000U
#define AIC_IDCR_PID13_BIT 13
#define AIC_IDCR_PID14_MASK 0x4000U
#define AIC_IDCR_PID14 0x4000U
#define AIC_IDCR_PID14_BIT 14
#define AIC_IDCR_PID15_MASK 0x8000U
#define AIC_IDCR_PID15 0x8000U
#define AIC_IDCR_PID15_BIT 15
#define AIC_IDCR_PID16_MASK 0x10000U
#define AIC_IDCR_PID16 0x10000U
#define AIC_IDCR_PID16_BIT 16
#define AIC_IDCR_PID17_MASK 0x20000U
#define AIC_IDCR_PID17 0x20000U
#define AIC_IDCR_PID17_BIT 17
#define AIC_IDCR_PID18_MASK 0x40000U
#define AIC_IDCR_PID18 0x40000U
#define AIC_IDCR_PID18_BIT 18
#define AIC_IDCR_PID19_MASK 0x80000U
#define AIC_IDCR_PID19 0x80000U
#define AIC_IDCR_PID19_BIT 19
#define AIC_IDCR_PID20_MASK 0x100000U
#define AIC_IDCR_PID20 0x100000U
#define AIC_IDCR_PID20_BIT 20
#define AIC_IDCR_PID21_MASK 0x200000U
#define AIC_IDCR_PID21 0x200000U
#define AIC_IDCR_PID21_BIT 21
#define AIC_IDCR_PID22_MASK 0x400000U
#define AIC_IDCR_PID22 0x400000U
#define AIC_IDCR_PID22_BIT 22
#define AIC_IDCR_PID23_MASK 0x800000U
#define AIC_IDCR_PID23 0x800000U
#define AIC_IDCR_PID23_BIT 23
#define AIC_IDCR_PID24_MASK 0x1000000U
#define AIC_IDCR_PID24 0x1000000U
#define AIC_IDCR_PID24_BIT 24
#define AIC_IDCR_PID25_MASK 0x2000000U
#define AIC_IDCR_PID25 0x2000000U
#define AIC_IDCR_PID25_BIT 25
#define AIC_IDCR_PID26_MASK 0x4000000U
#define AIC_IDCR_PID26 0x4000000U
#define AIC_IDCR_PID26_BIT 26
#define AIC_IDCR_PID27_MASK 0x8000000U
#define AIC_IDCR_PID27 0x8000000U
#define AIC_IDCR_PID27_BIT 27
#define AIC_IDCR_PID28_MASK 0x10000000U
#define AIC_IDCR_PID28 0x10000000U
#define AIC_IDCR_PID28_BIT 28
#define AIC_IDCR_PID29_MASK 0x20000000U
#define AIC_IDCR_PID29 0x20000000U
#define AIC_IDCR_PID29_BIT 29
#define AIC_IDCR_PID30_MASK 0x40000000U
#define AIC_IDCR_PID30 0x40000000U
#define AIC_IDCR_PID30_BIT 30
#define AIC_IDCR_PID31_MASK 0x80000000U
#define AIC_IDCR_PID31 0x80000000U
#define AIC_IDCR_PID31_BIT 31

#define AIC_ICCR (*(volatile unsigned long *)0xFFFFF128)
#define AIC_ICCR_OFFSET 0x128
#define AIC_ICCR_FIQ_MASK 0x1U
#define AIC_ICCR_FIQ 0x1U
#define AIC_ICCR_FIQ_BIT 0
#define AIC_ICCR_SYS_MASK 0x2U
#define AIC_ICCR_SYS 0x2U
#define AIC_ICCR_SYS_BIT 1
#define AIC_ICCR_PID2_MASK 0x4U
#define AIC_ICCR_PID2 0x4U
#define AIC_ICCR_PID2_BIT 2
#define AIC_ICCR_PID3_MASK 0x8U
#define AIC_ICCR_PID3 0x8U
#define AIC_ICCR_PID3_BIT 3
#define AIC_ICCR_PID4_MASK 0x10U
#define AIC_ICCR_PID4 0x10U
#define AIC_ICCR_PID4_BIT 4
#define AIC_ICCR_PID5_MASK 0x20U
#define AIC_ICCR_PID5 0x20U
#define AIC_ICCR_PID5_BIT 5
#define AIC_ICCR_PID6_MASK 0x40U
#define AIC_ICCR_PID6 0x40U
#define AIC_ICCR_PID6_BIT 6
#define AIC_ICCR_PID7_MASK 0x80U
#define AIC_ICCR_PID7 0x80U
#define AIC_ICCR_PID7_BIT 7
#define AIC_ICCR_PID8_MASK 0x100U
#define AIC_ICCR_PID8 0x100U
#define AIC_ICCR_PID8_BIT 8
#define AIC_ICCR_PID9_MASK 0x200U
#define AIC_ICCR_PID9 0x200U
#define AIC_ICCR_PID9_BIT 9
#define AIC_ICCR_PID10_MASK 0x400U
#define AIC_ICCR_PID10 0x400U
#define AIC_ICCR_PID10_BIT 10
#define AIC_ICCR_PID11_MASK 0x800U
#define AIC_ICCR_PID11 0x800U
#define AIC_ICCR_PID11_BIT 11
#define AIC_ICCR_PID12_MASK 0x1000U
#define AIC_ICCR_PID12 0x1000U
#define AIC_ICCR_PID12_BIT 12
#define AIC_ICCR_PID13_MASK 0x2000U
#define AIC_ICCR_PID13 0x2000U
#define AIC_ICCR_PID13_BIT 13
#define AIC_ICCR_PID14_MASK 0x4000U
#define AIC_ICCR_PID14 0x4000U
#define AIC_ICCR_PID14_BIT 14
#define AIC_ICCR_PID15_MASK 0x8000U
#define AIC_ICCR_PID15 0x8000U
#define AIC_ICCR_PID15_BIT 15
#define AIC_ICCR_PID16_MASK 0x10000U
#define AIC_ICCR_PID16 0x10000U
#define AIC_ICCR_PID16_BIT 16
#define AIC_ICCR_PID17_MASK 0x20000U
#define AIC_ICCR_PID17 0x20000U
#define AIC_ICCR_PID17_BIT 17
#define AIC_ICCR_PID18_MASK 0x40000U
#define AIC_ICCR_PID18 0x40000U
#define AIC_ICCR_PID18_BIT 18
#define AIC_ICCR_PID19_MASK 0x80000U
#define AIC_ICCR_PID19 0x80000U
#define AIC_ICCR_PID19_BIT 19
#define AIC_ICCR_PID20_MASK 0x100000U
#define AIC_ICCR_PID20 0x100000U
#define AIC_ICCR_PID20_BIT 20
#define AIC_ICCR_PID21_MASK 0x200000U
#define AIC_ICCR_PID21 0x200000U
#define AIC_ICCR_PID21_BIT 21
#define AIC_ICCR_PID22_MASK 0x400000U
#define AIC_ICCR_PID22 0x400000U
#define AIC_ICCR_PID22_BIT 22
#define AIC_ICCR_PID23_MASK 0x800000U
#define AIC_ICCR_PID23 0x800000U
#define AIC_ICCR_PID23_BIT 23
#define AIC_ICCR_PID24_MASK 0x1000000U
#define AIC_ICCR_PID24 0x1000000U
#define AIC_ICCR_PID24_BIT 24
#define AIC_ICCR_PID25_MASK 0x2000000U
#define AIC_ICCR_PID25 0x2000000U
#define AIC_ICCR_PID25_BIT 25
#define AIC_ICCR_PID26_MASK 0x4000000U
#define AIC_ICCR_PID26 0x4000000U
#define AIC_ICCR_PID26_BIT 26
#define AIC_ICCR_PID27_MASK 0x8000000U
#define AIC_ICCR_PID27 0x8000000U
#define AIC_ICCR_PID27_BIT 27
#define AIC_ICCR_PID28_MASK 0x10000000U
#define AIC_ICCR_PID28 0x10000000U
#define AIC_ICCR_PID28_BIT 28
#define AIC_ICCR_PID29_MASK 0x20000000U
#define AIC_ICCR_PID29 0x20000000U
#define AIC_ICCR_PID29_BIT 29
#define AIC_ICCR_PID30_MASK 0x40000000U
#define AIC_ICCR_PID30 0x40000000U
#define AIC_ICCR_PID30_BIT 30
#define AIC_ICCR_PID31_MASK 0x80000000U
#define AIC_ICCR_PID31 0x80000000U
#define AIC_ICCR_PID31_BIT 31

#define AIC_ISCR (*(volatile unsigned long *)0xFFFFF12C)
#define AIC_ISCR_OFFSET 0x12C
#define AIC_ISCR_FIQ_MASK 0x1U
#define AIC_ISCR_FIQ 0x1U
#define AIC_ISCR_FIQ_BIT 0
#define AIC_ISCR_SYS_MASK 0x2U
#define AIC_ISCR_SYS 0x2U
#define AIC_ISCR_SYS_BIT 1
#define AIC_ISCR_PID2_MASK 0x4U
#define AIC_ISCR_PID2 0x4U
#define AIC_ISCR_PID2_BIT 2
#define AIC_ISCR_PID3_MASK 0x8U
#define AIC_ISCR_PID3 0x8U
#define AIC_ISCR_PID3_BIT 3
#define AIC_ISCR_PID4_MASK 0x10U
#define AIC_ISCR_PID4 0x10U
#define AIC_ISCR_PID4_BIT 4
#define AIC_ISCR_PID5_MASK 0x20U
#define AIC_ISCR_PID5 0x20U
#define AIC_ISCR_PID5_BIT 5
#define AIC_ISCR_PID6_MASK 0x40U
#define AIC_ISCR_PID6 0x40U
#define AIC_ISCR_PID6_BIT 6
#define AIC_ISCR_PID7_MASK 0x80U
#define AIC_ISCR_PID7 0x80U
#define AIC_ISCR_PID7_BIT 7
#define AIC_ISCR_PID8_MASK 0x100U
#define AIC_ISCR_PID8 0x100U
#define AIC_ISCR_PID8_BIT 8
#define AIC_ISCR_PID9_MASK 0x200U
#define AIC_ISCR_PID9 0x200U
#define AIC_ISCR_PID9_BIT 9
#define AIC_ISCR_PID10_MASK 0x400U
#define AIC_ISCR_PID10 0x400U
#define AIC_ISCR_PID10_BIT 10
#define AIC_ISCR_PID11_MASK 0x800U
#define AIC_ISCR_PID11 0x800U
#define AIC_ISCR_PID11_BIT 11
#define AIC_ISCR_PID12_MASK 0x1000U
#define AIC_ISCR_PID12 0x1000U
#define AIC_ISCR_PID12_BIT 12
#define AIC_ISCR_PID13_MASK 0x2000U
#define AIC_ISCR_PID13 0x2000U
#define AIC_ISCR_PID13_BIT 13
#define AIC_ISCR_PID14_MASK 0x4000U
#define AIC_ISCR_PID14 0x4000U
#define AIC_ISCR_PID14_BIT 14
#define AIC_ISCR_PID15_MASK 0x8000U
#define AIC_ISCR_PID15 0x8000U
#define AIC_ISCR_PID15_BIT 15
#define AIC_ISCR_PID16_MASK 0x10000U
#define AIC_ISCR_PID16 0x10000U
#define AIC_ISCR_PID16_BIT 16
#define AIC_ISCR_PID17_MASK 0x20000U
#define AIC_ISCR_PID17 0x20000U
#define AIC_ISCR_PID17_BIT 17
#define AIC_ISCR_PID18_MASK 0x40000U
#define AIC_ISCR_PID18 0x40000U
#define AIC_ISCR_PID18_BIT 18
#define AIC_ISCR_PID19_MASK 0x80000U
#define AIC_ISCR_PID19 0x80000U
#define AIC_ISCR_PID19_BIT 19
#define AIC_ISCR_PID20_MASK 0x100000U
#define AIC_ISCR_PID20 0x100000U
#define AIC_ISCR_PID20_BIT 20
#define AIC_ISCR_PID21_MASK 0x200000U
#define AIC_ISCR_PID21 0x200000U
#define AIC_ISCR_PID21_BIT 21
#define AIC_ISCR_PID22_MASK 0x400000U
#define AIC_ISCR_PID22 0x400000U
#define AIC_ISCR_PID22_BIT 22
#define AIC_ISCR_PID23_MASK 0x800000U
#define AIC_ISCR_PID23 0x800000U
#define AIC_ISCR_PID23_BIT 23
#define AIC_ISCR_PID24_MASK 0x1000000U
#define AIC_ISCR_PID24 0x1000000U
#define AIC_ISCR_PID24_BIT 24
#define AIC_ISCR_PID25_MASK 0x2000000U
#define AIC_ISCR_PID25 0x2000000U
#define AIC_ISCR_PID25_BIT 25
#define AIC_ISCR_PID26_MASK 0x4000000U
#define AIC_ISCR_PID26 0x4000000U
#define AIC_ISCR_PID26_BIT 26
#define AIC_ISCR_PID27_MASK 0x8000000U
#define AIC_ISCR_PID27 0x8000000U
#define AIC_ISCR_PID27_BIT 27
#define AIC_ISCR_PID28_MASK 0x10000000U
#define AIC_ISCR_PID28 0x10000000U
#define AIC_ISCR_PID28_BIT 28
#define AIC_ISCR_PID29_MASK 0x20000000U
#define AIC_ISCR_PID29 0x20000000U
#define AIC_ISCR_PID29_BIT 29
#define AIC_ISCR_PID30_MASK 0x40000000U
#define AIC_ISCR_PID30 0x40000000U
#define AIC_ISCR_PID30_BIT 30
#define AIC_ISCR_PID31_MASK 0x80000000U
#define AIC_ISCR_PID31 0x80000000U
#define AIC_ISCR_PID31_BIT 31

#define AIC_EOICR (*(volatile unsigned long *)0xFFFFF130)
#define AIC_EOICR_OFFSET 0x130

#define AIC_SPU (*(volatile unsigned long *)0xFFFFF134)
#define AIC_SPU_OFFSET 0x134

#define AIC_DEBUG (*(volatile unsigned long *)0xFFFFF138)
#define AIC_DEBUG_OFFSET 0x138
#define AIC_DEBUG_PROT_MASK 0x1U
#define AIC_DEBUG_PROT 0x1U
#define AIC_DEBUG_PROT_BIT 0
#define AIC_DEBUG_GMSK_MASK 0x2U
#define AIC_DEBUG_GMSK 0x2U
#define AIC_DEBUG_GMSK_BIT 1

#define AIC_FFER (*(volatile unsigned long *)0xFFFFF140)
#define AIC_FFER_OFFSET 0x140
#define AIC_FFER_SYS_MASK 0x2U
#define AIC_FFER_SYS 0x2U
#define AIC_FFER_SYS_BIT 1
#define AIC_FFER_PID2_MASK 0x4U
#define AIC_FFER_PID2 0x4U
#define AIC_FFER_PID2_BIT 2
#define AIC_FFER_PID3_MASK 0x8U
#define AIC_FFER_PID3 0x8U
#define AIC_FFER_PID3_BIT 3
#define AIC_FFER_PID4_MASK 0x10U
#define AIC_FFER_PID4 0x10U
#define AIC_FFER_PID4_BIT 4
#define AIC_FFER_PID5_MASK 0x20U
#define AIC_FFER_PID5 0x20U
#define AIC_FFER_PID5_BIT 5
#define AIC_FFER_PID6_MASK 0x40U
#define AIC_FFER_PID6 0x40U
#define AIC_FFER_PID6_BIT 6
#define AIC_FFER_PID7_MASK 0x80U
#define AIC_FFER_PID7 0x80U
#define AIC_FFER_PID7_BIT 7
#define AIC_FFER_PID8_MASK 0x100U
#define AIC_FFER_PID8 0x100U
#define AIC_FFER_PID8_BIT 8
#define AIC_FFER_PID9_MASK 0x200U
#define AIC_FFER_PID9 0x200U
#define AIC_FFER_PID9_BIT 9
#define AIC_FFER_PID10_MASK 0x400U
#define AIC_FFER_PID10 0x400U
#define AIC_FFER_PID10_BIT 10
#define AIC_FFER_PID11_MASK 0x800U
#define AIC_FFER_PID11 0x800U
#define AIC_FFER_PID11_BIT 11
#define AIC_FFER_PID12_MASK 0x1000U
#define AIC_FFER_PID12 0x1000U
#define AIC_FFER_PID12_BIT 12
#define AIC_FFER_PID13_MASK 0x2000U
#define AIC_FFER_PID13 0x2000U
#define AIC_FFER_PID13_BIT 13
#define AIC_FFER_PID14_MASK 0x4000U
#define AIC_FFER_PID14 0x4000U
#define AIC_FFER_PID14_BIT 14
#define AIC_FFER_PID15_MASK 0x8000U
#define AIC_FFER_PID15 0x8000U
#define AIC_FFER_PID15_BIT 15
#define AIC_FFER_PID16_MASK 0x10000U
#define AIC_FFER_PID16 0x10000U
#define AIC_FFER_PID16_BIT 16
#define AIC_FFER_PID17_MASK 0x20000U
#define AIC_FFER_PID17 0x20000U
#define AIC_FFER_PID17_BIT 17
#define AIC_FFER_PID18_MASK 0x40000U
#define AIC_FFER_PID18 0x40000U
#define AIC_FFER_PID18_BIT 18
#define AIC_FFER_PID19_MASK 0x80000U
#define AIC_FFER_PID19 0x80000U
#define AIC_FFER_PID19_BIT 19
#define AIC_FFER_PID20_MASK 0x100000U
#define AIC_FFER_PID20 0x100000U
#define AIC_FFER_PID20_BIT 20
#define AIC_FFER_PID21_MASK 0x200000U
#define AIC_FFER_PID21 0x200000U
#define AIC_FFER_PID21_BIT 21
#define AIC_FFER_PID22_MASK 0x400000U
#define AIC_FFER_PID22 0x400000U
#define AIC_FFER_PID22_BIT 22
#define AIC_FFER_PID23_MASK 0x800000U
#define AIC_FFER_PID23 0x800000U
#define AIC_FFER_PID23_BIT 23
#define AIC_FFER_PID24_MASK 0x1000000U
#define AIC_FFER_PID24 0x1000000U
#define AIC_FFER_PID24_BIT 24
#define AIC_FFER_PID25_MASK 0x2000000U
#define AIC_FFER_PID25 0x2000000U
#define AIC_FFER_PID25_BIT 25
#define AIC_FFER_PID26_MASK 0x4000000U
#define AIC_FFER_PID26 0x4000000U
#define AIC_FFER_PID26_BIT 26
#define AIC_FFER_PID27_MASK 0x8000000U
#define AIC_FFER_PID27 0x8000000U
#define AIC_FFER_PID27_BIT 27
#define AIC_FFER_PID28_MASK 0x10000000U
#define AIC_FFER_PID28 0x10000000U
#define AIC_FFER_PID28_BIT 28
#define AIC_FFER_PID29_MASK 0x20000000U
#define AIC_FFER_PID29 0x20000000U
#define AIC_FFER_PID29_BIT 29
#define AIC_FFER_PID30_MASK 0x40000000U
#define AIC_FFER_PID30 0x40000000U
#define AIC_FFER_PID30_BIT 30
#define AIC_FFER_PID31_MASK 0x80000000U
#define AIC_FFER_PID31 0x80000000U
#define AIC_FFER_PID31_BIT 31

#define AIC_FFDR (*(volatile unsigned long *)0xFFFFF144)
#define AIC_FFDR_OFFSET 0x144
#define AIC_FFDR_SYS_MASK 0x2U
#define AIC_FFDR_SYS 0x2U
#define AIC_FFDR_SYS_BIT 1
#define AIC_FFDR_PID2_MASK 0x4U
#define AIC_FFDR_PID2 0x4U
#define AIC_FFDR_PID2_BIT 2
#define AIC_FFDR_PID3_MASK 0x8U
#define AIC_FFDR_PID3 0x8U
#define AIC_FFDR_PID3_BIT 3
#define AIC_FFDR_PID4_MASK 0x10U
#define AIC_FFDR_PID4 0x10U
#define AIC_FFDR_PID4_BIT 4
#define AIC_FFDR_PID5_MASK 0x20U
#define AIC_FFDR_PID5 0x20U
#define AIC_FFDR_PID5_BIT 5
#define AIC_FFDR_PID6_MASK 0x40U
#define AIC_FFDR_PID6 0x40U
#define AIC_FFDR_PID6_BIT 6
#define AIC_FFDR_PID7_MASK 0x80U
#define AIC_FFDR_PID7 0x80U
#define AIC_FFDR_PID7_BIT 7
#define AIC_FFDR_PID8_MASK 0x100U
#define AIC_FFDR_PID8 0x100U
#define AIC_FFDR_PID8_BIT 8
#define AIC_FFDR_PID9_MASK 0x200U
#define AIC_FFDR_PID9 0x200U
#define AIC_FFDR_PID9_BIT 9
#define AIC_FFDR_PID10_MASK 0x400U
#define AIC_FFDR_PID10 0x400U
#define AIC_FFDR_PID10_BIT 10
#define AIC_FFDR_PID11_MASK 0x800U
#define AIC_FFDR_PID11 0x800U
#define AIC_FFDR_PID11_BIT 11
#define AIC_FFDR_PID12_MASK 0x1000U
#define AIC_FFDR_PID12 0x1000U
#define AIC_FFDR_PID12_BIT 12
#define AIC_FFDR_PID13_MASK 0x2000U
#define AIC_FFDR_PID13 0x2000U
#define AIC_FFDR_PID13_BIT 13
#define AIC_FFDR_PID14_MASK 0x4000U
#define AIC_FFDR_PID14 0x4000U
#define AIC_FFDR_PID14_BIT 14
#define AIC_FFDR_PID15_MASK 0x8000U
#define AIC_FFDR_PID15 0x8000U
#define AIC_FFDR_PID15_BIT 15
#define AIC_FFDR_PID16_MASK 0x10000U
#define AIC_FFDR_PID16 0x10000U
#define AIC_FFDR_PID16_BIT 16
#define AIC_FFDR_PID17_MASK 0x20000U
#define AIC_FFDR_PID17 0x20000U
#define AIC_FFDR_PID17_BIT 17
#define AIC_FFDR_PID18_MASK 0x40000U
#define AIC_FFDR_PID18 0x40000U
#define AIC_FFDR_PID18_BIT 18
#define AIC_FFDR_PID19_MASK 0x80000U
#define AIC_FFDR_PID19 0x80000U
#define AIC_FFDR_PID19_BIT 19
#define AIC_FFDR_PID20_MASK 0x100000U
#define AIC_FFDR_PID20 0x100000U
#define AIC_FFDR_PID20_BIT 20
#define AIC_FFDR_PID21_MASK 0x200000U
#define AIC_FFDR_PID21 0x200000U
#define AIC_FFDR_PID21_BIT 21
#define AIC_FFDR_PID22_MASK 0x400000U
#define AIC_FFDR_PID22 0x400000U
#define AIC_FFDR_PID22_BIT 22
#define AIC_FFDR_PID23_MASK 0x800000U
#define AIC_FFDR_PID23 0x800000U
#define AIC_FFDR_PID23_BIT 23
#define AIC_FFDR_PID24_MASK 0x1000000U
#define AIC_FFDR_PID24 0x1000000U
#define AIC_FFDR_PID24_BIT 24
#define AIC_FFDR_PID25_MASK 0x2000000U
#define AIC_FFDR_PID25 0x2000000U
#define AIC_FFDR_PID25_BIT 25
#define AIC_FFDR_PID26_MASK 0x4000000U
#define AIC_FFDR_PID26 0x4000000U
#define AIC_FFDR_PID26_BIT 26
#define AIC_FFDR_PID27_MASK 0x8000000U
#define AIC_FFDR_PID27 0x8000000U
#define AIC_FFDR_PID27_BIT 27
#define AIC_FFDR_PID28_MASK 0x10000000U
#define AIC_FFDR_PID28 0x10000000U
#define AIC_FFDR_PID28_BIT 28
#define AIC_FFDR_PID29_MASK 0x20000000U
#define AIC_FFDR_PID29 0x20000000U
#define AIC_FFDR_PID29_BIT 29
#define AIC_FFDR_PID30_MASK 0x40000000U
#define AIC_FFDR_PID30 0x40000000U
#define AIC_FFDR_PID30_BIT 30
#define AIC_FFDR_PID31_MASK 0x80000000U
#define AIC_FFDR_PID31 0x80000000U
#define AIC_FFDR_PID31_BIT 31

#define AIC_FFSR (*(volatile unsigned long *)0xFFFFF148)
#define AIC_FFSR_OFFSET 0x148
#define AIC_FFSR_SYS_MASK 0x2U
#define AIC_FFSR_SYS 0x2U
#define AIC_FFSR_SYS_BIT 1
#define AIC_FFSR_PID2_MASK 0x4U
#define AIC_FFSR_PID2 0x4U
#define AIC_FFSR_PID2_BIT 2
#define AIC_FFSR_PID3_MASK 0x8U
#define AIC_FFSR_PID3 0x8U
#define AIC_FFSR_PID3_BIT 3
#define AIC_FFSR_PID4_MASK 0x10U
#define AIC_FFSR_PID4 0x10U
#define AIC_FFSR_PID4_BIT 4
#define AIC_FFSR_PID5_MASK 0x20U
#define AIC_FFSR_PID5 0x20U
#define AIC_FFSR_PID5_BIT 5
#define AIC_FFSR_PID6_MASK 0x40U
#define AIC_FFSR_PID6 0x40U
#define AIC_FFSR_PID6_BIT 6
#define AIC_FFSR_PID7_MASK 0x80U
#define AIC_FFSR_PID7 0x80U
#define AIC_FFSR_PID7_BIT 7
#define AIC_FFSR_PID8_MASK 0x100U
#define AIC_FFSR_PID8 0x100U
#define AIC_FFSR_PID8_BIT 8
#define AIC_FFSR_PID9_MASK 0x200U
#define AIC_FFSR_PID9 0x200U
#define AIC_FFSR_PID9_BIT 9
#define AIC_FFSR_PID10_MASK 0x400U
#define AIC_FFSR_PID10 0x400U
#define AIC_FFSR_PID10_BIT 10
#define AIC_FFSR_PID11_MASK 0x800U
#define AIC_FFSR_PID11 0x800U
#define AIC_FFSR_PID11_BIT 11
#define AIC_FFSR_PID12_MASK 0x1000U
#define AIC_FFSR_PID12 0x1000U
#define AIC_FFSR_PID12_BIT 12
#define AIC_FFSR_PID13_MASK 0x2000U
#define AIC_FFSR_PID13 0x2000U
#define AIC_FFSR_PID13_BIT 13
#define AIC_FFSR_PID14_MASK 0x4000U
#define AIC_FFSR_PID14 0x4000U
#define AIC_FFSR_PID14_BIT 14
#define AIC_FFSR_PID15_MASK 0x8000U
#define AIC_FFSR_PID15 0x8000U
#define AIC_FFSR_PID15_BIT 15
#define AIC_FFSR_PID16_MASK 0x10000U
#define AIC_FFSR_PID16 0x10000U
#define AIC_FFSR_PID16_BIT 16
#define AIC_FFSR_PID17_MASK 0x20000U
#define AIC_FFSR_PID17 0x20000U
#define AIC_FFSR_PID17_BIT 17
#define AIC_FFSR_PID18_MASK 0x40000U
#define AIC_FFSR_PID18 0x40000U
#define AIC_FFSR_PID18_BIT 18
#define AIC_FFSR_PID19_MASK 0x80000U
#define AIC_FFSR_PID19 0x80000U
#define AIC_FFSR_PID19_BIT 19
#define AIC_FFSR_PID20_MASK 0x100000U
#define AIC_FFSR_PID20 0x100000U
#define AIC_FFSR_PID20_BIT 20
#define AIC_FFSR_PID21_MASK 0x200000U
#define AIC_FFSR_PID21 0x200000U
#define AIC_FFSR_PID21_BIT 21
#define AIC_FFSR_PID22_MASK 0x400000U
#define AIC_FFSR_PID22 0x400000U
#define AIC_FFSR_PID22_BIT 22
#define AIC_FFSR_PID23_MASK 0x800000U
#define AIC_FFSR_PID23 0x800000U
#define AIC_FFSR_PID23_BIT 23
#define AIC_FFSR_PID24_MASK 0x1000000U
#define AIC_FFSR_PID24 0x1000000U
#define AIC_FFSR_PID24_BIT 24
#define AIC_FFSR_PID25_MASK 0x2000000U
#define AIC_FFSR_PID25 0x2000000U
#define AIC_FFSR_PID25_BIT 25
#define AIC_FFSR_PID26_MASK 0x4000000U
#define AIC_FFSR_PID26 0x4000000U
#define AIC_FFSR_PID26_BIT 26
#define AIC_FFSR_PID27_MASK 0x8000000U
#define AIC_FFSR_PID27 0x8000000U
#define AIC_FFSR_PID27_BIT 27
#define AIC_FFSR_PID28_MASK 0x10000000U
#define AIC_FFSR_PID28 0x10000000U
#define AIC_FFSR_PID28_BIT 28
#define AIC_FFSR_PID29_MASK 0x20000000U
#define AIC_FFSR_PID29 0x20000000U
#define AIC_FFSR_PID29_BIT 29
#define AIC_FFSR_PID30_MASK 0x40000000U
#define AIC_FFSR_PID30 0x40000000U
#define AIC_FFSR_PID30_BIT 30
#define AIC_FFSR_PID31_MASK 0x80000000U
#define AIC_FFSR_PID31 0x80000000U
#define AIC_FFSR_PID31_BIT 31

#define DBGU_BASE 0xFFFFF200

#define DBGU_CR (*(volatile unsigned long *)0xFFFFF200)
#define DBGU_CR_OFFSET 0x0
#define DBGU_CR_RSTRX_MASK 0x4U
#define DBGU_CR_RSTRX 0x4U
#define DBGU_CR_RSTRX_BIT 2
#define DBGU_CR_RSTTX_MASK 0x8U
#define DBGU_CR_RSTTX 0x8U
#define DBGU_CR_RSTTX_BIT 3
#define DBGU_CR_RXEN_MASK 0x10U
#define DBGU_CR_RXEN 0x10U
#define DBGU_CR_RXEN_BIT 4
#define DBGU_CR_RXDIS_MASK 0x20U
#define DBGU_CR_RXDIS 0x20U
#define DBGU_CR_RXDIS_BIT 5
#define DBGU_CR_TXEN_MASK 0x40U
#define DBGU_CR_TXEN 0x40U
#define DBGU_CR_TXEN_BIT 6
#define DBGU_CR_TXDIS_MASK 0x80U
#define DBGU_CR_TXDIS 0x80U
#define DBGU_CR_TXDIS_BIT 7
#define DBGU_CR_RSTSTA_MASK 0x100U
#define DBGU_CR_RSTSTA 0x100U
#define DBGU_CR_RSTSTA_BIT 8

#define DBGU_MR (*(volatile unsigned long *)0xFFFFF204)
#define DBGU_MR_OFFSET 0x4
#define DBGU_MR_PAR_MASK 0xE00U
#define DBGU_MR_PAR_BIT 9
#define DBGU_MR_CHMODE_MASK 0xC000U
#define DBGU_MR_CHMODE_BIT 14

#define DBGU_IER (*(volatile unsigned long *)0xFFFFF208)
#define DBGU_IER_OFFSET 0x8
#define DBGU_IER_RXRDY_MASK 0x1U
#define DBGU_IER_RXRDY 0x1U
#define DBGU_IER_RXRDY_BIT 0
#define DBGU_IER_TXRDY_MASK 0x2U
#define DBGU_IER_TXRDY 0x2U
#define DBGU_IER_TXRDY_BIT 1
#define DBGU_IER_ENDRX_MASK 0x8U
#define DBGU_IER_ENDRX 0x8U
#define DBGU_IER_ENDRX_BIT 3
#define DBGU_IER_ENDTX_MASK 0x10U
#define DBGU_IER_ENDTX 0x10U
#define DBGU_IER_ENDTX_BIT 4
#define DBGU_IER_OVRE_MASK 0x20U
#define DBGU_IER_OVRE 0x20U
#define DBGU_IER_OVRE_BIT 5
#define DBGU_IER_FRAME_MASK 0x40U
#define DBGU_IER_FRAME 0x40U
#define DBGU_IER_FRAME_BIT 6
#define DBGU_IER_PARE_MASK 0x80U
#define DBGU_IER_PARE 0x80U
#define DBGU_IER_PARE_BIT 7
#define DBGU_IER_TXEMPTY_MASK 0x200U
#define DBGU_IER_TXEMPTY 0x200U
#define DBGU_IER_TXEMPTY_BIT 9
#define DBGU_IER_TXBUFE_MASK 0x800U
#define DBGU_IER_TXBUFE 0x800U
#define DBGU_IER_TXBUFE_BIT 11
#define DBGU_IER_RXBUFF_MASK 0x1000U
#define DBGU_IER_RXBUFF 0x1000U
#define DBGU_IER_RXBUFF_BIT 12
#define DBGU_IER_COMMTX_MASK 0x40000000U
#define DBGU_IER_COMMTX 0x40000000U
#define DBGU_IER_COMMTX_BIT 30
#define DBGU_IER_COMMRX_MASK 0x80000000U
#define DBGU_IER_COMMRX 0x80000000U
#define DBGU_IER_COMMRX_BIT 31

#define DBGU_IDR (*(volatile unsigned long *)0xFFFFF20C)
#define DBGU_IDR_OFFSET 0xC
#define DBGU_IDR_RXRDY_MASK 0x1U
#define DBGU_IDR_RXRDY 0x1U
#define DBGU_IDR_RXRDY_BIT 0
#define DBGU_IDR_TXRDY_MASK 0x2U
#define DBGU_IDR_TXRDY 0x2U
#define DBGU_IDR_TXRDY_BIT 1
#define DBGU_IDR_ENDRX_MASK 0x8U
#define DBGU_IDR_ENDRX 0x8U
#define DBGU_IDR_ENDRX_BIT 3
#define DBGU_IDR_ENDTX_MASK 0x10U
#define DBGU_IDR_ENDTX 0x10U
#define DBGU_IDR_ENDTX_BIT 4
#define DBGU_IDR_OVRE_MASK 0x20U
#define DBGU_IDR_OVRE 0x20U
#define DBGU_IDR_OVRE_BIT 5
#define DBGU_IDR_FRAME_MASK 0x40U
#define DBGU_IDR_FRAME 0x40U
#define DBGU_IDR_FRAME_BIT 6
#define DBGU_IDR_PARE_MASK 0x80U
#define DBGU_IDR_PARE 0x80U
#define DBGU_IDR_PARE_BIT 7
#define DBGU_IDR_TXEMPTY_MASK 0x200U
#define DBGU_IDR_TXEMPTY 0x200U
#define DBGU_IDR_TXEMPTY_BIT 9
#define DBGU_IDR_TXBUFE_MASK 0x800U
#define DBGU_IDR_TXBUFE 0x800U
#define DBGU_IDR_TXBUFE_BIT 11
#define DBGU_IDR_RXBUFF_MASK 0x1000U
#define DBGU_IDR_RXBUFF 0x1000U
#define DBGU_IDR_RXBUFF_BIT 12
#define DBGU_IDR_COMMTX_MASK 0x40000000U
#define DBGU_IDR_COMMTX 0x40000000U
#define DBGU_IDR_COMMTX_BIT 30
#define DBGU_IDR_COMMRX_MASK 0x80000000U
#define DBGU_IDR_COMMRX 0x80000000U
#define DBGU_IDR_COMMRX_BIT 31

#define DBGU_IMR (*(volatile unsigned long *)0xFFFFF210)
#define DBGU_IMR_OFFSET 0x10
#define DBGU_IMR_RXRDY_MASK 0x1U
#define DBGU_IMR_RXRDY 0x1U
#define DBGU_IMR_RXRDY_BIT 0
#define DBGU_IMR_TXRDY_MASK 0x2U
#define DBGU_IMR_TXRDY 0x2U
#define DBGU_IMR_TXRDY_BIT 1
#define DBGU_IMR_ENDRX_MASK 0x8U
#define DBGU_IMR_ENDRX 0x8U
#define DBGU_IMR_ENDRX_BIT 3
#define DBGU_IMR_ENDTX_MASK 0x10U
#define DBGU_IMR_ENDTX 0x10U
#define DBGU_IMR_ENDTX_BIT 4
#define DBGU_IMR_OVRE_MASK 0x20U
#define DBGU_IMR_OVRE 0x20U
#define DBGU_IMR_OVRE_BIT 5
#define DBGU_IMR_FRAME_MASK 0x40U
#define DBGU_IMR_FRAME 0x40U
#define DBGU_IMR_FRAME_BIT 6
#define DBGU_IMR_PARE_MASK 0x80U
#define DBGU_IMR_PARE 0x80U
#define DBGU_IMR_PARE_BIT 7
#define DBGU_IMR_TXEMPTY_MASK 0x200U
#define DBGU_IMR_TXEMPTY 0x200U
#define DBGU_IMR_TXEMPTY_BIT 9
#define DBGU_IMR_TXBUFE_MASK 0x800U
#define DBGU_IMR_TXBUFE 0x800U
#define DBGU_IMR_TXBUFE_BIT 11
#define DBGU_IMR_RXBUFF_MASK 0x1000U
#define DBGU_IMR_RXBUFF 0x1000U
#define DBGU_IMR_RXBUFF_BIT 12
#define DBGU_IMR_COMMTX_MASK 0x40000000U
#define DBGU_IMR_COMMTX 0x40000000U
#define DBGU_IMR_COMMTX_BIT 30
#define DBGU_IMR_COMMRX_MASK 0x80000000U
#define DBGU_IMR_COMMRX 0x80000000U
#define DBGU_IMR_COMMRX_BIT 31

#define DBGU_SR (*(volatile unsigned long *)0xFFFFF214)
#define DBGU_SR_OFFSET 0x14
#define DBGU_SR_RXRDY_MASK 0x1U
#define DBGU_SR_RXRDY 0x1U
#define DBGU_SR_RXRDY_BIT 0
#define DBGU_SR_TXRDY_MASK 0x2U
#define DBGU_SR_TXRDY 0x2U
#define DBGU_SR_TXRDY_BIT 1
#define DBGU_SR_ENDRX_MASK 0x8U
#define DBGU_SR_ENDRX 0x8U
#define DBGU_SR_ENDRX_BIT 3
#define DBGU_SR_ENDTX_MASK 0x10U
#define DBGU_SR_ENDTX 0x10U
#define DBGU_SR_ENDTX_BIT 4
#define DBGU_SR_OVRE_MASK 0x20U
#define DBGU_SR_OVRE 0x20U
#define DBGU_SR_OVRE_BIT 5
#define DBGU_SR_FRAME_MASK 0x40U
#define DBGU_SR_FRAME 0x40U
#define DBGU_SR_FRAME_BIT 6
#define DBGU_SR_PARE_MASK 0x80U
#define DBGU_SR_PARE 0x80U
#define DBGU_SR_PARE_BIT 7
#define DBGU_SR_TXEMPTY_MASK 0x200U
#define DBGU_SR_TXEMPTY 0x200U
#define DBGU_SR_TXEMPTY_BIT 9
#define DBGU_SR_TXBUFE_MASK 0x800U
#define DBGU_SR_TXBUFE 0x800U
#define DBGU_SR_TXBUFE_BIT 11
#define DBGU_SR_RXBUFF_MASK 0x1000U
#define DBGU_SR_RXBUFF 0x1000U
#define DBGU_SR_RXBUFF_BIT 12
#define DBGU_SR_COMMTX_MASK 0x40000000U
#define DBGU_SR_COMMTX 0x40000000U
#define DBGU_SR_COMMTX_BIT 30
#define DBGU_SR_COMMRX_MASK 0x80000000U
#define DBGU_SR_COMMRX 0x80000000U
#define DBGU_SR_COMMRX_BIT 31

#define DBGU_RHR (*(volatile unsigned long *)0xFFFFF218)
#define DBGU_RHR_OFFSET 0x18

#define DBGU_THR (*(volatile unsigned long *)0xFFFFF21C)
#define DBGU_THR_OFFSET 0x1C

#define DBGU_BRGR (*(volatile unsigned long *)0xFFFFF220)
#define DBGU_BRGR_OFFSET 0x20

#define DBGU_CIDR (*(volatile unsigned long *)0xFFFFF240)
#define DBGU_CIDR_OFFSET 0x40
#define DBGU_CIDR_VERSION_MASK 0x1FU
#define DBGU_CIDR_VERSION_BIT 0
#define DBGU_CIDR_EPROC_MASK 0xE0U
#define DBGU_CIDR_EPROC_BIT 5
#define DBGU_CIDR_NVPSIZ_MASK 0xF00U
#define DBGU_CIDR_NVPSIZ_BIT 8
#define DBGU_CIDR_NVPSIZ2_MASK 0xF000U
#define DBGU_CIDR_NVPSIZ2_BIT 12
#define DBGU_CIDR_SRAMSIZ_MASK 0xF0000U
#define DBGU_CIDR_SRAMSIZ_BIT 16
#define DBGU_CIDR_ARCH_MASK 0xFF00000U
#define DBGU_CIDR_ARCH_BIT 20
#define DBGU_CIDR_NVPTYP_MASK 0x70000000U
#define DBGU_CIDR_NVPTYP_BIT 28
#define DBGU_CIDR_EXT_MASK 0x80000000U
#define DBGU_CIDR_EXT 0x80000000U
#define DBGU_CIDR_EXT_BIT 31

#define DBGU_EXID (*(volatile unsigned long *)0xFFFFF244)
#define DBGU_EXID_OFFSET 0x44

#define DBGU_FNR (*(volatile unsigned long *)0xFFFFF248)
#define DBGU_FNR_OFFSET 0x48

#define DBGU_RPR (*(volatile unsigned long *)0xFFFFF300)
#define DBGU_RPR_OFFSET 0x100

#define DBGU_RCR (*(volatile unsigned long *)0xFFFFF304)
#define DBGU_RCR_OFFSET 0x104

#define DBGU_TPR (*(volatile unsigned long *)0xFFFFF308)
#define DBGU_TPR_OFFSET 0x108

#define DBGU_TCR (*(volatile unsigned long *)0xFFFFF30C)
#define DBGU_TCR_OFFSET 0x10C

#define DBGU_RNPR (*(volatile unsigned long *)0xFFFFF310)
#define DBGU_RNPR_OFFSET 0x110

#define DBGU_RNCR (*(volatile unsigned long *)0xFFFFF314)
#define DBGU_RNCR_OFFSET 0x114

#define DBGU_TNPR (*(volatile unsigned long *)0xFFFFF318)
#define DBGU_TNPR_OFFSET 0x118

#define DBGU_TNCR (*(volatile unsigned long *)0xFFFFF31C)
#define DBGU_TNCR_OFFSET 0x11C

#define DBGU_PTCR (*(volatile unsigned long *)0xFFFFF320)
#define DBGU_PTCR_OFFSET 0x120
#define DBGU_PTCR_RXTEN_MASK 0x1U
#define DBGU_PTCR_RXTEN 0x1U
#define DBGU_PTCR_RXTEN_BIT 0
#define DBGU_PTCR_RXTDIS_MASK 0x2U
#define DBGU_PTCR_RXTDIS 0x2U
#define DBGU_PTCR_RXTDIS_BIT 1
#define DBGU_PTCR_TXTEN_MASK 0x100U
#define DBGU_PTCR_TXTEN 0x100U
#define DBGU_PTCR_TXTEN_BIT 8
#define DBGU_PTCR_TXTDIS_MASK 0x1E00U
#define DBGU_PTCR_TXTDIS_BIT 9

#define DBGU_PTSR (*(volatile unsigned long *)0xFFFFF324)
#define DBGU_PTSR_OFFSET 0x124
#define DBGU_PTSR_RXTEN_MASK 0x1U
#define DBGU_PTSR_RXTEN 0x1U
#define DBGU_PTSR_RXTEN_BIT 0
#define DBGU_PTSR_TXTEN_MASK 0x1E00U
#define DBGU_PTSR_TXTEN_BIT 9

#define PIOA_BASE 0xFFFFF400

#define PIOA_PER (*(volatile unsigned long *)0xFFFFF400)
#define PIOA_PER_OFFSET 0x0
#define PIOA_PER_P0_MASK 0x1U
#define PIOA_PER_P0 0x1U
#define PIOA_PER_P0_BIT 0
#define PIOA_PER_P1_MASK 0x2U
#define PIOA_PER_P1 0x2U
#define PIOA_PER_P1_BIT 1
#define PIOA_PER_P2_MASK 0x4U
#define PIOA_PER_P2 0x4U
#define PIOA_PER_P2_BIT 2
#define PIOA_PER_P3_MASK 0x8U
#define PIOA_PER_P3 0x8U
#define PIOA_PER_P3_BIT 3
#define PIOA_PER_P4_MASK 0x10U
#define PIOA_PER_P4 0x10U
#define PIOA_PER_P4_BIT 4
#define PIOA_PER_P5_MASK 0x20U
#define PIOA_PER_P5 0x20U
#define PIOA_PER_P5_BIT 5
#define PIOA_PER_P6_MASK 0x40U
#define PIOA_PER_P6 0x40U
#define PIOA_PER_P6_BIT 6
#define PIOA_PER_P7_MASK 0x80U
#define PIOA_PER_P7 0x80U
#define PIOA_PER_P7_BIT 7
#define PIOA_PER_P8_MASK 0x100U
#define PIOA_PER_P8 0x100U
#define PIOA_PER_P8_BIT 8
#define PIOA_PER_P9_MASK 0x200U
#define PIOA_PER_P9 0x200U
#define PIOA_PER_P9_BIT 9
#define PIOA_PER_P10_MASK 0x400U
#define PIOA_PER_P10 0x400U
#define PIOA_PER_P10_BIT 10
#define PIOA_PER_P11_MASK 0x800U
#define PIOA_PER_P11 0x800U
#define PIOA_PER_P11_BIT 11
#define PIOA_PER_P12_MASK 0x1000U
#define PIOA_PER_P12 0x1000U
#define PIOA_PER_P12_BIT 12
#define PIOA_PER_P13_MASK 0x2000U
#define PIOA_PER_P13 0x2000U
#define PIOA_PER_P13_BIT 13
#define PIOA_PER_P14_MASK 0x4000U
#define PIOA_PER_P14 0x4000U
#define PIOA_PER_P14_BIT 14
#define PIOA_PER_P15_MASK 0x8000U
#define PIOA_PER_P15 0x8000U
#define PIOA_PER_P15_BIT 15
#define PIOA_PER_P16_MASK 0x10000U
#define PIOA_PER_P16 0x10000U
#define PIOA_PER_P16_BIT 16
#define PIOA_PER_P17_MASK 0x20000U
#define PIOA_PER_P17 0x20000U
#define PIOA_PER_P17_BIT 17
#define PIOA_PER_P18_MASK 0x40000U
#define PIOA_PER_P18 0x40000U
#define PIOA_PER_P18_BIT 18
#define PIOA_PER_P19_MASK 0x80000U
#define PIOA_PER_P19 0x80000U
#define PIOA_PER_P19_BIT 19
#define PIOA_PER_P20_MASK 0x100000U
#define PIOA_PER_P20 0x100000U
#define PIOA_PER_P20_BIT 20
#define PIOA_PER_P21_MASK 0x200000U
#define PIOA_PER_P21 0x200000U
#define PIOA_PER_P21_BIT 21
#define PIOA_PER_P22_MASK 0x400000U
#define PIOA_PER_P22 0x400000U
#define PIOA_PER_P22_BIT 22
#define PIOA_PER_P23_MASK 0x800000U
#define PIOA_PER_P23 0x800000U
#define PIOA_PER_P23_BIT 23
#define PIOA_PER_P24_MASK 0x1000000U
#define PIOA_PER_P24 0x1000000U
#define PIOA_PER_P24_BIT 24
#define PIOA_PER_P25_MASK 0x2000000U
#define PIOA_PER_P25 0x2000000U
#define PIOA_PER_P25_BIT 25
#define PIOA_PER_P26_MASK 0x4000000U
#define PIOA_PER_P26 0x4000000U
#define PIOA_PER_P26_BIT 26
#define PIOA_PER_P27_MASK 0x8000000U
#define PIOA_PER_P27 0x8000000U
#define PIOA_PER_P27_BIT 27
#define PIOA_PER_P28_MASK 0x10000000U
#define PIOA_PER_P28 0x10000000U
#define PIOA_PER_P28_BIT 28
#define PIOA_PER_P29_MASK 0x20000000U
#define PIOA_PER_P29 0x20000000U
#define PIOA_PER_P29_BIT 29
#define PIOA_PER_P30_MASK 0x40000000U
#define PIOA_PER_P30 0x40000000U
#define PIOA_PER_P30_BIT 30
#define PIOA_PER_P31_MASK 0x80000000U
#define PIOA_PER_P31 0x80000000U
#define PIOA_PER_P31_BIT 31

#define PIOA_PDR (*(volatile unsigned long *)0xFFFFF404)
#define PIOA_PDR_OFFSET 0x4
#define PIOA_PDR_P0_MASK 0x1U
#define PIOA_PDR_P0 0x1U
#define PIOA_PDR_P0_BIT 0
#define PIOA_PDR_P1_MASK 0x2U
#define PIOA_PDR_P1 0x2U
#define PIOA_PDR_P1_BIT 1
#define PIOA_PDR_P2_MASK 0x4U
#define PIOA_PDR_P2 0x4U
#define PIOA_PDR_P2_BIT 2
#define PIOA_PDR_P3_MASK 0x8U
#define PIOA_PDR_P3 0x8U
#define PIOA_PDR_P3_BIT 3
#define PIOA_PDR_P4_MASK 0x10U
#define PIOA_PDR_P4 0x10U
#define PIOA_PDR_P4_BIT 4
#define PIOA_PDR_P5_MASK 0x20U
#define PIOA_PDR_P5 0x20U
#define PIOA_PDR_P5_BIT 5
#define PIOA_PDR_P6_MASK 0x40U
#define PIOA_PDR_P6 0x40U
#define PIOA_PDR_P6_BIT 6
#define PIOA_PDR_P7_MASK 0x80U
#define PIOA_PDR_P7 0x80U
#define PIOA_PDR_P7_BIT 7
#define PIOA_PDR_P8_MASK 0x100U
#define PIOA_PDR_P8 0x100U
#define PIOA_PDR_P8_BIT 8
#define PIOA_PDR_P9_MASK 0x200U
#define PIOA_PDR_P9 0x200U
#define PIOA_PDR_P9_BIT 9
#define PIOA_PDR_P10_MASK 0x400U
#define PIOA_PDR_P10 0x400U
#define PIOA_PDR_P10_BIT 10
#define PIOA_PDR_P11_MASK 0x800U
#define PIOA_PDR_P11 0x800U
#define PIOA_PDR_P11_BIT 11
#define PIOA_PDR_P12_MASK 0x1000U
#define PIOA_PDR_P12 0x1000U
#define PIOA_PDR_P12_BIT 12
#define PIOA_PDR_P13_MASK 0x2000U
#define PIOA_PDR_P13 0x2000U
#define PIOA_PDR_P13_BIT 13
#define PIOA_PDR_P14_MASK 0x4000U
#define PIOA_PDR_P14 0x4000U
#define PIOA_PDR_P14_BIT 14
#define PIOA_PDR_P15_MASK 0x8000U
#define PIOA_PDR_P15 0x8000U
#define PIOA_PDR_P15_BIT 15
#define PIOA_PDR_P16_MASK 0x10000U
#define PIOA_PDR_P16 0x10000U
#define PIOA_PDR_P16_BIT 16
#define PIOA_PDR_P17_MASK 0x20000U
#define PIOA_PDR_P17 0x20000U
#define PIOA_PDR_P17_BIT 17
#define PIOA_PDR_P18_MASK 0x40000U
#define PIOA_PDR_P18 0x40000U
#define PIOA_PDR_P18_BIT 18
#define PIOA_PDR_P19_MASK 0x80000U
#define PIOA_PDR_P19 0x80000U
#define PIOA_PDR_P19_BIT 19
#define PIOA_PDR_P20_MASK 0x100000U
#define PIOA_PDR_P20 0x100000U
#define PIOA_PDR_P20_BIT 20
#define PIOA_PDR_P21_MASK 0x200000U
#define PIOA_PDR_P21 0x200000U
#define PIOA_PDR_P21_BIT 21
#define PIOA_PDR_P22_MASK 0x400000U
#define PIOA_PDR_P22 0x400000U
#define PIOA_PDR_P22_BIT 22
#define PIOA_PDR_P23_MASK 0x800000U
#define PIOA_PDR_P23 0x800000U
#define PIOA_PDR_P23_BIT 23
#define PIOA_PDR_P24_MASK 0x1000000U
#define PIOA_PDR_P24 0x1000000U
#define PIOA_PDR_P24_BIT 24
#define PIOA_PDR_P25_MASK 0x2000000U
#define PIOA_PDR_P25 0x2000000U
#define PIOA_PDR_P25_BIT 25
#define PIOA_PDR_P26_MASK 0x4000000U
#define PIOA_PDR_P26 0x4000000U
#define PIOA_PDR_P26_BIT 26
#define PIOA_PDR_P27_MASK 0x8000000U
#define PIOA_PDR_P27 0x8000000U
#define PIOA_PDR_P27_BIT 27
#define PIOA_PDR_P28_MASK 0x10000000U
#define PIOA_PDR_P28 0x10000000U
#define PIOA_PDR_P28_BIT 28
#define PIOA_PDR_P29_MASK 0x20000000U
#define PIOA_PDR_P29 0x20000000U
#define PIOA_PDR_P29_BIT 29
#define PIOA_PDR_P30_MASK 0x40000000U
#define PIOA_PDR_P30 0x40000000U
#define PIOA_PDR_P30_BIT 30
#define PIOA_PDR_P31_MASK 0x80000000U
#define PIOA_PDR_P31 0x80000000U
#define PIOA_PDR_P31_BIT 31

#define PIOA_PSR (*(volatile unsigned long *)0xFFFFF408)
#define PIOA_PSR_OFFSET 0x8
#define PIOA_PSR_P0_MASK 0x1U
#define PIOA_PSR_P0 0x1U
#define PIOA_PSR_P0_BIT 0
#define PIOA_PSR_P1_MASK 0x2U
#define PIOA_PSR_P1 0x2U
#define PIOA_PSR_P1_BIT 1
#define PIOA_PSR_P2_MASK 0x4U
#define PIOA_PSR_P2 0x4U
#define PIOA_PSR_P2_BIT 2
#define PIOA_PSR_P3_MASK 0x8U
#define PIOA_PSR_P3 0x8U
#define PIOA_PSR_P3_BIT 3
#define PIOA_PSR_P4_MASK 0x10U
#define PIOA_PSR_P4 0x10U
#define PIOA_PSR_P4_BIT 4
#define PIOA_PSR_P5_MASK 0x20U
#define PIOA_PSR_P5 0x20U
#define PIOA_PSR_P5_BIT 5
#define PIOA_PSR_P6_MASK 0x40U
#define PIOA_PSR_P6 0x40U
#define PIOA_PSR_P6_BIT 6
#define PIOA_PSR_P7_MASK 0x80U
#define PIOA_PSR_P7 0x80U
#define PIOA_PSR_P7_BIT 7
#define PIOA_PSR_P8_MASK 0x100U
#define PIOA_PSR_P8 0x100U
#define PIOA_PSR_P8_BIT 8
#define PIOA_PSR_P9_MASK 0x200U
#define PIOA_PSR_P9 0x200U
#define PIOA_PSR_P9_BIT 9
#define PIOA_PSR_P10_MASK 0x400U
#define PIOA_PSR_P10 0x400U
#define PIOA_PSR_P10_BIT 10
#define PIOA_PSR_P11_MASK 0x800U
#define PIOA_PSR_P11 0x800U
#define PIOA_PSR_P11_BIT 11
#define PIOA_PSR_P12_MASK 0x1000U
#define PIOA_PSR_P12 0x1000U
#define PIOA_PSR_P12_BIT 12
#define PIOA_PSR_P13_MASK 0x2000U
#define PIOA_PSR_P13 0x2000U
#define PIOA_PSR_P13_BIT 13
#define PIOA_PSR_P14_MASK 0x4000U
#define PIOA_PSR_P14 0x4000U
#define PIOA_PSR_P14_BIT 14
#define PIOA_PSR_P15_MASK 0x8000U
#define PIOA_PSR_P15 0x8000U
#define PIOA_PSR_P15_BIT 15
#define PIOA_PSR_P16_MASK 0x10000U
#define PIOA_PSR_P16 0x10000U
#define PIOA_PSR_P16_BIT 16
#define PIOA_PSR_P17_MASK 0x20000U
#define PIOA_PSR_P17 0x20000U
#define PIOA_PSR_P17_BIT 17
#define PIOA_PSR_P18_MASK 0x40000U
#define PIOA_PSR_P18 0x40000U
#define PIOA_PSR_P18_BIT 18
#define PIOA_PSR_P19_MASK 0x80000U
#define PIOA_PSR_P19 0x80000U
#define PIOA_PSR_P19_BIT 19
#define PIOA_PSR_P20_MASK 0x100000U
#define PIOA_PSR_P20 0x100000U
#define PIOA_PSR_P20_BIT 20
#define PIOA_PSR_P21_MASK 0x200000U
#define PIOA_PSR_P21 0x200000U
#define PIOA_PSR_P21_BIT 21
#define PIOA_PSR_P22_MASK 0x400000U
#define PIOA_PSR_P22 0x400000U
#define PIOA_PSR_P22_BIT 22
#define PIOA_PSR_P23_MASK 0x800000U
#define PIOA_PSR_P23 0x800000U
#define PIOA_PSR_P23_BIT 23
#define PIOA_PSR_P24_MASK 0x1000000U
#define PIOA_PSR_P24 0x1000000U
#define PIOA_PSR_P24_BIT 24
#define PIOA_PSR_P25_MASK 0x2000000U
#define PIOA_PSR_P25 0x2000000U
#define PIOA_PSR_P25_BIT 25
#define PIOA_PSR_P26_MASK 0x4000000U
#define PIOA_PSR_P26 0x4000000U
#define PIOA_PSR_P26_BIT 26
#define PIOA_PSR_P27_MASK 0x8000000U
#define PIOA_PSR_P27 0x8000000U
#define PIOA_PSR_P27_BIT 27
#define PIOA_PSR_P28_MASK 0x10000000U
#define PIOA_PSR_P28 0x10000000U
#define PIOA_PSR_P28_BIT 28
#define PIOA_PSR_P29_MASK 0x20000000U
#define PIOA_PSR_P29 0x20000000U
#define PIOA_PSR_P29_BIT 29
#define PIOA_PSR_P30_MASK 0x40000000U
#define PIOA_PSR_P30 0x40000000U
#define PIOA_PSR_P30_BIT 30
#define PIOA_PSR_P31_MASK 0x80000000U
#define PIOA_PSR_P31 0x80000000U
#define PIOA_PSR_P31_BIT 31

#define PIOA_OER (*(volatile unsigned long *)0xFFFFF410)
#define PIOA_OER_OFFSET 0x10
#define PIOA_OER_P0_MASK 0x1U
#define PIOA_OER_P0 0x1U
#define PIOA_OER_P0_BIT 0
#define PIOA_OER_P1_MASK 0x2U
#define PIOA_OER_P1 0x2U
#define PIOA_OER_P1_BIT 1
#define PIOA_OER_P2_MASK 0x4U
#define PIOA_OER_P2 0x4U
#define PIOA_OER_P2_BIT 2
#define PIOA_OER_P3_MASK 0x8U
#define PIOA_OER_P3 0x8U
#define PIOA_OER_P3_BIT 3
#define PIOA_OER_P4_MASK 0x10U
#define PIOA_OER_P4 0x10U
#define PIOA_OER_P4_BIT 4
#define PIOA_OER_P5_MASK 0x20U
#define PIOA_OER_P5 0x20U
#define PIOA_OER_P5_BIT 5
#define PIOA_OER_P6_MASK 0x40U
#define PIOA_OER_P6 0x40U
#define PIOA_OER_P6_BIT 6
#define PIOA_OER_P7_MASK 0x80U
#define PIOA_OER_P7 0x80U
#define PIOA_OER_P7_BIT 7
#define PIOA_OER_P8_MASK 0x100U
#define PIOA_OER_P8 0x100U
#define PIOA_OER_P8_BIT 8
#define PIOA_OER_P9_MASK 0x200U
#define PIOA_OER_P9 0x200U
#define PIOA_OER_P9_BIT 9
#define PIOA_OER_P10_MASK 0x400U
#define PIOA_OER_P10 0x400U
#define PIOA_OER_P10_BIT 10
#define PIOA_OER_P11_MASK 0x800U
#define PIOA_OER_P11 0x800U
#define PIOA_OER_P11_BIT 11
#define PIOA_OER_P12_MASK 0x1000U
#define PIOA_OER_P12 0x1000U
#define PIOA_OER_P12_BIT 12
#define PIOA_OER_P13_MASK 0x2000U
#define PIOA_OER_P13 0x2000U
#define PIOA_OER_P13_BIT 13
#define PIOA_OER_P14_MASK 0x4000U
#define PIOA_OER_P14 0x4000U
#define PIOA_OER_P14_BIT 14
#define PIOA_OER_P15_MASK 0x8000U
#define PIOA_OER_P15 0x8000U
#define PIOA_OER_P15_BIT 15
#define PIOA_OER_P16_MASK 0x10000U
#define PIOA_OER_P16 0x10000U
#define PIOA_OER_P16_BIT 16
#define PIOA_OER_P17_MASK 0x20000U
#define PIOA_OER_P17 0x20000U
#define PIOA_OER_P17_BIT 17
#define PIOA_OER_P18_MASK 0x40000U
#define PIOA_OER_P18 0x40000U
#define PIOA_OER_P18_BIT 18
#define PIOA_OER_P19_MASK 0x80000U
#define PIOA_OER_P19 0x80000U
#define PIOA_OER_P19_BIT 19
#define PIOA_OER_P20_MASK 0x100000U
#define PIOA_OER_P20 0x100000U
#define PIOA_OER_P20_BIT 20
#define PIOA_OER_P21_MASK 0x200000U
#define PIOA_OER_P21 0x200000U
#define PIOA_OER_P21_BIT 21
#define PIOA_OER_P22_MASK 0x400000U
#define PIOA_OER_P22 0x400000U
#define PIOA_OER_P22_BIT 22
#define PIOA_OER_P23_MASK 0x800000U
#define PIOA_OER_P23 0x800000U
#define PIOA_OER_P23_BIT 23
#define PIOA_OER_P24_MASK 0x1000000U
#define PIOA_OER_P24 0x1000000U
#define PIOA_OER_P24_BIT 24
#define PIOA_OER_P25_MASK 0x2000000U
#define PIOA_OER_P25 0x2000000U
#define PIOA_OER_P25_BIT 25
#define PIOA_OER_P26_MASK 0x4000000U
#define PIOA_OER_P26 0x4000000U
#define PIOA_OER_P26_BIT 26
#define PIOA_OER_P27_MASK 0x8000000U
#define PIOA_OER_P27 0x8000000U
#define PIOA_OER_P27_BIT 27
#define PIOA_OER_P28_MASK 0x10000000U
#define PIOA_OER_P28 0x10000000U
#define PIOA_OER_P28_BIT 28
#define PIOA_OER_P29_MASK 0x20000000U
#define PIOA_OER_P29 0x20000000U
#define PIOA_OER_P29_BIT 29
#define PIOA_OER_P30_MASK 0x40000000U
#define PIOA_OER_P30 0x40000000U
#define PIOA_OER_P30_BIT 30
#define PIOA_OER_P31_MASK 0x80000000U
#define PIOA_OER_P31 0x80000000U
#define PIOA_OER_P31_BIT 31

#define PIOA_ODR (*(volatile unsigned long *)0xFFFFF414)
#define PIOA_ODR_OFFSET 0x14
#define PIOA_ODR_P0_MASK 0x1U
#define PIOA_ODR_P0 0x1U
#define PIOA_ODR_P0_BIT 0
#define PIOA_ODR_P1_MASK 0x2U
#define PIOA_ODR_P1 0x2U
#define PIOA_ODR_P1_BIT 1
#define PIOA_ODR_P2_MASK 0x4U
#define PIOA_ODR_P2 0x4U
#define PIOA_ODR_P2_BIT 2
#define PIOA_ODR_P3_MASK 0x8U
#define PIOA_ODR_P3 0x8U
#define PIOA_ODR_P3_BIT 3
#define PIOA_ODR_P4_MASK 0x10U
#define PIOA_ODR_P4 0x10U
#define PIOA_ODR_P4_BIT 4
#define PIOA_ODR_P5_MASK 0x20U
#define PIOA_ODR_P5 0x20U
#define PIOA_ODR_P5_BIT 5
#define PIOA_ODR_P6_MASK 0x40U
#define PIOA_ODR_P6 0x40U
#define PIOA_ODR_P6_BIT 6
#define PIOA_ODR_P7_MASK 0x80U
#define PIOA_ODR_P7 0x80U
#define PIOA_ODR_P7_BIT 7
#define PIOA_ODR_P8_MASK 0x100U
#define PIOA_ODR_P8 0x100U
#define PIOA_ODR_P8_BIT 8
#define PIOA_ODR_P9_MASK 0x200U
#define PIOA_ODR_P9 0x200U
#define PIOA_ODR_P9_BIT 9
#define PIOA_ODR_P10_MASK 0x400U
#define PIOA_ODR_P10 0x400U
#define PIOA_ODR_P10_BIT 10
#define PIOA_ODR_P11_MASK 0x800U
#define PIOA_ODR_P11 0x800U
#define PIOA_ODR_P11_BIT 11
#define PIOA_ODR_P12_MASK 0x1000U
#define PIOA_ODR_P12 0x1000U
#define PIOA_ODR_P12_BIT 12
#define PIOA_ODR_P13_MASK 0x2000U
#define PIOA_ODR_P13 0x2000U
#define PIOA_ODR_P13_BIT 13
#define PIOA_ODR_P14_MASK 0x4000U
#define PIOA_ODR_P14 0x4000U
#define PIOA_ODR_P14_BIT 14
#define PIOA_ODR_P15_MASK 0x8000U
#define PIOA_ODR_P15 0x8000U
#define PIOA_ODR_P15_BIT 15
#define PIOA_ODR_P16_MASK 0x10000U
#define PIOA_ODR_P16 0x10000U
#define PIOA_ODR_P16_BIT 16
#define PIOA_ODR_P17_MASK 0x20000U
#define PIOA_ODR_P17 0x20000U
#define PIOA_ODR_P17_BIT 17
#define PIOA_ODR_P18_MASK 0x40000U
#define PIOA_ODR_P18 0x40000U
#define PIOA_ODR_P18_BIT 18
#define PIOA_ODR_P19_MASK 0x80000U
#define PIOA_ODR_P19 0x80000U
#define PIOA_ODR_P19_BIT 19
#define PIOA_ODR_P20_MASK 0x100000U
#define PIOA_ODR_P20 0x100000U
#define PIOA_ODR_P20_BIT 20
#define PIOA_ODR_P21_MASK 0x200000U
#define PIOA_ODR_P21 0x200000U
#define PIOA_ODR_P21_BIT 21
#define PIOA_ODR_P22_MASK 0x400000U
#define PIOA_ODR_P22 0x400000U
#define PIOA_ODR_P22_BIT 22
#define PIOA_ODR_P23_MASK 0x800000U
#define PIOA_ODR_P23 0x800000U
#define PIOA_ODR_P23_BIT 23
#define PIOA_ODR_P24_MASK 0x1000000U
#define PIOA_ODR_P24 0x1000000U
#define PIOA_ODR_P24_BIT 24
#define PIOA_ODR_P25_MASK 0x2000000U
#define PIOA_ODR_P25 0x2000000U
#define PIOA_ODR_P25_BIT 25
#define PIOA_ODR_P26_MASK 0x4000000U
#define PIOA_ODR_P26 0x4000000U
#define PIOA_ODR_P26_BIT 26
#define PIOA_ODR_P27_MASK 0x8000000U
#define PIOA_ODR_P27 0x8000000U
#define PIOA_ODR_P27_BIT 27
#define PIOA_ODR_P28_MASK 0x10000000U
#define PIOA_ODR_P28 0x10000000U
#define PIOA_ODR_P28_BIT 28
#define PIOA_ODR_P29_MASK 0x20000000U
#define PIOA_ODR_P29 0x20000000U
#define PIOA_ODR_P29_BIT 29
#define PIOA_ODR_P30_MASK 0x40000000U
#define PIOA_ODR_P30 0x40000000U
#define PIOA_ODR_P30_BIT 30
#define PIOA_ODR_P31_MASK 0x80000000U
#define PIOA_ODR_P31 0x80000000U
#define PIOA_ODR_P31_BIT 31

#define PIOA_OSR (*(volatile unsigned long *)0xFFFFF418)
#define PIOA_OSR_OFFSET 0x18
#define PIOA_OSR_P0_MASK 0x1U
#define PIOA_OSR_P0 0x1U
#define PIOA_OSR_P0_BIT 0
#define PIOA_OSR_P1_MASK 0x2U
#define PIOA_OSR_P1 0x2U
#define PIOA_OSR_P1_BIT 1
#define PIOA_OSR_P2_MASK 0x4U
#define PIOA_OSR_P2 0x4U
#define PIOA_OSR_P2_BIT 2
#define PIOA_OSR_P3_MASK 0x8U
#define PIOA_OSR_P3 0x8U
#define PIOA_OSR_P3_BIT 3
#define PIOA_OSR_P4_MASK 0x10U
#define PIOA_OSR_P4 0x10U
#define PIOA_OSR_P4_BIT 4
#define PIOA_OSR_P5_MASK 0x20U
#define PIOA_OSR_P5 0x20U
#define PIOA_OSR_P5_BIT 5
#define PIOA_OSR_P6_MASK 0x40U
#define PIOA_OSR_P6 0x40U
#define PIOA_OSR_P6_BIT 6
#define PIOA_OSR_P7_MASK 0x80U
#define PIOA_OSR_P7 0x80U
#define PIOA_OSR_P7_BIT 7
#define PIOA_OSR_P8_MASK 0x100U
#define PIOA_OSR_P8 0x100U
#define PIOA_OSR_P8_BIT 8
#define PIOA_OSR_P9_MASK 0x200U
#define PIOA_OSR_P9 0x200U
#define PIOA_OSR_P9_BIT 9
#define PIOA_OSR_P10_MASK 0x400U
#define PIOA_OSR_P10 0x400U
#define PIOA_OSR_P10_BIT 10
#define PIOA_OSR_P11_MASK 0x800U
#define PIOA_OSR_P11 0x800U
#define PIOA_OSR_P11_BIT 11
#define PIOA_OSR_P12_MASK 0x1000U
#define PIOA_OSR_P12 0x1000U
#define PIOA_OSR_P12_BIT 12
#define PIOA_OSR_P13_MASK 0x2000U
#define PIOA_OSR_P13 0x2000U
#define PIOA_OSR_P13_BIT 13
#define PIOA_OSR_P14_MASK 0x4000U
#define PIOA_OSR_P14 0x4000U
#define PIOA_OSR_P14_BIT 14
#define PIOA_OSR_P15_MASK 0x8000U
#define PIOA_OSR_P15 0x8000U
#define PIOA_OSR_P15_BIT 15
#define PIOA_OSR_P16_MASK 0x10000U
#define PIOA_OSR_P16 0x10000U
#define PIOA_OSR_P16_BIT 16
#define PIOA_OSR_P17_MASK 0x20000U
#define PIOA_OSR_P17 0x20000U
#define PIOA_OSR_P17_BIT 17
#define PIOA_OSR_P18_MASK 0x40000U
#define PIOA_OSR_P18 0x40000U
#define PIOA_OSR_P18_BIT 18
#define PIOA_OSR_P19_MASK 0x80000U
#define PIOA_OSR_P19 0x80000U
#define PIOA_OSR_P19_BIT 19
#define PIOA_OSR_P20_MASK 0x100000U
#define PIOA_OSR_P20 0x100000U
#define PIOA_OSR_P20_BIT 20
#define PIOA_OSR_P21_MASK 0x200000U
#define PIOA_OSR_P21 0x200000U
#define PIOA_OSR_P21_BIT 21
#define PIOA_OSR_P22_MASK 0x400000U
#define PIOA_OSR_P22 0x400000U
#define PIOA_OSR_P22_BIT 22
#define PIOA_OSR_P23_MASK 0x800000U
#define PIOA_OSR_P23 0x800000U
#define PIOA_OSR_P23_BIT 23
#define PIOA_OSR_P24_MASK 0x1000000U
#define PIOA_OSR_P24 0x1000000U
#define PIOA_OSR_P24_BIT 24
#define PIOA_OSR_P25_MASK 0x2000000U
#define PIOA_OSR_P25 0x2000000U
#define PIOA_OSR_P25_BIT 25
#define PIOA_OSR_P26_MASK 0x4000000U
#define PIOA_OSR_P26 0x4000000U
#define PIOA_OSR_P26_BIT 26
#define PIOA_OSR_P27_MASK 0x8000000U
#define PIOA_OSR_P27 0x8000000U
#define PIOA_OSR_P27_BIT 27
#define PIOA_OSR_P28_MASK 0x10000000U
#define PIOA_OSR_P28 0x10000000U
#define PIOA_OSR_P28_BIT 28
#define PIOA_OSR_P29_MASK 0x20000000U
#define PIOA_OSR_P29 0x20000000U
#define PIOA_OSR_P29_BIT 29
#define PIOA_OSR_P30_MASK 0x40000000U
#define PIOA_OSR_P30 0x40000000U
#define PIOA_OSR_P30_BIT 30
#define PIOA_OSR_P31_MASK 0x80000000U
#define PIOA_OSR_P31 0x80000000U
#define PIOA_OSR_P31_BIT 31

#define PIOA_IFER (*(volatile unsigned long *)0xFFFFF420)
#define PIOA_IFER_OFFSET 0x20
#define PIOA_IFER_P0_MASK 0x1U
#define PIOA_IFER_P0 0x1U
#define PIOA_IFER_P0_BIT 0
#define PIOA_IFER_P1_MASK 0x2U
#define PIOA_IFER_P1 0x2U
#define PIOA_IFER_P1_BIT 1
#define PIOA_IFER_P2_MASK 0x4U
#define PIOA_IFER_P2 0x4U
#define PIOA_IFER_P2_BIT 2
#define PIOA_IFER_P3_MASK 0x8U
#define PIOA_IFER_P3 0x8U
#define PIOA_IFER_P3_BIT 3
#define PIOA_IFER_P4_MASK 0x10U
#define PIOA_IFER_P4 0x10U
#define PIOA_IFER_P4_BIT 4
#define PIOA_IFER_P5_MASK 0x20U
#define PIOA_IFER_P5 0x20U
#define PIOA_IFER_P5_BIT 5
#define PIOA_IFER_P6_MASK 0x40U
#define PIOA_IFER_P6 0x40U
#define PIOA_IFER_P6_BIT 6
#define PIOA_IFER_P7_MASK 0x80U
#define PIOA_IFER_P7 0x80U
#define PIOA_IFER_P7_BIT 7
#define PIOA_IFER_P8_MASK 0x100U
#define PIOA_IFER_P8 0x100U
#define PIOA_IFER_P8_BIT 8
#define PIOA_IFER_P9_MASK 0x200U
#define PIOA_IFER_P9 0x200U
#define PIOA_IFER_P9_BIT 9
#define PIOA_IFER_P10_MASK 0x400U
#define PIOA_IFER_P10 0x400U
#define PIOA_IFER_P10_BIT 10
#define PIOA_IFER_P11_MASK 0x800U
#define PIOA_IFER_P11 0x800U
#define PIOA_IFER_P11_BIT 11
#define PIOA_IFER_P12_MASK 0x1000U
#define PIOA_IFER_P12 0x1000U
#define PIOA_IFER_P12_BIT 12
#define PIOA_IFER_P13_MASK 0x2000U
#define PIOA_IFER_P13 0x2000U
#define PIOA_IFER_P13_BIT 13
#define PIOA_IFER_P14_MASK 0x4000U
#define PIOA_IFER_P14 0x4000U
#define PIOA_IFER_P14_BIT 14
#define PIOA_IFER_P15_MASK 0x8000U
#define PIOA_IFER_P15 0x8000U
#define PIOA_IFER_P15_BIT 15
#define PIOA_IFER_P16_MASK 0x10000U
#define PIOA_IFER_P16 0x10000U
#define PIOA_IFER_P16_BIT 16
#define PIOA_IFER_P17_MASK 0x20000U
#define PIOA_IFER_P17 0x20000U
#define PIOA_IFER_P17_BIT 17
#define PIOA_IFER_P18_MASK 0x40000U
#define PIOA_IFER_P18 0x40000U
#define PIOA_IFER_P18_BIT 18
#define PIOA_IFER_P19_MASK 0x80000U
#define PIOA_IFER_P19 0x80000U
#define PIOA_IFER_P19_BIT 19
#define PIOA_IFER_P20_MASK 0x100000U
#define PIOA_IFER_P20 0x100000U
#define PIOA_IFER_P20_BIT 20
#define PIOA_IFER_P21_MASK 0x200000U
#define PIOA_IFER_P21 0x200000U
#define PIOA_IFER_P21_BIT 21
#define PIOA_IFER_P22_MASK 0x400000U
#define PIOA_IFER_P22 0x400000U
#define PIOA_IFER_P22_BIT 22
#define PIOA_IFER_P23_MASK 0x800000U
#define PIOA_IFER_P23 0x800000U
#define PIOA_IFER_P23_BIT 23
#define PIOA_IFER_P24_MASK 0x1000000U
#define PIOA_IFER_P24 0x1000000U
#define PIOA_IFER_P24_BIT 24
#define PIOA_IFER_P25_MASK 0x2000000U
#define PIOA_IFER_P25 0x2000000U
#define PIOA_IFER_P25_BIT 25
#define PIOA_IFER_P26_MASK 0x4000000U
#define PIOA_IFER_P26 0x4000000U
#define PIOA_IFER_P26_BIT 26
#define PIOA_IFER_P27_MASK 0x8000000U
#define PIOA_IFER_P27 0x8000000U
#define PIOA_IFER_P27_BIT 27
#define PIOA_IFER_P28_MASK 0x10000000U
#define PIOA_IFER_P28 0x10000000U
#define PIOA_IFER_P28_BIT 28
#define PIOA_IFER_P29_MASK 0x20000000U
#define PIOA_IFER_P29 0x20000000U
#define PIOA_IFER_P29_BIT 29
#define PIOA_IFER_P30_MASK 0x40000000U
#define PIOA_IFER_P30 0x40000000U
#define PIOA_IFER_P30_BIT 30
#define PIOA_IFER_P31_MASK 0x80000000U
#define PIOA_IFER_P31 0x80000000U
#define PIOA_IFER_P31_BIT 31

#define PIOA_IFDR (*(volatile unsigned long *)0xFFFFF424)
#define PIOA_IFDR_OFFSET 0x24
#define PIOA_IFDR_P0_MASK 0x1U
#define PIOA_IFDR_P0 0x1U
#define PIOA_IFDR_P0_BIT 0
#define PIOA_IFDR_P1_MASK 0x2U
#define PIOA_IFDR_P1 0x2U
#define PIOA_IFDR_P1_BIT 1
#define PIOA_IFDR_P2_MASK 0x4U
#define PIOA_IFDR_P2 0x4U
#define PIOA_IFDR_P2_BIT 2
#define PIOA_IFDR_P3_MASK 0x8U
#define PIOA_IFDR_P3 0x8U
#define PIOA_IFDR_P3_BIT 3
#define PIOA_IFDR_P4_MASK 0x10U
#define PIOA_IFDR_P4 0x10U
#define PIOA_IFDR_P4_BIT 4
#define PIOA_IFDR_P5_MASK 0x20U
#define PIOA_IFDR_P5 0x20U
#define PIOA_IFDR_P5_BIT 5
#define PIOA_IFDR_P6_MASK 0x40U
#define PIOA_IFDR_P6 0x40U
#define PIOA_IFDR_P6_BIT 6
#define PIOA_IFDR_P7_MASK 0x80U
#define PIOA_IFDR_P7 0x80U
#define PIOA_IFDR_P7_BIT 7
#define PIOA_IFDR_P8_MASK 0x100U
#define PIOA_IFDR_P8 0x100U
#define PIOA_IFDR_P8_BIT 8
#define PIOA_IFDR_P9_MASK 0x200U
#define PIOA_IFDR_P9 0x200U
#define PIOA_IFDR_P9_BIT 9
#define PIOA_IFDR_P10_MASK 0x400U
#define PIOA_IFDR_P10 0x400U
#define PIOA_IFDR_P10_BIT 10
#define PIOA_IFDR_P11_MASK 0x800U
#define PIOA_IFDR_P11 0x800U
#define PIOA_IFDR_P11_BIT 11
#define PIOA_IFDR_P12_MASK 0x1000U
#define PIOA_IFDR_P12 0x1000U
#define PIOA_IFDR_P12_BIT 12
#define PIOA_IFDR_P13_MASK 0x2000U
#define PIOA_IFDR_P13 0x2000U
#define PIOA_IFDR_P13_BIT 13
#define PIOA_IFDR_P14_MASK 0x4000U
#define PIOA_IFDR_P14 0x4000U
#define PIOA_IFDR_P14_BIT 14
#define PIOA_IFDR_P15_MASK 0x8000U
#define PIOA_IFDR_P15 0x8000U
#define PIOA_IFDR_P15_BIT 15
#define PIOA_IFDR_P16_MASK 0x10000U
#define PIOA_IFDR_P16 0x10000U
#define PIOA_IFDR_P16_BIT 16
#define PIOA_IFDR_P17_MASK 0x20000U
#define PIOA_IFDR_P17 0x20000U
#define PIOA_IFDR_P17_BIT 17
#define PIOA_IFDR_P18_MASK 0x40000U
#define PIOA_IFDR_P18 0x40000U
#define PIOA_IFDR_P18_BIT 18
#define PIOA_IFDR_P19_MASK 0x80000U
#define PIOA_IFDR_P19 0x80000U
#define PIOA_IFDR_P19_BIT 19
#define PIOA_IFDR_P20_MASK 0x100000U
#define PIOA_IFDR_P20 0x100000U
#define PIOA_IFDR_P20_BIT 20
#define PIOA_IFDR_P21_MASK 0x200000U
#define PIOA_IFDR_P21 0x200000U
#define PIOA_IFDR_P21_BIT 21
#define PIOA_IFDR_P22_MASK 0x400000U
#define PIOA_IFDR_P22 0x400000U
#define PIOA_IFDR_P22_BIT 22
#define PIOA_IFDR_P23_MASK 0x800000U
#define PIOA_IFDR_P23 0x800000U
#define PIOA_IFDR_P23_BIT 23
#define PIOA_IFDR_P24_MASK 0x1000000U
#define PIOA_IFDR_P24 0x1000000U
#define PIOA_IFDR_P24_BIT 24
#define PIOA_IFDR_P25_MASK 0x2000000U
#define PIOA_IFDR_P25 0x2000000U
#define PIOA_IFDR_P25_BIT 25
#define PIOA_IFDR_P26_MASK 0x4000000U
#define PIOA_IFDR_P26 0x4000000U
#define PIOA_IFDR_P26_BIT 26
#define PIOA_IFDR_P27_MASK 0x8000000U
#define PIOA_IFDR_P27 0x8000000U
#define PIOA_IFDR_P27_BIT 27
#define PIOA_IFDR_P28_MASK 0x10000000U
#define PIOA_IFDR_P28 0x10000000U
#define PIOA_IFDR_P28_BIT 28
#define PIOA_IFDR_P29_MASK 0x20000000U
#define PIOA_IFDR_P29 0x20000000U
#define PIOA_IFDR_P29_BIT 29
#define PIOA_IFDR_P30_MASK 0x40000000U
#define PIOA_IFDR_P30 0x40000000U
#define PIOA_IFDR_P30_BIT 30
#define PIOA_IFDR_P31_MASK 0x80000000U
#define PIOA_IFDR_P31 0x80000000U
#define PIOA_IFDR_P31_BIT 31

#define PIOA_IFSR (*(volatile unsigned long *)0xFFFFF428)
#define PIOA_IFSR_OFFSET 0x28
#define PIOA_IFSR_P0_MASK 0x1U
#define PIOA_IFSR_P0 0x1U
#define PIOA_IFSR_P0_BIT 0
#define PIOA_IFSR_P1_MASK 0x2U
#define PIOA_IFSR_P1 0x2U
#define PIOA_IFSR_P1_BIT 1
#define PIOA_IFSR_P2_MASK 0x4U
#define PIOA_IFSR_P2 0x4U
#define PIOA_IFSR_P2_BIT 2
#define PIOA_IFSR_P3_MASK 0x8U
#define PIOA_IFSR_P3 0x8U
#define PIOA_IFSR_P3_BIT 3
#define PIOA_IFSR_P4_MASK 0x10U
#define PIOA_IFSR_P4 0x10U
#define PIOA_IFSR_P4_BIT 4
#define PIOA_IFSR_P5_MASK 0x20U
#define PIOA_IFSR_P5 0x20U
#define PIOA_IFSR_P5_BIT 5
#define PIOA_IFSR_P6_MASK 0x40U
#define PIOA_IFSR_P6 0x40U
#define PIOA_IFSR_P6_BIT 6
#define PIOA_IFSR_P7_MASK 0x80U
#define PIOA_IFSR_P7 0x80U
#define PIOA_IFSR_P7_BIT 7
#define PIOA_IFSR_P8_MASK 0x100U
#define PIOA_IFSR_P8 0x100U
#define PIOA_IFSR_P8_BIT 8
#define PIOA_IFSR_P9_MASK 0x200U
#define PIOA_IFSR_P9 0x200U
#define PIOA_IFSR_P9_BIT 9
#define PIOA_IFSR_P10_MASK 0x400U
#define PIOA_IFSR_P10 0x400U
#define PIOA_IFSR_P10_BIT 10
#define PIOA_IFSR_P11_MASK 0x800U
#define PIOA_IFSR_P11 0x800U
#define PIOA_IFSR_P11_BIT 11
#define PIOA_IFSR_P12_MASK 0x1000U
#define PIOA_IFSR_P12 0x1000U
#define PIOA_IFSR_P12_BIT 12
#define PIOA_IFSR_P13_MASK 0x2000U
#define PIOA_IFSR_P13 0x2000U
#define PIOA_IFSR_P13_BIT 13
#define PIOA_IFSR_P14_MASK 0x4000U
#define PIOA_IFSR_P14 0x4000U
#define PIOA_IFSR_P14_BIT 14
#define PIOA_IFSR_P15_MASK 0x8000U
#define PIOA_IFSR_P15 0x8000U
#define PIOA_IFSR_P15_BIT 15
#define PIOA_IFSR_P16_MASK 0x10000U
#define PIOA_IFSR_P16 0x10000U
#define PIOA_IFSR_P16_BIT 16
#define PIOA_IFSR_P17_MASK 0x20000U
#define PIOA_IFSR_P17 0x20000U
#define PIOA_IFSR_P17_BIT 17
#define PIOA_IFSR_P18_MASK 0x40000U
#define PIOA_IFSR_P18 0x40000U
#define PIOA_IFSR_P18_BIT 18
#define PIOA_IFSR_P19_MASK 0x80000U
#define PIOA_IFSR_P19 0x80000U
#define PIOA_IFSR_P19_BIT 19
#define PIOA_IFSR_P20_MASK 0x100000U
#define PIOA_IFSR_P20 0x100000U
#define PIOA_IFSR_P20_BIT 20
#define PIOA_IFSR_P21_MASK 0x200000U
#define PIOA_IFSR_P21 0x200000U
#define PIOA_IFSR_P21_BIT 21
#define PIOA_IFSR_P22_MASK 0x400000U
#define PIOA_IFSR_P22 0x400000U
#define PIOA_IFSR_P22_BIT 22
#define PIOA_IFSR_P23_MASK 0x800000U
#define PIOA_IFSR_P23 0x800000U
#define PIOA_IFSR_P23_BIT 23
#define PIOA_IFSR_P24_MASK 0x1000000U
#define PIOA_IFSR_P24 0x1000000U
#define PIOA_IFSR_P24_BIT 24
#define PIOA_IFSR_P25_MASK 0x2000000U
#define PIOA_IFSR_P25 0x2000000U
#define PIOA_IFSR_P25_BIT 25
#define PIOA_IFSR_P26_MASK 0x4000000U
#define PIOA_IFSR_P26 0x4000000U
#define PIOA_IFSR_P26_BIT 26
#define PIOA_IFSR_P27_MASK 0x8000000U
#define PIOA_IFSR_P27 0x8000000U
#define PIOA_IFSR_P27_BIT 27
#define PIOA_IFSR_P28_MASK 0x10000000U
#define PIOA_IFSR_P28 0x10000000U
#define PIOA_IFSR_P28_BIT 28
#define PIOA_IFSR_P29_MASK 0x20000000U
#define PIOA_IFSR_P29 0x20000000U
#define PIOA_IFSR_P29_BIT 29
#define PIOA_IFSR_P30_MASK 0x40000000U
#define PIOA_IFSR_P30 0x40000000U
#define PIOA_IFSR_P30_BIT 30
#define PIOA_IFSR_P31_MASK 0x80000000U
#define PIOA_IFSR_P31 0x80000000U
#define PIOA_IFSR_P31_BIT 31

#define PIOA_SODR (*(volatile unsigned long *)0xFFFFF430)
#define PIOA_SODR_OFFSET 0x30
#define PIOA_SODR_P0_MASK 0x1U
#define PIOA_SODR_P0 0x1U
#define PIOA_SODR_P0_BIT 0
#define PIOA_SODR_P1_MASK 0x2U
#define PIOA_SODR_P1 0x2U
#define PIOA_SODR_P1_BIT 1
#define PIOA_SODR_P2_MASK 0x4U
#define PIOA_SODR_P2 0x4U
#define PIOA_SODR_P2_BIT 2
#define PIOA_SODR_P3_MASK 0x8U
#define PIOA_SODR_P3 0x8U
#define PIOA_SODR_P3_BIT 3
#define PIOA_SODR_P4_MASK 0x10U
#define PIOA_SODR_P4 0x10U
#define PIOA_SODR_P4_BIT 4
#define PIOA_SODR_P5_MASK 0x20U
#define PIOA_SODR_P5 0x20U
#define PIOA_SODR_P5_BIT 5
#define PIOA_SODR_P6_MASK 0x40U
#define PIOA_SODR_P6 0x40U
#define PIOA_SODR_P6_BIT 6
#define PIOA_SODR_P7_MASK 0x80U
#define PIOA_SODR_P7 0x80U
#define PIOA_SODR_P7_BIT 7
#define PIOA_SODR_P8_MASK 0x100U
#define PIOA_SODR_P8 0x100U
#define PIOA_SODR_P8_BIT 8
#define PIOA_SODR_P9_MASK 0x200U
#define PIOA_SODR_P9 0x200U
#define PIOA_SODR_P9_BIT 9
#define PIOA_SODR_P10_MASK 0x400U
#define PIOA_SODR_P10 0x400U
#define PIOA_SODR_P10_BIT 10
#define PIOA_SODR_P11_MASK 0x800U
#define PIOA_SODR_P11 0x800U
#define PIOA_SODR_P11_BIT 11
#define PIOA_SODR_P12_MASK 0x1000U
#define PIOA_SODR_P12 0x1000U
#define PIOA_SODR_P12_BIT 12
#define PIOA_SODR_P13_MASK 0x2000U
#define PIOA_SODR_P13 0x2000U
#define PIOA_SODR_P13_BIT 13
#define PIOA_SODR_P14_MASK 0x4000U
#define PIOA_SODR_P14 0x4000U
#define PIOA_SODR_P14_BIT 14
#define PIOA_SODR_P15_MASK 0x8000U
#define PIOA_SODR_P15 0x8000U
#define PIOA_SODR_P15_BIT 15
#define PIOA_SODR_P16_MASK 0x10000U
#define PIOA_SODR_P16 0x10000U
#define PIOA_SODR_P16_BIT 16
#define PIOA_SODR_P17_MASK 0x20000U
#define PIOA_SODR_P17 0x20000U
#define PIOA_SODR_P17_BIT 17
#define PIOA_SODR_P18_MASK 0x40000U
#define PIOA_SODR_P18 0x40000U
#define PIOA_SODR_P18_BIT 18
#define PIOA_SODR_P19_MASK 0x80000U
#define PIOA_SODR_P19 0x80000U
#define PIOA_SODR_P19_BIT 19
#define PIOA_SODR_P20_MASK 0x100000U
#define PIOA_SODR_P20 0x100000U
#define PIOA_SODR_P20_BIT 20
#define PIOA_SODR_P21_MASK 0x200000U
#define PIOA_SODR_P21 0x200000U
#define PIOA_SODR_P21_BIT 21
#define PIOA_SODR_P22_MASK 0x400000U
#define PIOA_SODR_P22 0x400000U
#define PIOA_SODR_P22_BIT 22
#define PIOA_SODR_P23_MASK 0x800000U
#define PIOA_SODR_P23 0x800000U
#define PIOA_SODR_P23_BIT 23
#define PIOA_SODR_P24_MASK 0x1000000U
#define PIOA_SODR_P24 0x1000000U
#define PIOA_SODR_P24_BIT 24
#define PIOA_SODR_P25_MASK 0x2000000U
#define PIOA_SODR_P25 0x2000000U
#define PIOA_SODR_P25_BIT 25
#define PIOA_SODR_P26_MASK 0x4000000U
#define PIOA_SODR_P26 0x4000000U
#define PIOA_SODR_P26_BIT 26
#define PIOA_SODR_P27_MASK 0x8000000U
#define PIOA_SODR_P27 0x8000000U
#define PIOA_SODR_P27_BIT 27
#define PIOA_SODR_P28_MASK 0x10000000U
#define PIOA_SODR_P28 0x10000000U
#define PIOA_SODR_P28_BIT 28
#define PIOA_SODR_P29_MASK 0x20000000U
#define PIOA_SODR_P29 0x20000000U
#define PIOA_SODR_P29_BIT 29
#define PIOA_SODR_P30_MASK 0x40000000U
#define PIOA_SODR_P30 0x40000000U
#define PIOA_SODR_P30_BIT 30
#define PIOA_SODR_P31_MASK 0x80000000U
#define PIOA_SODR_P31 0x80000000U
#define PIOA_SODR_P31_BIT 31

#define PIOA_CODR (*(volatile unsigned long *)0xFFFFF434)
#define PIOA_CODR_OFFSET 0x34
#define PIOA_CODR_P0_MASK 0x1U
#define PIOA_CODR_P0 0x1U
#define PIOA_CODR_P0_BIT 0
#define PIOA_CODR_P1_MASK 0x2U
#define PIOA_CODR_P1 0x2U
#define PIOA_CODR_P1_BIT 1
#define PIOA_CODR_P2_MASK 0x4U
#define PIOA_CODR_P2 0x4U
#define PIOA_CODR_P2_BIT 2
#define PIOA_CODR_P3_MASK 0x8U
#define PIOA_CODR_P3 0x8U
#define PIOA_CODR_P3_BIT 3
#define PIOA_CODR_P4_MASK 0x10U
#define PIOA_CODR_P4 0x10U
#define PIOA_CODR_P4_BIT 4
#define PIOA_CODR_P5_MASK 0x20U
#define PIOA_CODR_P5 0x20U
#define PIOA_CODR_P5_BIT 5
#define PIOA_CODR_P6_MASK 0x40U
#define PIOA_CODR_P6 0x40U
#define PIOA_CODR_P6_BIT 6
#define PIOA_CODR_P7_MASK 0x80U
#define PIOA_CODR_P7 0x80U
#define PIOA_CODR_P7_BIT 7
#define PIOA_CODR_P8_MASK 0x100U
#define PIOA_CODR_P8 0x100U
#define PIOA_CODR_P8_BIT 8
#define PIOA_CODR_P9_MASK 0x200U
#define PIOA_CODR_P9 0x200U
#define PIOA_CODR_P9_BIT 9
#define PIOA_CODR_P10_MASK 0x400U
#define PIOA_CODR_P10 0x400U
#define PIOA_CODR_P10_BIT 10
#define PIOA_CODR_P11_MASK 0x800U
#define PIOA_CODR_P11 0x800U
#define PIOA_CODR_P11_BIT 11
#define PIOA_CODR_P12_MASK 0x1000U
#define PIOA_CODR_P12 0x1000U
#define PIOA_CODR_P12_BIT 12
#define PIOA_CODR_P13_MASK 0x2000U
#define PIOA_CODR_P13 0x2000U
#define PIOA_CODR_P13_BIT 13
#define PIOA_CODR_P14_MASK 0x4000U
#define PIOA_CODR_P14 0x4000U
#define PIOA_CODR_P14_BIT 14
#define PIOA_CODR_P15_MASK 0x8000U
#define PIOA_CODR_P15 0x8000U
#define PIOA_CODR_P15_BIT 15
#define PIOA_CODR_P16_MASK 0x10000U
#define PIOA_CODR_P16 0x10000U
#define PIOA_CODR_P16_BIT 16
#define PIOA_CODR_P17_MASK 0x20000U
#define PIOA_CODR_P17 0x20000U
#define PIOA_CODR_P17_BIT 17
#define PIOA_CODR_P18_MASK 0x40000U
#define PIOA_CODR_P18 0x40000U
#define PIOA_CODR_P18_BIT 18
#define PIOA_CODR_P19_MASK 0x80000U
#define PIOA_CODR_P19 0x80000U
#define PIOA_CODR_P19_BIT 19
#define PIOA_CODR_P20_MASK 0x100000U
#define PIOA_CODR_P20 0x100000U
#define PIOA_CODR_P20_BIT 20
#define PIOA_CODR_P21_MASK 0x200000U
#define PIOA_CODR_P21 0x200000U
#define PIOA_CODR_P21_BIT 21
#define PIOA_CODR_P22_MASK 0x400000U
#define PIOA_CODR_P22 0x400000U
#define PIOA_CODR_P22_BIT 22
#define PIOA_CODR_P23_MASK 0x800000U
#define PIOA_CODR_P23 0x800000U
#define PIOA_CODR_P23_BIT 23
#define PIOA_CODR_P24_MASK 0x1000000U
#define PIOA_CODR_P24 0x1000000U
#define PIOA_CODR_P24_BIT 24
#define PIOA_CODR_P25_MASK 0x2000000U
#define PIOA_CODR_P25 0x2000000U
#define PIOA_CODR_P25_BIT 25
#define PIOA_CODR_P26_MASK 0x4000000U
#define PIOA_CODR_P26 0x4000000U
#define PIOA_CODR_P26_BIT 26
#define PIOA_CODR_P27_MASK 0x8000000U
#define PIOA_CODR_P27 0x8000000U
#define PIOA_CODR_P27_BIT 27
#define PIOA_CODR_P28_MASK 0x10000000U
#define PIOA_CODR_P28 0x10000000U
#define PIOA_CODR_P28_BIT 28
#define PIOA_CODR_P29_MASK 0x20000000U
#define PIOA_CODR_P29 0x20000000U
#define PIOA_CODR_P29_BIT 29
#define PIOA_CODR_P30_MASK 0x40000000U
#define PIOA_CODR_P30 0x40000000U
#define PIOA_CODR_P30_BIT 30
#define PIOA_CODR_P31_MASK 0x80000000U
#define PIOA_CODR_P31 0x80000000U
#define PIOA_CODR_P31_BIT 31

#define PIOA_ODSR (*(volatile unsigned long *)0xFFFFF438)
#define PIOA_ODSR_OFFSET 0x38
#define PIOA_ODSR_P0_MASK 0x1U
#define PIOA_ODSR_P0 0x1U
#define PIOA_ODSR_P0_BIT 0
#define PIOA_ODSR_P1_MASK 0x2U
#define PIOA_ODSR_P1 0x2U
#define PIOA_ODSR_P1_BIT 1
#define PIOA_ODSR_P2_MASK 0x4U
#define PIOA_ODSR_P2 0x4U
#define PIOA_ODSR_P2_BIT 2
#define PIOA_ODSR_P3_MASK 0x8U
#define PIOA_ODSR_P3 0x8U
#define PIOA_ODSR_P3_BIT 3
#define PIOA_ODSR_P4_MASK 0x10U
#define PIOA_ODSR_P4 0x10U
#define PIOA_ODSR_P4_BIT 4
#define PIOA_ODSR_P5_MASK 0x20U
#define PIOA_ODSR_P5 0x20U
#define PIOA_ODSR_P5_BIT 5
#define PIOA_ODSR_P6_MASK 0x40U
#define PIOA_ODSR_P6 0x40U
#define PIOA_ODSR_P6_BIT 6
#define PIOA_ODSR_P7_MASK 0x80U
#define PIOA_ODSR_P7 0x80U
#define PIOA_ODSR_P7_BIT 7
#define PIOA_ODSR_P8_MASK 0x100U
#define PIOA_ODSR_P8 0x100U
#define PIOA_ODSR_P8_BIT 8
#define PIOA_ODSR_P9_MASK 0x200U
#define PIOA_ODSR_P9 0x200U
#define PIOA_ODSR_P9_BIT 9
#define PIOA_ODSR_P10_MASK 0x400U
#define PIOA_ODSR_P10 0x400U
#define PIOA_ODSR_P10_BIT 10
#define PIOA_ODSR_P11_MASK 0x800U
#define PIOA_ODSR_P11 0x800U
#define PIOA_ODSR_P11_BIT 11
#define PIOA_ODSR_P12_MASK 0x1000U
#define PIOA_ODSR_P12 0x1000U
#define PIOA_ODSR_P12_BIT 12
#define PIOA_ODSR_P13_MASK 0x2000U
#define PIOA_ODSR_P13 0x2000U
#define PIOA_ODSR_P13_BIT 13
#define PIOA_ODSR_P14_MASK 0x4000U
#define PIOA_ODSR_P14 0x4000U
#define PIOA_ODSR_P14_BIT 14
#define PIOA_ODSR_P15_MASK 0x8000U
#define PIOA_ODSR_P15 0x8000U
#define PIOA_ODSR_P15_BIT 15
#define PIOA_ODSR_P16_MASK 0x10000U
#define PIOA_ODSR_P16 0x10000U
#define PIOA_ODSR_P16_BIT 16
#define PIOA_ODSR_P17_MASK 0x20000U
#define PIOA_ODSR_P17 0x20000U
#define PIOA_ODSR_P17_BIT 17
#define PIOA_ODSR_P18_MASK 0x40000U
#define PIOA_ODSR_P18 0x40000U
#define PIOA_ODSR_P18_BIT 18
#define PIOA_ODSR_P19_MASK 0x80000U
#define PIOA_ODSR_P19 0x80000U
#define PIOA_ODSR_P19_BIT 19
#define PIOA_ODSR_P20_MASK 0x100000U
#define PIOA_ODSR_P20 0x100000U
#define PIOA_ODSR_P20_BIT 20
#define PIOA_ODSR_P21_MASK 0x200000U
#define PIOA_ODSR_P21 0x200000U
#define PIOA_ODSR_P21_BIT 21
#define PIOA_ODSR_P22_MASK 0x400000U
#define PIOA_ODSR_P22 0x400000U
#define PIOA_ODSR_P22_BIT 22
#define PIOA_ODSR_P23_MASK 0x800000U
#define PIOA_ODSR_P23 0x800000U
#define PIOA_ODSR_P23_BIT 23
#define PIOA_ODSR_P24_MASK 0x1000000U
#define PIOA_ODSR_P24 0x1000000U
#define PIOA_ODSR_P24_BIT 24
#define PIOA_ODSR_P25_MASK 0x2000000U
#define PIOA_ODSR_P25 0x2000000U
#define PIOA_ODSR_P25_BIT 25
#define PIOA_ODSR_P26_MASK 0x4000000U
#define PIOA_ODSR_P26 0x4000000U
#define PIOA_ODSR_P26_BIT 26
#define PIOA_ODSR_P27_MASK 0x8000000U
#define PIOA_ODSR_P27 0x8000000U
#define PIOA_ODSR_P27_BIT 27
#define PIOA_ODSR_P28_MASK 0x10000000U
#define PIOA_ODSR_P28 0x10000000U
#define PIOA_ODSR_P28_BIT 28
#define PIOA_ODSR_P29_MASK 0x20000000U
#define PIOA_ODSR_P29 0x20000000U
#define PIOA_ODSR_P29_BIT 29
#define PIOA_ODSR_P30_MASK 0x40000000U
#define PIOA_ODSR_P30 0x40000000U
#define PIOA_ODSR_P30_BIT 30
#define PIOA_ODSR_P31_MASK 0x80000000U
#define PIOA_ODSR_P31 0x80000000U
#define PIOA_ODSR_P31_BIT 31

#define PIOA_PDSR (*(volatile unsigned long *)0xFFFFF43C)
#define PIOA_PDSR_OFFSET 0x3C
#define PIOA_PDSR_P0_MASK 0x1U
#define PIOA_PDSR_P0 0x1U
#define PIOA_PDSR_P0_BIT 0
#define PIOA_PDSR_P1_MASK 0x2U
#define PIOA_PDSR_P1 0x2U
#define PIOA_PDSR_P1_BIT 1
#define PIOA_PDSR_P2_MASK 0x4U
#define PIOA_PDSR_P2 0x4U
#define PIOA_PDSR_P2_BIT 2
#define PIOA_PDSR_P3_MASK 0x8U
#define PIOA_PDSR_P3 0x8U
#define PIOA_PDSR_P3_BIT 3
#define PIOA_PDSR_P4_MASK 0x10U
#define PIOA_PDSR_P4 0x10U
#define PIOA_PDSR_P4_BIT 4
#define PIOA_PDSR_P5_MASK 0x20U
#define PIOA_PDSR_P5 0x20U
#define PIOA_PDSR_P5_BIT 5
#define PIOA_PDSR_P6_MASK 0x40U
#define PIOA_PDSR_P6 0x40U
#define PIOA_PDSR_P6_BIT 6
#define PIOA_PDSR_P7_MASK 0x80U
#define PIOA_PDSR_P7 0x80U
#define PIOA_PDSR_P7_BIT 7
#define PIOA_PDSR_P8_MASK 0x100U
#define PIOA_PDSR_P8 0x100U
#define PIOA_PDSR_P8_BIT 8
#define PIOA_PDSR_P9_MASK 0x200U
#define PIOA_PDSR_P9 0x200U
#define PIOA_PDSR_P9_BIT 9
#define PIOA_PDSR_P10_MASK 0x400U
#define PIOA_PDSR_P10 0x400U
#define PIOA_PDSR_P10_BIT 10
#define PIOA_PDSR_P11_MASK 0x800U
#define PIOA_PDSR_P11 0x800U
#define PIOA_PDSR_P11_BIT 11
#define PIOA_PDSR_P12_MASK 0x1000U
#define PIOA_PDSR_P12 0x1000U
#define PIOA_PDSR_P12_BIT 12
#define PIOA_PDSR_P13_MASK 0x2000U
#define PIOA_PDSR_P13 0x2000U
#define PIOA_PDSR_P13_BIT 13
#define PIOA_PDSR_P14_MASK 0x4000U
#define PIOA_PDSR_P14 0x4000U
#define PIOA_PDSR_P14_BIT 14
#define PIOA_PDSR_P15_MASK 0x8000U
#define PIOA_PDSR_P15 0x8000U
#define PIOA_PDSR_P15_BIT 15
#define PIOA_PDSR_P16_MASK 0x10000U
#define PIOA_PDSR_P16 0x10000U
#define PIOA_PDSR_P16_BIT 16
#define PIOA_PDSR_P17_MASK 0x20000U
#define PIOA_PDSR_P17 0x20000U
#define PIOA_PDSR_P17_BIT 17
#define PIOA_PDSR_P18_MASK 0x40000U
#define PIOA_PDSR_P18 0x40000U
#define PIOA_PDSR_P18_BIT 18
#define PIOA_PDSR_P19_MASK 0x80000U
#define PIOA_PDSR_P19 0x80000U
#define PIOA_PDSR_P19_BIT 19
#define PIOA_PDSR_P20_MASK 0x100000U
#define PIOA_PDSR_P20 0x100000U
#define PIOA_PDSR_P20_BIT 20
#define PIOA_PDSR_P21_MASK 0x200000U
#define PIOA_PDSR_P21 0x200000U
#define PIOA_PDSR_P21_BIT 21
#define PIOA_PDSR_P22_MASK 0x400000U
#define PIOA_PDSR_P22 0x400000U
#define PIOA_PDSR_P22_BIT 22
#define PIOA_PDSR_P23_MASK 0x800000U
#define PIOA_PDSR_P23 0x800000U
#define PIOA_PDSR_P23_BIT 23
#define PIOA_PDSR_P24_MASK 0x1000000U
#define PIOA_PDSR_P24 0x1000000U
#define PIOA_PDSR_P24_BIT 24
#define PIOA_PDSR_P25_MASK 0x2000000U
#define PIOA_PDSR_P25 0x2000000U
#define PIOA_PDSR_P25_BIT 25
#define PIOA_PDSR_P26_MASK 0x4000000U
#define PIOA_PDSR_P26 0x4000000U
#define PIOA_PDSR_P26_BIT 26
#define PIOA_PDSR_P27_MASK 0x8000000U
#define PIOA_PDSR_P27 0x8000000U
#define PIOA_PDSR_P27_BIT 27
#define PIOA_PDSR_P28_MASK 0x10000000U
#define PIOA_PDSR_P28 0x10000000U
#define PIOA_PDSR_P28_BIT 28
#define PIOA_PDSR_P29_MASK 0x20000000U
#define PIOA_PDSR_P29 0x20000000U
#define PIOA_PDSR_P29_BIT 29
#define PIOA_PDSR_P30_MASK 0x40000000U
#define PIOA_PDSR_P30 0x40000000U
#define PIOA_PDSR_P30_BIT 30
#define PIOA_PDSR_P31_MASK 0x80000000U
#define PIOA_PDSR_P31 0x80000000U
#define PIOA_PDSR_P31_BIT 31

#define PIOA_IER (*(volatile unsigned long *)0xFFFFF440)
#define PIOA_IER_OFFSET 0x40
#define PIOA_IER_P0_MASK 0x1U
#define PIOA_IER_P0 0x1U
#define PIOA_IER_P0_BIT 0
#define PIOA_IER_P1_MASK 0x2U
#define PIOA_IER_P1 0x2U
#define PIOA_IER_P1_BIT 1
#define PIOA_IER_P2_MASK 0x4U
#define PIOA_IER_P2 0x4U
#define PIOA_IER_P2_BIT 2
#define PIOA_IER_P3_MASK 0x8U
#define PIOA_IER_P3 0x8U
#define PIOA_IER_P3_BIT 3
#define PIOA_IER_P4_MASK 0x10U
#define PIOA_IER_P4 0x10U
#define PIOA_IER_P4_BIT 4
#define PIOA_IER_P5_MASK 0x20U
#define PIOA_IER_P5 0x20U
#define PIOA_IER_P5_BIT 5
#define PIOA_IER_P6_MASK 0x40U
#define PIOA_IER_P6 0x40U
#define PIOA_IER_P6_BIT 6
#define PIOA_IER_P7_MASK 0x80U
#define PIOA_IER_P7 0x80U
#define PIOA_IER_P7_BIT 7
#define PIOA_IER_P8_MASK 0x100U
#define PIOA_IER_P8 0x100U
#define PIOA_IER_P8_BIT 8
#define PIOA_IER_P9_MASK 0x200U
#define PIOA_IER_P9 0x200U
#define PIOA_IER_P9_BIT 9
#define PIOA_IER_P10_MASK 0x400U
#define PIOA_IER_P10 0x400U
#define PIOA_IER_P10_BIT 10
#define PIOA_IER_P11_MASK 0x800U
#define PIOA_IER_P11 0x800U
#define PIOA_IER_P11_BIT 11
#define PIOA_IER_P12_MASK 0x1000U
#define PIOA_IER_P12 0x1000U
#define PIOA_IER_P12_BIT 12
#define PIOA_IER_P13_MASK 0x2000U
#define PIOA_IER_P13 0x2000U
#define PIOA_IER_P13_BIT 13
#define PIOA_IER_P14_MASK 0x4000U
#define PIOA_IER_P14 0x4000U
#define PIOA_IER_P14_BIT 14
#define PIOA_IER_P15_MASK 0x8000U
#define PIOA_IER_P15 0x8000U
#define PIOA_IER_P15_BIT 15
#define PIOA_IER_P16_MASK 0x10000U
#define PIOA_IER_P16 0x10000U
#define PIOA_IER_P16_BIT 16
#define PIOA_IER_P17_MASK 0x20000U
#define PIOA_IER_P17 0x20000U
#define PIOA_IER_P17_BIT 17
#define PIOA_IER_P18_MASK 0x40000U
#define PIOA_IER_P18 0x40000U
#define PIOA_IER_P18_BIT 18
#define PIOA_IER_P19_MASK 0x80000U
#define PIOA_IER_P19 0x80000U
#define PIOA_IER_P19_BIT 19
#define PIOA_IER_P20_MASK 0x100000U
#define PIOA_IER_P20 0x100000U
#define PIOA_IER_P20_BIT 20
#define PIOA_IER_P21_MASK 0x200000U
#define PIOA_IER_P21 0x200000U
#define PIOA_IER_P21_BIT 21
#define PIOA_IER_P22_MASK 0x400000U
#define PIOA_IER_P22 0x400000U
#define PIOA_IER_P22_BIT 22
#define PIOA_IER_P23_MASK 0x800000U
#define PIOA_IER_P23 0x800000U
#define PIOA_IER_P23_BIT 23
#define PIOA_IER_P24_MASK 0x1000000U
#define PIOA_IER_P24 0x1000000U
#define PIOA_IER_P24_BIT 24
#define PIOA_IER_P25_MASK 0x2000000U
#define PIOA_IER_P25 0x2000000U
#define PIOA_IER_P25_BIT 25
#define PIOA_IER_P26_MASK 0x4000000U
#define PIOA_IER_P26 0x4000000U
#define PIOA_IER_P26_BIT 26
#define PIOA_IER_P27_MASK 0x8000000U
#define PIOA_IER_P27 0x8000000U
#define PIOA_IER_P27_BIT 27
#define PIOA_IER_P28_MASK 0x10000000U
#define PIOA_IER_P28 0x10000000U
#define PIOA_IER_P28_BIT 28
#define PIOA_IER_P29_MASK 0x20000000U
#define PIOA_IER_P29 0x20000000U
#define PIOA_IER_P29_BIT 29
#define PIOA_IER_P30_MASK 0x40000000U
#define PIOA_IER_P30 0x40000000U
#define PIOA_IER_P30_BIT 30
#define PIOA_IER_P31_MASK 0x80000000U
#define PIOA_IER_P31 0x80000000U
#define PIOA_IER_P31_BIT 31

#define PIOA_IDR (*(volatile unsigned long *)0xFFFFF444)
#define PIOA_IDR_OFFSET 0x44
#define PIOA_IDR_P0_MASK 0x1U
#define PIOA_IDR_P0 0x1U
#define PIOA_IDR_P0_BIT 0
#define PIOA_IDR_P1_MASK 0x2U
#define PIOA_IDR_P1 0x2U
#define PIOA_IDR_P1_BIT 1
#define PIOA_IDR_P2_MASK 0x4U
#define PIOA_IDR_P2 0x4U
#define PIOA_IDR_P2_BIT 2
#define PIOA_IDR_P3_MASK 0x8U
#define PIOA_IDR_P3 0x8U
#define PIOA_IDR_P3_BIT 3
#define PIOA_IDR_P4_MASK 0x10U
#define PIOA_IDR_P4 0x10U
#define PIOA_IDR_P4_BIT 4
#define PIOA_IDR_P5_MASK 0x20U
#define PIOA_IDR_P5 0x20U
#define PIOA_IDR_P5_BIT 5
#define PIOA_IDR_P6_MASK 0x40U
#define PIOA_IDR_P6 0x40U
#define PIOA_IDR_P6_BIT 6
#define PIOA_IDR_P7_MASK 0x80U
#define PIOA_IDR_P7 0x80U
#define PIOA_IDR_P7_BIT 7
#define PIOA_IDR_P8_MASK 0x100U
#define PIOA_IDR_P8 0x100U
#define PIOA_IDR_P8_BIT 8
#define PIOA_IDR_P9_MASK 0x200U
#define PIOA_IDR_P9 0x200U
#define PIOA_IDR_P9_BIT 9
#define PIOA_IDR_P10_MASK 0x400U
#define PIOA_IDR_P10 0x400U
#define PIOA_IDR_P10_BIT 10
#define PIOA_IDR_P11_MASK 0x800U
#define PIOA_IDR_P11 0x800U
#define PIOA_IDR_P11_BIT 11
#define PIOA_IDR_P12_MASK 0x1000U
#define PIOA_IDR_P12 0x1000U
#define PIOA_IDR_P12_BIT 12
#define PIOA_IDR_P13_MASK 0x2000U
#define PIOA_IDR_P13 0x2000U
#define PIOA_IDR_P13_BIT 13
#define PIOA_IDR_P14_MASK 0x4000U
#define PIOA_IDR_P14 0x4000U
#define PIOA_IDR_P14_BIT 14
#define PIOA_IDR_P15_MASK 0x8000U
#define PIOA_IDR_P15 0x8000U
#define PIOA_IDR_P15_BIT 15
#define PIOA_IDR_P16_MASK 0x10000U
#define PIOA_IDR_P16 0x10000U
#define PIOA_IDR_P16_BIT 16
#define PIOA_IDR_P17_MASK 0x20000U
#define PIOA_IDR_P17 0x20000U
#define PIOA_IDR_P17_BIT 17
#define PIOA_IDR_P18_MASK 0x40000U
#define PIOA_IDR_P18 0x40000U
#define PIOA_IDR_P18_BIT 18
#define PIOA_IDR_P19_MASK 0x80000U
#define PIOA_IDR_P19 0x80000U
#define PIOA_IDR_P19_BIT 19
#define PIOA_IDR_P20_MASK 0x100000U
#define PIOA_IDR_P20 0x100000U
#define PIOA_IDR_P20_BIT 20
#define PIOA_IDR_P21_MASK 0x200000U
#define PIOA_IDR_P21 0x200000U
#define PIOA_IDR_P21_BIT 21
#define PIOA_IDR_P22_MASK 0x400000U
#define PIOA_IDR_P22 0x400000U
#define PIOA_IDR_P22_BIT 22
#define PIOA_IDR_P23_MASK 0x800000U
#define PIOA_IDR_P23 0x800000U
#define PIOA_IDR_P23_BIT 23
#define PIOA_IDR_P24_MASK 0x1000000U
#define PIOA_IDR_P24 0x1000000U
#define PIOA_IDR_P24_BIT 24
#define PIOA_IDR_P25_MASK 0x2000000U
#define PIOA_IDR_P25 0x2000000U
#define PIOA_IDR_P25_BIT 25
#define PIOA_IDR_P26_MASK 0x4000000U
#define PIOA_IDR_P26 0x4000000U
#define PIOA_IDR_P26_BIT 26
#define PIOA_IDR_P27_MASK 0x8000000U
#define PIOA_IDR_P27 0x8000000U
#define PIOA_IDR_P27_BIT 27
#define PIOA_IDR_P28_MASK 0x10000000U
#define PIOA_IDR_P28 0x10000000U
#define PIOA_IDR_P28_BIT 28
#define PIOA_IDR_P29_MASK 0x20000000U
#define PIOA_IDR_P29 0x20000000U
#define PIOA_IDR_P29_BIT 29
#define PIOA_IDR_P30_MASK 0x40000000U
#define PIOA_IDR_P30 0x40000000U
#define PIOA_IDR_P30_BIT 30
#define PIOA_IDR_P31_MASK 0x80000000U
#define PIOA_IDR_P31 0x80000000U
#define PIOA_IDR_P31_BIT 31

#define PIOA_IMR (*(volatile unsigned long *)0xFFFFF448)
#define PIOA_IMR_OFFSET 0x48
#define PIOA_IMR_P0_MASK 0x1U
#define PIOA_IMR_P0 0x1U
#define PIOA_IMR_P0_BIT 0
#define PIOA_IMR_P1_MASK 0x2U
#define PIOA_IMR_P1 0x2U
#define PIOA_IMR_P1_BIT 1
#define PIOA_IMR_P2_MASK 0x4U
#define PIOA_IMR_P2 0x4U
#define PIOA_IMR_P2_BIT 2
#define PIOA_IMR_P3_MASK 0x8U
#define PIOA_IMR_P3 0x8U
#define PIOA_IMR_P3_BIT 3
#define PIOA_IMR_P4_MASK 0x10U
#define PIOA_IMR_P4 0x10U
#define PIOA_IMR_P4_BIT 4
#define PIOA_IMR_P5_MASK 0x20U
#define PIOA_IMR_P5 0x20U
#define PIOA_IMR_P5_BIT 5
#define PIOA_IMR_P6_MASK 0x40U
#define PIOA_IMR_P6 0x40U
#define PIOA_IMR_P6_BIT 6
#define PIOA_IMR_P7_MASK 0x80U
#define PIOA_IMR_P7 0x80U
#define PIOA_IMR_P7_BIT 7
#define PIOA_IMR_P8_MASK 0x100U
#define PIOA_IMR_P8 0x100U
#define PIOA_IMR_P8_BIT 8
#define PIOA_IMR_P9_MASK 0x200U
#define PIOA_IMR_P9 0x200U
#define PIOA_IMR_P9_BIT 9
#define PIOA_IMR_P10_MASK 0x400U
#define PIOA_IMR_P10 0x400U
#define PIOA_IMR_P10_BIT 10
#define PIOA_IMR_P11_MASK 0x800U
#define PIOA_IMR_P11 0x800U
#define PIOA_IMR_P11_BIT 11
#define PIOA_IMR_P12_MASK 0x1000U
#define PIOA_IMR_P12 0x1000U
#define PIOA_IMR_P12_BIT 12
#define PIOA_IMR_P13_MASK 0x2000U
#define PIOA_IMR_P13 0x2000U
#define PIOA_IMR_P13_BIT 13
#define PIOA_IMR_P14_MASK 0x4000U
#define PIOA_IMR_P14 0x4000U
#define PIOA_IMR_P14_BIT 14
#define PIOA_IMR_P15_MASK 0x8000U
#define PIOA_IMR_P15 0x8000U
#define PIOA_IMR_P15_BIT 15
#define PIOA_IMR_P16_MASK 0x10000U
#define PIOA_IMR_P16 0x10000U
#define PIOA_IMR_P16_BIT 16
#define PIOA_IMR_P17_MASK 0x20000U
#define PIOA_IMR_P17 0x20000U
#define PIOA_IMR_P17_BIT 17
#define PIOA_IMR_P18_MASK 0x40000U
#define PIOA_IMR_P18 0x40000U
#define PIOA_IMR_P18_BIT 18
#define PIOA_IMR_P19_MASK 0x80000U
#define PIOA_IMR_P19 0x80000U
#define PIOA_IMR_P19_BIT 19
#define PIOA_IMR_P20_MASK 0x100000U
#define PIOA_IMR_P20 0x100000U
#define PIOA_IMR_P20_BIT 20
#define PIOA_IMR_P21_MASK 0x200000U
#define PIOA_IMR_P21 0x200000U
#define PIOA_IMR_P21_BIT 21
#define PIOA_IMR_P22_MASK 0x400000U
#define PIOA_IMR_P22 0x400000U
#define PIOA_IMR_P22_BIT 22
#define PIOA_IMR_P23_MASK 0x800000U
#define PIOA_IMR_P23 0x800000U
#define PIOA_IMR_P23_BIT 23
#define PIOA_IMR_P24_MASK 0x1000000U
#define PIOA_IMR_P24 0x1000000U
#define PIOA_IMR_P24_BIT 24
#define PIOA_IMR_P25_MASK 0x2000000U
#define PIOA_IMR_P25 0x2000000U
#define PIOA_IMR_P25_BIT 25
#define PIOA_IMR_P26_MASK 0x4000000U
#define PIOA_IMR_P26 0x4000000U
#define PIOA_IMR_P26_BIT 26
#define PIOA_IMR_P27_MASK 0x8000000U
#define PIOA_IMR_P27 0x8000000U
#define PIOA_IMR_P27_BIT 27
#define PIOA_IMR_P28_MASK 0x10000000U
#define PIOA_IMR_P28 0x10000000U
#define PIOA_IMR_P28_BIT 28
#define PIOA_IMR_P29_MASK 0x20000000U
#define PIOA_IMR_P29 0x20000000U
#define PIOA_IMR_P29_BIT 29
#define PIOA_IMR_P30_MASK 0x40000000U
#define PIOA_IMR_P30 0x40000000U
#define PIOA_IMR_P30_BIT 30
#define PIOA_IMR_P31_MASK 0x80000000U
#define PIOA_IMR_P31 0x80000000U
#define PIOA_IMR_P31_BIT 31

#define PIOA_ISR (*(volatile unsigned long *)0xFFFFF44C)
#define PIOA_ISR_OFFSET 0x4C
#define PIOA_ISR_P0_MASK 0x1U
#define PIOA_ISR_P0 0x1U
#define PIOA_ISR_P0_BIT 0
#define PIOA_ISR_P1_MASK 0x2U
#define PIOA_ISR_P1 0x2U
#define PIOA_ISR_P1_BIT 1
#define PIOA_ISR_P2_MASK 0x4U
#define PIOA_ISR_P2 0x4U
#define PIOA_ISR_P2_BIT 2
#define PIOA_ISR_P3_MASK 0x8U
#define PIOA_ISR_P3 0x8U
#define PIOA_ISR_P3_BIT 3
#define PIOA_ISR_P4_MASK 0x10U
#define PIOA_ISR_P4 0x10U
#define PIOA_ISR_P4_BIT 4
#define PIOA_ISR_P5_MASK 0x20U
#define PIOA_ISR_P5 0x20U
#define PIOA_ISR_P5_BIT 5
#define PIOA_ISR_P6_MASK 0x40U
#define PIOA_ISR_P6 0x40U
#define PIOA_ISR_P6_BIT 6
#define PIOA_ISR_P7_MASK 0x80U
#define PIOA_ISR_P7 0x80U
#define PIOA_ISR_P7_BIT 7
#define PIOA_ISR_P8_MASK 0x100U
#define PIOA_ISR_P8 0x100U
#define PIOA_ISR_P8_BIT 8
#define PIOA_ISR_P9_MASK 0x200U
#define PIOA_ISR_P9 0x200U
#define PIOA_ISR_P9_BIT 9
#define PIOA_ISR_P10_MASK 0x400U
#define PIOA_ISR_P10 0x400U
#define PIOA_ISR_P10_BIT 10
#define PIOA_ISR_P11_MASK 0x800U
#define PIOA_ISR_P11 0x800U
#define PIOA_ISR_P11_BIT 11
#define PIOA_ISR_P12_MASK 0x1000U
#define PIOA_ISR_P12 0x1000U
#define PIOA_ISR_P12_BIT 12
#define PIOA_ISR_P13_MASK 0x2000U
#define PIOA_ISR_P13 0x2000U
#define PIOA_ISR_P13_BIT 13
#define PIOA_ISR_P14_MASK 0x4000U
#define PIOA_ISR_P14 0x4000U
#define PIOA_ISR_P14_BIT 14
#define PIOA_ISR_P15_MASK 0x8000U
#define PIOA_ISR_P15 0x8000U
#define PIOA_ISR_P15_BIT 15
#define PIOA_ISR_P16_MASK 0x10000U
#define PIOA_ISR_P16 0x10000U
#define PIOA_ISR_P16_BIT 16
#define PIOA_ISR_P17_MASK 0x20000U
#define PIOA_ISR_P17 0x20000U
#define PIOA_ISR_P17_BIT 17
#define PIOA_ISR_P18_MASK 0x40000U
#define PIOA_ISR_P18 0x40000U
#define PIOA_ISR_P18_BIT 18
#define PIOA_ISR_P19_MASK 0x80000U
#define PIOA_ISR_P19 0x80000U
#define PIOA_ISR_P19_BIT 19
#define PIOA_ISR_P20_MASK 0x100000U
#define PIOA_ISR_P20 0x100000U
#define PIOA_ISR_P20_BIT 20
#define PIOA_ISR_P21_MASK 0x200000U
#define PIOA_ISR_P21 0x200000U
#define PIOA_ISR_P21_BIT 21
#define PIOA_ISR_P22_MASK 0x400000U
#define PIOA_ISR_P22 0x400000U
#define PIOA_ISR_P22_BIT 22
#define PIOA_ISR_P23_MASK 0x800000U
#define PIOA_ISR_P23 0x800000U
#define PIOA_ISR_P23_BIT 23
#define PIOA_ISR_P24_MASK 0x1000000U
#define PIOA_ISR_P24 0x1000000U
#define PIOA_ISR_P24_BIT 24
#define PIOA_ISR_P25_MASK 0x2000000U
#define PIOA_ISR_P25 0x2000000U
#define PIOA_ISR_P25_BIT 25
#define PIOA_ISR_P26_MASK 0x4000000U
#define PIOA_ISR_P26 0x4000000U
#define PIOA_ISR_P26_BIT 26
#define PIOA_ISR_P27_MASK 0x8000000U
#define PIOA_ISR_P27 0x8000000U
#define PIOA_ISR_P27_BIT 27
#define PIOA_ISR_P28_MASK 0x10000000U
#define PIOA_ISR_P28 0x10000000U
#define PIOA_ISR_P28_BIT 28
#define PIOA_ISR_P29_MASK 0x20000000U
#define PIOA_ISR_P29 0x20000000U
#define PIOA_ISR_P29_BIT 29
#define PIOA_ISR_P30_MASK 0x40000000U
#define PIOA_ISR_P30 0x40000000U
#define PIOA_ISR_P30_BIT 30
#define PIOA_ISR_P31_MASK 0x80000000U
#define PIOA_ISR_P31 0x80000000U
#define PIOA_ISR_P31_BIT 31

#define PIOA_MDER (*(volatile unsigned long *)0xFFFFF450)
#define PIOA_MDER_OFFSET 0x50
#define PIOA_MDER_P0_MASK 0x1U
#define PIOA_MDER_P0 0x1U
#define PIOA_MDER_P0_BIT 0
#define PIOA_MDER_P1_MASK 0x2U
#define PIOA_MDER_P1 0x2U
#define PIOA_MDER_P1_BIT 1
#define PIOA_MDER_P2_MASK 0x4U
#define PIOA_MDER_P2 0x4U
#define PIOA_MDER_P2_BIT 2
#define PIOA_MDER_P3_MASK 0x8U
#define PIOA_MDER_P3 0x8U
#define PIOA_MDER_P3_BIT 3
#define PIOA_MDER_P4_MASK 0x10U
#define PIOA_MDER_P4 0x10U
#define PIOA_MDER_P4_BIT 4
#define PIOA_MDER_P5_MASK 0x20U
#define PIOA_MDER_P5 0x20U
#define PIOA_MDER_P5_BIT 5
#define PIOA_MDER_P6_MASK 0x40U
#define PIOA_MDER_P6 0x40U
#define PIOA_MDER_P6_BIT 6
#define PIOA_MDER_P7_MASK 0x80U
#define PIOA_MDER_P7 0x80U
#define PIOA_MDER_P7_BIT 7
#define PIOA_MDER_P8_MASK 0x100U
#define PIOA_MDER_P8 0x100U
#define PIOA_MDER_P8_BIT 8
#define PIOA_MDER_P9_MASK 0x200U
#define PIOA_MDER_P9 0x200U
#define PIOA_MDER_P9_BIT 9
#define PIOA_MDER_P10_MASK 0x400U
#define PIOA_MDER_P10 0x400U
#define PIOA_MDER_P10_BIT 10
#define PIOA_MDER_P11_MASK 0x800U
#define PIOA_MDER_P11 0x800U
#define PIOA_MDER_P11_BIT 11
#define PIOA_MDER_P12_MASK 0x1000U
#define PIOA_MDER_P12 0x1000U
#define PIOA_MDER_P12_BIT 12
#define PIOA_MDER_P13_MASK 0x2000U
#define PIOA_MDER_P13 0x2000U
#define PIOA_MDER_P13_BIT 13
#define PIOA_MDER_P14_MASK 0x4000U
#define PIOA_MDER_P14 0x4000U
#define PIOA_MDER_P14_BIT 14
#define PIOA_MDER_P15_MASK 0x8000U
#define PIOA_MDER_P15 0x8000U
#define PIOA_MDER_P15_BIT 15
#define PIOA_MDER_P16_MASK 0x10000U
#define PIOA_MDER_P16 0x10000U
#define PIOA_MDER_P16_BIT 16
#define PIOA_MDER_P17_MASK 0x20000U
#define PIOA_MDER_P17 0x20000U
#define PIOA_MDER_P17_BIT 17
#define PIOA_MDER_P18_MASK 0x40000U
#define PIOA_MDER_P18 0x40000U
#define PIOA_MDER_P18_BIT 18
#define PIOA_MDER_P19_MASK 0x80000U
#define PIOA_MDER_P19 0x80000U
#define PIOA_MDER_P19_BIT 19
#define PIOA_MDER_P20_MASK 0x100000U
#define PIOA_MDER_P20 0x100000U
#define PIOA_MDER_P20_BIT 20
#define PIOA_MDER_P21_MASK 0x200000U
#define PIOA_MDER_P21 0x200000U
#define PIOA_MDER_P21_BIT 21
#define PIOA_MDER_P22_MASK 0x400000U
#define PIOA_MDER_P22 0x400000U
#define PIOA_MDER_P22_BIT 22
#define PIOA_MDER_P23_MASK 0x800000U
#define PIOA_MDER_P23 0x800000U
#define PIOA_MDER_P23_BIT 23
#define PIOA_MDER_P24_MASK 0x1000000U
#define PIOA_MDER_P24 0x1000000U
#define PIOA_MDER_P24_BIT 24
#define PIOA_MDER_P25_MASK 0x2000000U
#define PIOA_MDER_P25 0x2000000U
#define PIOA_MDER_P25_BIT 25
#define PIOA_MDER_P26_MASK 0x4000000U
#define PIOA_MDER_P26 0x4000000U
#define PIOA_MDER_P26_BIT 26
#define PIOA_MDER_P27_MASK 0x8000000U
#define PIOA_MDER_P27 0x8000000U
#define PIOA_MDER_P27_BIT 27
#define PIOA_MDER_P28_MASK 0x10000000U
#define PIOA_MDER_P28 0x10000000U
#define PIOA_MDER_P28_BIT 28
#define PIOA_MDER_P29_MASK 0x20000000U
#define PIOA_MDER_P29 0x20000000U
#define PIOA_MDER_P29_BIT 29
#define PIOA_MDER_P30_MASK 0x40000000U
#define PIOA_MDER_P30 0x40000000U
#define PIOA_MDER_P30_BIT 30
#define PIOA_MDER_P31_MASK 0x80000000U
#define PIOA_MDER_P31 0x80000000U
#define PIOA_MDER_P31_BIT 31

#define PIOA_MDDR (*(volatile unsigned long *)0xFFFFF454)
#define PIOA_MDDR_OFFSET 0x54
#define PIOA_MDDR_P0_MASK 0x1U
#define PIOA_MDDR_P0 0x1U
#define PIOA_MDDR_P0_BIT 0
#define PIOA_MDDR_P1_MASK 0x2U
#define PIOA_MDDR_P1 0x2U
#define PIOA_MDDR_P1_BIT 1
#define PIOA_MDDR_P2_MASK 0x4U
#define PIOA_MDDR_P2 0x4U
#define PIOA_MDDR_P2_BIT 2
#define PIOA_MDDR_P3_MASK 0x8U
#define PIOA_MDDR_P3 0x8U
#define PIOA_MDDR_P3_BIT 3
#define PIOA_MDDR_P4_MASK 0x10U
#define PIOA_MDDR_P4 0x10U
#define PIOA_MDDR_P4_BIT 4
#define PIOA_MDDR_P5_MASK 0x20U
#define PIOA_MDDR_P5 0x20U
#define PIOA_MDDR_P5_BIT 5
#define PIOA_MDDR_P6_MASK 0x40U
#define PIOA_MDDR_P6 0x40U
#define PIOA_MDDR_P6_BIT 6
#define PIOA_MDDR_P7_MASK 0x80U
#define PIOA_MDDR_P7 0x80U
#define PIOA_MDDR_P7_BIT 7
#define PIOA_MDDR_P8_MASK 0x100U
#define PIOA_MDDR_P8 0x100U
#define PIOA_MDDR_P8_BIT 8
#define PIOA_MDDR_P9_MASK 0x200U
#define PIOA_MDDR_P9 0x200U
#define PIOA_MDDR_P9_BIT 9
#define PIOA_MDDR_P10_MASK 0x400U
#define PIOA_MDDR_P10 0x400U
#define PIOA_MDDR_P10_BIT 10
#define PIOA_MDDR_P11_MASK 0x800U
#define PIOA_MDDR_P11 0x800U
#define PIOA_MDDR_P11_BIT 11
#define PIOA_MDDR_P12_MASK 0x1000U
#define PIOA_MDDR_P12 0x1000U
#define PIOA_MDDR_P12_BIT 12
#define PIOA_MDDR_P13_MASK 0x2000U
#define PIOA_MDDR_P13 0x2000U
#define PIOA_MDDR_P13_BIT 13
#define PIOA_MDDR_P14_MASK 0x4000U
#define PIOA_MDDR_P14 0x4000U
#define PIOA_MDDR_P14_BIT 14
#define PIOA_MDDR_P15_MASK 0x8000U
#define PIOA_MDDR_P15 0x8000U
#define PIOA_MDDR_P15_BIT 15
#define PIOA_MDDR_P16_MASK 0x10000U
#define PIOA_MDDR_P16 0x10000U
#define PIOA_MDDR_P16_BIT 16
#define PIOA_MDDR_P17_MASK 0x20000U
#define PIOA_MDDR_P17 0x20000U
#define PIOA_MDDR_P17_BIT 17
#define PIOA_MDDR_P18_MASK 0x40000U
#define PIOA_MDDR_P18 0x40000U
#define PIOA_MDDR_P18_BIT 18
#define PIOA_MDDR_P19_MASK 0x80000U
#define PIOA_MDDR_P19 0x80000U
#define PIOA_MDDR_P19_BIT 19
#define PIOA_MDDR_P20_MASK 0x100000U
#define PIOA_MDDR_P20 0x100000U
#define PIOA_MDDR_P20_BIT 20
#define PIOA_MDDR_P21_MASK 0x200000U
#define PIOA_MDDR_P21 0x200000U
#define PIOA_MDDR_P21_BIT 21
#define PIOA_MDDR_P22_MASK 0x400000U
#define PIOA_MDDR_P22 0x400000U
#define PIOA_MDDR_P22_BIT 22
#define PIOA_MDDR_P23_MASK 0x800000U
#define PIOA_MDDR_P23 0x800000U
#define PIOA_MDDR_P23_BIT 23
#define PIOA_MDDR_P24_MASK 0x1000000U
#define PIOA_MDDR_P24 0x1000000U
#define PIOA_MDDR_P24_BIT 24
#define PIOA_MDDR_P25_MASK 0x2000000U
#define PIOA_MDDR_P25 0x2000000U
#define PIOA_MDDR_P25_BIT 25
#define PIOA_MDDR_P26_MASK 0x4000000U
#define PIOA_MDDR_P26 0x4000000U
#define PIOA_MDDR_P26_BIT 26
#define PIOA_MDDR_P27_MASK 0x8000000U
#define PIOA_MDDR_P27 0x8000000U
#define PIOA_MDDR_P27_BIT 27
#define PIOA_MDDR_P28_MASK 0x10000000U
#define PIOA_MDDR_P28 0x10000000U
#define PIOA_MDDR_P28_BIT 28
#define PIOA_MDDR_P29_MASK 0x20000000U
#define PIOA_MDDR_P29 0x20000000U
#define PIOA_MDDR_P29_BIT 29
#define PIOA_MDDR_P30_MASK 0x40000000U
#define PIOA_MDDR_P30 0x40000000U
#define PIOA_MDDR_P30_BIT 30
#define PIOA_MDDR_P31_MASK 0x80000000U
#define PIOA_MDDR_P31 0x80000000U
#define PIOA_MDDR_P31_BIT 31

#define PIOA_MDSR (*(volatile unsigned long *)0xFFFFF458)
#define PIOA_MDSR_OFFSET 0x58
#define PIOA_MDSR_P0_MASK 0x1U
#define PIOA_MDSR_P0 0x1U
#define PIOA_MDSR_P0_BIT 0
#define PIOA_MDSR_P1_MASK 0x2U
#define PIOA_MDSR_P1 0x2U
#define PIOA_MDSR_P1_BIT 1
#define PIOA_MDSR_P2_MASK 0x4U
#define PIOA_MDSR_P2 0x4U
#define PIOA_MDSR_P2_BIT 2
#define PIOA_MDSR_P3_MASK 0x8U
#define PIOA_MDSR_P3 0x8U
#define PIOA_MDSR_P3_BIT 3
#define PIOA_MDSR_P4_MASK 0x10U
#define PIOA_MDSR_P4 0x10U
#define PIOA_MDSR_P4_BIT 4
#define PIOA_MDSR_P5_MASK 0x20U
#define PIOA_MDSR_P5 0x20U
#define PIOA_MDSR_P5_BIT 5
#define PIOA_MDSR_P6_MASK 0x40U
#define PIOA_MDSR_P6 0x40U
#define PIOA_MDSR_P6_BIT 6
#define PIOA_MDSR_P7_MASK 0x80U
#define PIOA_MDSR_P7 0x80U
#define PIOA_MDSR_P7_BIT 7
#define PIOA_MDSR_P8_MASK 0x100U
#define PIOA_MDSR_P8 0x100U
#define PIOA_MDSR_P8_BIT 8
#define PIOA_MDSR_P9_MASK 0x200U
#define PIOA_MDSR_P9 0x200U
#define PIOA_MDSR_P9_BIT 9
#define PIOA_MDSR_P10_MASK 0x400U
#define PIOA_MDSR_P10 0x400U
#define PIOA_MDSR_P10_BIT 10
#define PIOA_MDSR_P11_MASK 0x800U
#define PIOA_MDSR_P11 0x800U
#define PIOA_MDSR_P11_BIT 11
#define PIOA_MDSR_P12_MASK 0x1000U
#define PIOA_MDSR_P12 0x1000U
#define PIOA_MDSR_P12_BIT 12
#define PIOA_MDSR_P13_MASK 0x2000U
#define PIOA_MDSR_P13 0x2000U
#define PIOA_MDSR_P13_BIT 13
#define PIOA_MDSR_P14_MASK 0x4000U
#define PIOA_MDSR_P14 0x4000U
#define PIOA_MDSR_P14_BIT 14
#define PIOA_MDSR_P15_MASK 0x8000U
#define PIOA_MDSR_P15 0x8000U
#define PIOA_MDSR_P15_BIT 15
#define PIOA_MDSR_P16_MASK 0x10000U
#define PIOA_MDSR_P16 0x10000U
#define PIOA_MDSR_P16_BIT 16
#define PIOA_MDSR_P17_MASK 0x20000U
#define PIOA_MDSR_P17 0x20000U
#define PIOA_MDSR_P17_BIT 17
#define PIOA_MDSR_P18_MASK 0x40000U
#define PIOA_MDSR_P18 0x40000U
#define PIOA_MDSR_P18_BIT 18
#define PIOA_MDSR_P19_MASK 0x80000U
#define PIOA_MDSR_P19 0x80000U
#define PIOA_MDSR_P19_BIT 19
#define PIOA_MDSR_P20_MASK 0x100000U
#define PIOA_MDSR_P20 0x100000U
#define PIOA_MDSR_P20_BIT 20
#define PIOA_MDSR_P21_MASK 0x200000U
#define PIOA_MDSR_P21 0x200000U
#define PIOA_MDSR_P21_BIT 21
#define PIOA_MDSR_P22_MASK 0x400000U
#define PIOA_MDSR_P22 0x400000U
#define PIOA_MDSR_P22_BIT 22
#define PIOA_MDSR_P23_MASK 0x800000U
#define PIOA_MDSR_P23 0x800000U
#define PIOA_MDSR_P23_BIT 23
#define PIOA_MDSR_P24_MASK 0x1000000U
#define PIOA_MDSR_P24 0x1000000U
#define PIOA_MDSR_P24_BIT 24
#define PIOA_MDSR_P25_MASK 0x2000000U
#define PIOA_MDSR_P25 0x2000000U
#define PIOA_MDSR_P25_BIT 25
#define PIOA_MDSR_P26_MASK 0x4000000U
#define PIOA_MDSR_P26 0x4000000U
#define PIOA_MDSR_P26_BIT 26
#define PIOA_MDSR_P27_MASK 0x8000000U
#define PIOA_MDSR_P27 0x8000000U
#define PIOA_MDSR_P27_BIT 27
#define PIOA_MDSR_P28_MASK 0x10000000U
#define PIOA_MDSR_P28 0x10000000U
#define PIOA_MDSR_P28_BIT 28
#define PIOA_MDSR_P29_MASK 0x20000000U
#define PIOA_MDSR_P29 0x20000000U
#define PIOA_MDSR_P29_BIT 29
#define PIOA_MDSR_P30_MASK 0x40000000U
#define PIOA_MDSR_P30 0x40000000U
#define PIOA_MDSR_P30_BIT 30
#define PIOA_MDSR_P31_MASK 0x80000000U
#define PIOA_MDSR_P31 0x80000000U
#define PIOA_MDSR_P31_BIT 31

#define PIOA_PUDR (*(volatile unsigned long *)0xFFFFF460)
#define PIOA_PUDR_OFFSET 0x60
#define PIOA_PUDR_P0_MASK 0x1U
#define PIOA_PUDR_P0 0x1U
#define PIOA_PUDR_P0_BIT 0
#define PIOA_PUDR_P1_MASK 0x2U
#define PIOA_PUDR_P1 0x2U
#define PIOA_PUDR_P1_BIT 1
#define PIOA_PUDR_P2_MASK 0x4U
#define PIOA_PUDR_P2 0x4U
#define PIOA_PUDR_P2_BIT 2
#define PIOA_PUDR_P3_MASK 0x8U
#define PIOA_PUDR_P3 0x8U
#define PIOA_PUDR_P3_BIT 3
#define PIOA_PUDR_P4_MASK 0x10U
#define PIOA_PUDR_P4 0x10U
#define PIOA_PUDR_P4_BIT 4
#define PIOA_PUDR_P5_MASK 0x20U
#define PIOA_PUDR_P5 0x20U
#define PIOA_PUDR_P5_BIT 5
#define PIOA_PUDR_P6_MASK 0x40U
#define PIOA_PUDR_P6 0x40U
#define PIOA_PUDR_P6_BIT 6
#define PIOA_PUDR_P7_MASK 0x80U
#define PIOA_PUDR_P7 0x80U
#define PIOA_PUDR_P7_BIT 7
#define PIOA_PUDR_P8_MASK 0x100U
#define PIOA_PUDR_P8 0x100U
#define PIOA_PUDR_P8_BIT 8
#define PIOA_PUDR_P9_MASK 0x200U
#define PIOA_PUDR_P9 0x200U
#define PIOA_PUDR_P9_BIT 9
#define PIOA_PUDR_P10_MASK 0x400U
#define PIOA_PUDR_P10 0x400U
#define PIOA_PUDR_P10_BIT 10
#define PIOA_PUDR_P11_MASK 0x800U
#define PIOA_PUDR_P11 0x800U
#define PIOA_PUDR_P11_BIT 11
#define PIOA_PUDR_P12_MASK 0x1000U
#define PIOA_PUDR_P12 0x1000U
#define PIOA_PUDR_P12_BIT 12
#define PIOA_PUDR_P13_MASK 0x2000U
#define PIOA_PUDR_P13 0x2000U
#define PIOA_PUDR_P13_BIT 13
#define PIOA_PUDR_P14_MASK 0x4000U
#define PIOA_PUDR_P14 0x4000U
#define PIOA_PUDR_P14_BIT 14
#define PIOA_PUDR_P15_MASK 0x8000U
#define PIOA_PUDR_P15 0x8000U
#define PIOA_PUDR_P15_BIT 15
#define PIOA_PUDR_P16_MASK 0x10000U
#define PIOA_PUDR_P16 0x10000U
#define PIOA_PUDR_P16_BIT 16
#define PIOA_PUDR_P17_MASK 0x20000U
#define PIOA_PUDR_P17 0x20000U
#define PIOA_PUDR_P17_BIT 17
#define PIOA_PUDR_P18_MASK 0x40000U
#define PIOA_PUDR_P18 0x40000U
#define PIOA_PUDR_P18_BIT 18
#define PIOA_PUDR_P19_MASK 0x80000U
#define PIOA_PUDR_P19 0x80000U
#define PIOA_PUDR_P19_BIT 19
#define PIOA_PUDR_P20_MASK 0x100000U
#define PIOA_PUDR_P20 0x100000U
#define PIOA_PUDR_P20_BIT 20
#define PIOA_PUDR_P21_MASK 0x200000U
#define PIOA_PUDR_P21 0x200000U
#define PIOA_PUDR_P21_BIT 21
#define PIOA_PUDR_P22_MASK 0x400000U
#define PIOA_PUDR_P22 0x400000U
#define PIOA_PUDR_P22_BIT 22
#define PIOA_PUDR_P23_MASK 0x800000U
#define PIOA_PUDR_P23 0x800000U
#define PIOA_PUDR_P23_BIT 23
#define PIOA_PUDR_P24_MASK 0x1000000U
#define PIOA_PUDR_P24 0x1000000U
#define PIOA_PUDR_P24_BIT 24
#define PIOA_PUDR_P25_MASK 0x2000000U
#define PIOA_PUDR_P25 0x2000000U
#define PIOA_PUDR_P25_BIT 25
#define PIOA_PUDR_P26_MASK 0x4000000U
#define PIOA_PUDR_P26 0x4000000U
#define PIOA_PUDR_P26_BIT 26
#define PIOA_PUDR_P27_MASK 0x8000000U
#define PIOA_PUDR_P27 0x8000000U
#define PIOA_PUDR_P27_BIT 27
#define PIOA_PUDR_P28_MASK 0x10000000U
#define PIOA_PUDR_P28 0x10000000U
#define PIOA_PUDR_P28_BIT 28
#define PIOA_PUDR_P29_MASK 0x20000000U
#define PIOA_PUDR_P29 0x20000000U
#define PIOA_PUDR_P29_BIT 29
#define PIOA_PUDR_P30_MASK 0x40000000U
#define PIOA_PUDR_P30 0x40000000U
#define PIOA_PUDR_P30_BIT 30
#define PIOA_PUDR_P31_MASK 0x80000000U
#define PIOA_PUDR_P31 0x80000000U
#define PIOA_PUDR_P31_BIT 31

#define PIOA_PUER (*(volatile unsigned long *)0xFFFFF464)
#define PIOA_PUER_OFFSET 0x64
#define PIOA_PUER_P0_MASK 0x1U
#define PIOA_PUER_P0 0x1U
#define PIOA_PUER_P0_BIT 0
#define PIOA_PUER_P1_MASK 0x2U
#define PIOA_PUER_P1 0x2U
#define PIOA_PUER_P1_BIT 1
#define PIOA_PUER_P2_MASK 0x4U
#define PIOA_PUER_P2 0x4U
#define PIOA_PUER_P2_BIT 2
#define PIOA_PUER_P3_MASK 0x8U
#define PIOA_PUER_P3 0x8U
#define PIOA_PUER_P3_BIT 3
#define PIOA_PUER_P4_MASK 0x10U
#define PIOA_PUER_P4 0x10U
#define PIOA_PUER_P4_BIT 4
#define PIOA_PUER_P5_MASK 0x20U
#define PIOA_PUER_P5 0x20U
#define PIOA_PUER_P5_BIT 5
#define PIOA_PUER_P6_MASK 0x40U
#define PIOA_PUER_P6 0x40U
#define PIOA_PUER_P6_BIT 6
#define PIOA_PUER_P7_MASK 0x80U
#define PIOA_PUER_P7 0x80U
#define PIOA_PUER_P7_BIT 7
#define PIOA_PUER_P8_MASK 0x100U
#define PIOA_PUER_P8 0x100U
#define PIOA_PUER_P8_BIT 8
#define PIOA_PUER_P9_MASK 0x200U
#define PIOA_PUER_P9 0x200U
#define PIOA_PUER_P9_BIT 9
#define PIOA_PUER_P10_MASK 0x400U
#define PIOA_PUER_P10 0x400U
#define PIOA_PUER_P10_BIT 10
#define PIOA_PUER_P11_MASK 0x800U
#define PIOA_PUER_P11 0x800U
#define PIOA_PUER_P11_BIT 11
#define PIOA_PUER_P12_MASK 0x1000U
#define PIOA_PUER_P12 0x1000U
#define PIOA_PUER_P12_BIT 12
#define PIOA_PUER_P13_MASK 0x2000U
#define PIOA_PUER_P13 0x2000U
#define PIOA_PUER_P13_BIT 13
#define PIOA_PUER_P14_MASK 0x4000U
#define PIOA_PUER_P14 0x4000U
#define PIOA_PUER_P14_BIT 14
#define PIOA_PUER_P15_MASK 0x8000U
#define PIOA_PUER_P15 0x8000U
#define PIOA_PUER_P15_BIT 15
#define PIOA_PUER_P16_MASK 0x10000U
#define PIOA_PUER_P16 0x10000U
#define PIOA_PUER_P16_BIT 16
#define PIOA_PUER_P17_MASK 0x20000U
#define PIOA_PUER_P17 0x20000U
#define PIOA_PUER_P17_BIT 17
#define PIOA_PUER_P18_MASK 0x40000U
#define PIOA_PUER_P18 0x40000U
#define PIOA_PUER_P18_BIT 18
#define PIOA_PUER_P19_MASK 0x80000U
#define PIOA_PUER_P19 0x80000U
#define PIOA_PUER_P19_BIT 19
#define PIOA_PUER_P20_MASK 0x100000U
#define PIOA_PUER_P20 0x100000U
#define PIOA_PUER_P20_BIT 20
#define PIOA_PUER_P21_MASK 0x200000U
#define PIOA_PUER_P21 0x200000U
#define PIOA_PUER_P21_BIT 21
#define PIOA_PUER_P22_MASK 0x400000U
#define PIOA_PUER_P22 0x400000U
#define PIOA_PUER_P22_BIT 22
#define PIOA_PUER_P23_MASK 0x800000U
#define PIOA_PUER_P23 0x800000U
#define PIOA_PUER_P23_BIT 23
#define PIOA_PUER_P24_MASK 0x1000000U
#define PIOA_PUER_P24 0x1000000U
#define PIOA_PUER_P24_BIT 24
#define PIOA_PUER_P25_MASK 0x2000000U
#define PIOA_PUER_P25 0x2000000U
#define PIOA_PUER_P25_BIT 25
#define PIOA_PUER_P26_MASK 0x4000000U
#define PIOA_PUER_P26 0x4000000U
#define PIOA_PUER_P26_BIT 26
#define PIOA_PUER_P27_MASK 0x8000000U
#define PIOA_PUER_P27 0x8000000U
#define PIOA_PUER_P27_BIT 27
#define PIOA_PUER_P28_MASK 0x10000000U
#define PIOA_PUER_P28 0x10000000U
#define PIOA_PUER_P28_BIT 28
#define PIOA_PUER_P29_MASK 0x20000000U
#define PIOA_PUER_P29 0x20000000U
#define PIOA_PUER_P29_BIT 29
#define PIOA_PUER_P30_MASK 0x40000000U
#define PIOA_PUER_P30 0x40000000U
#define PIOA_PUER_P30_BIT 30
#define PIOA_PUER_P31_MASK 0x80000000U
#define PIOA_PUER_P31 0x80000000U
#define PIOA_PUER_P31_BIT 31

#define PIOA_PUSR (*(volatile unsigned long *)0xFFFFF468)
#define PIOA_PUSR_OFFSET 0x68
#define PIOA_PUSR_P0_MASK 0x1U
#define PIOA_PUSR_P0 0x1U
#define PIOA_PUSR_P0_BIT 0
#define PIOA_PUSR_P1_MASK 0x2U
#define PIOA_PUSR_P1 0x2U
#define PIOA_PUSR_P1_BIT 1
#define PIOA_PUSR_P2_MASK 0x4U
#define PIOA_PUSR_P2 0x4U
#define PIOA_PUSR_P2_BIT 2
#define PIOA_PUSR_P3_MASK 0x8U
#define PIOA_PUSR_P3 0x8U
#define PIOA_PUSR_P3_BIT 3
#define PIOA_PUSR_P4_MASK 0x10U
#define PIOA_PUSR_P4 0x10U
#define PIOA_PUSR_P4_BIT 4
#define PIOA_PUSR_P5_MASK 0x20U
#define PIOA_PUSR_P5 0x20U
#define PIOA_PUSR_P5_BIT 5
#define PIOA_PUSR_P6_MASK 0x40U
#define PIOA_PUSR_P6 0x40U
#define PIOA_PUSR_P6_BIT 6
#define PIOA_PUSR_P7_MASK 0x80U
#define PIOA_PUSR_P7 0x80U
#define PIOA_PUSR_P7_BIT 7
#define PIOA_PUSR_P8_MASK 0x100U
#define PIOA_PUSR_P8 0x100U
#define PIOA_PUSR_P8_BIT 8
#define PIOA_PUSR_P9_MASK 0x200U
#define PIOA_PUSR_P9 0x200U
#define PIOA_PUSR_P9_BIT 9
#define PIOA_PUSR_P10_MASK 0x400U
#define PIOA_PUSR_P10 0x400U
#define PIOA_PUSR_P10_BIT 10
#define PIOA_PUSR_P11_MASK 0x800U
#define PIOA_PUSR_P11 0x800U
#define PIOA_PUSR_P11_BIT 11
#define PIOA_PUSR_P12_MASK 0x1000U
#define PIOA_PUSR_P12 0x1000U
#define PIOA_PUSR_P12_BIT 12
#define PIOA_PUSR_P13_MASK 0x2000U
#define PIOA_PUSR_P13 0x2000U
#define PIOA_PUSR_P13_BIT 13
#define PIOA_PUSR_P14_MASK 0x4000U
#define PIOA_PUSR_P14 0x4000U
#define PIOA_PUSR_P14_BIT 14
#define PIOA_PUSR_P15_MASK 0x8000U
#define PIOA_PUSR_P15 0x8000U
#define PIOA_PUSR_P15_BIT 15
#define PIOA_PUSR_P16_MASK 0x10000U
#define PIOA_PUSR_P16 0x10000U
#define PIOA_PUSR_P16_BIT 16
#define PIOA_PUSR_P17_MASK 0x20000U
#define PIOA_PUSR_P17 0x20000U
#define PIOA_PUSR_P17_BIT 17
#define PIOA_PUSR_P18_MASK 0x40000U
#define PIOA_PUSR_P18 0x40000U
#define PIOA_PUSR_P18_BIT 18
#define PIOA_PUSR_P19_MASK 0x80000U
#define PIOA_PUSR_P19 0x80000U
#define PIOA_PUSR_P19_BIT 19
#define PIOA_PUSR_P20_MASK 0x100000U
#define PIOA_PUSR_P20 0x100000U
#define PIOA_PUSR_P20_BIT 20
#define PIOA_PUSR_P21_MASK 0x200000U
#define PIOA_PUSR_P21 0x200000U
#define PIOA_PUSR_P21_BIT 21
#define PIOA_PUSR_P22_MASK 0x400000U
#define PIOA_PUSR_P22 0x400000U
#define PIOA_PUSR_P22_BIT 22
#define PIOA_PUSR_P23_MASK 0x800000U
#define PIOA_PUSR_P23 0x800000U
#define PIOA_PUSR_P23_BIT 23
#define PIOA_PUSR_P24_MASK 0x1000000U
#define PIOA_PUSR_P24 0x1000000U
#define PIOA_PUSR_P24_BIT 24
#define PIOA_PUSR_P25_MASK 0x2000000U
#define PIOA_PUSR_P25 0x2000000U
#define PIOA_PUSR_P25_BIT 25
#define PIOA_PUSR_P26_MASK 0x4000000U
#define PIOA_PUSR_P26 0x4000000U
#define PIOA_PUSR_P26_BIT 26
#define PIOA_PUSR_P27_MASK 0x8000000U
#define PIOA_PUSR_P27 0x8000000U
#define PIOA_PUSR_P27_BIT 27
#define PIOA_PUSR_P28_MASK 0x10000000U
#define PIOA_PUSR_P28 0x10000000U
#define PIOA_PUSR_P28_BIT 28
#define PIOA_PUSR_P29_MASK 0x20000000U
#define PIOA_PUSR_P29 0x20000000U
#define PIOA_PUSR_P29_BIT 29
#define PIOA_PUSR_P30_MASK 0x40000000U
#define PIOA_PUSR_P30 0x40000000U
#define PIOA_PUSR_P30_BIT 30
#define PIOA_PUSR_P31_MASK 0x80000000U
#define PIOA_PUSR_P31 0x80000000U
#define PIOA_PUSR_P31_BIT 31

#define PIOA_ASR (*(volatile unsigned long *)0xFFFFF470)
#define PIOA_ASR_OFFSET 0x70
#define PIOA_ASR_P0_MASK 0x1U
#define PIOA_ASR_P0 0x1U
#define PIOA_ASR_P0_BIT 0
#define PIOA_ASR_P1_MASK 0x2U
#define PIOA_ASR_P1 0x2U
#define PIOA_ASR_P1_BIT 1
#define PIOA_ASR_P2_MASK 0x4U
#define PIOA_ASR_P2 0x4U
#define PIOA_ASR_P2_BIT 2
#define PIOA_ASR_P3_MASK 0x8U
#define PIOA_ASR_P3 0x8U
#define PIOA_ASR_P3_BIT 3
#define PIOA_ASR_P4_MASK 0x10U
#define PIOA_ASR_P4 0x10U
#define PIOA_ASR_P4_BIT 4
#define PIOA_ASR_P5_MASK 0x20U
#define PIOA_ASR_P5 0x20U
#define PIOA_ASR_P5_BIT 5
#define PIOA_ASR_P6_MASK 0x40U
#define PIOA_ASR_P6 0x40U
#define PIOA_ASR_P6_BIT 6
#define PIOA_ASR_P7_MASK 0x80U
#define PIOA_ASR_P7 0x80U
#define PIOA_ASR_P7_BIT 7
#define PIOA_ASR_P8_MASK 0x100U
#define PIOA_ASR_P8 0x100U
#define PIOA_ASR_P8_BIT 8
#define PIOA_ASR_P9_MASK 0x200U
#define PIOA_ASR_P9 0x200U
#define PIOA_ASR_P9_BIT 9
#define PIOA_ASR_P10_MASK 0x400U
#define PIOA_ASR_P10 0x400U
#define PIOA_ASR_P10_BIT 10
#define PIOA_ASR_P11_MASK 0x800U
#define PIOA_ASR_P11 0x800U
#define PIOA_ASR_P11_BIT 11
#define PIOA_ASR_P12_MASK 0x1000U
#define PIOA_ASR_P12 0x1000U
#define PIOA_ASR_P12_BIT 12
#define PIOA_ASR_P13_MASK 0x2000U
#define PIOA_ASR_P13 0x2000U
#define PIOA_ASR_P13_BIT 13
#define PIOA_ASR_P14_MASK 0x4000U
#define PIOA_ASR_P14 0x4000U
#define PIOA_ASR_P14_BIT 14
#define PIOA_ASR_P15_MASK 0x8000U
#define PIOA_ASR_P15 0x8000U
#define PIOA_ASR_P15_BIT 15
#define PIOA_ASR_P16_MASK 0x10000U
#define PIOA_ASR_P16 0x10000U
#define PIOA_ASR_P16_BIT 16
#define PIOA_ASR_P17_MASK 0x20000U
#define PIOA_ASR_P17 0x20000U
#define PIOA_ASR_P17_BIT 17
#define PIOA_ASR_P18_MASK 0x40000U
#define PIOA_ASR_P18 0x40000U
#define PIOA_ASR_P18_BIT 18
#define PIOA_ASR_P19_MASK 0x80000U
#define PIOA_ASR_P19 0x80000U
#define PIOA_ASR_P19_BIT 19
#define PIOA_ASR_P20_MASK 0x100000U
#define PIOA_ASR_P20 0x100000U
#define PIOA_ASR_P20_BIT 20
#define PIOA_ASR_P21_MASK 0x200000U
#define PIOA_ASR_P21 0x200000U
#define PIOA_ASR_P21_BIT 21
#define PIOA_ASR_P22_MASK 0x400000U
#define PIOA_ASR_P22 0x400000U
#define PIOA_ASR_P22_BIT 22
#define PIOA_ASR_P23_MASK 0x800000U
#define PIOA_ASR_P23 0x800000U
#define PIOA_ASR_P23_BIT 23
#define PIOA_ASR_P24_MASK 0x1000000U
#define PIOA_ASR_P24 0x1000000U
#define PIOA_ASR_P24_BIT 24
#define PIOA_ASR_P25_MASK 0x2000000U
#define PIOA_ASR_P25 0x2000000U
#define PIOA_ASR_P25_BIT 25
#define PIOA_ASR_P26_MASK 0x4000000U
#define PIOA_ASR_P26 0x4000000U
#define PIOA_ASR_P26_BIT 26
#define PIOA_ASR_P27_MASK 0x8000000U
#define PIOA_ASR_P27 0x8000000U
#define PIOA_ASR_P27_BIT 27
#define PIOA_ASR_P28_MASK 0x10000000U
#define PIOA_ASR_P28 0x10000000U
#define PIOA_ASR_P28_BIT 28
#define PIOA_ASR_P29_MASK 0x20000000U
#define PIOA_ASR_P29 0x20000000U
#define PIOA_ASR_P29_BIT 29
#define PIOA_ASR_P30_MASK 0x40000000U
#define PIOA_ASR_P30 0x40000000U
#define PIOA_ASR_P30_BIT 30
#define PIOA_ASR_P31_MASK 0x80000000U
#define PIOA_ASR_P31 0x80000000U
#define PIOA_ASR_P31_BIT 31

#define PIOA_BSR (*(volatile unsigned long *)0xFFFFF474)
#define PIOA_BSR_OFFSET 0x74
#define PIOA_BSR_P0_MASK 0x1U
#define PIOA_BSR_P0 0x1U
#define PIOA_BSR_P0_BIT 0
#define PIOA_BSR_P1_MASK 0x2U
#define PIOA_BSR_P1 0x2U
#define PIOA_BSR_P1_BIT 1
#define PIOA_BSR_P2_MASK 0x4U
#define PIOA_BSR_P2 0x4U
#define PIOA_BSR_P2_BIT 2
#define PIOA_BSR_P3_MASK 0x8U
#define PIOA_BSR_P3 0x8U
#define PIOA_BSR_P3_BIT 3
#define PIOA_BSR_P4_MASK 0x10U
#define PIOA_BSR_P4 0x10U
#define PIOA_BSR_P4_BIT 4
#define PIOA_BSR_P5_MASK 0x20U
#define PIOA_BSR_P5 0x20U
#define PIOA_BSR_P5_BIT 5
#define PIOA_BSR_P6_MASK 0x40U
#define PIOA_BSR_P6 0x40U
#define PIOA_BSR_P6_BIT 6
#define PIOA_BSR_P7_MASK 0x80U
#define PIOA_BSR_P7 0x80U
#define PIOA_BSR_P7_BIT 7
#define PIOA_BSR_P8_MASK 0x100U
#define PIOA_BSR_P8 0x100U
#define PIOA_BSR_P8_BIT 8
#define PIOA_BSR_P9_MASK 0x200U
#define PIOA_BSR_P9 0x200U
#define PIOA_BSR_P9_BIT 9
#define PIOA_BSR_P10_MASK 0x400U
#define PIOA_BSR_P10 0x400U
#define PIOA_BSR_P10_BIT 10
#define PIOA_BSR_P11_MASK 0x800U
#define PIOA_BSR_P11 0x800U
#define PIOA_BSR_P11_BIT 11
#define PIOA_BSR_P12_MASK 0x1000U
#define PIOA_BSR_P12 0x1000U
#define PIOA_BSR_P12_BIT 12
#define PIOA_BSR_P13_MASK 0x2000U
#define PIOA_BSR_P13 0x2000U
#define PIOA_BSR_P13_BIT 13
#define PIOA_BSR_P14_MASK 0x4000U
#define PIOA_BSR_P14 0x4000U
#define PIOA_BSR_P14_BIT 14
#define PIOA_BSR_P15_MASK 0x8000U
#define PIOA_BSR_P15 0x8000U
#define PIOA_BSR_P15_BIT 15
#define PIOA_BSR_P16_MASK 0x10000U
#define PIOA_BSR_P16 0x10000U
#define PIOA_BSR_P16_BIT 16
#define PIOA_BSR_P17_MASK 0x20000U
#define PIOA_BSR_P17 0x20000U
#define PIOA_BSR_P17_BIT 17
#define PIOA_BSR_P18_MASK 0x40000U
#define PIOA_BSR_P18 0x40000U
#define PIOA_BSR_P18_BIT 18
#define PIOA_BSR_P19_MASK 0x80000U
#define PIOA_BSR_P19 0x80000U
#define PIOA_BSR_P19_BIT 19
#define PIOA_BSR_P20_MASK 0x100000U
#define PIOA_BSR_P20 0x100000U
#define PIOA_BSR_P20_BIT 20
#define PIOA_BSR_P21_MASK 0x200000U
#define PIOA_BSR_P21 0x200000U
#define PIOA_BSR_P21_BIT 21
#define PIOA_BSR_P22_MASK 0x400000U
#define PIOA_BSR_P22 0x400000U
#define PIOA_BSR_P22_BIT 22
#define PIOA_BSR_P23_MASK 0x800000U
#define PIOA_BSR_P23 0x800000U
#define PIOA_BSR_P23_BIT 23
#define PIOA_BSR_P24_MASK 0x1000000U
#define PIOA_BSR_P24 0x1000000U
#define PIOA_BSR_P24_BIT 24
#define PIOA_BSR_P25_MASK 0x2000000U
#define PIOA_BSR_P25 0x2000000U
#define PIOA_BSR_P25_BIT 25
#define PIOA_BSR_P26_MASK 0x4000000U
#define PIOA_BSR_P26 0x4000000U
#define PIOA_BSR_P26_BIT 26
#define PIOA_BSR_P27_MASK 0x8000000U
#define PIOA_BSR_P27 0x8000000U
#define PIOA_BSR_P27_BIT 27
#define PIOA_BSR_P28_MASK 0x10000000U
#define PIOA_BSR_P28 0x10000000U
#define PIOA_BSR_P28_BIT 28
#define PIOA_BSR_P29_MASK 0x20000000U
#define PIOA_BSR_P29 0x20000000U
#define PIOA_BSR_P29_BIT 29
#define PIOA_BSR_P30_MASK 0x40000000U
#define PIOA_BSR_P30 0x40000000U
#define PIOA_BSR_P30_BIT 30
#define PIOA_BSR_P31_MASK 0x80000000U
#define PIOA_BSR_P31 0x80000000U
#define PIOA_BSR_P31_BIT 31

#define PIOA_ABSR (*(volatile unsigned long *)0xFFFFF478)
#define PIOA_ABSR_OFFSET 0x78
#define PIOA_ABSR_P0_MASK 0x1U
#define PIOA_ABSR_P0 0x1U
#define PIOA_ABSR_P0_BIT 0
#define PIOA_ABSR_P1_MASK 0x2U
#define PIOA_ABSR_P1 0x2U
#define PIOA_ABSR_P1_BIT 1
#define PIOA_ABSR_P2_MASK 0x4U
#define PIOA_ABSR_P2 0x4U
#define PIOA_ABSR_P2_BIT 2
#define PIOA_ABSR_P3_MASK 0x8U
#define PIOA_ABSR_P3 0x8U
#define PIOA_ABSR_P3_BIT 3
#define PIOA_ABSR_P4_MASK 0x10U
#define PIOA_ABSR_P4 0x10U
#define PIOA_ABSR_P4_BIT 4
#define PIOA_ABSR_P5_MASK 0x20U
#define PIOA_ABSR_P5 0x20U
#define PIOA_ABSR_P5_BIT 5
#define PIOA_ABSR_P6_MASK 0x40U
#define PIOA_ABSR_P6 0x40U
#define PIOA_ABSR_P6_BIT 6
#define PIOA_ABSR_P7_MASK 0x80U
#define PIOA_ABSR_P7 0x80U
#define PIOA_ABSR_P7_BIT 7
#define PIOA_ABSR_P8_MASK 0x100U
#define PIOA_ABSR_P8 0x100U
#define PIOA_ABSR_P8_BIT 8
#define PIOA_ABSR_P9_MASK 0x200U
#define PIOA_ABSR_P9 0x200U
#define PIOA_ABSR_P9_BIT 9
#define PIOA_ABSR_P10_MASK 0x400U
#define PIOA_ABSR_P10 0x400U
#define PIOA_ABSR_P10_BIT 10
#define PIOA_ABSR_P11_MASK 0x800U
#define PIOA_ABSR_P11 0x800U
#define PIOA_ABSR_P11_BIT 11
#define PIOA_ABSR_P12_MASK 0x1000U
#define PIOA_ABSR_P12 0x1000U
#define PIOA_ABSR_P12_BIT 12
#define PIOA_ABSR_P13_MASK 0x2000U
#define PIOA_ABSR_P13 0x2000U
#define PIOA_ABSR_P13_BIT 13
#define PIOA_ABSR_P14_MASK 0x4000U
#define PIOA_ABSR_P14 0x4000U
#define PIOA_ABSR_P14_BIT 14
#define PIOA_ABSR_P15_MASK 0x8000U
#define PIOA_ABSR_P15 0x8000U
#define PIOA_ABSR_P15_BIT 15
#define PIOA_ABSR_P16_MASK 0x10000U
#define PIOA_ABSR_P16 0x10000U
#define PIOA_ABSR_P16_BIT 16
#define PIOA_ABSR_P17_MASK 0x20000U
#define PIOA_ABSR_P17 0x20000U
#define PIOA_ABSR_P17_BIT 17
#define PIOA_ABSR_P18_MASK 0x40000U
#define PIOA_ABSR_P18 0x40000U
#define PIOA_ABSR_P18_BIT 18
#define PIOA_ABSR_P19_MASK 0x80000U
#define PIOA_ABSR_P19 0x80000U
#define PIOA_ABSR_P19_BIT 19
#define PIOA_ABSR_P20_MASK 0x100000U
#define PIOA_ABSR_P20 0x100000U
#define PIOA_ABSR_P20_BIT 20
#define PIOA_ABSR_P21_MASK 0x200000U
#define PIOA_ABSR_P21 0x200000U
#define PIOA_ABSR_P21_BIT 21
#define PIOA_ABSR_P22_MASK 0x400000U
#define PIOA_ABSR_P22 0x400000U
#define PIOA_ABSR_P22_BIT 22
#define PIOA_ABSR_P23_MASK 0x800000U
#define PIOA_ABSR_P23 0x800000U
#define PIOA_ABSR_P23_BIT 23
#define PIOA_ABSR_P24_MASK 0x1000000U
#define PIOA_ABSR_P24 0x1000000U
#define PIOA_ABSR_P24_BIT 24
#define PIOA_ABSR_P25_MASK 0x2000000U
#define PIOA_ABSR_P25 0x2000000U
#define PIOA_ABSR_P25_BIT 25
#define PIOA_ABSR_P26_MASK 0x4000000U
#define PIOA_ABSR_P26 0x4000000U
#define PIOA_ABSR_P26_BIT 26
#define PIOA_ABSR_P27_MASK 0x8000000U
#define PIOA_ABSR_P27 0x8000000U
#define PIOA_ABSR_P27_BIT 27
#define PIOA_ABSR_P28_MASK 0x10000000U
#define PIOA_ABSR_P28 0x10000000U
#define PIOA_ABSR_P28_BIT 28
#define PIOA_ABSR_P29_MASK 0x20000000U
#define PIOA_ABSR_P29 0x20000000U
#define PIOA_ABSR_P29_BIT 29
#define PIOA_ABSR_P30_MASK 0x40000000U
#define PIOA_ABSR_P30 0x40000000U
#define PIOA_ABSR_P30_BIT 30
#define PIOA_ABSR_P31_MASK 0x80000000U
#define PIOA_ABSR_P31 0x80000000U
#define PIOA_ABSR_P31_BIT 31

#define PIOA_OWER (*(volatile unsigned long *)0xFFFFF4A0)
#define PIOA_OWER_OFFSET 0xA0
#define PIOA_OWER_P0_MASK 0x1U
#define PIOA_OWER_P0 0x1U
#define PIOA_OWER_P0_BIT 0
#define PIOA_OWER_P1_MASK 0x2U
#define PIOA_OWER_P1 0x2U
#define PIOA_OWER_P1_BIT 1
#define PIOA_OWER_P2_MASK 0x4U
#define PIOA_OWER_P2 0x4U
#define PIOA_OWER_P2_BIT 2
#define PIOA_OWER_P3_MASK 0x8U
#define PIOA_OWER_P3 0x8U
#define PIOA_OWER_P3_BIT 3
#define PIOA_OWER_P4_MASK 0x10U
#define PIOA_OWER_P4 0x10U
#define PIOA_OWER_P4_BIT 4
#define PIOA_OWER_P5_MASK 0x20U
#define PIOA_OWER_P5 0x20U
#define PIOA_OWER_P5_BIT 5
#define PIOA_OWER_P6_MASK 0x40U
#define PIOA_OWER_P6 0x40U
#define PIOA_OWER_P6_BIT 6
#define PIOA_OWER_P7_MASK 0x80U
#define PIOA_OWER_P7 0x80U
#define PIOA_OWER_P7_BIT 7
#define PIOA_OWER_P8_MASK 0x100U
#define PIOA_OWER_P8 0x100U
#define PIOA_OWER_P8_BIT 8
#define PIOA_OWER_P9_MASK 0x200U
#define PIOA_OWER_P9 0x200U
#define PIOA_OWER_P9_BIT 9
#define PIOA_OWER_P10_MASK 0x400U
#define PIOA_OWER_P10 0x400U
#define PIOA_OWER_P10_BIT 10
#define PIOA_OWER_P11_MASK 0x800U
#define PIOA_OWER_P11 0x800U
#define PIOA_OWER_P11_BIT 11
#define PIOA_OWER_P12_MASK 0x1000U
#define PIOA_OWER_P12 0x1000U
#define PIOA_OWER_P12_BIT 12
#define PIOA_OWER_P13_MASK 0x2000U
#define PIOA_OWER_P13 0x2000U
#define PIOA_OWER_P13_BIT 13
#define PIOA_OWER_P14_MASK 0x4000U
#define PIOA_OWER_P14 0x4000U
#define PIOA_OWER_P14_BIT 14
#define PIOA_OWER_P15_MASK 0x8000U
#define PIOA_OWER_P15 0x8000U
#define PIOA_OWER_P15_BIT 15
#define PIOA_OWER_P16_MASK 0x10000U
#define PIOA_OWER_P16 0x10000U
#define PIOA_OWER_P16_BIT 16
#define PIOA_OWER_P17_MASK 0x20000U
#define PIOA_OWER_P17 0x20000U
#define PIOA_OWER_P17_BIT 17
#define PIOA_OWER_P18_MASK 0x40000U
#define PIOA_OWER_P18 0x40000U
#define PIOA_OWER_P18_BIT 18
#define PIOA_OWER_P19_MASK 0x80000U
#define PIOA_OWER_P19 0x80000U
#define PIOA_OWER_P19_BIT 19
#define PIOA_OWER_P20_MASK 0x100000U
#define PIOA_OWER_P20 0x100000U
#define PIOA_OWER_P20_BIT 20
#define PIOA_OWER_P21_MASK 0x200000U
#define PIOA_OWER_P21 0x200000U
#define PIOA_OWER_P21_BIT 21
#define PIOA_OWER_P22_MASK 0x400000U
#define PIOA_OWER_P22 0x400000U
#define PIOA_OWER_P22_BIT 22
#define PIOA_OWER_P23_MASK 0x800000U
#define PIOA_OWER_P23 0x800000U
#define PIOA_OWER_P23_BIT 23
#define PIOA_OWER_P24_MASK 0x1000000U
#define PIOA_OWER_P24 0x1000000U
#define PIOA_OWER_P24_BIT 24
#define PIOA_OWER_P25_MASK 0x2000000U
#define PIOA_OWER_P25 0x2000000U
#define PIOA_OWER_P25_BIT 25
#define PIOA_OWER_P26_MASK 0x4000000U
#define PIOA_OWER_P26 0x4000000U
#define PIOA_OWER_P26_BIT 26
#define PIOA_OWER_P27_MASK 0x8000000U
#define PIOA_OWER_P27 0x8000000U
#define PIOA_OWER_P27_BIT 27
#define PIOA_OWER_P28_MASK 0x10000000U
#define PIOA_OWER_P28 0x10000000U
#define PIOA_OWER_P28_BIT 28
#define PIOA_OWER_P29_MASK 0x20000000U
#define PIOA_OWER_P29 0x20000000U
#define PIOA_OWER_P29_BIT 29
#define PIOA_OWER_P30_MASK 0x40000000U
#define PIOA_OWER_P30 0x40000000U
#define PIOA_OWER_P30_BIT 30
#define PIOA_OWER_P31_MASK 0x80000000U
#define PIOA_OWER_P31 0x80000000U
#define PIOA_OWER_P31_BIT 31

#define PIOA_OWDR (*(volatile unsigned long *)0xFFFFF4A4)
#define PIOA_OWDR_OFFSET 0xA4
#define PIOA_OWDR_P0_MASK 0x1U
#define PIOA_OWDR_P0 0x1U
#define PIOA_OWDR_P0_BIT 0
#define PIOA_OWDR_P1_MASK 0x2U
#define PIOA_OWDR_P1 0x2U
#define PIOA_OWDR_P1_BIT 1
#define PIOA_OWDR_P2_MASK 0x4U
#define PIOA_OWDR_P2 0x4U
#define PIOA_OWDR_P2_BIT 2
#define PIOA_OWDR_P3_MASK 0x8U
#define PIOA_OWDR_P3 0x8U
#define PIOA_OWDR_P3_BIT 3
#define PIOA_OWDR_P4_MASK 0x10U
#define PIOA_OWDR_P4 0x10U
#define PIOA_OWDR_P4_BIT 4
#define PIOA_OWDR_P5_MASK 0x20U
#define PIOA_OWDR_P5 0x20U
#define PIOA_OWDR_P5_BIT 5
#define PIOA_OWDR_P6_MASK 0x40U
#define PIOA_OWDR_P6 0x40U
#define PIOA_OWDR_P6_BIT 6
#define PIOA_OWDR_P7_MASK 0x80U
#define PIOA_OWDR_P7 0x80U
#define PIOA_OWDR_P7_BIT 7
#define PIOA_OWDR_P8_MASK 0x100U
#define PIOA_OWDR_P8 0x100U
#define PIOA_OWDR_P8_BIT 8
#define PIOA_OWDR_P9_MASK 0x200U
#define PIOA_OWDR_P9 0x200U
#define PIOA_OWDR_P9_BIT 9
#define PIOA_OWDR_P10_MASK 0x400U
#define PIOA_OWDR_P10 0x400U
#define PIOA_OWDR_P10_BIT 10
#define PIOA_OWDR_P11_MASK 0x800U
#define PIOA_OWDR_P11 0x800U
#define PIOA_OWDR_P11_BIT 11
#define PIOA_OWDR_P12_MASK 0x1000U
#define PIOA_OWDR_P12 0x1000U
#define PIOA_OWDR_P12_BIT 12
#define PIOA_OWDR_P13_MASK 0x2000U
#define PIOA_OWDR_P13 0x2000U
#define PIOA_OWDR_P13_BIT 13
#define PIOA_OWDR_P14_MASK 0x4000U
#define PIOA_OWDR_P14 0x4000U
#define PIOA_OWDR_P14_BIT 14
#define PIOA_OWDR_P15_MASK 0x8000U
#define PIOA_OWDR_P15 0x8000U
#define PIOA_OWDR_P15_BIT 15
#define PIOA_OWDR_P16_MASK 0x10000U
#define PIOA_OWDR_P16 0x10000U
#define PIOA_OWDR_P16_BIT 16
#define PIOA_OWDR_P17_MASK 0x20000U
#define PIOA_OWDR_P17 0x20000U
#define PIOA_OWDR_P17_BIT 17
#define PIOA_OWDR_P18_MASK 0x40000U
#define PIOA_OWDR_P18 0x40000U
#define PIOA_OWDR_P18_BIT 18
#define PIOA_OWDR_P19_MASK 0x80000U
#define PIOA_OWDR_P19 0x80000U
#define PIOA_OWDR_P19_BIT 19
#define PIOA_OWDR_P20_MASK 0x100000U
#define PIOA_OWDR_P20 0x100000U
#define PIOA_OWDR_P20_BIT 20
#define PIOA_OWDR_P21_MASK 0x200000U
#define PIOA_OWDR_P21 0x200000U
#define PIOA_OWDR_P21_BIT 21
#define PIOA_OWDR_P22_MASK 0x400000U
#define PIOA_OWDR_P22 0x400000U
#define PIOA_OWDR_P22_BIT 22
#define PIOA_OWDR_P23_MASK 0x800000U
#define PIOA_OWDR_P23 0x800000U
#define PIOA_OWDR_P23_BIT 23
#define PIOA_OWDR_P24_MASK 0x1000000U
#define PIOA_OWDR_P24 0x1000000U
#define PIOA_OWDR_P24_BIT 24
#define PIOA_OWDR_P25_MASK 0x2000000U
#define PIOA_OWDR_P25 0x2000000U
#define PIOA_OWDR_P25_BIT 25
#define PIOA_OWDR_P26_MASK 0x4000000U
#define PIOA_OWDR_P26 0x4000000U
#define PIOA_OWDR_P26_BIT 26
#define PIOA_OWDR_P27_MASK 0x8000000U
#define PIOA_OWDR_P27 0x8000000U
#define PIOA_OWDR_P27_BIT 27
#define PIOA_OWDR_P28_MASK 0x10000000U
#define PIOA_OWDR_P28 0x10000000U
#define PIOA_OWDR_P28_BIT 28
#define PIOA_OWDR_P29_MASK 0x20000000U
#define PIOA_OWDR_P29 0x20000000U
#define PIOA_OWDR_P29_BIT 29
#define PIOA_OWDR_P30_MASK 0x40000000U
#define PIOA_OWDR_P30 0x40000000U
#define PIOA_OWDR_P30_BIT 30
#define PIOA_OWDR_P31_MASK 0x80000000U
#define PIOA_OWDR_P31 0x80000000U
#define PIOA_OWDR_P31_BIT 31

#define PIOA_OWSR (*(volatile unsigned long *)0xFFFFF4A8)
#define PIOA_OWSR_OFFSET 0xA8
#define PIOA_OWSR_P0_MASK 0x1U
#define PIOA_OWSR_P0 0x1U
#define PIOA_OWSR_P0_BIT 0
#define PIOA_OWSR_P1_MASK 0x2U
#define PIOA_OWSR_P1 0x2U
#define PIOA_OWSR_P1_BIT 1
#define PIOA_OWSR_P2_MASK 0x4U
#define PIOA_OWSR_P2 0x4U
#define PIOA_OWSR_P2_BIT 2
#define PIOA_OWSR_P3_MASK 0x8U
#define PIOA_OWSR_P3 0x8U
#define PIOA_OWSR_P3_BIT 3
#define PIOA_OWSR_P4_MASK 0x10U
#define PIOA_OWSR_P4 0x10U
#define PIOA_OWSR_P4_BIT 4
#define PIOA_OWSR_P5_MASK 0x20U
#define PIOA_OWSR_P5 0x20U
#define PIOA_OWSR_P5_BIT 5
#define PIOA_OWSR_P6_MASK 0x40U
#define PIOA_OWSR_P6 0x40U
#define PIOA_OWSR_P6_BIT 6
#define PIOA_OWSR_P7_MASK 0x80U
#define PIOA_OWSR_P7 0x80U
#define PIOA_OWSR_P7_BIT 7
#define PIOA_OWSR_P8_MASK 0x100U
#define PIOA_OWSR_P8 0x100U
#define PIOA_OWSR_P8_BIT 8
#define PIOA_OWSR_P9_MASK 0x200U
#define PIOA_OWSR_P9 0x200U
#define PIOA_OWSR_P9_BIT 9
#define PIOA_OWSR_P10_MASK 0x400U
#define PIOA_OWSR_P10 0x400U
#define PIOA_OWSR_P10_BIT 10
#define PIOA_OWSR_P11_MASK 0x800U
#define PIOA_OWSR_P11 0x800U
#define PIOA_OWSR_P11_BIT 11
#define PIOA_OWSR_P12_MASK 0x1000U
#define PIOA_OWSR_P12 0x1000U
#define PIOA_OWSR_P12_BIT 12
#define PIOA_OWSR_P13_MASK 0x2000U
#define PIOA_OWSR_P13 0x2000U
#define PIOA_OWSR_P13_BIT 13
#define PIOA_OWSR_P14_MASK 0x4000U
#define PIOA_OWSR_P14 0x4000U
#define PIOA_OWSR_P14_BIT 14
#define PIOA_OWSR_P15_MASK 0x8000U
#define PIOA_OWSR_P15 0x8000U
#define PIOA_OWSR_P15_BIT 15
#define PIOA_OWSR_P16_MASK 0x10000U
#define PIOA_OWSR_P16 0x10000U
#define PIOA_OWSR_P16_BIT 16
#define PIOA_OWSR_P17_MASK 0x20000U
#define PIOA_OWSR_P17 0x20000U
#define PIOA_OWSR_P17_BIT 17
#define PIOA_OWSR_P18_MASK 0x40000U
#define PIOA_OWSR_P18 0x40000U
#define PIOA_OWSR_P18_BIT 18
#define PIOA_OWSR_P19_MASK 0x80000U
#define PIOA_OWSR_P19 0x80000U
#define PIOA_OWSR_P19_BIT 19
#define PIOA_OWSR_P20_MASK 0x100000U
#define PIOA_OWSR_P20 0x100000U
#define PIOA_OWSR_P20_BIT 20
#define PIOA_OWSR_P21_MASK 0x200000U
#define PIOA_OWSR_P21 0x200000U
#define PIOA_OWSR_P21_BIT 21
#define PIOA_OWSR_P22_MASK 0x400000U
#define PIOA_OWSR_P22 0x400000U
#define PIOA_OWSR_P22_BIT 22
#define PIOA_OWSR_P23_MASK 0x800000U
#define PIOA_OWSR_P23 0x800000U
#define PIOA_OWSR_P23_BIT 23
#define PIOA_OWSR_P24_MASK 0x1000000U
#define PIOA_OWSR_P24 0x1000000U
#define PIOA_OWSR_P24_BIT 24
#define PIOA_OWSR_P25_MASK 0x2000000U
#define PIOA_OWSR_P25 0x2000000U
#define PIOA_OWSR_P25_BIT 25
#define PIOA_OWSR_P26_MASK 0x4000000U
#define PIOA_OWSR_P26 0x4000000U
#define PIOA_OWSR_P26_BIT 26
#define PIOA_OWSR_P27_MASK 0x8000000U
#define PIOA_OWSR_P27 0x8000000U
#define PIOA_OWSR_P27_BIT 27
#define PIOA_OWSR_P28_MASK 0x10000000U
#define PIOA_OWSR_P28 0x10000000U
#define PIOA_OWSR_P28_BIT 28
#define PIOA_OWSR_P29_MASK 0x20000000U
#define PIOA_OWSR_P29 0x20000000U
#define PIOA_OWSR_P29_BIT 29
#define PIOA_OWSR_P30_MASK 0x40000000U
#define PIOA_OWSR_P30 0x40000000U
#define PIOA_OWSR_P30_BIT 30
#define PIOA_OWSR_P31_MASK 0x80000000U
#define PIOA_OWSR_P31 0x80000000U
#define PIOA_OWSR_P31_BIT 31

#define PMC_BASE 0xFFFFFC00

#define PMC_SCER (*(volatile unsigned long *)0xFFFFFC00)
#define PMC_SCER_OFFSET 0x0
#define PMC_SCER_PCK_MASK 0x1U
#define PMC_SCER_PCK 0x1U
#define PMC_SCER_PCK_BIT 0
#define PMC_SCER_UDP_MASK 0x80U
#define PMC_SCER_UDP 0x80U
#define PMC_SCER_UDP_BIT 7
#define PMC_SCER_PCK0_MASK 0x100U
#define PMC_SCER_PCK0 0x100U
#define PMC_SCER_PCK0_BIT 8
#define PMC_SCER_PCK1_MASK 0x200U
#define PMC_SCER_PCK1 0x200U
#define PMC_SCER_PCK1_BIT 9
#define PMC_SCER_PCK2_MASK 0x400U
#define PMC_SCER_PCK2 0x400U
#define PMC_SCER_PCK2_BIT 10

#define PMC_SCDR (*(volatile unsigned long *)0xFFFFFC04)
#define PMC_SCDR_OFFSET 0x4
#define PMC_SCDR_PCK_MASK 0x1U
#define PMC_SCDR_PCK 0x1U
#define PMC_SCDR_PCK_BIT 0
#define PMC_SCDR_UDP_MASK 0x80U
#define PMC_SCDR_UDP 0x80U
#define PMC_SCDR_UDP_BIT 7
#define PMC_SCDR_PCK0_MASK 0x100U
#define PMC_SCDR_PCK0 0x100U
#define PMC_SCDR_PCK0_BIT 8
#define PMC_SCDR_PCK1_MASK 0x200U
#define PMC_SCDR_PCK1 0x200U
#define PMC_SCDR_PCK1_BIT 9
#define PMC_SCDR_PCK2_MASK 0x400U
#define PMC_SCDR_PCK2 0x400U
#define PMC_SCDR_PCK2_BIT 10

#define PMC_SCSR (*(volatile unsigned long *)0xFFFFFC08)
#define PMC_SCSR_OFFSET 0x8
#define PMC_SCSR_PCK_MASK 0x1U
#define PMC_SCSR_PCK 0x1U
#define PMC_SCSR_PCK_BIT 0
#define PMC_SCSR_UDP_MASK 0x80U
#define PMC_SCSR_UDP 0x80U
#define PMC_SCSR_UDP_BIT 7
#define PMC_SCSR_PCK0_MASK 0x100U
#define PMC_SCSR_PCK0 0x100U
#define PMC_SCSR_PCK0_BIT 8
#define PMC_SCSR_PCK1_MASK 0x200U
#define PMC_SCSR_PCK1 0x200U
#define PMC_SCSR_PCK1_BIT 9
#define PMC_SCSR_PCK2_MASK 0x400U
#define PMC_SCSR_PCK2 0x400U
#define PMC_SCSR_PCK2_BIT 10

#define PMC_PCER (*(volatile unsigned long *)0xFFFFFC10)
#define PMC_PCER_OFFSET 0x10
#define PMC_PCER_PID2_MASK 0x4U
#define PMC_PCER_PID2 0x4U
#define PMC_PCER_PID2_BIT 2
#define PMC_PCER_PID3_MASK 0x8U
#define PMC_PCER_PID3 0x8U
#define PMC_PCER_PID3_BIT 3
#define PMC_PCER_PID4_MASK 0x10U
#define PMC_PCER_PID4 0x10U
#define PMC_PCER_PID4_BIT 4
#define PMC_PCER_PID5_MASK 0x20U
#define PMC_PCER_PID5 0x20U
#define PMC_PCER_PID5_BIT 5
#define PMC_PCER_PID6_MASK 0x40U
#define PMC_PCER_PID6 0x40U
#define PMC_PCER_PID6_BIT 6
#define PMC_PCER_PID7_MASK 0x80U
#define PMC_PCER_PID7 0x80U
#define PMC_PCER_PID7_BIT 7
#define PMC_PCER_PID8_MASK 0x100U
#define PMC_PCER_PID8 0x100U
#define PMC_PCER_PID8_BIT 8
#define PMC_PCER_PID9_MASK 0x200U
#define PMC_PCER_PID9 0x200U
#define PMC_PCER_PID9_BIT 9
#define PMC_PCER_PID10_MASK 0x400U
#define PMC_PCER_PID10 0x400U
#define PMC_PCER_PID10_BIT 10
#define PMC_PCER_PID11_MASK 0x800U
#define PMC_PCER_PID11 0x800U
#define PMC_PCER_PID11_BIT 11
#define PMC_PCER_PID12_MASK 0x1000U
#define PMC_PCER_PID12 0x1000U
#define PMC_PCER_PID12_BIT 12
#define PMC_PCER_PID13_MASK 0x2000U
#define PMC_PCER_PID13 0x2000U
#define PMC_PCER_PID13_BIT 13
#define PMC_PCER_PID14_MASK 0x4000U
#define PMC_PCER_PID14 0x4000U
#define PMC_PCER_PID14_BIT 14
#define PMC_PCER_PID15_MASK 0x8000U
#define PMC_PCER_PID15 0x8000U
#define PMC_PCER_PID15_BIT 15
#define PMC_PCER_PID16_MASK 0x10000U
#define PMC_PCER_PID16 0x10000U
#define PMC_PCER_PID16_BIT 16
#define PMC_PCER_PID17_MASK 0x20000U
#define PMC_PCER_PID17 0x20000U
#define PMC_PCER_PID17_BIT 17
#define PMC_PCER_PID18_MASK 0x40000U
#define PMC_PCER_PID18 0x40000U
#define PMC_PCER_PID18_BIT 18
#define PMC_PCER_PID19_MASK 0x80000U
#define PMC_PCER_PID19 0x80000U
#define PMC_PCER_PID19_BIT 19
#define PMC_PCER_PID20_MASK 0x100000U
#define PMC_PCER_PID20 0x100000U
#define PMC_PCER_PID20_BIT 20
#define PMC_PCER_PID21_MASK 0x200000U
#define PMC_PCER_PID21 0x200000U
#define PMC_PCER_PID21_BIT 21
#define PMC_PCER_PID22_MASK 0x400000U
#define PMC_PCER_PID22 0x400000U
#define PMC_PCER_PID22_BIT 22
#define PMC_PCER_PID23_MASK 0x800000U
#define PMC_PCER_PID23 0x800000U
#define PMC_PCER_PID23_BIT 23
#define PMC_PCER_PID24_MASK 0x1000000U
#define PMC_PCER_PID24 0x1000000U
#define PMC_PCER_PID24_BIT 24
#define PMC_PCER_PID25_MASK 0x2000000U
#define PMC_PCER_PID25 0x2000000U
#define PMC_PCER_PID25_BIT 25
#define PMC_PCER_PID26_MASK 0x4000000U
#define PMC_PCER_PID26 0x4000000U
#define PMC_PCER_PID26_BIT 26
#define PMC_PCER_PID27_MASK 0x8000000U
#define PMC_PCER_PID27 0x8000000U
#define PMC_PCER_PID27_BIT 27
#define PMC_PCER_PID28_MASK 0x10000000U
#define PMC_PCER_PID28 0x10000000U
#define PMC_PCER_PID28_BIT 28
#define PMC_PCER_PID29_MASK 0x20000000U
#define PMC_PCER_PID29 0x20000000U
#define PMC_PCER_PID29_BIT 29
#define PMC_PCER_PID30_MASK 0x40000000U
#define PMC_PCER_PID30 0x40000000U
#define PMC_PCER_PID30_BIT 30
#define PMC_PCER_PID31_MASK 0x80000000U
#define PMC_PCER_PID31 0x80000000U
#define PMC_PCER_PID31_BIT 31

#define PMC_PCDR (*(volatile unsigned long *)0xFFFFFC14)
#define PMC_PCDR_OFFSET 0x14
#define PMC_PCDR_PID2_MASK 0x4U
#define PMC_PCDR_PID2 0x4U
#define PMC_PCDR_PID2_BIT 2
#define PMC_PCDR_PID3_MASK 0x8U
#define PMC_PCDR_PID3 0x8U
#define PMC_PCDR_PID3_BIT 3
#define PMC_PCDR_PID4_MASK 0x10U
#define PMC_PCDR_PID4 0x10U
#define PMC_PCDR_PID4_BIT 4
#define PMC_PCDR_PID5_MASK 0x20U
#define PMC_PCDR_PID5 0x20U
#define PMC_PCDR_PID5_BIT 5
#define PMC_PCDR_PID6_MASK 0x40U
#define PMC_PCDR_PID6 0x40U
#define PMC_PCDR_PID6_BIT 6
#define PMC_PCDR_PID7_MASK 0x80U
#define PMC_PCDR_PID7 0x80U
#define PMC_PCDR_PID7_BIT 7
#define PMC_PCDR_PID8_MASK 0x100U
#define PMC_PCDR_PID8 0x100U
#define PMC_PCDR_PID8_BIT 8
#define PMC_PCDR_PID9_MASK 0x200U
#define PMC_PCDR_PID9 0x200U
#define PMC_PCDR_PID9_BIT 9
#define PMC_PCDR_PID10_MASK 0x400U
#define PMC_PCDR_PID10 0x400U
#define PMC_PCDR_PID10_BIT 10
#define PMC_PCDR_PID11_MASK 0x800U
#define PMC_PCDR_PID11 0x800U
#define PMC_PCDR_PID11_BIT 11
#define PMC_PCDR_PID12_MASK 0x1000U
#define PMC_PCDR_PID12 0x1000U
#define PMC_PCDR_PID12_BIT 12
#define PMC_PCDR_PID13_MASK 0x2000U
#define PMC_PCDR_PID13 0x2000U
#define PMC_PCDR_PID13_BIT 13
#define PMC_PCDR_PID14_MASK 0x4000U
#define PMC_PCDR_PID14 0x4000U
#define PMC_PCDR_PID14_BIT 14
#define PMC_PCDR_PID15_MASK 0x8000U
#define PMC_PCDR_PID15 0x8000U
#define PMC_PCDR_PID15_BIT 15
#define PMC_PCDR_PID16_MASK 0x10000U
#define PMC_PCDR_PID16 0x10000U
#define PMC_PCDR_PID16_BIT 16
#define PMC_PCDR_PID17_MASK 0x20000U
#define PMC_PCDR_PID17 0x20000U
#define PMC_PCDR_PID17_BIT 17
#define PMC_PCDR_PID18_MASK 0x40000U
#define PMC_PCDR_PID18 0x40000U
#define PMC_PCDR_PID18_BIT 18
#define PMC_PCDR_PID19_MASK 0x80000U
#define PMC_PCDR_PID19 0x80000U
#define PMC_PCDR_PID19_BIT 19
#define PMC_PCDR_PID20_MASK 0x100000U
#define PMC_PCDR_PID20 0x100000U
#define PMC_PCDR_PID20_BIT 20
#define PMC_PCDR_PID21_MASK 0x200000U
#define PMC_PCDR_PID21 0x200000U
#define PMC_PCDR_PID21_BIT 21
#define PMC_PCDR_PID22_MASK 0x400000U
#define PMC_PCDR_PID22 0x400000U
#define PMC_PCDR_PID22_BIT 22
#define PMC_PCDR_PID23_MASK 0x800000U
#define PMC_PCDR_PID23 0x800000U
#define PMC_PCDR_PID23_BIT 23
#define PMC_PCDR_PID24_MASK 0x1000000U
#define PMC_PCDR_PID24 0x1000000U
#define PMC_PCDR_PID24_BIT 24
#define PMC_PCDR_PID25_MASK 0x2000000U
#define PMC_PCDR_PID25 0x2000000U
#define PMC_PCDR_PID25_BIT 25
#define PMC_PCDR_PID26_MASK 0x4000000U
#define PMC_PCDR_PID26 0x4000000U
#define PMC_PCDR_PID26_BIT 26
#define PMC_PCDR_PID27_MASK 0x8000000U
#define PMC_PCDR_PID27 0x8000000U
#define PMC_PCDR_PID27_BIT 27
#define PMC_PCDR_PID28_MASK 0x10000000U
#define PMC_PCDR_PID28 0x10000000U
#define PMC_PCDR_PID28_BIT 28
#define PMC_PCDR_PID29_MASK 0x20000000U
#define PMC_PCDR_PID29 0x20000000U
#define PMC_PCDR_PID29_BIT 29
#define PMC_PCDR_PID30_MASK 0x40000000U
#define PMC_PCDR_PID30 0x40000000U
#define PMC_PCDR_PID30_BIT 30
#define PMC_PCDR_PID31_MASK 0x80000000U
#define PMC_PCDR_PID31 0x80000000U
#define PMC_PCDR_PID31_BIT 31

#define PMC_PCSR (*(volatile unsigned long *)0xFFFFFC18)
#define PMC_PCSR_OFFSET 0x18
#define PMC_PCSR_PID2_MASK 0x4U
#define PMC_PCSR_PID2 0x4U
#define PMC_PCSR_PID2_BIT 2
#define PMC_PCSR_PID3_MASK 0x8U
#define PMC_PCSR_PID3 0x8U
#define PMC_PCSR_PID3_BIT 3
#define PMC_PCSR_PID4_MASK 0x10U
#define PMC_PCSR_PID4 0x10U
#define PMC_PCSR_PID4_BIT 4
#define PMC_PCSR_PID5_MASK 0x20U
#define PMC_PCSR_PID5 0x20U
#define PMC_PCSR_PID5_BIT 5
#define PMC_PCSR_PID6_MASK 0x40U
#define PMC_PCSR_PID6 0x40U
#define PMC_PCSR_PID6_BIT 6
#define PMC_PCSR_PID7_MASK 0x80U
#define PMC_PCSR_PID7 0x80U
#define PMC_PCSR_PID7_BIT 7
#define PMC_PCSR_PID8_MASK 0x100U
#define PMC_PCSR_PID8 0x100U
#define PMC_PCSR_PID8_BIT 8
#define PMC_PCSR_PID9_MASK 0x200U
#define PMC_PCSR_PID9 0x200U
#define PMC_PCSR_PID9_BIT 9
#define PMC_PCSR_PID10_MASK 0x400U
#define PMC_PCSR_PID10 0x400U
#define PMC_PCSR_PID10_BIT 10
#define PMC_PCSR_PID11_MASK 0x800U
#define PMC_PCSR_PID11 0x800U
#define PMC_PCSR_PID11_BIT 11
#define PMC_PCSR_PID12_MASK 0x1000U
#define PMC_PCSR_PID12 0x1000U
#define PMC_PCSR_PID12_BIT 12
#define PMC_PCSR_PID13_MASK 0x2000U
#define PMC_PCSR_PID13 0x2000U
#define PMC_PCSR_PID13_BIT 13
#define PMC_PCSR_PID14_MASK 0x4000U
#define PMC_PCSR_PID14 0x4000U
#define PMC_PCSR_PID14_BIT 14
#define PMC_PCSR_PID15_MASK 0x8000U
#define PMC_PCSR_PID15 0x8000U
#define PMC_PCSR_PID15_BIT 15
#define PMC_PCSR_PID16_MASK 0x10000U
#define PMC_PCSR_PID16 0x10000U
#define PMC_PCSR_PID16_BIT 16
#define PMC_PCSR_PID17_MASK 0x20000U
#define PMC_PCSR_PID17 0x20000U
#define PMC_PCSR_PID17_BIT 17
#define PMC_PCSR_PID18_MASK 0x40000U
#define PMC_PCSR_PID18 0x40000U
#define PMC_PCSR_PID18_BIT 18
#define PMC_PCSR_PID19_MASK 0x80000U
#define PMC_PCSR_PID19 0x80000U
#define PMC_PCSR_PID19_BIT 19
#define PMC_PCSR_PID20_MASK 0x100000U
#define PMC_PCSR_PID20 0x100000U
#define PMC_PCSR_PID20_BIT 20
#define PMC_PCSR_PID21_MASK 0x200000U
#define PMC_PCSR_PID21 0x200000U
#define PMC_PCSR_PID21_BIT 21
#define PMC_PCSR_PID22_MASK 0x400000U
#define PMC_PCSR_PID22 0x400000U
#define PMC_PCSR_PID22_BIT 22
#define PMC_PCSR_PID23_MASK 0x800000U
#define PMC_PCSR_PID23 0x800000U
#define PMC_PCSR_PID23_BIT 23
#define PMC_PCSR_PID24_MASK 0x1000000U
#define PMC_PCSR_PID24 0x1000000U
#define PMC_PCSR_PID24_BIT 24
#define PMC_PCSR_PID25_MASK 0x2000000U
#define PMC_PCSR_PID25 0x2000000U
#define PMC_PCSR_PID25_BIT 25
#define PMC_PCSR_PID26_MASK 0x4000000U
#define PMC_PCSR_PID26 0x4000000U
#define PMC_PCSR_PID26_BIT 26
#define PMC_PCSR_PID27_MASK 0x8000000U
#define PMC_PCSR_PID27 0x8000000U
#define PMC_PCSR_PID27_BIT 27
#define PMC_PCSR_PID28_MASK 0x10000000U
#define PMC_PCSR_PID28 0x10000000U
#define PMC_PCSR_PID28_BIT 28
#define PMC_PCSR_PID29_MASK 0x20000000U
#define PMC_PCSR_PID29 0x20000000U
#define PMC_PCSR_PID29_BIT 29
#define PMC_PCSR_PID30_MASK 0x40000000U
#define PMC_PCSR_PID30 0x40000000U
#define PMC_PCSR_PID30_BIT 30
#define PMC_PCSR_PID31_MASK 0x80000000U
#define PMC_PCSR_PID31 0x80000000U
#define PMC_PCSR_PID31_BIT 31

#define CKGR_MOR (*(volatile unsigned long *)0xFFFFFC20)
#define CKGR_MOR_OFFSET 0x20
#define CKGR_MOR_MOSCEN_MASK 0x1U
#define CKGR_MOR_MOSCEN 0x1U
#define CKGR_MOR_MOSCEN_BIT 0
#define CKGR_MOR_OSCBYPASS_MASK 0x2U
#define CKGR_MOR_OSCBYPASS 0x2U
#define CKGR_MOR_OSCBYPASS_BIT 1
#define CKGR_MOR_OSCOUNT_MASK 0xFF00U
#define CKGR_MOR_OSCOUNT_BIT 8

#define CKGR_MCFR (*(volatile unsigned long *)0xFFFFFC24)
#define CKGR_MCFR_OFFSET 0x24
#define CKGR_MCFR_MAINF_MASK 0xFFFFU
#define CKGR_MCFR_MAINF_BIT 0
#define CKGR_MCFR_MAINRDY_MASK 0x10000U
#define CKGR_MCFR_MAINRDY 0x10000U
#define CKGR_MCFR_MAINRDY_BIT 16

#define CKGR_PLLR (*(volatile unsigned long *)0xFFFFFC2C)
#define CKGR_PLLR_OFFSET 0x2C
#define CKGR_PLLR_DIV_MASK 0xFFU
#define CKGR_PLLR_DIV_BIT 0
#define CKGR_PLLR_PLLCOUNT_MASK 0x3F00U
#define CKGR_PLLR_PLLCOUNT_BIT 8
#define CKGR_PLLR_OUT_MASK 0xC000U
#define CKGR_PLLR_OUT_BIT 14
#define CKGR_PLLR_MUL_MASK 0x7FF0000U
#define CKGR_PLLR_MUL_BIT 16
#define CKGR_PLLR_USBDIV_MASK 0x30000000U
#define CKGR_PLLR_USBDIV_BIT 28

#define PMC_MCKR (*(volatile unsigned long *)0xFFFFFC30)
#define PMC_MCKR_OFFSET 0x30
#define PMC_MCKR_CSS_MASK 0x3U
#define PMC_MCKR_CSS_BIT 0
#define PMC_MCKR_PRES_MASK 0x1CU
#define PMC_MCKR_PRES_BIT 2

#define PMC_PCK0 (*(volatile unsigned long *)0xFFFFFC40)
#define PMC_PCK0_OFFSET 0x40
#define PMC_PCK0_CSS_MASK 0x3U
#define PMC_PCK0_CSS_BIT 0
#define PMC_PCK0_PRES_MASK 0x1CU
#define PMC_PCK0_PRES_BIT 2

#define PMC_PCK1 (*(volatile unsigned long *)0xFFFFFC44)
#define PMC_PCK1_OFFSET 0x44
#define PMC_PCK1_CSS_MASK 0x3U
#define PMC_PCK1_CSS_BIT 0
#define PMC_PCK1_PRES_MASK 0x1CU
#define PMC_PCK1_PRES_BIT 2

#define PMC_IER (*(volatile unsigned long *)0xFFFFFC60)
#define PMC_IER_OFFSET 0x60
#define PMC_IER_MOSCS_MASK 0x1U
#define PMC_IER_MOSCS 0x1U
#define PMC_IER_MOSCS_BIT 0
#define PMC_IER_LOCK_MASK 0x4U
#define PMC_IER_LOCK 0x4U
#define PMC_IER_LOCK_BIT 2
#define PMC_IER_MCKRDY_MASK 0x8U
#define PMC_IER_MCKRDY 0x8U
#define PMC_IER_MCKRDY_BIT 3
#define PMC_IER_PCKRDY0_MASK 0x100U
#define PMC_IER_PCKRDY0 0x100U
#define PMC_IER_PCKRDY0_BIT 8
#define PMC_IER_PCKRDY1_MASK 0x200U
#define PMC_IER_PCKRDY1 0x200U
#define PMC_IER_PCKRDY1_BIT 9
#define PMC_IER_PCKRDY2_MASK 0x400U
#define PMC_IER_PCKRDY2 0x400U
#define PMC_IER_PCKRDY2_BIT 10
#define PMC_IER_PCKRDY3_MASK 0x800U
#define PMC_IER_PCKRDY3 0x800U
#define PMC_IER_PCKRDY3_BIT 11

#define PMC_IDR (*(volatile unsigned long *)0xFFFFFC64)
#define PMC_IDR_OFFSET 0x64
#define PMC_IDR_MOSCS_MASK 0x1U
#define PMC_IDR_MOSCS 0x1U
#define PMC_IDR_MOSCS_BIT 0
#define PMC_IDR_LOCK_MASK 0x4U
#define PMC_IDR_LOCK 0x4U
#define PMC_IDR_LOCK_BIT 2
#define PMC_IDR_MCKRDY_MASK 0x8U
#define PMC_IDR_MCKRDY 0x8U
#define PMC_IDR_MCKRDY_BIT 3
#define PMC_IDR_PCKRDY0_MASK 0x100U
#define PMC_IDR_PCKRDY0 0x100U
#define PMC_IDR_PCKRDY0_BIT 8
#define PMC_IDR_PCKRDY1_MASK 0x200U
#define PMC_IDR_PCKRDY1 0x200U
#define PMC_IDR_PCKRDY1_BIT 9
#define PMC_IDR_PCKRDY2_MASK 0x400U
#define PMC_IDR_PCKRDY2 0x400U
#define PMC_IDR_PCKRDY2_BIT 10
#define PMC_IDR_PCKRDY3_MASK 0x800U
#define PMC_IDR_PCKRDY3 0x800U
#define PMC_IDR_PCKRDY3_BIT 11

#define PMC_SR (*(volatile unsigned long *)0xFFFFFC68)
#define PMC_SR_OFFSET 0x68
#define PMC_SR_MOSCS_MASK 0x1U
#define PMC_SR_MOSCS 0x1U
#define PMC_SR_MOSCS_BIT 0
#define PMC_SR_LOCK_MASK 0x4U
#define PMC_SR_LOCK 0x4U
#define PMC_SR_LOCK_BIT 2
#define PMC_SR_MCKRDY_MASK 0x8U
#define PMC_SR_MCKRDY 0x8U
#define PMC_SR_MCKRDY_BIT 3
#define PMC_SR_PCKRDY0_MASK 0x100U
#define PMC_SR_PCKRDY0 0x100U
#define PMC_SR_PCKRDY0_BIT 8
#define PMC_SR_PCKRDY1_MASK 0x200U
#define PMC_SR_PCKRDY1 0x200U
#define PMC_SR_PCKRDY1_BIT 9
#define PMC_SR_PCKRDY2_MASK 0x400U
#define PMC_SR_PCKRDY2 0x400U
#define PMC_SR_PCKRDY2_BIT 10
#define PMC_SR_PCKRDY3_MASK 0x800U
#define PMC_SR_PCKRDY3 0x800U
#define PMC_SR_PCKRDY3_BIT 11

#define PMC_IMR (*(volatile unsigned long *)0xFFFFFC6C)
#define PMC_IMR_OFFSET 0x6C
#define PMC_IMR_MOSCS_MASK 0x1U
#define PMC_IMR_MOSCS 0x1U
#define PMC_IMR_MOSCS_BIT 0
#define PMC_IMR_LOCK_MASK 0x4U
#define PMC_IMR_LOCK 0x4U
#define PMC_IMR_LOCK_BIT 2
#define PMC_IMR_MCKRDY_MASK 0x8U
#define PMC_IMR_MCKRDY 0x8U
#define PMC_IMR_MCKRDY_BIT 3
#define PMC_IMR_PCKRDY0_MASK 0x100U
#define PMC_IMR_PCKRDY0 0x100U
#define PMC_IMR_PCKRDY0_BIT 8
#define PMC_IMR_PCKRDY1_MASK 0x200U
#define PMC_IMR_PCKRDY1 0x200U
#define PMC_IMR_PCKRDY1_BIT 9
#define PMC_IMR_PCKRDY2_MASK 0x400U
#define PMC_IMR_PCKRDY2 0x400U
#define PMC_IMR_PCKRDY2_BIT 10
#define PMC_IMR_PCKRDY3_MASK 0x800U
#define PMC_IMR_PCKRDY3 0x800U
#define PMC_IMR_PCKRDY3_BIT 11

#define RSTC_BASE 0xFFFFFD00

#define RSTC_CR (*(volatile unsigned long *)0xFFFFFD00)
#define RSTC_CR_OFFSET 0x0
#define RSTC_CR_PROCRST_MASK 0x1U
#define RSTC_CR_PROCRST 0x1U
#define RSTC_CR_PROCRST_BIT 0
#define RSTC_CR_PERRST_MASK 0x4U
#define RSTC_CR_PERRST 0x4U
#define RSTC_CR_PERRST_BIT 2
#define RSTC_CR_EXTRST_MASK 0x8U
#define RSTC_CR_EXTRST 0x8U
#define RSTC_CR_EXTRST_BIT 3
#define RSTC_CR_KEY_MASK 0xFF000000U
#define RSTC_CR_KEY_BIT 24

#define RSTC_SR (*(volatile unsigned long *)0xFFFFFD04)
#define RSTC_SR_OFFSET 0x4
#define RSTC_SR_URSTS_MASK 0x1U
#define RSTC_SR_URSTS 0x1U
#define RSTC_SR_URSTS_BIT 0
#define RSTC_SR_BODSTS_MASK 0x2U
#define RSTC_SR_BODSTS 0x2U
#define RSTC_SR_BODSTS_BIT 1
#define RSTC_SR_RSTTYP_MASK 0x700U
#define RSTC_SR_RSTTYP_BIT 8
#define RSTC_SR_NRSTL_MASK 0x10000U
#define RSTC_SR_NRSTL 0x10000U
#define RSTC_SR_NRSTL_BIT 16
#define RSTC_SR_SRCMP_MASK 0x20000U
#define RSTC_SR_SRCMP 0x20000U
#define RSTC_SR_SRCMP_BIT 17

#define RSTC_MR (*(volatile unsigned long *)0xFFFFFD08)
#define RSTC_MR_OFFSET 0x8
#define RSTC_MR_URSTEN_MASK 0x1U
#define RSTC_MR_URSTEN 0x1U
#define RSTC_MR_URSTEN_BIT 0
#define RSTC_MR_URSTIEN_MASK 0x10U
#define RSTC_MR_URSTIEN 0x10U
#define RSTC_MR_URSTIEN_BIT 4
#define RSTC_MR_ERSTL_MASK 0xF00U
#define RSTC_MR_ERSTL_BIT 8
#define RSTC_MR_BODIEN_MASK 0x10000U
#define RSTC_MR_BODIEN 0x10000U
#define RSTC_MR_BODIEN_BIT 16
#define RSTC_MR_KEY_MASK 0xFF000000U
#define RSTC_MR_KEY_BIT 24

#define RTT_BASE 0xFFFFFD20

#define RTT_MR (*(volatile unsigned long *)0xFFFFFD20)
#define RTT_MR_OFFSET 0x0
#define RTT_MR_RTPRES_MASK 0xFFFFU
#define RTT_MR_RTPRES_BIT 0
#define RTT_MR_ALMIEN_MASK 0x10000U
#define RTT_MR_ALMIEN 0x10000U
#define RTT_MR_ALMIEN_BIT 16
#define RTT_MR_RTTINCIEN_MASK 0x20000U
#define RTT_MR_RTTINCIEN 0x20000U
#define RTT_MR_RTTINCIEN_BIT 17
#define RTT_MR_RTTRST_MASK 0x40000U
#define RTT_MR_RTTRST 0x40000U
#define RTT_MR_RTTRST_BIT 18

#define RTT_AR (*(volatile unsigned long *)0xFFFFFD24)
#define RTT_AR_OFFSET 0x4

#define RTT_VR (*(volatile unsigned long *)0xFFFFFD28)
#define RTT_VR_OFFSET 0x8

#define RTT_SR (*(volatile unsigned long *)0xFFFFFD2C)
#define RTT_SR_OFFSET 0xC
#define RTT_SR_ALMS_MASK 0x1U
#define RTT_SR_ALMS 0x1U
#define RTT_SR_ALMS_BIT 0
#define RTT_SR_RTTINC_MASK 0x2U
#define RTT_SR_RTTINC 0x2U
#define RTT_SR_RTTINC_BIT 1

#define PIT_BASE 0xFFFFFD30

#define PIT_MR (*(volatile unsigned long *)0xFFFFFD30)
#define PIT_MR_OFFSET 0x0
#define PIT_MR_PIV_MASK 0xFFFFFFU
#define PIT_MR_PIV_BIT 0
#define PIT_MR_PITEN_MASK 0x1000000U
#define PIT_MR_PITEN 0x1000000U
#define PIT_MR_PITEN_BIT 24
#define PIT_MR_PITIEN_MASK 0x2000000U
#define PIT_MR_PITIEN 0x2000000U
#define PIT_MR_PITIEN_BIT 25

#define PIT_SR (*(volatile unsigned long *)0xFFFFFD34)
#define PIT_SR_OFFSET 0x4

#define PIT_PIVR (*(volatile unsigned long *)0xFFFFFD38)
#define PIT_PIVR_OFFSET 0x8
#define PIT_PIVR_CPIV_MASK 0xFFFFFU
#define PIT_PIVR_CPIV_BIT 0
#define PIT_PIVR_PICNT_MASK 0xFFF00000U
#define PIT_PIVR_PICNT_BIT 20

#define PIT_PIIR (*(volatile unsigned long *)0xFFFFFD3C)
#define PIT_PIIR_OFFSET 0xC
#define PIT_PIIR_CPIV_MASK 0xFFFFFU
#define PIT_PIIR_CPIV_BIT 0
#define PIT_PIIR_PICNT_MASK 0xFFF00000U
#define PIT_PIIR_PICNT_BIT 20

#define WDT_BASE 0xFFFFFD40

#define WDT_CR (*(volatile unsigned long *)0xFFFFFD40)
#define WDT_CR_OFFSET 0x0
#define WDT_CR_WDRSTT_MASK 0x1U
#define WDT_CR_WDRSTT 0x1U
#define WDT_CR_WDRSTT_BIT 0
#define WDT_CR_KEY_MASK 0xFF000000U
#define WDT_CR_KEY_BIT 24

#define WDT_MR (*(volatile unsigned long *)0xFFFFFD44)
#define WDT_MR_OFFSET 0x4
#define WDT_MR_WDV_MASK 0xFFFU
#define WDT_MR_WDV_BIT 0
#define WDT_MR_WDFIEN_MASK 0x1000U
#define WDT_MR_WDFIEN 0x1000U
#define WDT_MR_WDFIEN_BIT 12
#define WDT_MR_WDRSTEN_MASK 0x2000U
#define WDT_MR_WDRSTEN 0x2000U
#define WDT_MR_WDRSTEN_BIT 13
#define WDT_MR_WDRPROC_MASK 0x4000U
#define WDT_MR_WDRPROC 0x4000U
#define WDT_MR_WDRPROC_BIT 14
#define WDT_MR_WDDIS_MASK 0x8000U
#define WDT_MR_WDDIS 0x8000U
#define WDT_MR_WDDIS_BIT 15
#define WDT_MR_WDD_MASK 0xFFF0000U
#define WDT_MR_WDD_BIT 16
#define WDT_MR_WDDBGHLT_MASK 0x10000000U
#define WDT_MR_WDDBGHLT 0x10000000U
#define WDT_MR_WDDBGHLT_BIT 28
#define WDT_MR_WDIDLEHLT_MASK 0x20000000U
#define WDT_MR_WDIDLEHLT 0x20000000U
#define WDT_MR_WDIDLEHLT_BIT 29

#define WDT_SR (*(volatile unsigned long *)0xFFFFFD48)
#define WDT_SR_OFFSET 0x8
#define WDT_SR_WDUNF_MASK 0x1U
#define WDT_SR_WDUNF 0x1U
#define WDT_SR_WDUNF_BIT 0
#define WDT_SR_WDERR_MASK 0x2U
#define WDT_SR_WDERR 0x2U
#define WDT_SR_WDERR_BIT 1

#define VREG_BASE 0xFFFFFD60

#define WREG_MR (*(volatile unsigned long *)0xFFFFFD60)
#define WREG_MR_OFFSET 0x0

#define MC_BASE 0xFFFFFF00

#define MC_RCR (*(volatile unsigned long *)0xFFFFFF00)
#define MC_RCR_OFFSET 0x0

#define MC_ASR (*(volatile unsigned long *)0xFFFFFF04)
#define MC_ASR_OFFSET 0x4
#define MC_ASR_UNDADD_MASK 0x1U
#define MC_ASR_UNDADD 0x1U
#define MC_ASR_UNDADD_BIT 0
#define MC_ASR_MISADD_MASK 0x2U
#define MC_ASR_MISADD 0x2U
#define MC_ASR_MISADD_BIT 1
#define MC_ASR_ABTSZ_MASK 0x300U
#define MC_ASR_ABTSZ_BIT 8
#define MC_ASR_ABTTYP_MASK 0xC00U
#define MC_ASR_ABTTYP_BIT 10
#define MC_ASR_MST0_MASK 0x10000U
#define MC_ASR_MST0 0x10000U
#define MC_ASR_MST0_BIT 16
#define MC_ASR_MST1_MASK 0x20000U
#define MC_ASR_MST1 0x20000U
#define MC_ASR_MST1_BIT 17
#define MC_ASR_SVMST0_MASK 0x1000000U
#define MC_ASR_SVMST0 0x1000000U
#define MC_ASR_SVMST0_BIT 24
#define MC_ASR_SVMST1_MASK 0x2000000U
#define MC_ASR_SVMST1 0x2000000U
#define MC_ASR_SVMST1_BIT 25

#define MC_AASR (*(volatile unsigned long *)0xFFFFFF08)
#define MC_AASR_OFFSET 0x8

#define MC_FMR (*(volatile unsigned long *)0xFFFFFF60)
#define MC_FMR_OFFSET 0x60
#define MC_FMR_FRDY_MASK 0x1U
#define MC_FMR_FRDY 0x1U
#define MC_FMR_FRDY_BIT 0
#define MC_FMR_LOCKE_MASK 0x4U
#define MC_FMR_LOCKE 0x4U
#define MC_FMR_LOCKE_BIT 2
#define MC_FMR_PROGE_MASK 0x8U
#define MC_FMR_PROGE 0x8U
#define MC_FMR_PROGE_BIT 3
#define MC_FMR_NEBP_MASK 0x80U
#define MC_FMR_NEBP 0x80U
#define MC_FMR_NEBP_BIT 7
#define MC_FMR_FWS_MASK 0x300U
#define MC_FMR_FWS_BIT 8
#define MC_FMR_FMCN_MASK 0xFFFF0000U
#define MC_FMR_FMCN_BIT 16

#define MC_FCR (*(volatile unsigned long *)0xFFFFFF64)
#define MC_FCR_OFFSET 0x64
#define MC_FCR_FCMD_MASK 0xFU
#define MC_FCR_FCMD_BIT 0
#define MC_FCR_PAGEN_MASK 0x3FF00U
#define MC_FCR_PAGEN_BIT 8
#define MC_FCR_KEY_MASK 0xFF000000U
#define MC_FCR_KEY_BIT 24

#define MC_FSR (*(volatile unsigned long *)0xFFFFFF68)
#define MC_FSR_OFFSET 0x68
#define MC_FSR_FRDY_MASK 0x1U
#define MC_FSR_FRDY 0x1U
#define MC_FSR_FRDY_BIT 0
#define MC_FSR_LOCKE_MASK 0x4U
#define MC_FSR_LOCKE 0x4U
#define MC_FSR_LOCKE_BIT 2
#define MC_FSR_PROGE_MASK 0x8U
#define MC_FSR_PROGE 0x8U
#define MC_FSR_PROGE_BIT 3
#define MC_FSR_SECURITY_MASK 0x10U
#define MC_FSR_SECURITY 0x10U
#define MC_FSR_SECURITY_BIT 4
#define MC_FSR_GPNVM0_MASK 0x100U
#define MC_FSR_GPNVM0 0x100U
#define MC_FSR_GPNVM0_BIT 8
#define MC_FSR_GPNVM1_MASK 0x200U
#define MC_FSR_GPNVM1 0x200U
#define MC_FSR_GPNVM1_BIT 9
#define MC_FSR_LOCKS0_MASK 0x10000U
#define MC_FSR_LOCKS0 0x10000U
#define MC_FSR_LOCKS0_BIT 16
#define MC_FSR_LOCKS1_MASK 0x20000U
#define MC_FSR_LOCKS1 0x20000U
#define MC_FSR_LOCKS1_BIT 17
#define MC_FSR_LOCKS2_MASK 0x40000U
#define MC_FSR_LOCKS2 0x40000U
#define MC_FSR_LOCKS2_BIT 18
#define MC_FSR_LOCKS3_MASK 0x80000U
#define MC_FSR_LOCKS3 0x80000U
#define MC_FSR_LOCKS3_BIT 19
#define MC_FSR_LOCKS4_MASK 0x100000U
#define MC_FSR_LOCKS4 0x100000U
#define MC_FSR_LOCKS4_BIT 20
#define MC_FSR_LOCKS5_MASK 0x200000U
#define MC_FSR_LOCKS5 0x200000U
#define MC_FSR_LOCKS5_BIT 21
#define MC_FSR_LOCKS6_MASK 0x400000U
#define MC_FSR_LOCKS6 0x400000U
#define MC_FSR_LOCKS6_BIT 22
#define MC_FSR_LOCKS7_MASK 0x800000U
#define MC_FSR_LOCKS7 0x800000U
#define MC_FSR_LOCKS7_BIT 23
#define MC_FSR_LOCKS8_MASK 0x1000000U
#define MC_FSR_LOCKS8 0x1000000U
#define MC_FSR_LOCKS8_BIT 24
#define MC_FSR_LOCKS9_MASK 0x2000000U
#define MC_FSR_LOCKS9 0x2000000U
#define MC_FSR_LOCKS9_BIT 25
#define MC_FSR_LOCKS10_MASK 0x4000000U
#define MC_FSR_LOCKS10 0x4000000U
#define MC_FSR_LOCKS10_BIT 26
#define MC_FSR_LOCKS11_MASK 0x8000000U
#define MC_FSR_LOCKS11 0x8000000U
#define MC_FSR_LOCKS11_BIT 27
#define MC_FSR_LOCKS12_MASK 0x10000000U
#define MC_FSR_LOCKS12 0x10000000U
#define MC_FSR_LOCKS12_BIT 28
#define MC_FSR_LOCKS13_MASK 0x20000000U
#define MC_FSR_LOCKS13 0x20000000U
#define MC_FSR_LOCKS13_BIT 29
#define MC_FSR_LOCKS14_MASK 0x40000000U
#define MC_FSR_LOCKS14 0x40000000U
#define MC_FSR_LOCKS14_BIT 30
#define MC_FSR_LOCKS15_MASK 0x80000000U
#define MC_FSR_LOCKS15 0x80000000U
#define MC_FSR_LOCKS15_BIT 31

#define TC012_BASE 0xFFFA0000

#define TC0_CCR (*(volatile unsigned long *)0xFFFA0000)
#define TC0_CCR_OFFSET 0x0
#define TC0_CCR_CLKEN_MASK 0x1U
#define TC0_CCR_CLKEN 0x1U
#define TC0_CCR_CLKEN_BIT 0
#define TC0_CCR_CLKDIS_MASK 0x2U
#define TC0_CCR_CLKDIS 0x2U
#define TC0_CCR_CLKDIS_BIT 1
#define TC0_CCR_SWTRG_MASK 0x4U
#define TC0_CCR_SWTRG 0x4U
#define TC0_CCR_SWTRG_BIT 2

#define TC0_CMR (*(volatile unsigned long *)0xFFFA0004)
#define TC0_CMR_OFFSET 0x4
#define TC0_CMR_TCCLKS_MASK 0x7U
#define TC0_CMR_TCCLKS_BIT 0
#define TC0_CMR_CLKI_MASK 0x8U
#define TC0_CMR_CLKI 0x8U
#define TC0_CMR_CLKI_BIT 3
#define TC0_CMR_BURST_MASK 0x30U
#define TC0_CMR_BURST_BIT 4
#define TC0_CMR_LDBSTOP_MASK 0x40U
#define TC0_CMR_LDBSTOP 0x40U
#define TC0_CMR_LDBSTOP_BIT 6
#define TC0_CMR_LDBDIS_MASK 0x80U
#define TC0_CMR_LDBDIS 0x80U
#define TC0_CMR_LDBDIS_BIT 7
#define TC0_CMR_ETRGEDG_MASK 0x300U
#define TC0_CMR_ETRGEDG_BIT 8
#define TC0_CMR_ABETRG_MASK 0x400U
#define TC0_CMR_ABETRG 0x400U
#define TC0_CMR_ABETRG_BIT 10
#define TC0_CMR_CPCTRG_MASK 0x4000U
#define TC0_CMR_CPCTRG 0x4000U
#define TC0_CMR_CPCTRG_BIT 14
#define TC0_CMR_WAVE_MASK 0x8000U
#define TC0_CMR_WAVE 0x8000U
#define TC0_CMR_WAVE_BIT 15
#define TC0_CMR_LDRA_MASK 0x30000U
#define TC0_CMR_LDRA_BIT 16
#define TC0_CMR_LDRB_MASK 0xC0000U
#define TC0_CMR_LDRB_BIT 18

#define TC0_CV (*(volatile unsigned long *)0xFFFA0010)
#define TC0_CV_OFFSET 0x10

#define TC0_RA (*(volatile unsigned long *)0xFFFA0014)
#define TC0_RA_OFFSET 0x14

#define TC0_RB (*(volatile unsigned long *)0xFFFA0018)
#define TC0_RB_OFFSET 0x18

#define TC0_RC (*(volatile unsigned long *)0xFFFA001C)
#define TC0_RC_OFFSET 0x1C

#define TC0_SR (*(volatile unsigned long *)0xFFFA0020)
#define TC0_SR_OFFSET 0x20
#define TC0_SR_COVFS_MASK 0x1U
#define TC0_SR_COVFS 0x1U
#define TC0_SR_COVFS_BIT 0
#define TC0_SR_LOVRS_MASK 0x2U
#define TC0_SR_LOVRS 0x2U
#define TC0_SR_LOVRS_BIT 1
#define TC0_SR_CPAS_MASK 0x4U
#define TC0_SR_CPAS 0x4U
#define TC0_SR_CPAS_BIT 2
#define TC0_SR_CPBS_MASK 0x8U
#define TC0_SR_CPBS 0x8U
#define TC0_SR_CPBS_BIT 3
#define TC0_SR_CPCS_MASK 0x10U
#define TC0_SR_CPCS 0x10U
#define TC0_SR_CPCS_BIT 4
#define TC0_SR_LDRAS_MASK 0x20U
#define TC0_SR_LDRAS 0x20U
#define TC0_SR_LDRAS_BIT 5
#define TC0_SR_LDRBS_MASK 0x40U
#define TC0_SR_LDRBS 0x40U
#define TC0_SR_LDRBS_BIT 6
#define TC0_SR_ETRGS_MASK 0x80U
#define TC0_SR_ETRGS 0x80U
#define TC0_SR_ETRGS_BIT 7
#define TC0_SR_CLKSTA_MASK 0x10000U
#define TC0_SR_CLKSTA 0x10000U
#define TC0_SR_CLKSTA_BIT 16
#define TC0_SR_MTIOA_MASK 0x20000U
#define TC0_SR_MTIOA 0x20000U
#define TC0_SR_MTIOA_BIT 17
#define TC0_SR_MTIOB_MASK 0x40000U
#define TC0_SR_MTIOB 0x40000U
#define TC0_SR_MTIOB_BIT 18

#define TC0_IER (*(volatile unsigned long *)0xFFFA0024)
#define TC0_IER_OFFSET 0x24
#define TC0_IER_COVFS_MASK 0x1U
#define TC0_IER_COVFS 0x1U
#define TC0_IER_COVFS_BIT 0
#define TC0_IER_LOVRS_MASK 0x2U
#define TC0_IER_LOVRS 0x2U
#define TC0_IER_LOVRS_BIT 1
#define TC0_IER_CPAS_MASK 0x4U
#define TC0_IER_CPAS 0x4U
#define TC0_IER_CPAS_BIT 2
#define TC0_IER_CPBS_MASK 0x8U
#define TC0_IER_CPBS 0x8U
#define TC0_IER_CPBS_BIT 3
#define TC0_IER_CPCS_MASK 0x10U
#define TC0_IER_CPCS 0x10U
#define TC0_IER_CPCS_BIT 4
#define TC0_IER_LDRAS_MASK 0x20U
#define TC0_IER_LDRAS 0x20U
#define TC0_IER_LDRAS_BIT 5
#define TC0_IER_LDRBS_MASK 0x40U
#define TC0_IER_LDRBS 0x40U
#define TC0_IER_LDRBS_BIT 6
#define TC0_IER_ETRGS_MASK 0x80U
#define TC0_IER_ETRGS 0x80U
#define TC0_IER_ETRGS_BIT 7

#define TC0_IDR (*(volatile unsigned long *)0xFFFA0028)
#define TC0_IDR_OFFSET 0x28
#define TC0_IDR_COVFS_MASK 0x1U
#define TC0_IDR_COVFS 0x1U
#define TC0_IDR_COVFS_BIT 0
#define TC0_IDR_LOVRS_MASK 0x2U
#define TC0_IDR_LOVRS 0x2U
#define TC0_IDR_LOVRS_BIT 1
#define TC0_IDR_CPAS_MASK 0x4U
#define TC0_IDR_CPAS 0x4U
#define TC0_IDR_CPAS_BIT 2
#define TC0_IDR_CPBS_MASK 0x8U
#define TC0_IDR_CPBS 0x8U
#define TC0_IDR_CPBS_BIT 3
#define TC0_IDR_CPCS_MASK 0x10U
#define TC0_IDR_CPCS 0x10U
#define TC0_IDR_CPCS_BIT 4
#define TC0_IDR_LDRAS_MASK 0x20U
#define TC0_IDR_LDRAS 0x20U
#define TC0_IDR_LDRAS_BIT 5
#define TC0_IDR_LDRBS_MASK 0x40U
#define TC0_IDR_LDRBS 0x40U
#define TC0_IDR_LDRBS_BIT 6
#define TC0_IDR_ETRGS_MASK 0x80U
#define TC0_IDR_ETRGS 0x80U
#define TC0_IDR_ETRGS_BIT 7

#define TC0_IMR (*(volatile unsigned long *)0xFFFA002C)
#define TC0_IMR_OFFSET 0x2C
#define TC0_IMR_COVFS_MASK 0x1U
#define TC0_IMR_COVFS 0x1U
#define TC0_IMR_COVFS_BIT 0
#define TC0_IMR_LOVRS_MASK 0x2U
#define TC0_IMR_LOVRS 0x2U
#define TC0_IMR_LOVRS_BIT 1
#define TC0_IMR_CPAS_MASK 0x4U
#define TC0_IMR_CPAS 0x4U
#define TC0_IMR_CPAS_BIT 2
#define TC0_IMR_CPBS_MASK 0x8U
#define TC0_IMR_CPBS 0x8U
#define TC0_IMR_CPBS_BIT 3
#define TC0_IMR_CPCS_MASK 0x10U
#define TC0_IMR_CPCS 0x10U
#define TC0_IMR_CPCS_BIT 4
#define TC0_IMR_LDRAS_MASK 0x20U
#define TC0_IMR_LDRAS 0x20U
#define TC0_IMR_LDRAS_BIT 5
#define TC0_IMR_LDRBS_MASK 0x40U
#define TC0_IMR_LDRBS 0x40U
#define TC0_IMR_LDRBS_BIT 6
#define TC0_IMR_ETRGS_MASK 0x80U
#define TC0_IMR_ETRGS 0x80U
#define TC0_IMR_ETRGS_BIT 7

#define TC1_CCR (*(volatile unsigned long *)0xFFFA0040)
#define TC1_CCR_OFFSET 0x40
#define TC1_CCR_CLKEN_MASK 0x1U
#define TC1_CCR_CLKEN 0x1U
#define TC1_CCR_CLKEN_BIT 0
#define TC1_CCR_CLKDIS_MASK 0x2U
#define TC1_CCR_CLKDIS 0x2U
#define TC1_CCR_CLKDIS_BIT 1
#define TC1_CCR_SWTRG_MASK 0x4U
#define TC1_CCR_SWTRG 0x4U
#define TC1_CCR_SWTRG_BIT 2

#define TC1_CMR (*(volatile unsigned long *)0xFFFA0044)
#define TC1_CMR_OFFSET 0x44
#define TC1_CMR_TCCLKS_MASK 0x7U
#define TC1_CMR_TCCLKS_BIT 0
#define TC1_CMR_CLKI_MASK 0x8U
#define TC1_CMR_CLKI 0x8U
#define TC1_CMR_CLKI_BIT 3
#define TC1_CMR_BURST_MASK 0x30U
#define TC1_CMR_BURST_BIT 4
#define TC1_CMR_LDBSTOP_MASK 0x40U
#define TC1_CMR_LDBSTOP 0x40U
#define TC1_CMR_LDBSTOP_BIT 6
#define TC1_CMR_LDBDIS_MASK 0x80U
#define TC1_CMR_LDBDIS 0x80U
#define TC1_CMR_LDBDIS_BIT 7
#define TC1_CMR_ETRGEDG_MASK 0x300U
#define TC1_CMR_ETRGEDG_BIT 8
#define TC1_CMR_ABETRG_MASK 0x400U
#define TC1_CMR_ABETRG 0x400U
#define TC1_CMR_ABETRG_BIT 10
#define TC1_CMR_CPCTRG_MASK 0x4000U
#define TC1_CMR_CPCTRG 0x4000U
#define TC1_CMR_CPCTRG_BIT 14
#define TC1_CMR_WAVE_MASK 0x8000U
#define TC1_CMR_WAVE 0x8000U
#define TC1_CMR_WAVE_BIT 15
#define TC1_CMR_LDRA_MASK 0x30000U
#define TC1_CMR_LDRA_BIT 16
#define TC1_CMR_LDRB_MASK 0xC0000U
#define TC1_CMR_LDRB_BIT 18

#define TC1_CV (*(volatile unsigned long *)0xFFFA0050)
#define TC1_CV_OFFSET 0x50

#define TC1_RA (*(volatile unsigned long *)0xFFFA0054)
#define TC1_RA_OFFSET 0x54

#define TC1_RB (*(volatile unsigned long *)0xFFFA0058)
#define TC1_RB_OFFSET 0x58

#define TC1_RC (*(volatile unsigned long *)0xFFFA005C)
#define TC1_RC_OFFSET 0x5C

#define TC1_SR (*(volatile unsigned long *)0xFFFA0060)
#define TC1_SR_OFFSET 0x60
#define TC1_SR_COVFS_MASK 0x1U
#define TC1_SR_COVFS 0x1U
#define TC1_SR_COVFS_BIT 0
#define TC1_SR_LOVRS_MASK 0x2U
#define TC1_SR_LOVRS 0x2U
#define TC1_SR_LOVRS_BIT 1
#define TC1_SR_CPAS_MASK 0x4U
#define TC1_SR_CPAS 0x4U
#define TC1_SR_CPAS_BIT 2
#define TC1_SR_CPBS_MASK 0x8U
#define TC1_SR_CPBS 0x8U
#define TC1_SR_CPBS_BIT 3
#define TC1_SR_CPCS_MASK 0x10U
#define TC1_SR_CPCS 0x10U
#define TC1_SR_CPCS_BIT 4
#define TC1_SR_LDRAS_MASK 0x20U
#define TC1_SR_LDRAS 0x20U
#define TC1_SR_LDRAS_BIT 5
#define TC1_SR_LDRBS_MASK 0x40U
#define TC1_SR_LDRBS 0x40U
#define TC1_SR_LDRBS_BIT 6
#define TC1_SR_ETRGS_MASK 0x80U
#define TC1_SR_ETRGS 0x80U
#define TC1_SR_ETRGS_BIT 7
#define TC1_SR_CLKSTA_MASK 0x10000U
#define TC1_SR_CLKSTA 0x10000U
#define TC1_SR_CLKSTA_BIT 16
#define TC1_SR_MTIOA_MASK 0x20000U
#define TC1_SR_MTIOA 0x20000U
#define TC1_SR_MTIOA_BIT 17
#define TC1_SR_MTIOB_MASK 0x40000U
#define TC1_SR_MTIOB 0x40000U
#define TC1_SR_MTIOB_BIT 18

#define TC1_IER (*(volatile unsigned long *)0xFFFA0064)
#define TC1_IER_OFFSET 0x64
#define TC1_IER_COVFS_MASK 0x1U
#define TC1_IER_COVFS 0x1U
#define TC1_IER_COVFS_BIT 0
#define TC1_IER_LOVRS_MASK 0x2U
#define TC1_IER_LOVRS 0x2U
#define TC1_IER_LOVRS_BIT 1
#define TC1_IER_CPAS_MASK 0x4U
#define TC1_IER_CPAS 0x4U
#define TC1_IER_CPAS_BIT 2
#define TC1_IER_CPBS_MASK 0x8U
#define TC1_IER_CPBS 0x8U
#define TC1_IER_CPBS_BIT 3
#define TC1_IER_CPCS_MASK 0x10U
#define TC1_IER_CPCS 0x10U
#define TC1_IER_CPCS_BIT 4
#define TC1_IER_LDRAS_MASK 0x20U
#define TC1_IER_LDRAS 0x20U
#define TC1_IER_LDRAS_BIT 5
#define TC1_IER_LDRBS_MASK 0x40U
#define TC1_IER_LDRBS 0x40U
#define TC1_IER_LDRBS_BIT 6
#define TC1_IER_ETRGS_MASK 0x80U
#define TC1_IER_ETRGS 0x80U
#define TC1_IER_ETRGS_BIT 7

#define TC1_IDR (*(volatile unsigned long *)0xFFFA0068)
#define TC1_IDR_OFFSET 0x68
#define TC1_IDR_COVFS_MASK 0x1U
#define TC1_IDR_COVFS 0x1U
#define TC1_IDR_COVFS_BIT 0
#define TC1_IDR_LOVRS_MASK 0x2U
#define TC1_IDR_LOVRS 0x2U
#define TC1_IDR_LOVRS_BIT 1
#define TC1_IDR_CPAS_MASK 0x4U
#define TC1_IDR_CPAS 0x4U
#define TC1_IDR_CPAS_BIT 2
#define TC1_IDR_CPBS_MASK 0x8U
#define TC1_IDR_CPBS 0x8U
#define TC1_IDR_CPBS_BIT 3
#define TC1_IDR_CPCS_MASK 0x10U
#define TC1_IDR_CPCS 0x10U
#define TC1_IDR_CPCS_BIT 4
#define TC1_IDR_LDRAS_MASK 0x20U
#define TC1_IDR_LDRAS 0x20U
#define TC1_IDR_LDRAS_BIT 5
#define TC1_IDR_LDRBS_MASK 0x40U
#define TC1_IDR_LDRBS 0x40U
#define TC1_IDR_LDRBS_BIT 6
#define TC1_IDR_ETRGS_MASK 0x80U
#define TC1_IDR_ETRGS 0x80U
#define TC1_IDR_ETRGS_BIT 7

#define TC1_IMR (*(volatile unsigned long *)0xFFFA006C)
#define TC1_IMR_OFFSET 0x6C
#define TC1_IMR_COVFS_MASK 0x1U
#define TC1_IMR_COVFS 0x1U
#define TC1_IMR_COVFS_BIT 0
#define TC1_IMR_LOVRS_MASK 0x2U
#define TC1_IMR_LOVRS 0x2U
#define TC1_IMR_LOVRS_BIT 1
#define TC1_IMR_CPAS_MASK 0x4U
#define TC1_IMR_CPAS 0x4U
#define TC1_IMR_CPAS_BIT 2
#define TC1_IMR_CPBS_MASK 0x8U
#define TC1_IMR_CPBS 0x8U
#define TC1_IMR_CPBS_BIT 3
#define TC1_IMR_CPCS_MASK 0x10U
#define TC1_IMR_CPCS 0x10U
#define TC1_IMR_CPCS_BIT 4
#define TC1_IMR_LDRAS_MASK 0x20U
#define TC1_IMR_LDRAS 0x20U
#define TC1_IMR_LDRAS_BIT 5
#define TC1_IMR_LDRBS_MASK 0x40U
#define TC1_IMR_LDRBS 0x40U
#define TC1_IMR_LDRBS_BIT 6
#define TC1_IMR_ETRGS_MASK 0x80U
#define TC1_IMR_ETRGS 0x80U
#define TC1_IMR_ETRGS_BIT 7

#define TC2_CCR (*(volatile unsigned long *)0xFFFA0080)
#define TC2_CCR_OFFSET 0x80
#define TC2_CCR_CLKEN_MASK 0x1U
#define TC2_CCR_CLKEN 0x1U
#define TC2_CCR_CLKEN_BIT 0
#define TC2_CCR_CLKDIS_MASK 0x2U
#define TC2_CCR_CLKDIS 0x2U
#define TC2_CCR_CLKDIS_BIT 1
#define TC2_CCR_SWTRG_MASK 0x4U
#define TC2_CCR_SWTRG 0x4U
#define TC2_CCR_SWTRG_BIT 2

#define TC2_CMR (*(volatile unsigned long *)0xFFFA0084)
#define TC2_CMR_OFFSET 0x84
#define TC2_CMR_TCCLKS_MASK 0x7U
#define TC2_CMR_TCCLKS_BIT 0
#define TC2_CMR_CLKI_MASK 0x8U
#define TC2_CMR_CLKI 0x8U
#define TC2_CMR_CLKI_BIT 3
#define TC2_CMR_BURST_MASK 0x30U
#define TC2_CMR_BURST_BIT 4
#define TC2_CMR_LDBSTOP_MASK 0x40U
#define TC2_CMR_LDBSTOP 0x40U
#define TC2_CMR_LDBSTOP_BIT 6
#define TC2_CMR_LDBDIS_MASK 0x80U
#define TC2_CMR_LDBDIS 0x80U
#define TC2_CMR_LDBDIS_BIT 7
#define TC2_CMR_ETRGEDG_MASK 0x300U
#define TC2_CMR_ETRGEDG_BIT 8
#define TC2_CMR_ABETRG_MASK 0x400U
#define TC2_CMR_ABETRG 0x400U
#define TC2_CMR_ABETRG_BIT 10
#define TC2_CMR_CPCTRG_MASK 0x4000U
#define TC2_CMR_CPCTRG 0x4000U
#define TC2_CMR_CPCTRG_BIT 14
#define TC2_CMR_WAVE_MASK 0x8000U
#define TC2_CMR_WAVE 0x8000U
#define TC2_CMR_WAVE_BIT 15
#define TC2_CMR_LDRA_MASK 0x30000U
#define TC2_CMR_LDRA_BIT 16
#define TC2_CMR_LDRB_MASK 0xC0000U
#define TC2_CMR_LDRB_BIT 18

#define TC2_CV (*(volatile unsigned long *)0xFFFA0090)
#define TC2_CV_OFFSET 0x90

#define TC2_RA (*(volatile unsigned long *)0xFFFA0094)
#define TC2_RA_OFFSET 0x94

#define TC2_RB (*(volatile unsigned long *)0xFFFA0098)
#define TC2_RB_OFFSET 0x98

#define TC2_RC (*(volatile unsigned long *)0xFFFA009C)
#define TC2_RC_OFFSET 0x9C

#define TC2_SR (*(volatile unsigned long *)0xFFFA00A0)
#define TC2_SR_OFFSET 0xA0
#define TC2_SR_COVFS_MASK 0x1U
#define TC2_SR_COVFS 0x1U
#define TC2_SR_COVFS_BIT 0
#define TC2_SR_LOVRS_MASK 0x2U
#define TC2_SR_LOVRS 0x2U
#define TC2_SR_LOVRS_BIT 1
#define TC2_SR_CPAS_MASK 0x4U
#define TC2_SR_CPAS 0x4U
#define TC2_SR_CPAS_BIT 2
#define TC2_SR_CPBS_MASK 0x8U
#define TC2_SR_CPBS 0x8U
#define TC2_SR_CPBS_BIT 3
#define TC2_SR_CPCS_MASK 0x10U
#define TC2_SR_CPCS 0x10U
#define TC2_SR_CPCS_BIT 4
#define TC2_SR_LDRAS_MASK 0x20U
#define TC2_SR_LDRAS 0x20U
#define TC2_SR_LDRAS_BIT 5
#define TC2_SR_LDRBS_MASK 0x40U
#define TC2_SR_LDRBS 0x40U
#define TC2_SR_LDRBS_BIT 6
#define TC2_SR_ETRGS_MASK 0x80U
#define TC2_SR_ETRGS 0x80U
#define TC2_SR_ETRGS_BIT 7
#define TC2_SR_CLKSTA_MASK 0x10000U
#define TC2_SR_CLKSTA 0x10000U
#define TC2_SR_CLKSTA_BIT 16
#define TC2_SR_MTIOA_MASK 0x20000U
#define TC2_SR_MTIOA 0x20000U
#define TC2_SR_MTIOA_BIT 17
#define TC2_SR_MTIOB_MASK 0x40000U
#define TC2_SR_MTIOB 0x40000U
#define TC2_SR_MTIOB_BIT 18

#define TC2_IER (*(volatile unsigned long *)0xFFFA00A4)
#define TC2_IER_OFFSET 0xA4
#define TC2_IER_COVFS_MASK 0x1U
#define TC2_IER_COVFS 0x1U
#define TC2_IER_COVFS_BIT 0
#define TC2_IER_LOVRS_MASK 0x2U
#define TC2_IER_LOVRS 0x2U
#define TC2_IER_LOVRS_BIT 1
#define TC2_IER_CPAS_MASK 0x4U
#define TC2_IER_CPAS 0x4U
#define TC2_IER_CPAS_BIT 2
#define TC2_IER_CPBS_MASK 0x8U
#define TC2_IER_CPBS 0x8U
#define TC2_IER_CPBS_BIT 3
#define TC2_IER_CPCS_MASK 0x10U
#define TC2_IER_CPCS 0x10U
#define TC2_IER_CPCS_BIT 4
#define TC2_IER_LDRAS_MASK 0x20U
#define TC2_IER_LDRAS 0x20U
#define TC2_IER_LDRAS_BIT 5
#define TC2_IER_LDRBS_MASK 0x40U
#define TC2_IER_LDRBS 0x40U
#define TC2_IER_LDRBS_BIT 6
#define TC2_IER_ETRGS_MASK 0x80U
#define TC2_IER_ETRGS 0x80U
#define TC2_IER_ETRGS_BIT 7

#define TC2_IDR (*(volatile unsigned long *)0xFFFA00A8)
#define TC2_IDR_OFFSET 0xA8
#define TC2_IDR_COVFS_MASK 0x1U
#define TC2_IDR_COVFS 0x1U
#define TC2_IDR_COVFS_BIT 0
#define TC2_IDR_LOVRS_MASK 0x2U
#define TC2_IDR_LOVRS 0x2U
#define TC2_IDR_LOVRS_BIT 1
#define TC2_IDR_CPAS_MASK 0x4U
#define TC2_IDR_CPAS 0x4U
#define TC2_IDR_CPAS_BIT 2
#define TC2_IDR_CPBS_MASK 0x8U
#define TC2_IDR_CPBS 0x8U
#define TC2_IDR_CPBS_BIT 3
#define TC2_IDR_CPCS_MASK 0x10U
#define TC2_IDR_CPCS 0x10U
#define TC2_IDR_CPCS_BIT 4
#define TC2_IDR_LDRAS_MASK 0x20U
#define TC2_IDR_LDRAS 0x20U
#define TC2_IDR_LDRAS_BIT 5
#define TC2_IDR_LDRBS_MASK 0x40U
#define TC2_IDR_LDRBS 0x40U
#define TC2_IDR_LDRBS_BIT 6
#define TC2_IDR_ETRGS_MASK 0x80U
#define TC2_IDR_ETRGS 0x80U
#define TC2_IDR_ETRGS_BIT 7

#define TC2_IMR (*(volatile unsigned long *)0xFFFA00AC)
#define TC2_IMR_OFFSET 0xAC
#define TC2_IMR_COVFS_MASK 0x1U
#define TC2_IMR_COVFS 0x1U
#define TC2_IMR_COVFS_BIT 0
#define TC2_IMR_LOVRS_MASK 0x2U
#define TC2_IMR_LOVRS 0x2U
#define TC2_IMR_LOVRS_BIT 1
#define TC2_IMR_CPAS_MASK 0x4U
#define TC2_IMR_CPAS 0x4U
#define TC2_IMR_CPAS_BIT 2
#define TC2_IMR_CPBS_MASK 0x8U
#define TC2_IMR_CPBS 0x8U
#define TC2_IMR_CPBS_BIT 3
#define TC2_IMR_CPCS_MASK 0x10U
#define TC2_IMR_CPCS 0x10U
#define TC2_IMR_CPCS_BIT 4
#define TC2_IMR_LDRAS_MASK 0x20U
#define TC2_IMR_LDRAS 0x20U
#define TC2_IMR_LDRAS_BIT 5
#define TC2_IMR_LDRBS_MASK 0x40U
#define TC2_IMR_LDRBS 0x40U
#define TC2_IMR_LDRBS_BIT 6
#define TC2_IMR_ETRGS_MASK 0x80U
#define TC2_IMR_ETRGS 0x80U
#define TC2_IMR_ETRGS_BIT 7

#define TC012_BCR (*(volatile unsigned long *)0xFFFA00C0)
#define TC012_BCR_OFFSET 0xC0

#define TC012_BMR (*(volatile unsigned long *)0xFFFA00C4)
#define TC012_BMR_OFFSET 0xC4
#define TC012_BMR_TC0XC0S_MASK 0x3U
#define TC012_BMR_TC0XC0S_BIT 0
#define TC012_BMR_TC1XC1S_MASK 0xCU
#define TC012_BMR_TC1XC1S_BIT 2
#define TC012_BMR_TC2XC2S_MASK 0x30U
#define TC012_BMR_TC2XC2S_BIT 4

#define UDP_BASE 0xFFFB0000

#define USB_FRM_NUM (*(volatile unsigned long *)0xFFFB0000)
#define USB_FRM_NUM_OFFSET 0x0
#define USB_FRM_NUM_FRM_NUM_MASK 0x7FFU
#define USB_FRM_NUM_FRM_NUM_BIT 0
#define USB_FRM_NUM_FRM_ERR_MASK 0x10000U
#define USB_FRM_NUM_FRM_ERR 0x10000U
#define USB_FRM_NUM_FRM_ERR_BIT 16
#define USB_FRM_NUM_FRM_OK_MASK 0x20000U
#define USB_FRM_NUM_FRM_OK 0x20000U
#define USB_FRM_NUM_FRM_OK_BIT 17

#define USB_GLB_STAT (*(volatile unsigned long *)0xFFFB0004)
#define USB_GLB_STAT_OFFSET 0x4
#define USB_GLB_STAT_FADDEN_MASK 0x1U
#define USB_GLB_STAT_FADDEN 0x1U
#define USB_GLB_STAT_FADDEN_BIT 0
#define USB_GLB_STAT_CONFG_MASK 0x2U
#define USB_GLB_STAT_CONFG 0x2U
#define USB_GLB_STAT_CONFG_BIT 1
#define USB_GLB_STAT_ESR_MASK 0x4U
#define USB_GLB_STAT_ESR 0x4U
#define USB_GLB_STAT_ESR_BIT 2
#define USB_GLB_STAT_RSMINPR_MASK 0x8U
#define USB_GLB_STAT_RSMINPR 0x8U
#define USB_GLB_STAT_RSMINPR_BIT 3
#define USB_GLB_STAT_RMWUPE_MASK 0x10U
#define USB_GLB_STAT_RMWUPE 0x10U
#define USB_GLB_STAT_RMWUPE_BIT 4

#define USB_FADDR (*(volatile unsigned long *)0xFFFB0008)
#define USB_FADDR_OFFSET 0x8
#define USB_FADDR_FADD_MASK 0x7FU
#define USB_FADDR_FADD_BIT 0
#define USB_FADDR_FEN_MASK 0x100U
#define USB_FADDR_FEN 0x100U
#define USB_FADDR_FEN_BIT 8

#define USB_IER (*(volatile unsigned long *)0xFFFB0010)
#define USB_IER_OFFSET 0x10
#define USB_IER_EP0INT_MASK 0x1U
#define USB_IER_EP0INT 0x1U
#define USB_IER_EP0INT_BIT 0
#define USB_IER_EP1INT_MASK 0x2U
#define USB_IER_EP1INT 0x2U
#define USB_IER_EP1INT_BIT 1
#define USB_IER_EP2INT_MASK 0x4U
#define USB_IER_EP2INT 0x4U
#define USB_IER_EP2INT_BIT 2
#define USB_IER_EP3INT_MASK 0x8U
#define USB_IER_EP3INT 0x8U
#define USB_IER_EP3INT_BIT 3
#define USB_IER_RXSUSP_MASK 0x100U
#define USB_IER_RXSUSP 0x100U
#define USB_IER_RXSUSP_BIT 8
#define USB_IER_RXRSM_MASK 0x200U
#define USB_IER_RXRSM 0x200U
#define USB_IER_RXRSM_BIT 9
#define USB_IER_EXTRSM_MASK 0x400U
#define USB_IER_EXTRSM 0x400U
#define USB_IER_EXTRSM_BIT 10
#define USB_IER_SOFINT_MASK 0x800U
#define USB_IER_SOFINT 0x800U
#define USB_IER_SOFINT_BIT 11
#define USB_IER_WAKEUP_MASK 0x2000U
#define USB_IER_WAKEUP 0x2000U
#define USB_IER_WAKEUP_BIT 13

#define USB_IDR (*(volatile unsigned long *)0xFFFB0014)
#define USB_IDR_OFFSET 0x14
#define USB_IDR_EP0INT_MASK 0x1U
#define USB_IDR_EP0INT 0x1U
#define USB_IDR_EP0INT_BIT 0
#define USB_IDR_EP1INT_MASK 0x2U
#define USB_IDR_EP1INT 0x2U
#define USB_IDR_EP1INT_BIT 1
#define USB_IDR_EP2INT_MASK 0x4U
#define USB_IDR_EP2INT 0x4U
#define USB_IDR_EP2INT_BIT 2
#define USB_IDR_EP3INT_MASK 0x8U
#define USB_IDR_EP3INT 0x8U
#define USB_IDR_EP3INT_BIT 3
#define USB_IDR_RXSUSP_MASK 0x100U
#define USB_IDR_RXSUSP 0x100U
#define USB_IDR_RXSUSP_BIT 8
#define USB_IDR_RXRSM_MASK 0x200U
#define USB_IDR_RXRSM 0x200U
#define USB_IDR_RXRSM_BIT 9
#define USB_IDR_EXTRSM_MASK 0x400U
#define USB_IDR_EXTRSM 0x400U
#define USB_IDR_EXTRSM_BIT 10
#define USB_IDR_SOFINT_MASK 0x800U
#define USB_IDR_SOFINT 0x800U
#define USB_IDR_SOFINT_BIT 11
#define USB_IDR_WAKEUP_MASK 0x2000U
#define USB_IDR_WAKEUP 0x2000U
#define USB_IDR_WAKEUP_BIT 13

#define USB_IMR (*(volatile unsigned long *)0xFFFB0018)
#define USB_IMR_OFFSET 0x18
#define USB_IMR_EP0INT_MASK 0x1U
#define USB_IMR_EP0INT 0x1U
#define USB_IMR_EP0INT_BIT 0
#define USB_IMR_EP1INT_MASK 0x2U
#define USB_IMR_EP1INT 0x2U
#define USB_IMR_EP1INT_BIT 1
#define USB_IMR_EP2INT_MASK 0x4U
#define USB_IMR_EP2INT 0x4U
#define USB_IMR_EP2INT_BIT 2
#define USB_IMR_EP3INT_MASK 0x8U
#define USB_IMR_EP3INT 0x8U
#define USB_IMR_EP3INT_BIT 3
#define USB_IMR_RXSUSP_MASK 0x100U
#define USB_IMR_RXSUSP 0x100U
#define USB_IMR_RXSUSP_BIT 8
#define USB_IMR_RXRSM_MASK 0x200U
#define USB_IMR_RXRSM 0x200U
#define USB_IMR_RXRSM_BIT 9
#define USB_IMR_EXTRSM_MASK 0x400U
#define USB_IMR_EXTRSM 0x400U
#define USB_IMR_EXTRSM_BIT 10
#define USB_IMR_SOFINT_MASK 0x800U
#define USB_IMR_SOFINT 0x800U
#define USB_IMR_SOFINT_BIT 11
#define USB_IMR_WAKEUP_MASK 0x2000U
#define USB_IMR_WAKEUP 0x2000U
#define USB_IMR_WAKEUP_BIT 13

#define USB_ISR (*(volatile unsigned long *)0xFFFB001C)
#define USB_ISR_OFFSET 0x1C
#define USB_ISR_EP0INT_MASK 0x1U
#define USB_ISR_EP0INT 0x1U
#define USB_ISR_EP0INT_BIT 0
#define USB_ISR_EP1INT_MASK 0x2U
#define USB_ISR_EP1INT 0x2U
#define USB_ISR_EP1INT_BIT 1
#define USB_ISR_EP2INT_MASK 0x4U
#define USB_ISR_EP2INT 0x4U
#define USB_ISR_EP2INT_BIT 2
#define USB_ISR_EP3INT_MASK 0x8U
#define USB_ISR_EP3INT 0x8U
#define USB_ISR_EP3INT_BIT 3
#define USB_ISR_RXSUSP_MASK 0x100U
#define USB_ISR_RXSUSP 0x100U
#define USB_ISR_RXSUSP_BIT 8
#define USB_ISR_RXRSM_MASK 0x200U
#define USB_ISR_RXRSM 0x200U
#define USB_ISR_RXRSM_BIT 9
#define USB_ISR_EXTRSM_MASK 0x400U
#define USB_ISR_EXTRSM 0x400U
#define USB_ISR_EXTRSM_BIT 10
#define USB_ISR_SOFINT_MASK 0x800U
#define USB_ISR_SOFINT 0x800U
#define USB_ISR_SOFINT_BIT 11
#define USB_ISR_ENDBUSRES_MASK 0x1000U
#define USB_ISR_ENDBUSRES 0x1000U
#define USB_ISR_ENDBUSRES_BIT 12
#define USB_ISR_WAKEUP_MASK 0x2000U
#define USB_ISR_WAKEUP 0x2000U
#define USB_ISR_WAKEUP_BIT 13

#define USB_ICR (*(volatile unsigned long *)0xFFFB0020)
#define USB_ICR_OFFSET 0x20
#define USB_ICR_RXSUSP_MASK 0x100U
#define USB_ICR_RXSUSP 0x100U
#define USB_ICR_RXSUSP_BIT 8
#define USB_ICR_RXRSM_MASK 0x200U
#define USB_ICR_RXRSM 0x200U
#define USB_ICR_RXRSM_BIT 9
#define USB_ICR_EXTRSM_MASK 0x400U
#define USB_ICR_EXTRSM 0x400U
#define USB_ICR_EXTRSM_BIT 10
#define USB_ICR_SOFINT_MASK 0x800U
#define USB_ICR_SOFINT 0x800U
#define USB_ICR_SOFINT_BIT 11
#define USB_ICR_ENDBUSRES_MASK 0x1000U
#define USB_ICR_ENDBUSRES 0x1000U
#define USB_ICR_ENDBUSRES_BIT 12
#define USB_ICR_WAKEUP_MASK 0x2000U
#define USB_ICR_WAKEUP 0x2000U
#define USB_ICR_WAKEUP_BIT 13

#define USB_RST_EP (*(volatile unsigned long *)0xFFFB0028)
#define USB_RST_EP_OFFSET 0x28
#define USB_RST_EP_EP0_MASK 0x1U
#define USB_RST_EP_EP0 0x1U
#define USB_RST_EP_EP0_BIT 0
#define USB_RST_EP_EP1_MASK 0x2U
#define USB_RST_EP_EP1 0x2U
#define USB_RST_EP_EP1_BIT 1
#define USB_RST_EP_EP2_MASK 0x4U
#define USB_RST_EP_EP2 0x4U
#define USB_RST_EP_EP2_BIT 2
#define USB_RST_EP_EP3_MASK 0x8U
#define USB_RST_EP_EP3 0x8U
#define USB_RST_EP_EP3_BIT 3

#define USB_CSR0 (*(volatile unsigned long *)0xFFFB0030)
#define USB_CSR0_OFFSET 0x30
#define USB_CSR0_TXCOMP_MASK 0x1U
#define USB_CSR0_TXCOMP 0x1U
#define USB_CSR0_TXCOMP_BIT 0
#define USB_CSR0_RX_DATA_BK0_MASK 0x2U
#define USB_CSR0_RX_DATA_BK0 0x2U
#define USB_CSR0_RX_DATA_BK0_BIT 1
#define USB_CSR0_RXSETUP_MASK 0x4U
#define USB_CSR0_RXSETUP 0x4U
#define USB_CSR0_RXSETUP_BIT 2
#define USB_CSR0_STALLSENT_ISOERROR_MASK 0x8U
#define USB_CSR0_STALLSENT_ISOERROR 0x8U
#define USB_CSR0_STALLSENT_ISOERROR_BIT 3
#define USB_CSR0_TXPKTRDY_MASK 0x10U
#define USB_CSR0_TXPKTRDY 0x10U
#define USB_CSR0_TXPKTRDY_BIT 4
#define USB_CSR0_FORCE_STALL_MASK 0x20U
#define USB_CSR0_FORCE_STALL 0x20U
#define USB_CSR0_FORCE_STALL_BIT 5
#define USB_CSR0_RX_DATA_BK1_MASK 0x40U
#define USB_CSR0_RX_DATA_BK1 0x40U
#define USB_CSR0_RX_DATA_BK1_BIT 6
#define USB_CSR0_DIR_MASK 0x80U
#define USB_CSR0_DIR 0x80U
#define USB_CSR0_DIR_BIT 7
#define USB_CSR0_EPTYPE_MASK 0x700U
#define USB_CSR0_EPTYPE_BIT 8
#define USB_CSR0_DTGLE_MASK 0x800U
#define USB_CSR0_DTGLE 0x800U
#define USB_CSR0_DTGLE_BIT 11
#define USB_CSR0_EPEDS_MASK 0x8000U
#define USB_CSR0_EPEDS 0x8000U
#define USB_CSR0_EPEDS_BIT 15
#define USB_CSR0_RXBYTECNT_MASK 0x7FF0000U
#define USB_CSR0_RXBYTECNT_BIT 16

#define USB_CSR1 (*(volatile unsigned long *)0xFFFB0034)
#define USB_CSR1_OFFSET 0x34
#define USB_CSR1_TXCOMP_MASK 0x1U
#define USB_CSR1_TXCOMP 0x1U
#define USB_CSR1_TXCOMP_BIT 0
#define USB_CSR1_RX_DATA_BK0_MASK 0x2U
#define USB_CSR1_RX_DATA_BK0 0x2U
#define USB_CSR1_RX_DATA_BK0_BIT 1
#define USB_CSR1_RXSETUP_MASK 0x4U
#define USB_CSR1_RXSETUP 0x4U
#define USB_CSR1_RXSETUP_BIT 2
#define USB_CSR1_STALLSENT_ISOERROR_MASK 0x8U
#define USB_CSR1_STALLSENT_ISOERROR 0x8U
#define USB_CSR1_STALLSENT_ISOERROR_BIT 3
#define USB_CSR1_TXPKTRDY_MASK 0x10U
#define USB_CSR1_TXPKTRDY 0x10U
#define USB_CSR1_TXPKTRDY_BIT 4
#define USB_CSR1_FORCE_STALL_MASK 0x20U
#define USB_CSR1_FORCE_STALL 0x20U
#define USB_CSR1_FORCE_STALL_BIT 5
#define USB_CSR1_RX_DATA_BK1_MASK 0x40U
#define USB_CSR1_RX_DATA_BK1 0x40U
#define USB_CSR1_RX_DATA_BK1_BIT 6
#define USB_CSR1_DIR_MASK 0x80U
#define USB_CSR1_DIR 0x80U
#define USB_CSR1_DIR_BIT 7
#define USB_CSR1_EPTYPE_MASK 0x700U
#define USB_CSR1_EPTYPE_BIT 8
#define USB_CSR1_DTGLE_MASK 0x800U
#define USB_CSR1_DTGLE 0x800U
#define USB_CSR1_DTGLE_BIT 11
#define USB_CSR1_EPEDS_MASK 0x8000U
#define USB_CSR1_EPEDS 0x8000U
#define USB_CSR1_EPEDS_BIT 15
#define USB_CSR1_RXBYTECNT_MASK 0x7FF0000U
#define USB_CSR1_RXBYTECNT_BIT 16

#define USB_CSR2 (*(volatile unsigned long *)0xFFFB0038)
#define USB_CSR2_OFFSET 0x38
#define USB_CSR2_TXCOMP_MASK 0x1U
#define USB_CSR2_TXCOMP 0x1U
#define USB_CSR2_TXCOMP_BIT 0
#define USB_CSR2_RX_DATA_BK0_MASK 0x2U
#define USB_CSR2_RX_DATA_BK0 0x2U
#define USB_CSR2_RX_DATA_BK0_BIT 1
#define USB_CSR2_RXSETUP_MASK 0x4U
#define USB_CSR2_RXSETUP 0x4U
#define USB_CSR2_RXSETUP_BIT 2
#define USB_CSR2_STALLSENT_ISOERROR_MASK 0x8U
#define USB_CSR2_STALLSENT_ISOERROR 0x8U
#define USB_CSR2_STALLSENT_ISOERROR_BIT 3
#define USB_CSR2_TXPKTRDY_MASK 0x10U
#define USB_CSR2_TXPKTRDY 0x10U
#define USB_CSR2_TXPKTRDY_BIT 4
#define USB_CSR2_FORCE_STALL_MASK 0x20U
#define USB_CSR2_FORCE_STALL 0x20U
#define USB_CSR2_FORCE_STALL_BIT 5
#define USB_CSR2_RX_DATA_BK1_MASK 0x40U
#define USB_CSR2_RX_DATA_BK1 0x40U
#define USB_CSR2_RX_DATA_BK1_BIT 6
#define USB_CSR2_DIR_MASK 0x80U
#define USB_CSR2_DIR 0x80U
#define USB_CSR2_DIR_BIT 7
#define USB_CSR2_EPTYPE_MASK 0x700U
#define USB_CSR2_EPTYPE_BIT 8
#define USB_CSR2_DTGLE_MASK 0x800U
#define USB_CSR2_DTGLE 0x800U
#define USB_CSR2_DTGLE_BIT 11
#define USB_CSR2_EPEDS_MASK 0x8000U
#define USB_CSR2_EPEDS 0x8000U
#define USB_CSR2_EPEDS_BIT 15
#define USB_CSR2_RXBYTECNT_MASK 0x7FF0000U
#define USB_CSR2_RXBYTECNT_BIT 16

#define USB_CSR3 (*(volatile unsigned long *)0xFFFB003C)
#define USB_CSR3_OFFSET 0x3C
#define USB_CSR3_TXCOMP_MASK 0x1U
#define USB_CSR3_TXCOMP 0x1U
#define USB_CSR3_TXCOMP_BIT 0
#define USB_CSR3_RX_DATA_BK0_MASK 0x2U
#define USB_CSR3_RX_DATA_BK0 0x2U
#define USB_CSR3_RX_DATA_BK0_BIT 1
#define USB_CSR3_RXSETUP_MASK 0x4U
#define USB_CSR3_RXSETUP 0x4U
#define USB_CSR3_RXSETUP_BIT 2
#define USB_CSR3_STALLSENT_ISOERROR_MASK 0x8U
#define USB_CSR3_STALLSENT_ISOERROR 0x8U
#define USB_CSR3_STALLSENT_ISOERROR_BIT 3
#define USB_CSR3_TXPKTRDY_MASK 0x10U
#define USB_CSR3_TXPKTRDY 0x10U
#define USB_CSR3_TXPKTRDY_BIT 4
#define USB_CSR3_FORCE_STALL_MASK 0x20U
#define USB_CSR3_FORCE_STALL 0x20U
#define USB_CSR3_FORCE_STALL_BIT 5
#define USB_CSR3_RX_DATA_BK1_MASK 0x40U
#define USB_CSR3_RX_DATA_BK1 0x40U
#define USB_CSR3_RX_DATA_BK1_BIT 6
#define USB_CSR3_DIR_MASK 0x80U
#define USB_CSR3_DIR 0x80U
#define USB_CSR3_DIR_BIT 7
#define USB_CSR3_EPTYPE_MASK 0x700U
#define USB_CSR3_EPTYPE_BIT 8
#define USB_CSR3_DTGLE_MASK 0x800U
#define USB_CSR3_DTGLE 0x800U
#define USB_CSR3_DTGLE_BIT 11
#define USB_CSR3_EPEDS_MASK 0x8000U
#define USB_CSR3_EPEDS 0x8000U
#define USB_CSR3_EPEDS_BIT 15
#define USB_CSR3_RXBYTECNT_MASK 0x7FF0000U
#define USB_CSR3_RXBYTECNT_BIT 16

#define USB_FDR0 (*(volatile unsigned long *)0xFFFB0050)
#define USB_FDR0_OFFSET 0x50

#define USB_FDR1 (*(volatile unsigned long *)0xFFFB0054)
#define USB_FDR1_OFFSET 0x54

#define USB_FDR2 (*(volatile unsigned long *)0xFFFB0058)
#define USB_FDR2_OFFSET 0x58

#define USB_FDR3 (*(volatile unsigned long *)0xFFFB005C)
#define USB_FDR3_OFFSET 0x5C

#define USB_TXVC (*(volatile unsigned long *)0xFFFB0074)
#define USB_TXVC_OFFSET 0x74
#define USB_TXVC_TXVDIS_MASK 0x100U
#define USB_TXVC_TXVDIS 0x100U
#define USB_TXVC_TXVDIS_BIT 8

#define TWI_BASE 0xFFFB8000

#define TWI_CR (*(volatile unsigned long *)0xFFFB8000)
#define TWI_CR_OFFSET 0x0
#define TWI_CR_START_MASK 0x1U
#define TWI_CR_START 0x1U
#define TWI_CR_START_BIT 0
#define TWI_CR_STOP_MASK 0x2U
#define TWI_CR_STOP 0x2U
#define TWI_CR_STOP_BIT 1
#define TWI_CR_MSEN_MASK 0x4U
#define TWI_CR_MSEN 0x4U
#define TWI_CR_MSEN_BIT 2
#define TWI_CR_MSDIS_MASK 0x8U
#define TWI_CR_MSDIS 0x8U
#define TWI_CR_MSDIS_BIT 3
#define TWI_CR_SWRST_MASK 0x80U
#define TWI_CR_SWRST 0x80U
#define TWI_CR_SWRST_BIT 7

#define TWI_MMR (*(volatile unsigned long *)0xFFFB8004)
#define TWI_MMR_OFFSET 0x4
#define TWI_MMR_IADRSZ_MASK 0x300U
#define TWI_MMR_IADRSZ_BIT 8
#define TWI_MMR_MREAD_MASK 0xFFF000U
#define TWI_MMR_MREAD_BIT 12
#define TWI_MMR_DADR_MASK 0x7F0000U
#define TWI_MMR_DADR_BIT 16

#define TWI_IADR (*(volatile unsigned long *)0xFFFB800C)
#define TWI_IADR_OFFSET 0xC

#define TWI_CWGR (*(volatile unsigned long *)0xFFFB8010)
#define TWI_CWGR_OFFSET 0x10
#define TWI_CWGR_CLDIV_MASK 0xFF00U
#define TWI_CWGR_CLDIV_BIT 8
#define TWI_CWGR_CHDIV_MASK 0xFF00U
#define TWI_CWGR_CHDIV_BIT 8
#define TWI_CWGR_CKDIV_MASK 0x70000U
#define TWI_CWGR_CKDIV_BIT 16

#define TWI_SR (*(volatile unsigned long *)0xFFFB8020)
#define TWI_SR_OFFSET 0x20
#define TWI_SR_TXCOMP_MASK 0x1U
#define TWI_SR_TXCOMP 0x1U
#define TWI_SR_TXCOMP_BIT 0
#define TWI_SR_RXRDY_MASK 0x2U
#define TWI_SR_RXRDY 0x2U
#define TWI_SR_RXRDY_BIT 1
#define TWI_SR_TXRDY_MASK 0x4U
#define TWI_SR_TXRDY 0x4U
#define TWI_SR_TXRDY_BIT 2
#define TWI_SR_OVRE_MASK 0x40U
#define TWI_SR_OVRE 0x40U
#define TWI_SR_OVRE_BIT 6
#define TWI_SR_UNRE_MASK 0x80U
#define TWI_SR_UNRE 0x80U
#define TWI_SR_UNRE_BIT 7
#define TWI_SR_NACK_MASK 0x100U
#define TWI_SR_NACK 0x100U
#define TWI_SR_NACK_BIT 8

#define TWI_IER (*(volatile unsigned long *)0xFFFB8024)
#define TWI_IER_OFFSET 0x24
#define TWI_IER_TXCOMP_MASK 0x1U
#define TWI_IER_TXCOMP 0x1U
#define TWI_IER_TXCOMP_BIT 0
#define TWI_IER_RXRDY_MASK 0x2U
#define TWI_IER_RXRDY 0x2U
#define TWI_IER_RXRDY_BIT 1
#define TWI_IER_TXRDY_MASK 0x4U
#define TWI_IER_TXRDY 0x4U
#define TWI_IER_TXRDY_BIT 2
#define TWI_IER_OVRE_MASK 0x40U
#define TWI_IER_OVRE 0x40U
#define TWI_IER_OVRE_BIT 6
#define TWI_IER_UNRE_MASK 0x80U
#define TWI_IER_UNRE 0x80U
#define TWI_IER_UNRE_BIT 7
#define TWI_IER_NACK_MASK 0x100U
#define TWI_IER_NACK 0x100U
#define TWI_IER_NACK_BIT 8

#define TWI_IDR (*(volatile unsigned long *)0xFFFB8028)
#define TWI_IDR_OFFSET 0x28
#define TWI_IDR_TXCOMP_MASK 0x1U
#define TWI_IDR_TXCOMP 0x1U
#define TWI_IDR_TXCOMP_BIT 0
#define TWI_IDR_RXRDY_MASK 0x2U
#define TWI_IDR_RXRDY 0x2U
#define TWI_IDR_RXRDY_BIT 1
#define TWI_IDR_TXRDY_MASK 0x4U
#define TWI_IDR_TXRDY 0x4U
#define TWI_IDR_TXRDY_BIT 2
#define TWI_IDR_OVRE_MASK 0x40U
#define TWI_IDR_OVRE 0x40U
#define TWI_IDR_OVRE_BIT 6
#define TWI_IDR_UNRE_MASK 0x80U
#define TWI_IDR_UNRE 0x80U
#define TWI_IDR_UNRE_BIT 7
#define TWI_IDR_NACK_MASK 0x100U
#define TWI_IDR_NACK 0x100U
#define TWI_IDR_NACK_BIT 8

#define TWI_IMR (*(volatile unsigned long *)0xFFFB802C)
#define TWI_IMR_OFFSET 0x2C
#define TWI_IMR_TXCOMP_MASK 0x1U
#define TWI_IMR_TXCOMP 0x1U
#define TWI_IMR_TXCOMP_BIT 0
#define TWI_IMR_RXRDY_MASK 0x2U
#define TWI_IMR_RXRDY 0x2U
#define TWI_IMR_RXRDY_BIT 1
#define TWI_IMR_TXRDY_MASK 0x4U
#define TWI_IMR_TXRDY 0x4U
#define TWI_IMR_TXRDY_BIT 2
#define TWI_IMR_OVRE_MASK 0x40U
#define TWI_IMR_OVRE 0x40U
#define TWI_IMR_OVRE_BIT 6
#define TWI_IMR_UNRE_MASK 0x80U
#define TWI_IMR_UNRE 0x80U
#define TWI_IMR_UNRE_BIT 7
#define TWI_IMR_NACK_MASK 0x100U
#define TWI_IMR_NACK 0x100U
#define TWI_IMR_NACK_BIT 8

#define TWI_RHR (*(volatile unsigned long *)0xFFFB8030)
#define TWI_RHR_OFFSET 0x30

#define TWI_THR (*(volatile unsigned long *)0xFFFB8034)
#define TWI_THR_OFFSET 0x34

#define USART0_BASE 0xFFFC0000

#define US0_CR (*(volatile unsigned long *)0xFFFC0000)
#define US0_CR_OFFSET 0x0
#define US0_CR_RSTRX_MASK 0x4U
#define US0_CR_RSTRX 0x4U
#define US0_CR_RSTRX_BIT 2
#define US0_CR_RSTTX_MASK 0x8U
#define US0_CR_RSTTX 0x8U
#define US0_CR_RSTTX_BIT 3
#define US0_CR_RXEN_MASK 0x10U
#define US0_CR_RXEN 0x10U
#define US0_CR_RXEN_BIT 4
#define US0_CR_RXDIS_MASK 0x20U
#define US0_CR_RXDIS 0x20U
#define US0_CR_RXDIS_BIT 5
#define US0_CR_TXEN_MASK 0x40U
#define US0_CR_TXEN 0x40U
#define US0_CR_TXEN_BIT 6
#define US0_CR_TXDIS_MASK 0x80U
#define US0_CR_TXDIS 0x80U
#define US0_CR_TXDIS_BIT 7
#define US0_CR_RSTSTA_MASK 0x100U
#define US0_CR_RSTSTA 0x100U
#define US0_CR_RSTSTA_BIT 8
#define US0_CR_STTBRK_MASK 0x200U
#define US0_CR_STTBRK 0x200U
#define US0_CR_STTBRK_BIT 9
#define US0_CR_STPBRK_MASK 0x400U
#define US0_CR_STPBRK 0x400U
#define US0_CR_STPBRK_BIT 10
#define US0_CR_STTTO_MASK 0x800U
#define US0_CR_STTTO 0x800U
#define US0_CR_STTTO_BIT 11
#define US0_CR_SENDA_MASK 0x1000U
#define US0_CR_SENDA 0x1000U
#define US0_CR_SENDA_BIT 12
#define US0_CR_RSTIT_MASK 0x2000U
#define US0_CR_RSTIT 0x2000U
#define US0_CR_RSTIT_BIT 13
#define US0_CR_RSTNACK_MASK 0x4000U
#define US0_CR_RSTNACK 0x4000U
#define US0_CR_RSTNACK_BIT 14
#define US0_CR_RETTO_MASK 0x8000U
#define US0_CR_RETTO 0x8000U
#define US0_CR_RETTO_BIT 15
#define US0_CR_DTREN_MASK 0x10000U
#define US0_CR_DTREN 0x10000U
#define US0_CR_DTREN_BIT 16
#define US0_CR_DTRDIS_MASK 0x20000U
#define US0_CR_DTRDIS 0x20000U
#define US0_CR_DTRDIS_BIT 17
#define US0_CR_RTSEN_MASK 0x40000U
#define US0_CR_RTSEN 0x40000U
#define US0_CR_RTSEN_BIT 18
#define US0_CR_RTSDIS_MASK 0x80000U
#define US0_CR_RTSDIS 0x80000U
#define US0_CR_RTSDIS_BIT 19

#define US0_MR (*(volatile unsigned long *)0xFFFC0004)
#define US0_MR_OFFSET 0x4
#define US0_MR_USART_MODE_MASK 0xFU
#define US0_MR_USART_MODE_BIT 0
#define US0_MR_USCLKS_MASK 0x30U
#define US0_MR_USCLKS_BIT 4
#define US0_MR_CHRL_MASK 0xC0U
#define US0_MR_CHRL_BIT 6
#define US0_MR_SYNC_MASK 0x100U
#define US0_MR_SYNC 0x100U
#define US0_MR_SYNC_BIT 8
#define US0_MR_PAR_MASK 0xE00U
#define US0_MR_PAR_BIT 9
#define US0_MR_NBSTOP_MASK 0x3000U
#define US0_MR_NBSTOP_BIT 12
#define US0_MR_CHMODE_MASK 0xC000U
#define US0_MR_CHMODE_BIT 14
#define US0_MR_MSBF_MASK 0x10000U
#define US0_MR_MSBF 0x10000U
#define US0_MR_MSBF_BIT 16
#define US0_MR_MODE9_MASK 0x20000U
#define US0_MR_MODE9 0x20000U
#define US0_MR_MODE9_BIT 17
#define US0_MR_CLKO_MASK 0x40000U
#define US0_MR_CLKO 0x40000U
#define US0_MR_CLKO_BIT 18
#define US0_MR_OVER_MASK 0x80000U
#define US0_MR_OVER 0x80000U
#define US0_MR_OVER_BIT 19
#define US0_MR_INACK_MASK 0x100000U
#define US0_MR_INACK 0x100000U
#define US0_MR_INACK_BIT 20
#define US0_MR_DSNACK_MASK 0x200000U
#define US0_MR_DSNACK 0x200000U
#define US0_MR_DSNACK_BIT 21
#define US0_MR_MAX_ITERATION_MASK 0x7000000U
#define US0_MR_MAX_ITERATION_BIT 24
#define US0_MR_FILTER_MASK 0x10000000U
#define US0_MR_FILTER 0x10000000U
#define US0_MR_FILTER_BIT 28

#define US0_IER (*(volatile unsigned long *)0xFFFC0008)
#define US0_IER_OFFSET 0x8
#define US0_IER_RXRDY_MASK 0x1U
#define US0_IER_RXRDY 0x1U
#define US0_IER_RXRDY_BIT 0
#define US0_IER_TXRDY_MASK 0x2U
#define US0_IER_TXRDY 0x2U
#define US0_IER_TXRDY_BIT 1
#define US0_IER_RXBRK_MASK 0x4U
#define US0_IER_RXBRK 0x4U
#define US0_IER_RXBRK_BIT 2
#define US0_IER_ENDRX_MASK 0x8U
#define US0_IER_ENDRX 0x8U
#define US0_IER_ENDRX_BIT 3
#define US0_IER_ENDTX_MASK 0x10U
#define US0_IER_ENDTX 0x10U
#define US0_IER_ENDTX_BIT 4
#define US0_IER_OVRE_MASK 0x20U
#define US0_IER_OVRE 0x20U
#define US0_IER_OVRE_BIT 5
#define US0_IER_FRAME_MASK 0x40U
#define US0_IER_FRAME 0x40U
#define US0_IER_FRAME_BIT 6
#define US0_IER_PARE_MASK 0x80U
#define US0_IER_PARE 0x80U
#define US0_IER_PARE_BIT 7
#define US0_IER_TIMEOUT_MASK 0x100U
#define US0_IER_TIMEOUT 0x100U
#define US0_IER_TIMEOUT_BIT 8
#define US0_IER_TXEMPTY_MASK 0x200U
#define US0_IER_TXEMPTY 0x200U
#define US0_IER_TXEMPTY_BIT 9
#define US0_IER_ITERATION_MASK 0x400U
#define US0_IER_ITERATION 0x400U
#define US0_IER_ITERATION_BIT 10
#define US0_IER_TXBUFE_MASK 0x800U
#define US0_IER_TXBUFE 0x800U
#define US0_IER_TXBUFE_BIT 11
#define US0_IER_RXBUFF_MASK 0x1000U
#define US0_IER_RXBUFF 0x1000U
#define US0_IER_RXBUFF_BIT 12
#define US0_IER_NACK_MASK 0x2000U
#define US0_IER_NACK 0x2000U
#define US0_IER_NACK_BIT 13
#define US0_IER_RIIC_MASK 0x10000U
#define US0_IER_RIIC 0x10000U
#define US0_IER_RIIC_BIT 16
#define US0_IER_DSRIC_MASK 0x20000U
#define US0_IER_DSRIC 0x20000U
#define US0_IER_DSRIC_BIT 17
#define US0_IER_DCDIC_MASK 0x40000U
#define US0_IER_DCDIC 0x40000U
#define US0_IER_DCDIC_BIT 18
#define US0_IER_CTSIC_MASK 0x80000U
#define US0_IER_CTSIC 0x80000U
#define US0_IER_CTSIC_BIT 19

#define US0_IDR (*(volatile unsigned long *)0xFFFC000C)
#define US0_IDR_OFFSET 0xC
#define US0_IDR_RXRDY_MASK 0x1U
#define US0_IDR_RXRDY 0x1U
#define US0_IDR_RXRDY_BIT 0
#define US0_IDR_TXRDY_MASK 0x2U
#define US0_IDR_TXRDY 0x2U
#define US0_IDR_TXRDY_BIT 1
#define US0_IDR_RXBRK_MASK 0x4U
#define US0_IDR_RXBRK 0x4U
#define US0_IDR_RXBRK_BIT 2
#define US0_IDR_ENDRX_MASK 0x8U
#define US0_IDR_ENDRX 0x8U
#define US0_IDR_ENDRX_BIT 3
#define US0_IDR_ENDTX_MASK 0x10U
#define US0_IDR_ENDTX 0x10U
#define US0_IDR_ENDTX_BIT 4
#define US0_IDR_OVRE_MASK 0x20U
#define US0_IDR_OVRE 0x20U
#define US0_IDR_OVRE_BIT 5
#define US0_IDR_FRAME_MASK 0x40U
#define US0_IDR_FRAME 0x40U
#define US0_IDR_FRAME_BIT 6
#define US0_IDR_PARE_MASK 0x80U
#define US0_IDR_PARE 0x80U
#define US0_IDR_PARE_BIT 7
#define US0_IDR_TIMEOUT_MASK 0x100U
#define US0_IDR_TIMEOUT 0x100U
#define US0_IDR_TIMEOUT_BIT 8
#define US0_IDR_TXEMPTY_MASK 0x200U
#define US0_IDR_TXEMPTY 0x200U
#define US0_IDR_TXEMPTY_BIT 9
#define US0_IDR_ITERATION_MASK 0x400U
#define US0_IDR_ITERATION 0x400U
#define US0_IDR_ITERATION_BIT 10
#define US0_IDR_TXBUFE_MASK 0x800U
#define US0_IDR_TXBUFE 0x800U
#define US0_IDR_TXBUFE_BIT 11
#define US0_IDR_RXBUFF_MASK 0x1000U
#define US0_IDR_RXBUFF 0x1000U
#define US0_IDR_RXBUFF_BIT 12
#define US0_IDR_NACK_MASK 0x2000U
#define US0_IDR_NACK 0x2000U
#define US0_IDR_NACK_BIT 13
#define US0_IDR_RIIC_MASK 0x10000U
#define US0_IDR_RIIC 0x10000U
#define US0_IDR_RIIC_BIT 16
#define US0_IDR_DSRIC_MASK 0x20000U
#define US0_IDR_DSRIC 0x20000U
#define US0_IDR_DSRIC_BIT 17
#define US0_IDR_DCDIC_MASK 0x40000U
#define US0_IDR_DCDIC 0x40000U
#define US0_IDR_DCDIC_BIT 18
#define US0_IDR_CTSIC_MASK 0x80000U
#define US0_IDR_CTSIC 0x80000U
#define US0_IDR_CTSIC_BIT 19

#define US0_IMR (*(volatile unsigned long *)0xFFFC0010)
#define US0_IMR_OFFSET 0x10
#define US0_IMR_RXRDY_MASK 0x1U
#define US0_IMR_RXRDY 0x1U
#define US0_IMR_RXRDY_BIT 0
#define US0_IMR_TXRDY_MASK 0x2U
#define US0_IMR_TXRDY 0x2U
#define US0_IMR_TXRDY_BIT 1
#define US0_IMR_RXBRK_MASK 0x4U
#define US0_IMR_RXBRK 0x4U
#define US0_IMR_RXBRK_BIT 2
#define US0_IMR_ENDRX_MASK 0x8U
#define US0_IMR_ENDRX 0x8U
#define US0_IMR_ENDRX_BIT 3
#define US0_IMR_ENDTX_MASK 0x10U
#define US0_IMR_ENDTX 0x10U
#define US0_IMR_ENDTX_BIT 4
#define US0_IMR_OVRE_MASK 0x20U
#define US0_IMR_OVRE 0x20U
#define US0_IMR_OVRE_BIT 5
#define US0_IMR_FRAME_MASK 0x40U
#define US0_IMR_FRAME 0x40U
#define US0_IMR_FRAME_BIT 6
#define US0_IMR_PARE_MASK 0x80U
#define US0_IMR_PARE 0x80U
#define US0_IMR_PARE_BIT 7
#define US0_IMR_TIMEOUT_MASK 0x100U
#define US0_IMR_TIMEOUT 0x100U
#define US0_IMR_TIMEOUT_BIT 8
#define US0_IMR_TXEMPTY_MASK 0x200U
#define US0_IMR_TXEMPTY 0x200U
#define US0_IMR_TXEMPTY_BIT 9
#define US0_IMR_ITERATION_MASK 0x400U
#define US0_IMR_ITERATION 0x400U
#define US0_IMR_ITERATION_BIT 10
#define US0_IMR_TXBUFE_MASK 0x800U
#define US0_IMR_TXBUFE 0x800U
#define US0_IMR_TXBUFE_BIT 11
#define US0_IMR_RXBUFF_MASK 0x1000U
#define US0_IMR_RXBUFF 0x1000U
#define US0_IMR_RXBUFF_BIT 12
#define US0_IMR_NACK_MASK 0x2000U
#define US0_IMR_NACK 0x2000U
#define US0_IMR_NACK_BIT 13
#define US0_IMR_RIIC_MASK 0x10000U
#define US0_IMR_RIIC 0x10000U
#define US0_IMR_RIIC_BIT 16
#define US0_IMR_DSRIC_MASK 0x20000U
#define US0_IMR_DSRIC 0x20000U
#define US0_IMR_DSRIC_BIT 17
#define US0_IMR_DCDIC_MASK 0x40000U
#define US0_IMR_DCDIC 0x40000U
#define US0_IMR_DCDIC_BIT 18
#define US0_IMR_CTSIC_MASK 0x80000U
#define US0_IMR_CTSIC 0x80000U
#define US0_IMR_CTSIC_BIT 19

#define US0_CSR (*(volatile unsigned long *)0xFFFC0014)
#define US0_CSR_OFFSET 0x14
#define US0_CSR_RXRDY_MASK 0x1U
#define US0_CSR_RXRDY 0x1U
#define US0_CSR_RXRDY_BIT 0
#define US0_CSR_TXRDY_MASK 0x2U
#define US0_CSR_TXRDY 0x2U
#define US0_CSR_TXRDY_BIT 1
#define US0_CSR_RXBRK_MASK 0x4U
#define US0_CSR_RXBRK 0x4U
#define US0_CSR_RXBRK_BIT 2
#define US0_CSR_ENDRX_MASK 0x8U
#define US0_CSR_ENDRX 0x8U
#define US0_CSR_ENDRX_BIT 3
#define US0_CSR_ENDTX_MASK 0x10U
#define US0_CSR_ENDTX 0x10U
#define US0_CSR_ENDTX_BIT 4
#define US0_CSR_OVRE_MASK 0x20U
#define US0_CSR_OVRE 0x20U
#define US0_CSR_OVRE_BIT 5
#define US0_CSR_FRAME_MASK 0x40U
#define US0_CSR_FRAME 0x40U
#define US0_CSR_FRAME_BIT 6
#define US0_CSR_PARE_MASK 0x80U
#define US0_CSR_PARE 0x80U
#define US0_CSR_PARE_BIT 7
#define US0_CSR_TIMEOUT_MASK 0x100U
#define US0_CSR_TIMEOUT 0x100U
#define US0_CSR_TIMEOUT_BIT 8
#define US0_CSR_TXEMPTY_MASK 0x200U
#define US0_CSR_TXEMPTY 0x200U
#define US0_CSR_TXEMPTY_BIT 9
#define US0_CSR_ITERATION_MASK 0x400U
#define US0_CSR_ITERATION 0x400U
#define US0_CSR_ITERATION_BIT 10
#define US0_CSR_TXBUFE_MASK 0x800U
#define US0_CSR_TXBUFE 0x800U
#define US0_CSR_TXBUFE_BIT 11
#define US0_CSR_RXBUFF_MASK 0x1000U
#define US0_CSR_RXBUFF 0x1000U
#define US0_CSR_RXBUFF_BIT 12
#define US0_CSR_NACK_MASK 0x2000U
#define US0_CSR_NACK 0x2000U
#define US0_CSR_NACK_BIT 13
#define US0_CSR_RIIC_MASK 0x10000U
#define US0_CSR_RIIC 0x10000U
#define US0_CSR_RIIC_BIT 16
#define US0_CSR_DSRIC_MASK 0x20000U
#define US0_CSR_DSRIC 0x20000U
#define US0_CSR_DSRIC_BIT 17
#define US0_CSR_DCDIC_MASK 0x40000U
#define US0_CSR_DCDIC 0x40000U
#define US0_CSR_DCDIC_BIT 18
#define US0_CSR_CTSIC_MASK 0x80000U
#define US0_CSR_CTSIC 0x80000U
#define US0_CSR_CTSIC_BIT 19
#define US0_CSR_RI_MASK 0x100000U
#define US0_CSR_RI 0x100000U
#define US0_CSR_RI_BIT 20
#define US0_CSR_DSR_MASK 0x200000U
#define US0_CSR_DSR 0x200000U
#define US0_CSR_DSR_BIT 21
#define US0_CSR_DCD_MASK 0x400000U
#define US0_CSR_DCD 0x400000U
#define US0_CSR_DCD_BIT 22
#define US0_CSR_CTS_MASK 0x800000U
#define US0_CSR_CTS 0x800000U
#define US0_CSR_CTS_BIT 23

#define US0_RHR (*(volatile unsigned long *)0xFFFC0018)
#define US0_RHR_OFFSET 0x18

#define US0_THR (*(volatile unsigned long *)0xFFFC001C)
#define US0_THR_OFFSET 0x1C

#define US0_BRGR (*(volatile unsigned long *)0xFFFC0020)
#define US0_BRGR_OFFSET 0x20

#define US0_RTOR (*(volatile unsigned long *)0xFFFC0024)
#define US0_RTOR_OFFSET 0x24

#define US0_TTGR (*(volatile unsigned long *)0xFFFC0028)
#define US0_TTGR_OFFSET 0x28

#define US0_FIDI (*(volatile unsigned long *)0xFFFC0040)
#define US0_FIDI_OFFSET 0x40

#define US0_NER (*(volatile unsigned long *)0xFFFC0044)
#define US0_NER_OFFSET 0x44

#define US0_IF (*(volatile unsigned long *)0xFFFC004C)
#define US0_IF_OFFSET 0x4C

#define US0_RPR (*(volatile unsigned long *)0xFFFC0100)
#define US0_RPR_OFFSET 0x100

#define US0_RCR (*(volatile unsigned long *)0xFFFC0104)
#define US0_RCR_OFFSET 0x104

#define US0_TPR (*(volatile unsigned long *)0xFFFC0108)
#define US0_TPR_OFFSET 0x108

#define US0_TCR (*(volatile unsigned long *)0xFFFC010C)
#define US0_TCR_OFFSET 0x10C

#define US0_RNPR (*(volatile unsigned long *)0xFFFC0110)
#define US0_RNPR_OFFSET 0x110

#define US0_RNCR (*(volatile unsigned long *)0xFFFC0114)
#define US0_RNCR_OFFSET 0x114

#define US0_TNPR (*(volatile unsigned long *)0xFFFC0118)
#define US0_TNPR_OFFSET 0x118

#define US0_TNCR (*(volatile unsigned long *)0xFFFC011C)
#define US0_TNCR_OFFSET 0x11C

#define US0_PTCR (*(volatile unsigned long *)0xFFFC0120)
#define US0_PTCR_OFFSET 0x120
#define US0_PTCR_RXTEN_MASK 0x1U
#define US0_PTCR_RXTEN 0x1U
#define US0_PTCR_RXTEN_BIT 0
#define US0_PTCR_RXTDIS_MASK 0x2U
#define US0_PTCR_RXTDIS 0x2U
#define US0_PTCR_RXTDIS_BIT 1
#define US0_PTCR_TXTEN_MASK 0x100U
#define US0_PTCR_TXTEN 0x100U
#define US0_PTCR_TXTEN_BIT 8
#define US0_PTCR_TXTDIS_MASK 0x1E00U
#define US0_PTCR_TXTDIS_BIT 9

#define US0_PTSR (*(volatile unsigned long *)0xFFFC0124)
#define US0_PTSR_OFFSET 0x124
#define US0_PTSR_RXTEN_MASK 0x1U
#define US0_PTSR_RXTEN 0x1U
#define US0_PTSR_RXTEN_BIT 0
#define US0_PTSR_TXTEN_MASK 0x1E00U
#define US0_PTSR_TXTEN_BIT 9

#define USART1_BASE 0xFFFC4000

#define US1_CR (*(volatile unsigned long *)0xFFFC4000)
#define US1_CR_OFFSET 0x0
#define US1_CR_RSTRX_MASK 0x4U
#define US1_CR_RSTRX 0x4U
#define US1_CR_RSTRX_BIT 2
#define US1_CR_RSTTX_MASK 0x8U
#define US1_CR_RSTTX 0x8U
#define US1_CR_RSTTX_BIT 3
#define US1_CR_RXEN_MASK 0x10U
#define US1_CR_RXEN 0x10U
#define US1_CR_RXEN_BIT 4
#define US1_CR_RXDIS_MASK 0x20U
#define US1_CR_RXDIS 0x20U
#define US1_CR_RXDIS_BIT 5
#define US1_CR_TXEN_MASK 0x40U
#define US1_CR_TXEN 0x40U
#define US1_CR_TXEN_BIT 6
#define US1_CR_TXDIS_MASK 0x80U
#define US1_CR_TXDIS 0x80U
#define US1_CR_TXDIS_BIT 7
#define US1_CR_RSTSTA_MASK 0x100U
#define US1_CR_RSTSTA 0x100U
#define US1_CR_RSTSTA_BIT 8
#define US1_CR_STTBRK_MASK 0x200U
#define US1_CR_STTBRK 0x200U
#define US1_CR_STTBRK_BIT 9
#define US1_CR_STPBRK_MASK 0x400U
#define US1_CR_STPBRK 0x400U
#define US1_CR_STPBRK_BIT 10
#define US1_CR_STTTO_MASK 0x800U
#define US1_CR_STTTO 0x800U
#define US1_CR_STTTO_BIT 11
#define US1_CR_SENDA_MASK 0x1000U
#define US1_CR_SENDA 0x1000U
#define US1_CR_SENDA_BIT 12
#define US1_CR_RSTIT_MASK 0x2000U
#define US1_CR_RSTIT 0x2000U
#define US1_CR_RSTIT_BIT 13
#define US1_CR_RSTNACK_MASK 0x4000U
#define US1_CR_RSTNACK 0x4000U
#define US1_CR_RSTNACK_BIT 14
#define US1_CR_RETTO_MASK 0x8000U
#define US1_CR_RETTO 0x8000U
#define US1_CR_RETTO_BIT 15
#define US1_CR_DTREN_MASK 0x10000U
#define US1_CR_DTREN 0x10000U
#define US1_CR_DTREN_BIT 16
#define US1_CR_DTRDIS_MASK 0x20000U
#define US1_CR_DTRDIS 0x20000U
#define US1_CR_DTRDIS_BIT 17
#define US1_CR_RTSEN_MASK 0x40000U
#define US1_CR_RTSEN 0x40000U
#define US1_CR_RTSEN_BIT 18
#define US1_CR_RTSDIS_MASK 0x80000U
#define US1_CR_RTSDIS 0x80000U
#define US1_CR_RTSDIS_BIT 19

#define US1_MR (*(volatile unsigned long *)0xFFFC4004)
#define US1_MR_OFFSET 0x4
#define US1_MR_USART_MODE_MASK 0xFU
#define US1_MR_USART_MODE_BIT 0
#define US1_MR_USCLKS_MASK 0x30U
#define US1_MR_USCLKS_BIT 4
#define US1_MR_CHRL_MASK 0xC0U
#define US1_MR_CHRL_BIT 6
#define US1_MR_SYNC_MASK 0x100U
#define US1_MR_SYNC 0x100U
#define US1_MR_SYNC_BIT 8
#define US1_MR_PAR_MASK 0xE00U
#define US1_MR_PAR_BIT 9
#define US1_MR_NBSTOP_MASK 0x3000U
#define US1_MR_NBSTOP_BIT 12
#define US1_MR_CHMODE_MASK 0xC000U
#define US1_MR_CHMODE_BIT 14
#define US1_MR_MSBF_MASK 0x10000U
#define US1_MR_MSBF 0x10000U
#define US1_MR_MSBF_BIT 16
#define US1_MR_MODE9_MASK 0x20000U
#define US1_MR_MODE9 0x20000U
#define US1_MR_MODE9_BIT 17
#define US1_MR_CLKO_MASK 0x40000U
#define US1_MR_CLKO 0x40000U
#define US1_MR_CLKO_BIT 18
#define US1_MR_OVER_MASK 0x80000U
#define US1_MR_OVER 0x80000U
#define US1_MR_OVER_BIT 19
#define US1_MR_INACK_MASK 0x100000U
#define US1_MR_INACK 0x100000U
#define US1_MR_INACK_BIT 20
#define US1_MR_DSNACK_MASK 0x200000U
#define US1_MR_DSNACK 0x200000U
#define US1_MR_DSNACK_BIT 21
#define US1_MR_MAX_ITERATION_MASK 0x7000000U
#define US1_MR_MAX_ITERATION_BIT 24
#define US1_MR_FILTER_MASK 0x10000000U
#define US1_MR_FILTER 0x10000000U
#define US1_MR_FILTER_BIT 28

#define US1_IER (*(volatile unsigned long *)0xFFFC4008)
#define US1_IER_OFFSET 0x8
#define US1_IER_RXRDY_MASK 0x1U
#define US1_IER_RXRDY 0x1U
#define US1_IER_RXRDY_BIT 0
#define US1_IER_TXRDY_MASK 0x2U
#define US1_IER_TXRDY 0x2U
#define US1_IER_TXRDY_BIT 1
#define US1_IER_RXBRK_MASK 0x4U
#define US1_IER_RXBRK 0x4U
#define US1_IER_RXBRK_BIT 2
#define US1_IER_ENDRX_MASK 0x8U
#define US1_IER_ENDRX 0x8U
#define US1_IER_ENDRX_BIT 3
#define US1_IER_ENDTX_MASK 0x10U
#define US1_IER_ENDTX 0x10U
#define US1_IER_ENDTX_BIT 4
#define US1_IER_OVRE_MASK 0x20U
#define US1_IER_OVRE 0x20U
#define US1_IER_OVRE_BIT 5
#define US1_IER_FRAME_MASK 0x40U
#define US1_IER_FRAME 0x40U
#define US1_IER_FRAME_BIT 6
#define US1_IER_PARE_MASK 0x80U
#define US1_IER_PARE 0x80U
#define US1_IER_PARE_BIT 7
#define US1_IER_TIMEOUT_MASK 0x100U
#define US1_IER_TIMEOUT 0x100U
#define US1_IER_TIMEOUT_BIT 8
#define US1_IER_TXEMPTY_MASK 0x200U
#define US1_IER_TXEMPTY 0x200U
#define US1_IER_TXEMPTY_BIT 9
#define US1_IER_ITERATION_MASK 0x400U
#define US1_IER_ITERATION 0x400U
#define US1_IER_ITERATION_BIT 10
#define US1_IER_TXBUFE_MASK 0x800U
#define US1_IER_TXBUFE 0x800U
#define US1_IER_TXBUFE_BIT 11
#define US1_IER_RXBUFF_MASK 0x1000U
#define US1_IER_RXBUFF 0x1000U
#define US1_IER_RXBUFF_BIT 12
#define US1_IER_NACK_MASK 0x2000U
#define US1_IER_NACK 0x2000U
#define US1_IER_NACK_BIT 13
#define US1_IER_RIIC_MASK 0x10000U
#define US1_IER_RIIC 0x10000U
#define US1_IER_RIIC_BIT 16
#define US1_IER_DSRIC_MASK 0x20000U
#define US1_IER_DSRIC 0x20000U
#define US1_IER_DSRIC_BIT 17
#define US1_IER_DCDIC_MASK 0x40000U
#define US1_IER_DCDIC 0x40000U
#define US1_IER_DCDIC_BIT 18
#define US1_IER_CTSIC_MASK 0x80000U
#define US1_IER_CTSIC 0x80000U
#define US1_IER_CTSIC_BIT 19

#define US1_IDR (*(volatile unsigned long *)0xFFFC400C)
#define US1_IDR_OFFSET 0xC
#define US1_IDR_RXRDY_MASK 0x1U
#define US1_IDR_RXRDY 0x1U
#define US1_IDR_RXRDY_BIT 0
#define US1_IDR_TXRDY_MASK 0x2U
#define US1_IDR_TXRDY 0x2U
#define US1_IDR_TXRDY_BIT 1
#define US1_IDR_RXBRK_MASK 0x4U
#define US1_IDR_RXBRK 0x4U
#define US1_IDR_RXBRK_BIT 2
#define US1_IDR_ENDRX_MASK 0x8U
#define US1_IDR_ENDRX 0x8U
#define US1_IDR_ENDRX_BIT 3
#define US1_IDR_ENDTX_MASK 0x10U
#define US1_IDR_ENDTX 0x10U
#define US1_IDR_ENDTX_BIT 4
#define US1_IDR_OVRE_MASK 0x20U
#define US1_IDR_OVRE 0x20U
#define US1_IDR_OVRE_BIT 5
#define US1_IDR_FRAME_MASK 0x40U
#define US1_IDR_FRAME 0x40U
#define US1_IDR_FRAME_BIT 6
#define US1_IDR_PARE_MASK 0x80U
#define US1_IDR_PARE 0x80U
#define US1_IDR_PARE_BIT 7
#define US1_IDR_TIMEOUT_MASK 0x100U
#define US1_IDR_TIMEOUT 0x100U
#define US1_IDR_TIMEOUT_BIT 8
#define US1_IDR_TXEMPTY_MASK 0x200U
#define US1_IDR_TXEMPTY 0x200U
#define US1_IDR_TXEMPTY_BIT 9
#define US1_IDR_ITERATION_MASK 0x400U
#define US1_IDR_ITERATION 0x400U
#define US1_IDR_ITERATION_BIT 10
#define US1_IDR_TXBUFE_MASK 0x800U
#define US1_IDR_TXBUFE 0x800U
#define US1_IDR_TXBUFE_BIT 11
#define US1_IDR_RXBUFF_MASK 0x1000U
#define US1_IDR_RXBUFF 0x1000U
#define US1_IDR_RXBUFF_BIT 12
#define US1_IDR_NACK_MASK 0x2000U
#define US1_IDR_NACK 0x2000U
#define US1_IDR_NACK_BIT 13
#define US1_IDR_RIIC_MASK 0x10000U
#define US1_IDR_RIIC 0x10000U
#define US1_IDR_RIIC_BIT 16
#define US1_IDR_DSRIC_MASK 0x20000U
#define US1_IDR_DSRIC 0x20000U
#define US1_IDR_DSRIC_BIT 17
#define US1_IDR_DCDIC_MASK 0x40000U
#define US1_IDR_DCDIC 0x40000U
#define US1_IDR_DCDIC_BIT 18
#define US1_IDR_CTSIC_MASK 0x80000U
#define US1_IDR_CTSIC 0x80000U
#define US1_IDR_CTSIC_BIT 19

#define US1_IMR (*(volatile unsigned long *)0xFFFC4010)
#define US1_IMR_OFFSET 0x10
#define US1_IMR_RXRDY_MASK 0x1U
#define US1_IMR_RXRDY 0x1U
#define US1_IMR_RXRDY_BIT 0
#define US1_IMR_TXRDY_MASK 0x2U
#define US1_IMR_TXRDY 0x2U
#define US1_IMR_TXRDY_BIT 1
#define US1_IMR_RXBRK_MASK 0x4U
#define US1_IMR_RXBRK 0x4U
#define US1_IMR_RXBRK_BIT 2
#define US1_IMR_ENDRX_MASK 0x8U
#define US1_IMR_ENDRX 0x8U
#define US1_IMR_ENDRX_BIT 3
#define US1_IMR_ENDTX_MASK 0x10U
#define US1_IMR_ENDTX 0x10U
#define US1_IMR_ENDTX_BIT 4
#define US1_IMR_OVRE_MASK 0x20U
#define US1_IMR_OVRE 0x20U
#define US1_IMR_OVRE_BIT 5
#define US1_IMR_FRAME_MASK 0x40U
#define US1_IMR_FRAME 0x40U
#define US1_IMR_FRAME_BIT 6
#define US1_IMR_PARE_MASK 0x80U
#define US1_IMR_PARE 0x80U
#define US1_IMR_PARE_BIT 7
#define US1_IMR_TIMEOUT_MASK 0x100U
#define US1_IMR_TIMEOUT 0x100U
#define US1_IMR_TIMEOUT_BIT 8
#define US1_IMR_TXEMPTY_MASK 0x200U
#define US1_IMR_TXEMPTY 0x200U
#define US1_IMR_TXEMPTY_BIT 9
#define US1_IMR_ITERATION_MASK 0x400U
#define US1_IMR_ITERATION 0x400U
#define US1_IMR_ITERATION_BIT 10
#define US1_IMR_TXBUFE_MASK 0x800U
#define US1_IMR_TXBUFE 0x800U
#define US1_IMR_TXBUFE_BIT 11
#define US1_IMR_RXBUFF_MASK 0x1000U
#define US1_IMR_RXBUFF 0x1000U
#define US1_IMR_RXBUFF_BIT 12
#define US1_IMR_NACK_MASK 0x2000U
#define US1_IMR_NACK 0x2000U
#define US1_IMR_NACK_BIT 13
#define US1_IMR_RIIC_MASK 0x10000U
#define US1_IMR_RIIC 0x10000U
#define US1_IMR_RIIC_BIT 16
#define US1_IMR_DSRIC_MASK 0x20000U
#define US1_IMR_DSRIC 0x20000U
#define US1_IMR_DSRIC_BIT 17
#define US1_IMR_DCDIC_MASK 0x40000U
#define US1_IMR_DCDIC 0x40000U
#define US1_IMR_DCDIC_BIT 18
#define US1_IMR_CTSIC_MASK 0x80000U
#define US1_IMR_CTSIC 0x80000U
#define US1_IMR_CTSIC_BIT 19

#define US1_CSR (*(volatile unsigned long *)0xFFFC4014)
#define US1_CSR_OFFSET 0x14
#define US1_CSR_RXRDY_MASK 0x1U
#define US1_CSR_RXRDY 0x1U
#define US1_CSR_RXRDY_BIT 0
#define US1_CSR_TXRDY_MASK 0x2U
#define US1_CSR_TXRDY 0x2U
#define US1_CSR_TXRDY_BIT 1
#define US1_CSR_RXBRK_MASK 0x4U
#define US1_CSR_RXBRK 0x4U
#define US1_CSR_RXBRK_BIT 2
#define US1_CSR_ENDRX_MASK 0x8U
#define US1_CSR_ENDRX 0x8U
#define US1_CSR_ENDRX_BIT 3
#define US1_CSR_ENDTX_MASK 0x10U
#define US1_CSR_ENDTX 0x10U
#define US1_CSR_ENDTX_BIT 4
#define US1_CSR_OVRE_MASK 0x20U
#define US1_CSR_OVRE 0x20U
#define US1_CSR_OVRE_BIT 5
#define US1_CSR_FRAME_MASK 0x40U
#define US1_CSR_FRAME 0x40U
#define US1_CSR_FRAME_BIT 6
#define US1_CSR_PARE_MASK 0x80U
#define US1_CSR_PARE 0x80U
#define US1_CSR_PARE_BIT 7
#define US1_CSR_TIMEOUT_MASK 0x100U
#define US1_CSR_TIMEOUT 0x100U
#define US1_CSR_TIMEOUT_BIT 8
#define US1_CSR_TXEMPTY_MASK 0x200U
#define US1_CSR_TXEMPTY 0x200U
#define US1_CSR_TXEMPTY_BIT 9
#define US1_CSR_ITERATION_MASK 0x400U
#define US1_CSR_ITERATION 0x400U
#define US1_CSR_ITERATION_BIT 10
#define US1_CSR_TXBUFE_MASK 0x800U
#define US1_CSR_TXBUFE 0x800U
#define US1_CSR_TXBUFE_BIT 11
#define US1_CSR_RXBUFF_MASK 0x1000U
#define US1_CSR_RXBUFF 0x1000U
#define US1_CSR_RXBUFF_BIT 12
#define US1_CSR_NACK_MASK 0x2000U
#define US1_CSR_NACK 0x2000U
#define US1_CSR_NACK_BIT 13
#define US1_CSR_RIIC_MASK 0x10000U
#define US1_CSR_RIIC 0x10000U
#define US1_CSR_RIIC_BIT 16
#define US1_CSR_DSRIC_MASK 0x20000U
#define US1_CSR_DSRIC 0x20000U
#define US1_CSR_DSRIC_BIT 17
#define US1_CSR_DCDIC_MASK 0x40000U
#define US1_CSR_DCDIC 0x40000U
#define US1_CSR_DCDIC_BIT 18
#define US1_CSR_CTSIC_MASK 0x80000U
#define US1_CSR_CTSIC 0x80000U
#define US1_CSR_CTSIC_BIT 19
#define US1_CSR_RI_MASK 0x100000U
#define US1_CSR_RI 0x100000U
#define US1_CSR_RI_BIT 20
#define US1_CSR_DSR_MASK 0x200000U
#define US1_CSR_DSR 0x200000U
#define US1_CSR_DSR_BIT 21
#define US1_CSR_DCD_MASK 0x400000U
#define US1_CSR_DCD 0x400000U
#define US1_CSR_DCD_BIT 22
#define US1_CSR_CTS_MASK 0x800000U
#define US1_CSR_CTS 0x800000U
#define US1_CSR_CTS_BIT 23

#define US1_RHR (*(volatile unsigned long *)0xFFFC4018)
#define US1_RHR_OFFSET 0x18

#define US1_THR (*(volatile unsigned long *)0xFFFC401C)
#define US1_THR_OFFSET 0x1C

#define US1_BRGR (*(volatile unsigned long *)0xFFFC4020)
#define US1_BRGR_OFFSET 0x20

#define US1_RTOR (*(volatile unsigned long *)0xFFFC4024)
#define US1_RTOR_OFFSET 0x24

#define US1_TTGR (*(volatile unsigned long *)0xFFFC4028)
#define US1_TTGR_OFFSET 0x28

#define US1_FIDI (*(volatile unsigned long *)0xFFFC4040)
#define US1_FIDI_OFFSET 0x40

#define US1_NER (*(volatile unsigned long *)0xFFFC4044)
#define US1_NER_OFFSET 0x44

#define US1_IF (*(volatile unsigned long *)0xFFFC404C)
#define US1_IF_OFFSET 0x4C

#define US1_RPR (*(volatile unsigned long *)0xFFFC4100)
#define US1_RPR_OFFSET 0x100

#define US1_RCR (*(volatile unsigned long *)0xFFFC4104)
#define US1_RCR_OFFSET 0x104

#define US1_TPR (*(volatile unsigned long *)0xFFFC4108)
#define US1_TPR_OFFSET 0x108

#define US1_TCR (*(volatile unsigned long *)0xFFFC410C)
#define US1_TCR_OFFSET 0x10C

#define US1_RNPR (*(volatile unsigned long *)0xFFFC4110)
#define US1_RNPR_OFFSET 0x110

#define US1_RNCR (*(volatile unsigned long *)0xFFFC4114)
#define US1_RNCR_OFFSET 0x114

#define US1_TNPR (*(volatile unsigned long *)0xFFFC4118)
#define US1_TNPR_OFFSET 0x118

#define US1_TNCR (*(volatile unsigned long *)0xFFFC411C)
#define US1_TNCR_OFFSET 0x11C

#define US1_PTCR (*(volatile unsigned long *)0xFFFC4120)
#define US1_PTCR_OFFSET 0x120
#define US1_PTCR_RXTEN_MASK 0x1U
#define US1_PTCR_RXTEN 0x1U
#define US1_PTCR_RXTEN_BIT 0
#define US1_PTCR_RXTDIS_MASK 0x2U
#define US1_PTCR_RXTDIS 0x2U
#define US1_PTCR_RXTDIS_BIT 1
#define US1_PTCR_TXTEN_MASK 0x100U
#define US1_PTCR_TXTEN 0x100U
#define US1_PTCR_TXTEN_BIT 8
#define US1_PTCR_TXTDIS_MASK 0x1E00U
#define US1_PTCR_TXTDIS_BIT 9

#define US1_PTSR (*(volatile unsigned long *)0xFFFC4124)
#define US1_PTSR_OFFSET 0x124
#define US1_PTSR_RXTEN_MASK 0x1U
#define US1_PTSR_RXTEN 0x1U
#define US1_PTSR_RXTEN_BIT 0
#define US1_PTSR_TXTEN_MASK 0x1E00U
#define US1_PTSR_TXTEN_BIT 9

#define PWM_BASE 0xFFFCC000

#define PWM_MR (*(volatile unsigned long *)0xFFFCC000)
#define PWM_MR_OFFSET 0x0
#define PWM_MR_DIVA_MASK 0xFFU
#define PWM_MR_DIVA_BIT 0
#define PWM_MR_PREA_MASK 0xF00U
#define PWM_MR_PREA_BIT 8
#define PWM_MR_DIVB_MASK 0xFF0000U
#define PWM_MR_DIVB_BIT 16
#define PWM_MR_PREB_MASK 0xF000000U
#define PWM_MR_PREB_BIT 24

#define PWM_ENA (*(volatile unsigned long *)0xFFFCC004)
#define PWM_ENA_OFFSET 0x4
#define PWM_ENA_CHID0_MASK 0x1U
#define PWM_ENA_CHID0 0x1U
#define PWM_ENA_CHID0_BIT 0
#define PWM_ENA_CHID1_MASK 0x2U
#define PWM_ENA_CHID1 0x2U
#define PWM_ENA_CHID1_BIT 1
#define PWM_ENA_CHID2_MASK 0x4U
#define PWM_ENA_CHID2 0x4U
#define PWM_ENA_CHID2_BIT 2
#define PWM_ENA_CHID3_MASK 0x8U
#define PWM_ENA_CHID3 0x8U
#define PWM_ENA_CHID3_BIT 3

#define PWM_DIS (*(volatile unsigned long *)0xFFFCC008)
#define PWM_DIS_OFFSET 0x8
#define PWM_DIS_CHID0_MASK 0x1U
#define PWM_DIS_CHID0 0x1U
#define PWM_DIS_CHID0_BIT 0
#define PWM_DIS_CHID1_MASK 0x2U
#define PWM_DIS_CHID1 0x2U
#define PWM_DIS_CHID1_BIT 1
#define PWM_DIS_CHID2_MASK 0x4U
#define PWM_DIS_CHID2 0x4U
#define PWM_DIS_CHID2_BIT 2
#define PWM_DIS_CHID3_MASK 0x8U
#define PWM_DIS_CHID3 0x8U
#define PWM_DIS_CHID3_BIT 3

#define PWM_SR (*(volatile unsigned long *)0xFFFCC00C)
#define PWM_SR_OFFSET 0xC
#define PWM_SR_CHID0_MASK 0x1U
#define PWM_SR_CHID0 0x1U
#define PWM_SR_CHID0_BIT 0
#define PWM_SR_CHID1_MASK 0x2U
#define PWM_SR_CHID1 0x2U
#define PWM_SR_CHID1_BIT 1
#define PWM_SR_CHID2_MASK 0x4U
#define PWM_SR_CHID2 0x4U
#define PWM_SR_CHID2_BIT 2
#define PWM_SR_CHID3_MASK 0x8U
#define PWM_SR_CHID3 0x8U
#define PWM_SR_CHID3_BIT 3

#define PWM_IER (*(volatile unsigned long *)0xFFFCC010)
#define PWM_IER_OFFSET 0x10
#define PWM_IER_CHID0_MASK 0x1U
#define PWM_IER_CHID0 0x1U
#define PWM_IER_CHID0_BIT 0
#define PWM_IER_CHID1_MASK 0x2U
#define PWM_IER_CHID1 0x2U
#define PWM_IER_CHID1_BIT 1
#define PWM_IER_CHID2_MASK 0x4U
#define PWM_IER_CHID2 0x4U
#define PWM_IER_CHID2_BIT 2
#define PWM_IER_CHID3_MASK 0x8U
#define PWM_IER_CHID3 0x8U
#define PWM_IER_CHID3_BIT 3

#define PWM_IDR (*(volatile unsigned long *)0xFFFCC014)
#define PWM_IDR_OFFSET 0x14
#define PWM_IDR_CHID0_MASK 0x1U
#define PWM_IDR_CHID0 0x1U
#define PWM_IDR_CHID0_BIT 0
#define PWM_IDR_CHID1_MASK 0x2U
#define PWM_IDR_CHID1 0x2U
#define PWM_IDR_CHID1_BIT 1
#define PWM_IDR_CHID2_MASK 0x4U
#define PWM_IDR_CHID2 0x4U
#define PWM_IDR_CHID2_BIT 2
#define PWM_IDR_CHID3_MASK 0x8U
#define PWM_IDR_CHID3 0x8U
#define PWM_IDR_CHID3_BIT 3

#define PWM_IMR (*(volatile unsigned long *)0xFFFCC018)
#define PWM_IMR_OFFSET 0x18
#define PWM_IMR_CHID0_MASK 0x1U
#define PWM_IMR_CHID0 0x1U
#define PWM_IMR_CHID0_BIT 0
#define PWM_IMR_CHID1_MASK 0x2U
#define PWM_IMR_CHID1 0x2U
#define PWM_IMR_CHID1_BIT 1
#define PWM_IMR_CHID2_MASK 0x4U
#define PWM_IMR_CHID2 0x4U
#define PWM_IMR_CHID2_BIT 2
#define PWM_IMR_CHID3_MASK 0x8U
#define PWM_IMR_CHID3 0x8U
#define PWM_IMR_CHID3_BIT 3

#define PWM_ISR (*(volatile unsigned long *)0xFFFCC01C)
#define PWM_ISR_OFFSET 0x1C
#define PWM_ISR_CHID0_MASK 0x1U
#define PWM_ISR_CHID0 0x1U
#define PWM_ISR_CHID0_BIT 0
#define PWM_ISR_CHID1_MASK 0x2U
#define PWM_ISR_CHID1 0x2U
#define PWM_ISR_CHID1_BIT 1
#define PWM_ISR_CHID2_MASK 0x4U
#define PWM_ISR_CHID2 0x4U
#define PWM_ISR_CHID2_BIT 2
#define PWM_ISR_CHID3_MASK 0x8U
#define PWM_ISR_CHID3 0x8U
#define PWM_ISR_CHID3_BIT 3

#define PWM_VERSION (*(volatile unsigned long *)0xFFFCC0FC)
#define PWM_VERSION_OFFSET 0xFC
#define PWM_VERSION_VERSION_MASK 0xFFFU
#define PWM_VERSION_VERSION_BIT 0
#define PWM_VERSION_MFN_MASK 0x70000U
#define PWM_VERSION_MFN_BIT 16

#define PWM_CMR0 (*(volatile unsigned long *)0xFFFCC200)
#define PWM_CMR0_OFFSET 0x200
#define PWM_CMR0_CPRE_MASK 0xFU
#define PWM_CMR0_CPRE_BIT 0
#define PWM_CMR0_CALG_MASK 0x100U
#define PWM_CMR0_CALG 0x100U
#define PWM_CMR0_CALG_BIT 8
#define PWM_CMR0_CPOL_MASK 0x200U
#define PWM_CMR0_CPOL 0x200U
#define PWM_CMR0_CPOL_BIT 9
#define PWM_CMR0_CPD_MASK 0x400U
#define PWM_CMR0_CPD 0x400U
#define PWM_CMR0_CPD_BIT 10

#define PWM_CDTY0 (*(volatile unsigned long *)0xFFFCC204)
#define PWM_CDTY0_OFFSET 0x204

#define PWM_CPRD0 (*(volatile unsigned long *)0xFFFCC208)
#define PWM_CPRD0_OFFSET 0x208

#define PWM_CCNT0 (*(volatile unsigned long *)0xFFFCC20C)
#define PWM_CCNT0_OFFSET 0x20C

#define PWM_CUPD0 (*(volatile unsigned long *)0xFFFCC210)
#define PWM_CUPD0_OFFSET 0x210

#define PWM_CMR1 (*(volatile unsigned long *)0xFFFCC220)
#define PWM_CMR1_OFFSET 0x220

#define PWM_CDTY1 (*(volatile unsigned long *)0xFFFCC224)
#define PWM_CDTY1_OFFSET 0x224

#define PWM_CPRD1 (*(volatile unsigned long *)0xFFFCC228)
#define PWM_CPRD1_OFFSET 0x228

#define PWM_CCNT1 (*(volatile unsigned long *)0xFFFCC22C)
#define PWM_CCNT1_OFFSET 0x22C

#define PWM_CUPD1 (*(volatile unsigned long *)0xFFFCC230)
#define PWM_CUPD1_OFFSET 0x230

#define SSC_BASE 0xFFFD4000

#define SSC_CR (*(volatile unsigned long *)0xFFFD4000)
#define SSC_CR_OFFSET 0x0
#define SSC_CR_RXEN_MASK 0x1U
#define SSC_CR_RXEN 0x1U
#define SSC_CR_RXEN_BIT 0
#define SSC_CR_RXDIS_MASK 0x2U
#define SSC_CR_RXDIS 0x2U
#define SSC_CR_RXDIS_BIT 1
#define SSC_CR_TXEN_MASK 0x100U
#define SSC_CR_TXEN 0x100U
#define SSC_CR_TXEN_BIT 8
#define SSC_CR_TXDIS_MASK 0x200U
#define SSC_CR_TXDIS 0x200U
#define SSC_CR_TXDIS_BIT 9
#define SSC_CR_SWRST_MASK 0x8000U
#define SSC_CR_SWRST 0x8000U
#define SSC_CR_SWRST_BIT 15

#define SSC_CMR (*(volatile unsigned long *)0xFFFD4004)
#define SSC_CMR_OFFSET 0x4

#define SSC_RCMR (*(volatile unsigned long *)0xFFFD4010)
#define SSC_RCMR_OFFSET 0x10
#define SSC_RCMR_CKS_MASK 0x3U
#define SSC_RCMR_CKS_BIT 0
#define SSC_RCMR_CKO_MASK 0x1CU
#define SSC_RCMR_CKO_BIT 2
#define SSC_RCMR_CKI_MASK 0x20U
#define SSC_RCMR_CKI 0x20U
#define SSC_RCMR_CKI_BIT 5
#define SSC_RCMR_START_MASK 0xF00U
#define SSC_RCMR_START_BIT 8
#define SSC_RCMR_STTDLY_MASK 0xFF0000U
#define SSC_RCMR_STTDLY_BIT 16
#define SSC_RCMR_PERIOD_MASK 0xFF000000U
#define SSC_RCMR_PERIOD_BIT 24

#define SSC_RFMR (*(volatile unsigned long *)0xFFFD4014)
#define SSC_RFMR_OFFSET 0x14
#define SSC_RFMR_DATLEN_MASK 0x1FU
#define SSC_RFMR_DATLEN_BIT 0
#define SSC_RFMR_LOOP_MASK 0x20U
#define SSC_RFMR_LOOP 0x20U
#define SSC_RFMR_LOOP_BIT 5
#define SSC_RFMR_MSBF_MASK 0x80U
#define SSC_RFMR_MSBF 0x80U
#define SSC_RFMR_MSBF_BIT 7
#define SSC_RFMR_DATNB_MASK 0xF00U
#define SSC_RFMR_DATNB_BIT 8
#define SSC_RFMR_FSLEN_MASK 0xF0000U
#define SSC_RFMR_FSLEN_BIT 16
#define SSC_RFMR_FSOS_MASK 0xF00000U
#define SSC_RFMR_FSOS_BIT 20
#define SSC_RFMR_FSEDGE_MASK 0x1000000U
#define SSC_RFMR_FSEDGE 0x1000000U
#define SSC_RFMR_FSEDGE_BIT 24

#define SSC_TCMR (*(volatile unsigned long *)0xFFFD4018)
#define SSC_TCMR_OFFSET 0x18
#define SSC_TCMR_CKS_MASK 0x3U
#define SSC_TCMR_CKS_BIT 0
#define SSC_TCMR_CKO_MASK 0x1CU
#define SSC_TCMR_CKO_BIT 2
#define SSC_TCMR_CKI_MASK 0x20U
#define SSC_TCMR_CKI 0x20U
#define SSC_TCMR_CKI_BIT 5
#define SSC_TCMR_START_MASK 0xF00U
#define SSC_TCMR_START_BIT 8
#define SSC_TCMR_STTDLY_MASK 0xFF0000U
#define SSC_TCMR_STTDLY_BIT 16
#define SSC_TCMR_PERIOD_MASK 0xFF000000U
#define SSC_TCMR_PERIOD_BIT 24

#define SSC_TFMR (*(volatile unsigned long *)0xFFFD401C)
#define SSC_TFMR_OFFSET 0x1C
#define SSC_TFMR_DATLEN_MASK 0x1FU
#define SSC_TFMR_DATLEN_BIT 0
#define SSC_TFMR_DATDEF_MASK 0x20U
#define SSC_TFMR_DATDEF 0x20U
#define SSC_TFMR_DATDEF_BIT 5
#define SSC_TFMR_MSBF_MASK 0x80U
#define SSC_TFMR_MSBF 0x80U
#define SSC_TFMR_MSBF_BIT 7
#define SSC_TFMR_DATNB_MASK 0xF00U
#define SSC_TFMR_DATNB_BIT 8
#define SSC_TFMR_FSLEN_MASK 0xF0000U
#define SSC_TFMR_FSLEN_BIT 16
#define SSC_TFMR_FSOS_MASK 0x700000U
#define SSC_TFMR_FSOS_BIT 20
#define SSC_TFMR_FSDEN_MASK 0x1000000U
#define SSC_TFMR_FSDEN 0x1000000U
#define SSC_TFMR_FSDEN_BIT 24
#define SSC_TFMR_FSEDGE_MASK 0x1000000U
#define SSC_TFMR_FSEDGE 0x1000000U
#define SSC_TFMR_FSEDGE_BIT 24

#define SSC_RHR (*(volatile unsigned long *)0xFFFD4020)
#define SSC_RHR_OFFSET 0x20

#define SSC_THR (*(volatile unsigned long *)0xFFFD4024)
#define SSC_THR_OFFSET 0x24

#define SSC_RSHR (*(volatile unsigned long *)0xFFFD4030)
#define SSC_RSHR_OFFSET 0x30

#define SSC_TSHR (*(volatile unsigned long *)0xFFFD4034)
#define SSC_TSHR_OFFSET 0x34

#define SSC_SR (*(volatile unsigned long *)0xFFFD4040)
#define SSC_SR_OFFSET 0x40
#define SSC_SR_TXRDY_MASK 0x1U
#define SSC_SR_TXRDY 0x1U
#define SSC_SR_TXRDY_BIT 0
#define SSC_SR_TXEMPTY_MASK 0x2U
#define SSC_SR_TXEMPTY 0x2U
#define SSC_SR_TXEMPTY_BIT 1
#define SSC_SR_ENDTX_MASK 0x4U
#define SSC_SR_ENDTX 0x4U
#define SSC_SR_ENDTX_BIT 2
#define SSC_SR_TXBUFE_MASK 0x8U
#define SSC_SR_TXBUFE 0x8U
#define SSC_SR_TXBUFE_BIT 3
#define SSC_SR_RXRDY_MASK 0x10U
#define SSC_SR_RXRDY 0x10U
#define SSC_SR_RXRDY_BIT 4
#define SSC_SR_OVRUN_MASK 0x20U
#define SSC_SR_OVRUN 0x20U
#define SSC_SR_OVRUN_BIT 5
#define SSC_SR_ENDRX_MASK 0x40U
#define SSC_SR_ENDRX 0x40U
#define SSC_SR_ENDRX_BIT 6
#define SSC_SR_RXBUFF_MASK 0x80U
#define SSC_SR_RXBUFF 0x80U
#define SSC_SR_RXBUFF_BIT 7
#define SSC_SR_TXSYN_MASK 0x400U
#define SSC_SR_TXSYN 0x400U
#define SSC_SR_TXSYN_BIT 10
#define SSC_SR_RXSYN_MASK 0x800U
#define SSC_SR_RXSYN 0x800U
#define SSC_SR_RXSYN_BIT 11
#define SSC_SR_TXEN_MASK 0x10000U
#define SSC_SR_TXEN 0x10000U
#define SSC_SR_TXEN_BIT 16
#define SSC_SR_RXEN_MASK 0x20000U
#define SSC_SR_RXEN 0x20000U
#define SSC_SR_RXEN_BIT 17

#define SSC_IER (*(volatile unsigned long *)0xFFFD4044)
#define SSC_IER_OFFSET 0x44
#define SSC_IER_TXRDY_MASK 0x1U
#define SSC_IER_TXRDY 0x1U
#define SSC_IER_TXRDY_BIT 0
#define SSC_IER_TXEMPTY_MASK 0x2U
#define SSC_IER_TXEMPTY 0x2U
#define SSC_IER_TXEMPTY_BIT 1
#define SSC_IER_ENDTX_MASK 0x4U
#define SSC_IER_ENDTX 0x4U
#define SSC_IER_ENDTX_BIT 2
#define SSC_IER_TXBUFE_MASK 0x8U
#define SSC_IER_TXBUFE 0x8U
#define SSC_IER_TXBUFE_BIT 3
#define SSC_IER_RXRDY_MASK 0x10U
#define SSC_IER_RXRDY 0x10U
#define SSC_IER_RXRDY_BIT 4
#define SSC_IER_OVRUN_MASK 0x20U
#define SSC_IER_OVRUN 0x20U
#define SSC_IER_OVRUN_BIT 5
#define SSC_IER_ENDRX_MASK 0x40U
#define SSC_IER_ENDRX 0x40U
#define SSC_IER_ENDRX_BIT 6
#define SSC_IER_RXBUFF_MASK 0x80U
#define SSC_IER_RXBUFF 0x80U
#define SSC_IER_RXBUFF_BIT 7
#define SSC_IER_TXSYN_MASK 0x400U
#define SSC_IER_TXSYN 0x400U
#define SSC_IER_TXSYN_BIT 10
#define SSC_IER_RXSYN_MASK 0x800U
#define SSC_IER_RXSYN 0x800U
#define SSC_IER_RXSYN_BIT 11

#define SSC_IDR (*(volatile unsigned long *)0xFFFD4048)
#define SSC_IDR_OFFSET 0x48
#define SSC_IDR_TXRDY_MASK 0x1U
#define SSC_IDR_TXRDY 0x1U
#define SSC_IDR_TXRDY_BIT 0
#define SSC_IDR_TXEMPTY_MASK 0x2U
#define SSC_IDR_TXEMPTY 0x2U
#define SSC_IDR_TXEMPTY_BIT 1
#define SSC_IDR_ENDTX_MASK 0x4U
#define SSC_IDR_ENDTX 0x4U
#define SSC_IDR_ENDTX_BIT 2
#define SSC_IDR_TXBUFE_MASK 0x8U
#define SSC_IDR_TXBUFE 0x8U
#define SSC_IDR_TXBUFE_BIT 3
#define SSC_IDR_RXRDY_MASK 0x10U
#define SSC_IDR_RXRDY 0x10U
#define SSC_IDR_RXRDY_BIT 4
#define SSC_IDR_OVRUN_MASK 0x20U
#define SSC_IDR_OVRUN 0x20U
#define SSC_IDR_OVRUN_BIT 5
#define SSC_IDR_ENDRX_MASK 0x40U
#define SSC_IDR_ENDRX 0x40U
#define SSC_IDR_ENDRX_BIT 6
#define SSC_IDR_RXBUFF_MASK 0x80U
#define SSC_IDR_RXBUFF 0x80U
#define SSC_IDR_RXBUFF_BIT 7
#define SSC_IDR_TXSYN_MASK 0x400U
#define SSC_IDR_TXSYN 0x400U
#define SSC_IDR_TXSYN_BIT 10
#define SSC_IDR_RXSYN_MASK 0x800U
#define SSC_IDR_RXSYN 0x800U
#define SSC_IDR_RXSYN_BIT 11

#define SSC_IMR (*(volatile unsigned long *)0xFFFD404C)
#define SSC_IMR_OFFSET 0x4C
#define SSC_IMR_TXRDY_MASK 0x1U
#define SSC_IMR_TXRDY 0x1U
#define SSC_IMR_TXRDY_BIT 0
#define SSC_IMR_TXEMPTY_MASK 0x2U
#define SSC_IMR_TXEMPTY 0x2U
#define SSC_IMR_TXEMPTY_BIT 1
#define SSC_IMR_ENDTX_MASK 0x4U
#define SSC_IMR_ENDTX 0x4U
#define SSC_IMR_ENDTX_BIT 2
#define SSC_IMR_TXBUFE_MASK 0x8U
#define SSC_IMR_TXBUFE 0x8U
#define SSC_IMR_TXBUFE_BIT 3
#define SSC_IMR_RXRDY_MASK 0x10U
#define SSC_IMR_RXRDY 0x10U
#define SSC_IMR_RXRDY_BIT 4
#define SSC_IMR_OVRUN_MASK 0x20U
#define SSC_IMR_OVRUN 0x20U
#define SSC_IMR_OVRUN_BIT 5
#define SSC_IMR_ENDRX_MASK 0x40U
#define SSC_IMR_ENDRX 0x40U
#define SSC_IMR_ENDRX_BIT 6
#define SSC_IMR_RXBUFF_MASK 0x80U
#define SSC_IMR_RXBUFF 0x80U
#define SSC_IMR_RXBUFF_BIT 7
#define SSC_IMR_TXSYN_MASK 0x400U
#define SSC_IMR_TXSYN 0x400U
#define SSC_IMR_TXSYN_BIT 10
#define SSC_IMR_RXSYN_MASK 0x800U
#define SSC_IMR_RXSYN 0x800U
#define SSC_IMR_RXSYN_BIT 11

#define SSC_RPR (*(volatile unsigned long *)0xFFFD4100)
#define SSC_RPR_OFFSET 0x100

#define SSC_RCR (*(volatile unsigned long *)0xFFFD4104)
#define SSC_RCR_OFFSET 0x104

#define SSC_TPR (*(volatile unsigned long *)0xFFFD4108)
#define SSC_TPR_OFFSET 0x108

#define SSC_TCR (*(volatile unsigned long *)0xFFFD410C)
#define SSC_TCR_OFFSET 0x10C

#define SSC_RNPR (*(volatile unsigned long *)0xFFFD4110)
#define SSC_RNPR_OFFSET 0x110

#define SSC_RNCR (*(volatile unsigned long *)0xFFFD4114)
#define SSC_RNCR_OFFSET 0x114

#define SSC_TNPR (*(volatile unsigned long *)0xFFFD4118)
#define SSC_TNPR_OFFSET 0x118

#define SSC_TNCR (*(volatile unsigned long *)0xFFFD411C)
#define SSC_TNCR_OFFSET 0x11C

#define SSC_PTCR (*(volatile unsigned long *)0xFFFD4120)
#define SSC_PTCR_OFFSET 0x120
#define SSC_PTCR_RXTEN_MASK 0x1U
#define SSC_PTCR_RXTEN 0x1U
#define SSC_PTCR_RXTEN_BIT 0
#define SSC_PTCR_RXTDIS_MASK 0x2U
#define SSC_PTCR_RXTDIS 0x2U
#define SSC_PTCR_RXTDIS_BIT 1
#define SSC_PTCR_TXTEN_MASK 0x100U
#define SSC_PTCR_TXTEN 0x100U
#define SSC_PTCR_TXTEN_BIT 8
#define SSC_PTCR_TXTDIS_MASK 0x1E00U
#define SSC_PTCR_TXTDIS_BIT 9

#define SSC_PTSR (*(volatile unsigned long *)0xFFFD4124)
#define SSC_PTSR_OFFSET 0x124
#define SSC_PTSR_RXTEN_MASK 0x1U
#define SSC_PTSR_RXTEN 0x1U
#define SSC_PTSR_RXTEN_BIT 0
#define SSC_PTSR_TXTEN_MASK 0x1E00U
#define SSC_PTSR_TXTEN_BIT 9

#define ADC_BASE 0xFFFD8000

#define ADC_CR (*(volatile unsigned long *)0xFFFD8000)
#define ADC_CR_OFFSET 0x0
#define ADC_CR_SWRST_MASK 0x1U
#define ADC_CR_SWRST 0x1U
#define ADC_CR_SWRST_BIT 0
#define ADC_CR_START_MASK 0x2U
#define ADC_CR_START 0x2U
#define ADC_CR_START_BIT 1

#define ADC_MR (*(volatile unsigned long *)0xFFFD8004)
#define ADC_MR_OFFSET 0x4
#define ADC_MR_TRGEN_MASK 0x1U
#define ADC_MR_TRGEN 0x1U
#define ADC_MR_TRGEN_BIT 0
#define ADC_MR_TRGSEL_MASK 0xEU
#define ADC_MR_TRGSEL_BIT 1
#define ADC_MR_LOWRES_MASK 0x10U
#define ADC_MR_LOWRES 0x10U
#define ADC_MR_LOWRES_BIT 4
#define ADC_MR_SLEEP_MASK 0x20U
#define ADC_MR_SLEEP 0x20U
#define ADC_MR_SLEEP_BIT 5
#define ADC_MR_PRESCAL_MASK 0x3F00U
#define ADC_MR_PRESCAL_BIT 8
#define ADC_MR_STARTUP_MASK 0x1F0000U
#define ADC_MR_STARTUP_BIT 16
#define ADC_MR_SHTIM_MASK 0xF000000U
#define ADC_MR_SHTIM_BIT 24

#define ADC_CHER (*(volatile unsigned long *)0xFFFD8010)
#define ADC_CHER_OFFSET 0x10
#define ADC_CHER_CH0_MASK 0x1U
#define ADC_CHER_CH0 0x1U
#define ADC_CHER_CH0_BIT 0
#define ADC_CHER_CH1_MASK 0x2U
#define ADC_CHER_CH1 0x2U
#define ADC_CHER_CH1_BIT 1
#define ADC_CHER_CH2_MASK 0x4U
#define ADC_CHER_CH2 0x4U
#define ADC_CHER_CH2_BIT 2
#define ADC_CHER_CH3_MASK 0x8U
#define ADC_CHER_CH3 0x8U
#define ADC_CHER_CH3_BIT 3
#define ADC_CHER_CH4_MASK 0x10U
#define ADC_CHER_CH4 0x10U
#define ADC_CHER_CH4_BIT 4
#define ADC_CHER_CH5_MASK 0x20U
#define ADC_CHER_CH5 0x20U
#define ADC_CHER_CH5_BIT 5
#define ADC_CHER_CH6_MASK 0x40U
#define ADC_CHER_CH6 0x40U
#define ADC_CHER_CH6_BIT 6
#define ADC_CHER_CH7_MASK 0x80U
#define ADC_CHER_CH7 0x80U
#define ADC_CHER_CH7_BIT 7

#define ADC_CHDR (*(volatile unsigned long *)0xFFFD8014)
#define ADC_CHDR_OFFSET 0x14
#define ADC_CHDR_CH0_MASK 0x1U
#define ADC_CHDR_CH0 0x1U
#define ADC_CHDR_CH0_BIT 0
#define ADC_CHDR_CH1_MASK 0x2U
#define ADC_CHDR_CH1 0x2U
#define ADC_CHDR_CH1_BIT 1
#define ADC_CHDR_CH2_MASK 0x4U
#define ADC_CHDR_CH2 0x4U
#define ADC_CHDR_CH2_BIT 2
#define ADC_CHDR_CH3_MASK 0x8U
#define ADC_CHDR_CH3 0x8U
#define ADC_CHDR_CH3_BIT 3
#define ADC_CHDR_CH4_MASK 0x10U
#define ADC_CHDR_CH4 0x10U
#define ADC_CHDR_CH4_BIT 4
#define ADC_CHDR_CH5_MASK 0x20U
#define ADC_CHDR_CH5 0x20U
#define ADC_CHDR_CH5_BIT 5
#define ADC_CHDR_CH6_MASK 0x40U
#define ADC_CHDR_CH6 0x40U
#define ADC_CHDR_CH6_BIT 6
#define ADC_CHDR_CH7_MASK 0x80U
#define ADC_CHDR_CH7 0x80U
#define ADC_CHDR_CH7_BIT 7

#define ADC_CHSR (*(volatile unsigned long *)0xFFFD8018)
#define ADC_CHSR_OFFSET 0x18
#define ADC_CHSR_CH0_MASK 0x1U
#define ADC_CHSR_CH0 0x1U
#define ADC_CHSR_CH0_BIT 0
#define ADC_CHSR_CH1_MASK 0x2U
#define ADC_CHSR_CH1 0x2U
#define ADC_CHSR_CH1_BIT 1
#define ADC_CHSR_CH2_MASK 0x4U
#define ADC_CHSR_CH2 0x4U
#define ADC_CHSR_CH2_BIT 2
#define ADC_CHSR_CH3_MASK 0x8U
#define ADC_CHSR_CH3 0x8U
#define ADC_CHSR_CH3_BIT 3
#define ADC_CHSR_CH4_MASK 0x10U
#define ADC_CHSR_CH4 0x10U
#define ADC_CHSR_CH4_BIT 4
#define ADC_CHSR_CH5_MASK 0x20U
#define ADC_CHSR_CH5 0x20U
#define ADC_CHSR_CH5_BIT 5
#define ADC_CHSR_CH6_MASK 0x40U
#define ADC_CHSR_CH6 0x40U
#define ADC_CHSR_CH6_BIT 6
#define ADC_CHSR_CH7_MASK 0x80U
#define ADC_CHSR_CH7 0x80U
#define ADC_CHSR_CH7_BIT 7

#define ADC_SR (*(volatile unsigned long *)0xFFFD801C)
#define ADC_SR_OFFSET 0x1C
#define ADC_SR_EOC0_MASK 0x1U
#define ADC_SR_EOC0 0x1U
#define ADC_SR_EOC0_BIT 0
#define ADC_SR_EOC1_MASK 0x2U
#define ADC_SR_EOC1 0x2U
#define ADC_SR_EOC1_BIT 1
#define ADC_SR_EOC2_MASK 0x4U
#define ADC_SR_EOC2 0x4U
#define ADC_SR_EOC2_BIT 2
#define ADC_SR_EOC3_MASK 0x8U
#define ADC_SR_EOC3 0x8U
#define ADC_SR_EOC3_BIT 3
#define ADC_SR_EOC4_MASK 0x10U
#define ADC_SR_EOC4 0x10U
#define ADC_SR_EOC4_BIT 4
#define ADC_SR_EOC5_MASK 0x20U
#define ADC_SR_EOC5 0x20U
#define ADC_SR_EOC5_BIT 5
#define ADC_SR_EOC6_MASK 0x40U
#define ADC_SR_EOC6 0x40U
#define ADC_SR_EOC6_BIT 6
#define ADC_SR_EOC7_MASK 0x80U
#define ADC_SR_EOC7 0x80U
#define ADC_SR_EOC7_BIT 7
#define ADC_SR_OVRE0_MASK 0x100U
#define ADC_SR_OVRE0 0x100U
#define ADC_SR_OVRE0_BIT 8
#define ADC_SR_OVRE1_MASK 0x200U
#define ADC_SR_OVRE1 0x200U
#define ADC_SR_OVRE1_BIT 9
#define ADC_SR_OVRE2_MASK 0x400U
#define ADC_SR_OVRE2 0x400U
#define ADC_SR_OVRE2_BIT 10
#define ADC_SR_OVRE3_MASK 0x800U
#define ADC_SR_OVRE3 0x800U
#define ADC_SR_OVRE3_BIT 11
#define ADC_SR_OVRE4_MASK 0x1000U
#define ADC_SR_OVRE4 0x1000U
#define ADC_SR_OVRE4_BIT 12
#define ADC_SR_OVRE5_MASK 0x2000U
#define ADC_SR_OVRE5 0x2000U
#define ADC_SR_OVRE5_BIT 13
#define ADC_SR_OVRE6_MASK 0x4000U
#define ADC_SR_OVRE6 0x4000U
#define ADC_SR_OVRE6_BIT 14
#define ADC_SR_OVRE7_MASK 0x8000U
#define ADC_SR_OVRE7 0x8000U
#define ADC_SR_OVRE7_BIT 15
#define ADC_SR_DRDY_MASK 0x10000U
#define ADC_SR_DRDY 0x10000U
#define ADC_SR_DRDY_BIT 16
#define ADC_SR_GOVRE_MASK 0x20000U
#define ADC_SR_GOVRE 0x20000U
#define ADC_SR_GOVRE_BIT 17
#define ADC_SR_ENDRX_MASK 0x40000U
#define ADC_SR_ENDRX 0x40000U
#define ADC_SR_ENDRX_BIT 18
#define ADC_SR_RXBUFF_MASK 0x80000U
#define ADC_SR_RXBUFF 0x80000U
#define ADC_SR_RXBUFF_BIT 19

#define ADC_LCDR (*(volatile unsigned long *)0xFFFD8020)
#define ADC_LCDR_OFFSET 0x20

#define ADC_IER (*(volatile unsigned long *)0xFFFD8024)
#define ADC_IER_OFFSET 0x24
#define ADC_IER_EOC0_MASK 0x1U
#define ADC_IER_EOC0 0x1U
#define ADC_IER_EOC0_BIT 0
#define ADC_IER_EOC1_MASK 0x2U
#define ADC_IER_EOC1 0x2U
#define ADC_IER_EOC1_BIT 1
#define ADC_IER_EOC2_MASK 0x4U
#define ADC_IER_EOC2 0x4U
#define ADC_IER_EOC2_BIT 2
#define ADC_IER_EOC3_MASK 0x8U
#define ADC_IER_EOC3 0x8U
#define ADC_IER_EOC3_BIT 3
#define ADC_IER_EOC4_MASK 0x10U
#define ADC_IER_EOC4 0x10U
#define ADC_IER_EOC4_BIT 4
#define ADC_IER_EOC5_MASK 0x20U
#define ADC_IER_EOC5 0x20U
#define ADC_IER_EOC5_BIT 5
#define ADC_IER_EOC6_MASK 0x40U
#define ADC_IER_EOC6 0x40U
#define ADC_IER_EOC6_BIT 6
#define ADC_IER_EOC7_MASK 0x80U
#define ADC_IER_EOC7 0x80U
#define ADC_IER_EOC7_BIT 7
#define ADC_IER_OVRE0_MASK 0x100U
#define ADC_IER_OVRE0 0x100U
#define ADC_IER_OVRE0_BIT 8
#define ADC_IER_OVRE1_MASK 0x200U
#define ADC_IER_OVRE1 0x200U
#define ADC_IER_OVRE1_BIT 9
#define ADC_IER_OVRE2_MASK 0x400U
#define ADC_IER_OVRE2 0x400U
#define ADC_IER_OVRE2_BIT 10
#define ADC_IER_OVRE3_MASK 0x800U
#define ADC_IER_OVRE3 0x800U
#define ADC_IER_OVRE3_BIT 11
#define ADC_IER_OVRE4_MASK 0x1000U
#define ADC_IER_OVRE4 0x1000U
#define ADC_IER_OVRE4_BIT 12
#define ADC_IER_OVRE5_MASK 0x2000U
#define ADC_IER_OVRE5 0x2000U
#define ADC_IER_OVRE5_BIT 13
#define ADC_IER_OVRE6_MASK 0x4000U
#define ADC_IER_OVRE6 0x4000U
#define ADC_IER_OVRE6_BIT 14
#define ADC_IER_OVRE7_MASK 0x8000U
#define ADC_IER_OVRE7 0x8000U
#define ADC_IER_OVRE7_BIT 15
#define ADC_IER_DRDY_MASK 0x10000U
#define ADC_IER_DRDY 0x10000U
#define ADC_IER_DRDY_BIT 16
#define ADC_IER_GOVRE_MASK 0x20000U
#define ADC_IER_GOVRE 0x20000U
#define ADC_IER_GOVRE_BIT 17
#define ADC_IER_ENDRX_MASK 0x40000U
#define ADC_IER_ENDRX 0x40000U
#define ADC_IER_ENDRX_BIT 18
#define ADC_IER_RXBUFF_MASK 0x80000U
#define ADC_IER_RXBUFF 0x80000U
#define ADC_IER_RXBUFF_BIT 19

#define ADC_IDR (*(volatile unsigned long *)0xFFFD8028)
#define ADC_IDR_OFFSET 0x28
#define ADC_IDR_EOC0_MASK 0x1U
#define ADC_IDR_EOC0 0x1U
#define ADC_IDR_EOC0_BIT 0
#define ADC_IDR_EOC1_MASK 0x2U
#define ADC_IDR_EOC1 0x2U
#define ADC_IDR_EOC1_BIT 1
#define ADC_IDR_EOC2_MASK 0x4U
#define ADC_IDR_EOC2 0x4U
#define ADC_IDR_EOC2_BIT 2
#define ADC_IDR_EOC3_MASK 0x8U
#define ADC_IDR_EOC3 0x8U
#define ADC_IDR_EOC3_BIT 3
#define ADC_IDR_EOC4_MASK 0x10U
#define ADC_IDR_EOC4 0x10U
#define ADC_IDR_EOC4_BIT 4
#define ADC_IDR_EOC5_MASK 0x20U
#define ADC_IDR_EOC5 0x20U
#define ADC_IDR_EOC5_BIT 5
#define ADC_IDR_EOC6_MASK 0x40U
#define ADC_IDR_EOC6 0x40U
#define ADC_IDR_EOC6_BIT 6
#define ADC_IDR_EOC7_MASK 0x80U
#define ADC_IDR_EOC7 0x80U
#define ADC_IDR_EOC7_BIT 7
#define ADC_IDR_OVRE0_MASK 0x100U
#define ADC_IDR_OVRE0 0x100U
#define ADC_IDR_OVRE0_BIT 8
#define ADC_IDR_OVRE1_MASK 0x200U
#define ADC_IDR_OVRE1 0x200U
#define ADC_IDR_OVRE1_BIT 9
#define ADC_IDR_OVRE2_MASK 0x400U
#define ADC_IDR_OVRE2 0x400U
#define ADC_IDR_OVRE2_BIT 10
#define ADC_IDR_OVRE3_MASK 0x800U
#define ADC_IDR_OVRE3 0x800U
#define ADC_IDR_OVRE3_BIT 11
#define ADC_IDR_OVRE4_MASK 0x1000U
#define ADC_IDR_OVRE4 0x1000U
#define ADC_IDR_OVRE4_BIT 12
#define ADC_IDR_OVRE5_MASK 0x2000U
#define ADC_IDR_OVRE5 0x2000U
#define ADC_IDR_OVRE5_BIT 13
#define ADC_IDR_OVRE6_MASK 0x4000U
#define ADC_IDR_OVRE6 0x4000U
#define ADC_IDR_OVRE6_BIT 14
#define ADC_IDR_OVRE7_MASK 0x8000U
#define ADC_IDR_OVRE7 0x8000U
#define ADC_IDR_OVRE7_BIT 15
#define ADC_IDR_DRDY_MASK 0x10000U
#define ADC_IDR_DRDY 0x10000U
#define ADC_IDR_DRDY_BIT 16
#define ADC_IDR_GOVRE_MASK 0x20000U
#define ADC_IDR_GOVRE 0x20000U
#define ADC_IDR_GOVRE_BIT 17
#define ADC_IDR_ENDRX_MASK 0x40000U
#define ADC_IDR_ENDRX 0x40000U
#define ADC_IDR_ENDRX_BIT 18
#define ADC_IDR_RXBUFF_MASK 0x80000U
#define ADC_IDR_RXBUFF 0x80000U
#define ADC_IDR_RXBUFF_BIT 19

#define ADC_IMR (*(volatile unsigned long *)0xFFFD802C)
#define ADC_IMR_OFFSET 0x2C

#define ADC_CDR0 (*(volatile unsigned long *)0xFFFD8030)
#define ADC_CDR0_OFFSET 0x30

#define ADC_CDR1 (*(volatile unsigned long *)0xFFFD8034)
#define ADC_CDR1_OFFSET 0x34

#define ADC_CDR2 (*(volatile unsigned long *)0xFFFD8038)
#define ADC_CDR2_OFFSET 0x38

#define ADC_CDR3 (*(volatile unsigned long *)0xFFFD803C)
#define ADC_CDR3_OFFSET 0x3C

#define ADC_CDR4 (*(volatile unsigned long *)0xFFFD8040)
#define ADC_CDR4_OFFSET 0x40

#define ADC_CDR5 (*(volatile unsigned long *)0xFFFD8044)
#define ADC_CDR5_OFFSET 0x44

#define ADC_CDR6 (*(volatile unsigned long *)0xFFFD8048)
#define ADC_CDR6_OFFSET 0x48

#define ADC_CDR7 (*(volatile unsigned long *)0xFFFD804C)
#define ADC_CDR7_OFFSET 0x4C

#define ADC_RPR (*(volatile unsigned long *)0xFFFD8100)
#define ADC_RPR_OFFSET 0x100

#define ADC_RCR (*(volatile unsigned long *)0xFFFD8104)
#define ADC_RCR_OFFSET 0x104

#define ADC_TPR (*(volatile unsigned long *)0xFFFD8108)
#define ADC_TPR_OFFSET 0x108

#define ADC_TCR (*(volatile unsigned long *)0xFFFD810C)
#define ADC_TCR_OFFSET 0x10C

#define ADC_RNPR (*(volatile unsigned long *)0xFFFD8110)
#define ADC_RNPR_OFFSET 0x110

#define ADC_RNCR (*(volatile unsigned long *)0xFFFD8114)
#define ADC_RNCR_OFFSET 0x114

#define ADC_TNPR (*(volatile unsigned long *)0xFFFD8118)
#define ADC_TNPR_OFFSET 0x118

#define ADC_TNCR (*(volatile unsigned long *)0xFFFD811C)
#define ADC_TNCR_OFFSET 0x11C

#define ADC_PTCR (*(volatile unsigned long *)0xFFFD8120)
#define ADC_PTCR_OFFSET 0x120
#define ADC_PTCR_RXTEN_MASK 0x1U
#define ADC_PTCR_RXTEN 0x1U
#define ADC_PTCR_RXTEN_BIT 0
#define ADC_PTCR_RXTDIS_MASK 0x2U
#define ADC_PTCR_RXTDIS 0x2U
#define ADC_PTCR_RXTDIS_BIT 1
#define ADC_PTCR_TXTEN_MASK 0x100U
#define ADC_PTCR_TXTEN 0x100U
#define ADC_PTCR_TXTEN_BIT 8
#define ADC_PTCR_TXTDIS_MASK 0x1E00U
#define ADC_PTCR_TXTDIS_BIT 9

#define ADC_PTSR (*(volatile unsigned long *)0xFFFD8124)
#define ADC_PTSR_OFFSET 0x124
#define ADC_PTSR_RXTEN_MASK 0x1U
#define ADC_PTSR_RXTEN 0x1U
#define ADC_PTSR_RXTEN_BIT 0
#define ADC_PTSR_TXTEN_MASK 0x1E00U
#define ADC_PTSR_TXTEN_BIT 9

#define SPI_BASE 0xFFFE0000

#define SPI_CR (*(volatile unsigned long *)0xFFFE0000)
#define SPI_CR_OFFSET 0x0
#define SPI_CR_SPIEN_MASK 0x1U
#define SPI_CR_SPIEN 0x1U
#define SPI_CR_SPIEN_BIT 0
#define SPI_CR_SPIDIS_MASK 0x2U
#define SPI_CR_SPIDIS 0x2U
#define SPI_CR_SPIDIS_BIT 1
#define SPI_CR_SWRST_MASK 0x80U
#define SPI_CR_SWRST 0x80U
#define SPI_CR_SWRST_BIT 7
#define SPI_CR_LASTXFER_MASK 0x1000000U
#define SPI_CR_LASTXFER 0x1000000U
#define SPI_CR_LASTXFER_BIT 24

#define SPI_MR (*(volatile unsigned long *)0xFFFE0004)
#define SPI_MR_OFFSET 0x4
#define SPI_MR_MSTR_MASK 0x1U
#define SPI_MR_MSTR 0x1U
#define SPI_MR_MSTR_BIT 0
#define SPI_MR_PS_MASK 0x2U
#define SPI_MR_PS 0x2U
#define SPI_MR_PS_BIT 1
#define SPI_MR_PCSDEC_MASK 0x4U
#define SPI_MR_PCSDEC 0x4U
#define SPI_MR_PCSDEC_BIT 2
#define SPI_MR_FDIV_MASK 0x8U
#define SPI_MR_FDIV 0x8U
#define SPI_MR_FDIV_BIT 3
#define SPI_MR_MODFDIS_MASK 0x10U
#define SPI_MR_MODFDIS 0x10U
#define SPI_MR_MODFDIS_BIT 4
#define SPI_MR_LLB_MASK 0x80U
#define SPI_MR_LLB 0x80U
#define SPI_MR_LLB_BIT 7
#define SPI_MR_PCS_MASK 0xF0000U
#define SPI_MR_PCS_BIT 16
#define SPI_MR_DLYBCS_MASK 0xFF000000U
#define SPI_MR_DLYBCS_BIT 24

#define SPI_RDR (*(volatile unsigned long *)0xFFFE0008)
#define SPI_RDR_OFFSET 0x8
#define SPI_RDR_RD_MASK 0xFFFFU
#define SPI_RDR_RD_BIT 0
#define SPI_RDR_PCS_MASK 0xF0000U
#define SPI_RDR_PCS_BIT 16

#define SPI_TDR (*(volatile unsigned long *)0xFFFE000C)
#define SPI_TDR_OFFSET 0xC
#define SPI_TDR_TD_MASK 0xFFFFU
#define SPI_TDR_TD_BIT 0
#define SPI_TDR_PCS_MASK 0xF0000U
#define SPI_TDR_PCS_BIT 16
#define SPI_TDR_LASTXFER_MASK 0x1000000U
#define SPI_TDR_LASTXFER 0x1000000U
#define SPI_TDR_LASTXFER_BIT 24

#define SPI_SR (*(volatile unsigned long *)0xFFFE0010)
#define SPI_SR_OFFSET 0x10
#define SPI_SR_RDRF_MASK 0x1U
#define SPI_SR_RDRF 0x1U
#define SPI_SR_RDRF_BIT 0
#define SPI_SR_TDRE_MASK 0x2U
#define SPI_SR_TDRE 0x2U
#define SPI_SR_TDRE_BIT 1
#define SPI_SR_MODF_MASK 0x4U
#define SPI_SR_MODF 0x4U
#define SPI_SR_MODF_BIT 2
#define SPI_SR_OVRES_MASK 0x8U
#define SPI_SR_OVRES 0x8U
#define SPI_SR_OVRES_BIT 3
#define SPI_SR_ENDRX_MASK 0x10U
#define SPI_SR_ENDRX 0x10U
#define SPI_SR_ENDRX_BIT 4
#define SPI_SR_ENDTX_MASK 0x20U
#define SPI_SR_ENDTX 0x20U
#define SPI_SR_ENDTX_BIT 5
#define SPI_SR_RXBUFF_MASK 0x40U
#define SPI_SR_RXBUFF 0x40U
#define SPI_SR_RXBUFF_BIT 6
#define SPI_SR_TXBUFE_MASK 0x80U
#define SPI_SR_TXBUFE 0x80U
#define SPI_SR_TXBUFE_BIT 7
#define SPI_SR_NSSR_MASK 0x100U
#define SPI_SR_NSSR 0x100U
#define SPI_SR_NSSR_BIT 8
#define SPI_SR_TXEMPTY_MASK 0x200U
#define SPI_SR_TXEMPTY 0x200U
#define SPI_SR_TXEMPTY_BIT 9
#define SPI_SR_SPIENS_MASK 0x10000U
#define SPI_SR_SPIENS 0x10000U
#define SPI_SR_SPIENS_BIT 16

#define SPI_IER (*(volatile unsigned long *)0xFFFE0014)
#define SPI_IER_OFFSET 0x14
#define SPI_IER_RDRF_MASK 0x1U
#define SPI_IER_RDRF 0x1U
#define SPI_IER_RDRF_BIT 0
#define SPI_IER_TDRE_MASK 0x2U
#define SPI_IER_TDRE 0x2U
#define SPI_IER_TDRE_BIT 1
#define SPI_IER_MODF_MASK 0x4U
#define SPI_IER_MODF 0x4U
#define SPI_IER_MODF_BIT 2
#define SPI_IER_OVRES_MASK 0x8U
#define SPI_IER_OVRES 0x8U
#define SPI_IER_OVRES_BIT 3
#define SPI_IER_ENDRX_MASK 0x10U
#define SPI_IER_ENDRX 0x10U
#define SPI_IER_ENDRX_BIT 4
#define SPI_IER_ENDTX_MASK 0x20U
#define SPI_IER_ENDTX 0x20U
#define SPI_IER_ENDTX_BIT 5
#define SPI_IER_RXBUFF_MASK 0x40U
#define SPI_IER_RXBUFF 0x40U
#define SPI_IER_RXBUFF_BIT 6
#define SPI_IER_TXBUFE_MASK 0x80U
#define SPI_IER_TXBUFE 0x80U
#define SPI_IER_TXBUFE_BIT 7
#define SPI_IER_NSSR_MASK 0x100U
#define SPI_IER_NSSR 0x100U
#define SPI_IER_NSSR_BIT 8
#define SPI_IER_TXEMPTY_MASK 0x200U
#define SPI_IER_TXEMPTY 0x200U
#define SPI_IER_TXEMPTY_BIT 9

#define SPI_IDR (*(volatile unsigned long *)0xFFFE0018)
#define SPI_IDR_OFFSET 0x18
#define SPI_IDR_RDRF_MASK 0x1U
#define SPI_IDR_RDRF 0x1U
#define SPI_IDR_RDRF_BIT 0
#define SPI_IDR_TDRE_MASK 0x2U
#define SPI_IDR_TDRE 0x2U
#define SPI_IDR_TDRE_BIT 1
#define SPI_IDR_MODF_MASK 0x4U
#define SPI_IDR_MODF 0x4U
#define SPI_IDR_MODF_BIT 2
#define SPI_IDR_OVRES_MASK 0x8U
#define SPI_IDR_OVRES 0x8U
#define SPI_IDR_OVRES_BIT 3
#define SPI_IDR_ENDRX_MASK 0x10U
#define SPI_IDR_ENDRX 0x10U
#define SPI_IDR_ENDRX_BIT 4
#define SPI_IDR_ENDTX_MASK 0x20U
#define SPI_IDR_ENDTX 0x20U
#define SPI_IDR_ENDTX_BIT 5
#define SPI_IDR_RXBUFF_MASK 0x40U
#define SPI_IDR_RXBUFF 0x40U
#define SPI_IDR_RXBUFF_BIT 6
#define SPI_IDR_TXBUFE_MASK 0x80U
#define SPI_IDR_TXBUFE 0x80U
#define SPI_IDR_TXBUFE_BIT 7
#define SPI_IDR_NSSR_MASK 0x100U
#define SPI_IDR_NSSR 0x100U
#define SPI_IDR_NSSR_BIT 8
#define SPI_IDR_TXEMPTY_MASK 0x200U
#define SPI_IDR_TXEMPTY 0x200U
#define SPI_IDR_TXEMPTY_BIT 9

#define SPI_IMR (*(volatile unsigned long *)0xFFFE001C)
#define SPI_IMR_OFFSET 0x1C
#define SPI_IMR_RDRF_MASK 0x1U
#define SPI_IMR_RDRF 0x1U
#define SPI_IMR_RDRF_BIT 0
#define SPI_IMR_TDRE_MASK 0x2U
#define SPI_IMR_TDRE 0x2U
#define SPI_IMR_TDRE_BIT 1
#define SPI_IMR_MODF_MASK 0x4U
#define SPI_IMR_MODF 0x4U
#define SPI_IMR_MODF_BIT 2
#define SPI_IMR_OVRES_MASK 0x8U
#define SPI_IMR_OVRES 0x8U
#define SPI_IMR_OVRES_BIT 3
#define SPI_IMR_ENDRX_MASK 0x10U
#define SPI_IMR_ENDRX 0x10U
#define SPI_IMR_ENDRX_BIT 4
#define SPI_IMR_ENDTX_MASK 0x20U
#define SPI_IMR_ENDTX 0x20U
#define SPI_IMR_ENDTX_BIT 5
#define SPI_IMR_RXBUFF_MASK 0x40U
#define SPI_IMR_RXBUFF 0x40U
#define SPI_IMR_RXBUFF_BIT 6
#define SPI_IMR_TXBUFE_MASK 0x80U
#define SPI_IMR_TXBUFE 0x80U
#define SPI_IMR_TXBUFE_BIT 7
#define SPI_IMR_NSSR_MASK 0x100U
#define SPI_IMR_NSSR 0x100U
#define SPI_IMR_NSSR_BIT 8
#define SPI_IMR_TXEMPTY_MASK 0x200U
#define SPI_IMR_TXEMPTY 0x200U
#define SPI_IMR_TXEMPTY_BIT 9

#define SPI_CSR0 (*(volatile unsigned long *)0xFFFE0030)
#define SPI_CSR0_OFFSET 0x30
#define SPI_CSR0_CPOL_MASK 0x1U
#define SPI_CSR0_CPOL 0x1U
#define SPI_CSR0_CPOL_BIT 0
#define SPI_CSR0_NCPHA_MASK 0x2U
#define SPI_CSR0_NCPHA 0x2U
#define SPI_CSR0_NCPHA_BIT 1
#define SPI_CSR0_CSAAT_MASK 0x8U
#define SPI_CSR0_CSAAT 0x8U
#define SPI_CSR0_CSAAT_BIT 3
#define SPI_CSR0_BITS_MASK 0xF0U
#define SPI_CSR0_BITS_BIT 4
#define SPI_CSR0_SCBR_MASK 0xFF00U
#define SPI_CSR0_SCBR_BIT 8
#define SPI_CSR0_DLYBS_MASK 0xFF0000U
#define SPI_CSR0_DLYBS_BIT 16
#define SPI_CSR0_DLYBCT_MASK 0xFF000000U
#define SPI_CSR0_DLYBCT_BIT 24

#define SPI_CSR1 (*(volatile unsigned long *)0xFFFE0034)
#define SPI_CSR1_OFFSET 0x34
#define SPI_CSR1_CPOL_MASK 0x1U
#define SPI_CSR1_CPOL 0x1U
#define SPI_CSR1_CPOL_BIT 0
#define SPI_CSR1_NCPHA_MASK 0x2U
#define SPI_CSR1_NCPHA 0x2U
#define SPI_CSR1_NCPHA_BIT 1
#define SPI_CSR1_CSAAT_MASK 0x8U
#define SPI_CSR1_CSAAT 0x8U
#define SPI_CSR1_CSAAT_BIT 3
#define SPI_CSR1_BITS_MASK 0xF0U
#define SPI_CSR1_BITS_BIT 4
#define SPI_CSR1_SCBR_MASK 0xFF00U
#define SPI_CSR1_SCBR_BIT 8
#define SPI_CSR1_DLYBS_MASK 0xFF0000U
#define SPI_CSR1_DLYBS_BIT 16
#define SPI_CSR1_DLYBCT_MASK 0xFF000000U
#define SPI_CSR1_DLYBCT_BIT 24

#define SPI_CSR2 (*(volatile unsigned long *)0xFFFE0038)
#define SPI_CSR2_OFFSET 0x38
#define SPI_CSR2_CPOL_MASK 0x1U
#define SPI_CSR2_CPOL 0x1U
#define SPI_CSR2_CPOL_BIT 0
#define SPI_CSR2_NCPHA_MASK 0x2U
#define SPI_CSR2_NCPHA 0x2U
#define SPI_CSR2_NCPHA_BIT 1
#define SPI_CSR2_CSAAT_MASK 0x8U
#define SPI_CSR2_CSAAT 0x8U
#define SPI_CSR2_CSAAT_BIT 3
#define SPI_CSR2_BITS_MASK 0xF0U
#define SPI_CSR2_BITS_BIT 4
#define SPI_CSR2_SCBR_MASK 0xFF00U
#define SPI_CSR2_SCBR_BIT 8
#define SPI_CSR2_DLYBS_MASK 0xFF0000U
#define SPI_CSR2_DLYBS_BIT 16
#define SPI_CSR2_DLYBCT_MASK 0xFF000000U
#define SPI_CSR2_DLYBCT_BIT 24

#define SPI_CSR3 (*(volatile unsigned long *)0xFFFE003C)
#define SPI_CSR3_OFFSET 0x3C
#define SPI_CSR3_CPOL_MASK 0x1U
#define SPI_CSR3_CPOL 0x1U
#define SPI_CSR3_CPOL_BIT 0
#define SPI_CSR3_NCPHA_MASK 0x2U
#define SPI_CSR3_NCPHA 0x2U
#define SPI_CSR3_NCPHA_BIT 1
#define SPI_CSR3_CSAAT_MASK 0x8U
#define SPI_CSR3_CSAAT 0x8U
#define SPI_CSR3_CSAAT_BIT 3
#define SPI_CSR3_BITS_MASK 0xF0U
#define SPI_CSR3_BITS_BIT 4
#define SPI_CSR3_SCBR_MASK 0xFF00U
#define SPI_CSR3_SCBR_BIT 8
#define SPI_CSR3_DLYBS_MASK 0xFF0000U
#define SPI_CSR3_DLYBS_BIT 16
#define SPI_CSR3_DLYBCT_MASK 0xFF000000U
#define SPI_CSR3_DLYBCT_BIT 24

#define SPI_RPR (*(volatile unsigned long *)0xFFFE0100)
#define SPI_RPR_OFFSET 0x100

#define SPI_RCR (*(volatile unsigned long *)0xFFFE0104)
#define SPI_RCR_OFFSET 0x104

#define SPI_TPR (*(volatile unsigned long *)0xFFFE0108)
#define SPI_TPR_OFFSET 0x108

#define SPI_TCR (*(volatile unsigned long *)0xFFFE010C)
#define SPI_TCR_OFFSET 0x10C

#define SPI_RNPR (*(volatile unsigned long *)0xFFFE0110)
#define SPI_RNPR_OFFSET 0x110

#define SPI_RNCR (*(volatile unsigned long *)0xFFFE0114)
#define SPI_RNCR_OFFSET 0x114

#define SPI_TNPR (*(volatile unsigned long *)0xFFFE0118)
#define SPI_TNPR_OFFSET 0x118

#define SPI_TNCR (*(volatile unsigned long *)0xFFFE011C)
#define SPI_TNCR_OFFSET 0x11C

#define SPI_PTCR (*(volatile unsigned long *)0xFFFE0120)
#define SPI_PTCR_OFFSET 0x120
#define SPI_PTCR_RXTEN_MASK 0x1U
#define SPI_PTCR_RXTEN 0x1U
#define SPI_PTCR_RXTEN_BIT 0
#define SPI_PTCR_RXTDIS_MASK 0x2U
#define SPI_PTCR_RXTDIS 0x2U
#define SPI_PTCR_RXTDIS_BIT 1
#define SPI_PTCR_TXTEN_MASK 0x100U
#define SPI_PTCR_TXTEN 0x100U
#define SPI_PTCR_TXTEN_BIT 8
#define SPI_PTCR_TXTDIS_MASK 0x1E00U
#define SPI_PTCR_TXTDIS_BIT 9

#define SPI_PTSR (*(volatile unsigned long *)0xFFFE0124)
#define SPI_PTSR_OFFSET 0x124
#define SPI_PTSR_RXTEN_MASK 0x1U
#define SPI_PTSR_RXTEN 0x1U
#define SPI_PTSR_RXTEN_BIT 0
#define SPI_PTSR_TXTEN_MASK 0x1E00U
#define SPI_PTSR_TXTEN_BIT 9


#endif
