// AT91M55800A register and bit definitions.
//
// Copyright (c) 2005 Rowley Associates Limited.
//
// This file may be distributed under the terms of the License Agreement
// provided with this software.
//
// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE
// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.

#ifndef AT91M55800A_h
#define AT91M55800A_h

#define EBI_BASE 0xFFE00000

#define EBI_CSR0 (*(volatile unsigned *)0xFFE00000)
#define EBI_CSR0_OFFSET 0x0

#define EBI_CSR1 (*(volatile unsigned *)0xFFE00004)
#define EBI_CSR1_OFFSET 0x4

#define EBI_CSR2 (*(volatile unsigned *)0xFFE00008)
#define EBI_CSR2_OFFSET 0x8

#define EBI_CSR3 (*(volatile unsigned *)0xFFE0000C)
#define EBI_CSR3_OFFSET 0xC

#define EBI_CSR4 (*(volatile unsigned *)0xFFE00010)
#define EBI_CSR4_OFFSET 0x10

#define EBI_CSR5 (*(volatile unsigned *)0xFFE00014)
#define EBI_CSR5_OFFSET 0x14

#define EBI_CSR6 (*(volatile unsigned *)0xFFE00018)
#define EBI_CSR6_OFFSET 0x18

#define EBI_CSR7 (*(volatile unsigned *)0xFFE0001C)
#define EBI_CSR7_OFFSET 0x1C

#define EBI_RCR (*(volatile unsigned *)0xFFE00020)
#define EBI_RCR_OFFSET 0x20

#define EBI_MCR (*(volatile unsigned *)0xFFE00024)
#define EBI_MCR_OFFSET 0x24

#define SF_BASE 0xFFF00000

#define SF_CIDR (*(volatile unsigned *)0xFFF00000)
#define SF_CIDR_OFFSET 0x0

#define SF_EXID (*(volatile unsigned *)0xFFF00004)
#define SF_EXID_OFFSET 0x4

#define SF_RSR (*(volatile unsigned *)0xFFF00008)
#define SF_RSR_OFFSET 0x8

#define SF_PMR (*(volatile unsigned *)0xFFF00018)
#define SF_PMR_OFFSET 0x18

#define DAC0_BASE 0xFFFA8000

#define DAC0_CR (*(volatile unsigned *)0xFFFA8000)
#define DAC0_CR_OFFSET 0x0

#define DAC0_MR (*(volatile unsigned *)0xFFFA8004)
#define DAC0_MR_OFFSET 0x4

#define DAC0_DHR (*(volatile unsigned *)0xFFFA8008)
#define DAC0_DHR_OFFSET 0x8

#define DAC0_DOR (*(volatile unsigned *)0xFFFA800C)
#define DAC0_DOR_OFFSET 0xC

#define DAC0_SR (*(volatile unsigned *)0xFFFA8010)
#define DAC0_SR_OFFSET 0x10

#define DAC0_IER (*(volatile unsigned *)0xFFFA8014)
#define DAC0_IER_OFFSET 0x14

#define DAC0_IDR (*(volatile unsigned *)0xFFFA8018)
#define DAC0_IDR_OFFSET 0x18

#define DAC0_IMR (*(volatile unsigned *)0xFFFA801C)
#define DAC0_IMR_OFFSET 0x1C

#define DAC1_BASE 0xFFFAC000

#define DAC1_CR (*(volatile unsigned *)0xFFFAC000)
#define DAC1_CR_OFFSET 0x0

#define DAC1_MR (*(volatile unsigned *)0xFFFAC004)
#define DAC1_MR_OFFSET 0x4

#define DAC1_DHR (*(volatile unsigned *)0xFFFAC008)
#define DAC1_DHR_OFFSET 0x8

#define DAC1_DOR (*(volatile unsigned *)0xFFFAC00C)
#define DAC1_DOR_OFFSET 0xC

#define DAC1_SR (*(volatile unsigned *)0xFFFAC010)
#define DAC1_SR_OFFSET 0x10

#define DAC1_IER (*(volatile unsigned *)0xFFFAC014)
#define DAC1_IER_OFFSET 0x14

#define DAC1_IDR (*(volatile unsigned *)0xFFFAC018)
#define DAC1_IDR_OFFSET 0x18

#define DAC1_IMR (*(volatile unsigned *)0xFFFAC01C)
#define DAC1_IMR_OFFSET 0x1C

#define ADC0_BASE 0xFFFB0000

#define ADC0_CR (*(volatile unsigned *)0xFFFB0000)
#define ADC0_CR_OFFSET 0x0

#define ADC0_MR (*(volatile unsigned *)0xFFFB0004)
#define ADC0_MR_OFFSET 0x4

#define ADC0_CHER (*(volatile unsigned *)0xFFFB0010)
#define ADC0_CHER_OFFSET 0x10

#define ADC0_CHDR (*(volatile unsigned *)0xFFFB0014)
#define ADC0_CHDR_OFFSET 0x14

#define ADC0_CHSR (*(volatile unsigned *)0xFFFB0018)
#define ADC0_CHSR_OFFSET 0x18

#define ADC0_SR (*(volatile unsigned *)0xFFFB0020)
#define ADC0_SR_OFFSET 0x20

#define ADC0_IER (*(volatile unsigned *)0xFFFB0024)
#define ADC0_IER_OFFSET 0x24

#define ADC0_IDR (*(volatile unsigned *)0xFFFB0028)
#define ADC0_IDR_OFFSET 0x28

#define ADC0_IMR (*(volatile unsigned *)0xFFFB002C)
#define ADC0_IMR_OFFSET 0x2C

#define ADC0_CDR0 (*(volatile unsigned *)0xFFFB0030)
#define ADC0_CDR0_OFFSET 0x30

#define ADC0_CDR1 (*(volatile unsigned *)0xFFFB0034)
#define ADC0_CDR1_OFFSET 0x34

#define ADC0_CDR2 (*(volatile unsigned *)0xFFFB0038)
#define ADC0_CDR2_OFFSET 0x38

#define ADC0_CDR3 (*(volatile unsigned *)0xFFFB003C)
#define ADC0_CDR3_OFFSET 0x3C

#define ADC1_BASE 0xFFFB4000

#define ADC1_CR (*(volatile unsigned *)0xFFFB4000)
#define ADC1_CR_OFFSET 0x0

#define ADC1_MR (*(volatile unsigned *)0xFFFB4004)
#define ADC1_MR_OFFSET 0x4

#define ADC1_CHER (*(volatile unsigned *)0xFFFB4010)
#define ADC1_CHER_OFFSET 0x10

#define ADC1_CHDR (*(volatile unsigned *)0xFFFB4014)
#define ADC1_CHDR_OFFSET 0x14

#define ADC1_CHSR (*(volatile unsigned *)0xFFFB4018)
#define ADC1_CHSR_OFFSET 0x18

#define ADC1_SR (*(volatile unsigned *)0xFFFB4020)
#define ADC1_SR_OFFSET 0x20

#define ADC1_IER (*(volatile unsigned *)0xFFFB4024)
#define ADC1_IER_OFFSET 0x24

#define ADC1_IDR (*(volatile unsigned *)0xFFFB4028)
#define ADC1_IDR_OFFSET 0x28

#define ADC1_IMR (*(volatile unsigned *)0xFFFB402C)
#define ADC1_IMR_OFFSET 0x2C

#define ADC1_CDR0 (*(volatile unsigned *)0xFFFB4030)
#define ADC1_CDR0_OFFSET 0x30

#define ADC1_CDR1 (*(volatile unsigned *)0xFFFB4034)
#define ADC1_CDR1_OFFSET 0x34

#define ADC1_CDR2 (*(volatile unsigned *)0xFFFB4038)
#define ADC1_CDR2_OFFSET 0x38

#define ADC1_CDR3 (*(volatile unsigned *)0xFFFB403C)
#define ADC1_CDR3_OFFSET 0x3C

#define RTC_BASE 0xFFFB8000

#define RTC_MR (*(volatile unsigned *)0xFFFB8000)
#define RTC_MR_OFFSET 0x0

#define RTC_HMR (*(volatile unsigned *)0xFFFB8004)
#define RTC_HMR_OFFSET 0x4

#define RTC_TIMR (*(volatile unsigned *)0xFFFB8008)
#define RTC_TIMR_OFFSET 0x8

#define RTC_CALR (*(volatile unsigned *)0xFFFB800C)
#define RTC_CALR_OFFSET 0xC

#define RTC_TAR (*(volatile unsigned *)0xFFFB8010)
#define RTC_TAR_OFFSET 0x10

#define RTC_CAR (*(volatile unsigned *)0xFFFB8014)
#define RTC_CAR_OFFSET 0x14

#define RTC_SR (*(volatile unsigned *)0xFFFB8018)
#define RTC_SR_OFFSET 0x18

#define RTC_SCR (*(volatile unsigned *)0xFFFB801C)
#define RTC_SCR_OFFSET 0x1C

#define RTC_IER (*(volatile unsigned *)0xFFFB8020)
#define RTC_IER_OFFSET 0x20

#define RTC_IDR (*(volatile unsigned *)0xFFFB8024)
#define RTC_IDR_OFFSET 0x24

#define RTC_IMR (*(volatile unsigned *)0xFFFB8028)
#define RTC_IMR_OFFSET 0x28

#define RTC_VER (*(volatile unsigned *)0xFFFB802C)
#define RTC_VER_OFFSET 0x2C

#define SPI_BASE 0xFFFBC000

#define SP_CR (*(volatile unsigned *)0xFFFBC000)
#define SP_CR_OFFSET 0x0

#define SP_MR (*(volatile unsigned *)0xFFFBC004)
#define SP_MR_OFFSET 0x4

#define SP_RDR (*(volatile unsigned *)0xFFFBC008)
#define SP_RDR_OFFSET 0x8

#define SP_TDR (*(volatile unsigned *)0xFFFBC00C)
#define SP_TDR_OFFSET 0xC

#define SP_SR (*(volatile unsigned *)0xFFFBC010)
#define SP_SR_OFFSET 0x10

#define SP_IER (*(volatile unsigned *)0xFFFBC014)
#define SP_IER_OFFSET 0x14

#define SP_IDR (*(volatile unsigned *)0xFFFBC018)
#define SP_IDR_OFFSET 0x18

#define SP_IMR (*(volatile unsigned *)0xFFFBC01C)
#define SP_IMR_OFFSET 0x1C

#define SP_RPR (*(volatile unsigned *)0xFFFBC020)
#define SP_RPR_OFFSET 0x20

#define SP_RCR (*(volatile unsigned *)0xFFFBC024)
#define SP_RCR_OFFSET 0x24

#define SP_TPR (*(volatile unsigned *)0xFFFBC028)
#define SP_TPR_OFFSET 0x28

#define SP_TCR (*(volatile unsigned *)0xFFFBC02C)
#define SP_TCR_OFFSET 0x2C

#define SP_CSR0 (*(volatile unsigned *)0xFFFBC030)
#define SP_CSR0_OFFSET 0x30

#define SP_CSR1 (*(volatile unsigned *)0xFFFBC034)
#define SP_CSR1_OFFSET 0x34

#define SP_CSR2 (*(volatile unsigned *)0xFFFBC038)
#define SP_CSR2_OFFSET 0x38

#define SP_CSR3 (*(volatile unsigned *)0xFFFBC03C)
#define SP_CSR3_OFFSET 0x3C

#define USART0_BASE 0xFFFC0000

#define US0_CR (*(volatile unsigned *)0xFFFC0000)
#define US0_CR_OFFSET 0x0

#define US0_MR (*(volatile unsigned *)0xFFFC0004)
#define US0_MR_OFFSET 0x4

#define US0_IER (*(volatile unsigned *)0xFFFC0008)
#define US0_IER_OFFSET 0x8

#define US0_IDR (*(volatile unsigned *)0xFFFC000C)
#define US0_IDR_OFFSET 0xC

#define US0_IMR (*(volatile unsigned *)0xFFFC0010)
#define US0_IMR_OFFSET 0x10

#define US0_CSR (*(volatile unsigned *)0xFFFC0014)
#define US0_CSR_OFFSET 0x14

#define US0_RHR (*(volatile unsigned *)0xFFFC0018)
#define US0_RHR_OFFSET 0x18

#define US0_THR (*(volatile unsigned *)0xFFFC001C)
#define US0_THR_OFFSET 0x1C

#define US0_BRGR (*(volatile unsigned *)0xFFFC0020)
#define US0_BRGR_OFFSET 0x20

#define US0_RTOR (*(volatile unsigned *)0xFFFC0024)
#define US0_RTOR_OFFSET 0x24

#define US0_TTGR (*(volatile unsigned *)0xFFFC0028)
#define US0_TTGR_OFFSET 0x28

#define US0_RPR (*(volatile unsigned *)0xFFFC0030)
#define US0_RPR_OFFSET 0x30

#define US0_RCR (*(volatile unsigned *)0xFFFC0034)
#define US0_RCR_OFFSET 0x34

#define US0_TPR (*(volatile unsigned *)0xFFFC0038)
#define US0_TPR_OFFSET 0x38

#define US0_TCR (*(volatile unsigned *)0xFFFC003C)
#define US0_TCR_OFFSET 0x3C

#define USART1_BASE 0xFFFC4000

#define US1_CR (*(volatile unsigned *)0xFFFC4000)
#define US1_CR_OFFSET 0x0

#define US1_MR (*(volatile unsigned *)0xFFFC4004)
#define US1_MR_OFFSET 0x4

#define US1_IER (*(volatile unsigned *)0xFFFC4008)
#define US1_IER_OFFSET 0x8

#define US1_IDR (*(volatile unsigned *)0xFFFC400C)
#define US1_IDR_OFFSET 0xC

#define US1_IMR (*(volatile unsigned *)0xFFFC4010)
#define US1_IMR_OFFSET 0x10

#define US1_CSR (*(volatile unsigned *)0xFFFC4014)
#define US1_CSR_OFFSET 0x14

#define US1_RHR (*(volatile unsigned *)0xFFFC4018)
#define US1_RHR_OFFSET 0x18

#define US1_THR (*(volatile unsigned *)0xFFFC401C)
#define US1_THR_OFFSET 0x1C

#define US1_BRGR (*(volatile unsigned *)0xFFFC4020)
#define US1_BRGR_OFFSET 0x20

#define US1_RTOR (*(volatile unsigned *)0xFFFC4024)
#define US1_RTOR_OFFSET 0x24

#define US1_TTGR (*(volatile unsigned *)0xFFFC4028)
#define US1_TTGR_OFFSET 0x28

#define US1_RPR (*(volatile unsigned *)0xFFFC4030)
#define US1_RPR_OFFSET 0x30

#define US1_RCR (*(volatile unsigned *)0xFFFC4034)
#define US1_RCR_OFFSET 0x34

#define US1_TPR (*(volatile unsigned *)0xFFFC4038)
#define US1_TPR_OFFSET 0x38

#define US1_TCR (*(volatile unsigned *)0xFFFC403C)
#define US1_TCR_OFFSET 0x3C

#define USART2_BASE 0xFFFC8000

#define US2_CR (*(volatile unsigned *)0xFFFC8000)
#define US2_CR_OFFSET 0x0

#define US2_MR (*(volatile unsigned *)0xFFFC8004)
#define US2_MR_OFFSET 0x4

#define US2_IER (*(volatile unsigned *)0xFFFC8008)
#define US2_IER_OFFSET 0x8

#define US2_IDR (*(volatile unsigned *)0xFFFC800C)
#define US2_IDR_OFFSET 0xC

#define US2_IMR (*(volatile unsigned *)0xFFFC8010)
#define US2_IMR_OFFSET 0x10

#define US2_CSR (*(volatile unsigned *)0xFFFC8014)
#define US2_CSR_OFFSET 0x14

#define US2_RHR (*(volatile unsigned *)0xFFFC8018)
#define US2_RHR_OFFSET 0x18

#define US2_THR (*(volatile unsigned *)0xFFFC801C)
#define US2_THR_OFFSET 0x1C

#define US2_BRGR (*(volatile unsigned *)0xFFFC8020)
#define US2_BRGR_OFFSET 0x20

#define US2_RTOR (*(volatile unsigned *)0xFFFC8024)
#define US2_RTOR_OFFSET 0x24

#define US2_TTGR (*(volatile unsigned *)0xFFFC8028)
#define US2_TTGR_OFFSET 0x28

#define US2_RPR (*(volatile unsigned *)0xFFFC8030)
#define US2_RPR_OFFSET 0x30

#define US2_RCR (*(volatile unsigned *)0xFFFC8034)
#define US2_RCR_OFFSET 0x34

#define US2_TPR (*(volatile unsigned *)0xFFFC8038)
#define US2_TPR_OFFSET 0x38

#define US2_TCR (*(volatile unsigned *)0xFFFC803C)
#define US2_TCR_OFFSET 0x3C

#define TC012_BASE 0xFFFD0000

#define TC0_CCR (*(volatile unsigned *)0xFFFD0000)
#define TC0_CCR_OFFSET 0x0

#define TC0_CMR (*(volatile unsigned *)0xFFFD0004)
#define TC0_CMR_OFFSET 0x4

#define TC0_CV (*(volatile unsigned *)0xFFFD0010)
#define TC0_CV_OFFSET 0x10

#define TC0_RA (*(volatile unsigned *)0xFFFD0014)
#define TC0_RA_OFFSET 0x14

#define TC0_RB (*(volatile unsigned *)0xFFFD0018)
#define TC0_RB_OFFSET 0x18

#define TC0_RC (*(volatile unsigned *)0xFFFD001C)
#define TC0_RC_OFFSET 0x1C

#define TC0_SR (*(volatile unsigned *)0xFFFD0020)
#define TC0_SR_OFFSET 0x20

#define TC0_IER (*(volatile unsigned *)0xFFFD0024)
#define TC0_IER_OFFSET 0x24

#define TC0_IDR (*(volatile unsigned *)0xFFFD0028)
#define TC0_IDR_OFFSET 0x28

#define TC0_IMR (*(volatile unsigned *)0xFFFD002C)
#define TC0_IMR_OFFSET 0x2C

#define TC1_CCR (*(volatile unsigned *)0xFFFD0040)
#define TC1_CCR_OFFSET 0x40

#define TC1_CMR (*(volatile unsigned *)0xFFFD0044)
#define TC1_CMR_OFFSET 0x44

#define TC1_CV (*(volatile unsigned *)0xFFFD0050)
#define TC1_CV_OFFSET 0x50

#define TC1_RA (*(volatile unsigned *)0xFFFD0054)
#define TC1_RA_OFFSET 0x54

#define TC1_RB (*(volatile unsigned *)0xFFFD0058)
#define TC1_RB_OFFSET 0x58

#define TC1_RC (*(volatile unsigned *)0xFFFD005C)
#define TC1_RC_OFFSET 0x5C

#define TC1_SR (*(volatile unsigned *)0xFFFD0060)
#define TC1_SR_OFFSET 0x60

#define TC1_IER (*(volatile unsigned *)0xFFFD0064)
#define TC1_IER_OFFSET 0x64

#define TC1_IDR (*(volatile unsigned *)0xFFFD0068)
#define TC1_IDR_OFFSET 0x68

#define TC1_IMR (*(volatile unsigned *)0xFFFD006C)
#define TC1_IMR_OFFSET 0x6C

#define TC2_CCR (*(volatile unsigned *)0xFFFD0080)
#define TC2_CCR_OFFSET 0x80

#define TC2_CMR (*(volatile unsigned *)0xFFFD0084)
#define TC2_CMR_OFFSET 0x84

#define TC2_CV (*(volatile unsigned *)0xFFFD0090)
#define TC2_CV_OFFSET 0x90

#define TC2_RA (*(volatile unsigned *)0xFFFD0094)
#define TC2_RA_OFFSET 0x94

#define TC2_RB (*(volatile unsigned *)0xFFFD0098)
#define TC2_RB_OFFSET 0x98

#define TC2_RC (*(volatile unsigned *)0xFFFD009C)
#define TC2_RC_OFFSET 0x9C

#define TC2_SR (*(volatile unsigned *)0xFFFD00A0)
#define TC2_SR_OFFSET 0xA0

#define TC2_IER (*(volatile unsigned *)0xFFFD00A4)
#define TC2_IER_OFFSET 0xA4

#define TC2_IDR (*(volatile unsigned *)0xFFFD00A8)
#define TC2_IDR_OFFSET 0xA8

#define TC2_IMR (*(volatile unsigned *)0xFFFD00AC)
#define TC2_IMR_OFFSET 0xAC

#define TC012_BCR (*(volatile unsigned *)0xFFFD00C0)
#define TC012_BCR_OFFSET 0xC0

#define TC012_BMR (*(volatile unsigned *)0xFFFD00C4)
#define TC012_BMR_OFFSET 0xC4

#define TC345_BASE 0xFFFD4000

#define TC3_CCR (*(volatile unsigned *)0xFFFD4000)
#define TC3_CCR_OFFSET 0x0

#define TC3_CMR (*(volatile unsigned *)0xFFFD4004)
#define TC3_CMR_OFFSET 0x4

#define TC3_CV (*(volatile unsigned *)0xFFFD4010)
#define TC3_CV_OFFSET 0x10

#define TC3_RA (*(volatile unsigned *)0xFFFD4014)
#define TC3_RA_OFFSET 0x14

#define TC3_RB (*(volatile unsigned *)0xFFFD4018)
#define TC3_RB_OFFSET 0x18

#define TC3_RC (*(volatile unsigned *)0xFFFD401C)
#define TC3_RC_OFFSET 0x1C

#define TC3_SR (*(volatile unsigned *)0xFFFD4020)
#define TC3_SR_OFFSET 0x20

#define TC3_IER (*(volatile unsigned *)0xFFFD4024)
#define TC3_IER_OFFSET 0x24

#define TC3_IDR (*(volatile unsigned *)0xFFFD4028)
#define TC3_IDR_OFFSET 0x28

#define TC3_IMR (*(volatile unsigned *)0xFFFD402C)
#define TC3_IMR_OFFSET 0x2C

#define TC4_CCR (*(volatile unsigned *)0xFFFD4040)
#define TC4_CCR_OFFSET 0x40

#define TC4_CMR (*(volatile unsigned *)0xFFFD4044)
#define TC4_CMR_OFFSET 0x44

#define TC4_CV (*(volatile unsigned *)0xFFFD4050)
#define TC4_CV_OFFSET 0x50

#define TC4_RA (*(volatile unsigned *)0xFFFD4054)
#define TC4_RA_OFFSET 0x54

#define TC4_RB (*(volatile unsigned *)0xFFFD4058)
#define TC4_RB_OFFSET 0x58

#define TC4_RC (*(volatile unsigned *)0xFFFD405C)
#define TC4_RC_OFFSET 0x5C

#define TC4_SR (*(volatile unsigned *)0xFFFD4060)
#define TC4_SR_OFFSET 0x60

#define TC4_IER (*(volatile unsigned *)0xFFFD4064)
#define TC4_IER_OFFSET 0x64

#define TC4_IDR (*(volatile unsigned *)0xFFFD4068)
#define TC4_IDR_OFFSET 0x68

#define TC4_IMR (*(volatile unsigned *)0xFFFD406C)
#define TC4_IMR_OFFSET 0x6C

#define TC5_CCR (*(volatile unsigned *)0xFFFD4080)
#define TC5_CCR_OFFSET 0x80

#define TC5_CMR (*(volatile unsigned *)0xFFFD4084)
#define TC5_CMR_OFFSET 0x84

#define TC5_CV (*(volatile unsigned *)0xFFFD4090)
#define TC5_CV_OFFSET 0x90

#define TC5_RA (*(volatile unsigned *)0xFFFD4094)
#define TC5_RA_OFFSET 0x94

#define TC5_RB (*(volatile unsigned *)0xFFFD4098)
#define TC5_RB_OFFSET 0x98

#define TC5_RC (*(volatile unsigned *)0xFFFD409C)
#define TC5_RC_OFFSET 0x9C

#define TC5_SR (*(volatile unsigned *)0xFFFD40A0)
#define TC5_SR_OFFSET 0xA0

#define TC5_IER (*(volatile unsigned *)0xFFFD40A4)
#define TC5_IER_OFFSET 0xA4

#define TC5_IDR (*(volatile unsigned *)0xFFFD40A8)
#define TC5_IDR_OFFSET 0xA8

#define TC5_IMR (*(volatile unsigned *)0xFFFD40AC)
#define TC5_IMR_OFFSET 0xAC

#define TC345_BCR (*(volatile unsigned *)0xFFFD40C0)
#define TC345_BCR_OFFSET 0xC0

#define TC345_BMR (*(volatile unsigned *)0xFFFD40C4)
#define TC345_BMR_OFFSET 0xC4

#define PIOA_BASE 0xFFFEC000

#define PIOA_PER (*(volatile unsigned *)0xFFFEC000)
#define PIOA_PER_OFFSET 0x0

#define PIOA_PDR (*(volatile unsigned *)0xFFFEC004)
#define PIOA_PDR_OFFSET 0x4

#define PIOA_PSR (*(volatile unsigned *)0xFFFEC008)
#define PIOA_PSR_OFFSET 0x8

#define PIOA_OER (*(volatile unsigned *)0xFFFEC010)
#define PIOA_OER_OFFSET 0x10

#define PIOA_ODR (*(volatile unsigned *)0xFFFEC014)
#define PIOA_ODR_OFFSET 0x14

#define PIOA_OSR (*(volatile unsigned *)0xFFFEC018)
#define PIOA_OSR_OFFSET 0x18

#define PIOA_IFER (*(volatile unsigned *)0xFFFEC020)
#define PIOA_IFER_OFFSET 0x20

#define PIOA_IFDR (*(volatile unsigned *)0xFFFEC024)
#define PIOA_IFDR_OFFSET 0x24

#define PIOA_IFSR (*(volatile unsigned *)0xFFFEC028)
#define PIOA_IFSR_OFFSET 0x28

#define PIOA_SODR (*(volatile unsigned *)0xFFFEC030)
#define PIOA_SODR_OFFSET 0x30

#define PIOA_CODR (*(volatile unsigned *)0xFFFEC034)
#define PIOA_CODR_OFFSET 0x34

#define PIOA_ODSR (*(volatile unsigned *)0xFFFEC038)
#define PIOA_ODSR_OFFSET 0x38

#define PIOA_PDSR (*(volatile unsigned *)0xFFFEC03C)
#define PIOA_PDSR_OFFSET 0x3C

#define PIOA_IER (*(volatile unsigned *)0xFFFEC040)
#define PIOA_IER_OFFSET 0x40

#define PIOA_IDR (*(volatile unsigned *)0xFFFEC044)
#define PIOA_IDR_OFFSET 0x44

#define PIOA_IMR (*(volatile unsigned *)0xFFFEC048)
#define PIOA_IMR_OFFSET 0x48

#define PIOA_ISR (*(volatile unsigned *)0xFFFEC04C)
#define PIOA_ISR_OFFSET 0x4C

#define PIOA_MDER (*(volatile unsigned *)0xFFFEC050)
#define PIOA_MDER_OFFSET 0x50

#define PIOA_MDDR (*(volatile unsigned *)0xFFFEC054)
#define PIOA_MDDR_OFFSET 0x54

#define PIOA_MDSR (*(volatile unsigned *)0xFFFEC058)
#define PIOA_MDSR_OFFSET 0x58

#define PIOB_BASE 0xFFFF0000

#define PIOB_PER (*(volatile unsigned *)0xFFFF0000)
#define PIOB_PER_OFFSET 0x0

#define PIOB_PDR (*(volatile unsigned *)0xFFFF0004)
#define PIOB_PDR_OFFSET 0x4

#define PIOB_PSR (*(volatile unsigned *)0xFFFF0008)
#define PIOB_PSR_OFFSET 0x8

#define PIOB_OER (*(volatile unsigned *)0xFFFF0010)
#define PIOB_OER_OFFSET 0x10

#define PIOB_ODR (*(volatile unsigned *)0xFFFF0014)
#define PIOB_ODR_OFFSET 0x14

#define PIOB_OSR (*(volatile unsigned *)0xFFFF0018)
#define PIOB_OSR_OFFSET 0x18

#define PIOB_IFER (*(volatile unsigned *)0xFFFF0020)
#define PIOB_IFER_OFFSET 0x20

#define PIOB_IFDR (*(volatile unsigned *)0xFFFF0024)
#define PIOB_IFDR_OFFSET 0x24

#define PIOB_IFSR (*(volatile unsigned *)0xFFFF0028)
#define PIOB_IFSR_OFFSET 0x28

#define PIOB_SODR (*(volatile unsigned *)0xFFFF0030)
#define PIOB_SODR_OFFSET 0x30

#define PIOB_CODR (*(volatile unsigned *)0xFFFF0034)
#define PIOB_CODR_OFFSET 0x34

#define PIOB_ODSR (*(volatile unsigned *)0xFFFF0038)
#define PIOB_ODSR_OFFSET 0x38

#define PIOB_PDSR (*(volatile unsigned *)0xFFFF003C)
#define PIOB_PDSR_OFFSET 0x3C

#define PIOB_IER (*(volatile unsigned *)0xFFFF0040)
#define PIOB_IER_OFFSET 0x40

#define PIOB_IDR (*(volatile unsigned *)0xFFFF0044)
#define PIOB_IDR_OFFSET 0x44

#define PIOB_IMR (*(volatile unsigned *)0xFFFF0048)
#define PIOB_IMR_OFFSET 0x48

#define PIOB_ISR (*(volatile unsigned *)0xFFFF004C)
#define PIOB_ISR_OFFSET 0x4C

#define PIOB_MDER (*(volatile unsigned *)0xFFFF0050)
#define PIOB_MDER_OFFSET 0x50

#define PIOB_MDDR (*(volatile unsigned *)0xFFFF0054)
#define PIOB_MDDR_OFFSET 0x54

#define PIOB_MDSR (*(volatile unsigned *)0xFFFF0058)
#define PIOB_MDSR_OFFSET 0x58

#define APMC_BASE 0xFFFF4000

#define APMC_SCER (*(volatile unsigned *)0xFFFF4000)
#define APMC_SCER_OFFSET 0x0

#define APMC_SCDR (*(volatile unsigned *)0xFFFF4004)
#define APMC_SCDR_OFFSET 0x4

#define APMC_SCSR (*(volatile unsigned *)0xFFFF4008)
#define APMC_SCSR_OFFSET 0x8

#define APMC_PCER (*(volatile unsigned *)0xFFFF4010)
#define APMC_PCER_OFFSET 0x10

#define APMC_PCDR (*(volatile unsigned *)0xFFFF4014)
#define APMC_PCDR_OFFSET 0x14

#define APMC_PCSR (*(volatile unsigned *)0xFFFF4018)
#define APMC_PCSR_OFFSET 0x18

#define APMC_CGMR (*(volatile unsigned *)0xFFFF4020)
#define APMC_CGMR_OFFSET 0x20

#define APMC_PCR (*(volatile unsigned *)0xFFFF4028)
#define APMC_PCR_OFFSET 0x28

#define APMC_PMR (*(volatile unsigned *)0xFFFF402C)
#define APMC_PMR_OFFSET 0x2C

#define APMC_SR (*(volatile unsigned *)0xFFFF4030)
#define APMC_SR_OFFSET 0x30

#define APMC_IER (*(volatile unsigned *)0xFFFF4034)
#define APMC_IER_OFFSET 0x34

#define APMC_IDR (*(volatile unsigned *)0xFFFF4038)
#define APMC_IDR_OFFSET 0x38

#define APMC_IMR (*(volatile unsigned *)0xFFFF403C)
#define APMC_IMR_OFFSET 0x3C

#define WD_BASE 0xFFFF8000

#define WD_OMR (*(volatile unsigned *)0xFFFF8000)
#define WD_OMR_OFFSET 0x0

#define WD_CMR (*(volatile unsigned *)0xFFFF8004)
#define WD_CMR_OFFSET 0x4

#define WD_CR (*(volatile unsigned *)0xFFFF8008)
#define WD_CR_OFFSET 0x8

#define WD_SR (*(volatile unsigned *)0xFFFF800C)
#define WD_SR_OFFSET 0xC

#define AIC_BASE 0xFFFFF000

#define AIC_SMR0 (*(volatile unsigned *)0xFFFFF000)
#define AIC_SMR0_OFFSET 0x0

#define AIC_SMR1 (*(volatile unsigned *)0xFFFFF004)
#define AIC_SMR1_OFFSET 0x4

#define AIC_SMR2 (*(volatile unsigned *)0xFFFFF008)
#define AIC_SMR2_OFFSET 0x8

#define AIC_SMR3 (*(volatile unsigned *)0xFFFFF00C)
#define AIC_SMR3_OFFSET 0xC

#define AIC_SMR4 (*(volatile unsigned *)0xFFFFF010)
#define AIC_SMR4_OFFSET 0x10

#define AIC_SMR5 (*(volatile unsigned *)0xFFFFF014)
#define AIC_SMR5_OFFSET 0x14

#define AIC_SMR6 (*(volatile unsigned *)0xFFFFF018)
#define AIC_SMR6_OFFSET 0x18

#define AIC_SMR7 (*(volatile unsigned *)0xFFFFF01C)
#define AIC_SMR7_OFFSET 0x1C

#define AIC_SMR8 (*(volatile unsigned *)0xFFFFF020)
#define AIC_SMR8_OFFSET 0x20

#define AIC_SMR9 (*(volatile unsigned *)0xFFFFF024)
#define AIC_SMR9_OFFSET 0x24

#define AIC_SMR10 (*(volatile unsigned *)0xFFFFF028)
#define AIC_SMR10_OFFSET 0x28

#define AIC_SMR11 (*(volatile unsigned *)0xFFFFF02C)
#define AIC_SMR11_OFFSET 0x2C

#define AIC_SMR12 (*(volatile unsigned *)0xFFFFF030)
#define AIC_SMR12_OFFSET 0x30

#define AIC_SMR13 (*(volatile unsigned *)0xFFFFF034)
#define AIC_SMR13_OFFSET 0x34

#define AIC_SMR14 (*(volatile unsigned *)0xFFFFF038)
#define AIC_SMR14_OFFSET 0x38

#define AIC_SMR15 (*(volatile unsigned *)0xFFFFF03C)
#define AIC_SMR15_OFFSET 0x3C

#define AIC_SMR16 (*(volatile unsigned *)0xFFFFF040)
#define AIC_SMR16_OFFSET 0x40

#define AIC_SMR17 (*(volatile unsigned *)0xFFFFF044)
#define AIC_SMR17_OFFSET 0x44

#define AIC_SMR18 (*(volatile unsigned *)0xFFFFF048)
#define AIC_SMR18_OFFSET 0x48

#define AIC_SMR19 (*(volatile unsigned *)0xFFFFF04C)
#define AIC_SMR19_OFFSET 0x4C

#define AIC_SMR20 (*(volatile unsigned *)0xFFFFF050)
#define AIC_SMR20_OFFSET 0x50

#define AIC_SMR21 (*(volatile unsigned *)0xFFFFF054)
#define AIC_SMR21_OFFSET 0x54

#define AIC_SMR22 (*(volatile unsigned *)0xFFFFF058)
#define AIC_SMR22_OFFSET 0x58

#define AIC_SMR23 (*(volatile unsigned *)0xFFFFF05C)
#define AIC_SMR23_OFFSET 0x5C

#define AIC_SMR24 (*(volatile unsigned *)0xFFFFF060)
#define AIC_SMR24_OFFSET 0x60

#define AIC_SMR25 (*(volatile unsigned *)0xFFFFF064)
#define AIC_SMR25_OFFSET 0x64

#define AIC_SMR26 (*(volatile unsigned *)0xFFFFF068)
#define AIC_SMR26_OFFSET 0x68

#define AIC_SMR27 (*(volatile unsigned *)0xFFFFF06C)
#define AIC_SMR27_OFFSET 0x6C

#define AIC_SMR28 (*(volatile unsigned *)0xFFFFF070)
#define AIC_SMR28_OFFSET 0x70

#define AIC_SMR29 (*(volatile unsigned *)0xFFFFF074)
#define AIC_SMR29_OFFSET 0x74

#define AIC_SMR30 (*(volatile unsigned *)0xFFFFF078)
#define AIC_SMR30_OFFSET 0x78

#define AIC_SMR31 (*(volatile unsigned *)0xFFFFF07C)
#define AIC_SMR31_OFFSET 0x7C

#define AIC_SVR0 (*(volatile unsigned *)0xFFFFF080)
#define AIC_SVR0_OFFSET 0x80

#define AIC_SVR1 (*(volatile unsigned *)0xFFFFF084)
#define AIC_SVR1_OFFSET 0x84

#define AIC_SVR2 (*(volatile unsigned *)0xFFFFF088)
#define AIC_SVR2_OFFSET 0x88

#define AIC_SVR3 (*(volatile unsigned *)0xFFFFF08C)
#define AIC_SVR3_OFFSET 0x8C

#define AIC_SVR4 (*(volatile unsigned *)0xFFFFF090)
#define AIC_SVR4_OFFSET 0x90

#define AIC_SVR5 (*(volatile unsigned *)0xFFFFF094)
#define AIC_SVR5_OFFSET 0x94

#define AIC_SVR6 (*(volatile unsigned *)0xFFFFF098)
#define AIC_SVR6_OFFSET 0x98

#define AIC_SVR7 (*(volatile unsigned *)0xFFFFF09C)
#define AIC_SVR7_OFFSET 0x9C

#define AIC_SVR8 (*(volatile unsigned *)0xFFFFF0A0)
#define AIC_SVR8_OFFSET 0xA0

#define AIC_SVR9 (*(volatile unsigned *)0xFFFFF0A4)
#define AIC_SVR9_OFFSET 0xA4

#define AIC_SVR10 (*(volatile unsigned *)0xFFFFF0A8)
#define AIC_SVR10_OFFSET 0xA8

#define AIC_SVR11 (*(volatile unsigned *)0xFFFFF0AC)
#define AIC_SVR11_OFFSET 0xAC

#define AIC_SVR12 (*(volatile unsigned *)0xFFFFF0B0)
#define AIC_SVR12_OFFSET 0xB0

#define AIC_SVR13 (*(volatile unsigned *)0xFFFFF0B4)
#define AIC_SVR13_OFFSET 0xB4

#define AIC_SVR14 (*(volatile unsigned *)0xFFFFF0B8)
#define AIC_SVR14_OFFSET 0xB8

#define AIC_SVR15 (*(volatile unsigned *)0xFFFFF0BC)
#define AIC_SVR15_OFFSET 0xBC

#define AIC_SVR16 (*(volatile unsigned *)0xFFFFF0C0)
#define AIC_SVR16_OFFSET 0xC0

#define AIC_SVR17 (*(volatile unsigned *)0xFFFFF0C4)
#define AIC_SVR17_OFFSET 0xC4

#define AIC_SVR18 (*(volatile unsigned *)0xFFFFF0C8)
#define AIC_SVR18_OFFSET 0xC8

#define AIC_SVR19 (*(volatile unsigned *)0xFFFFF0CC)
#define AIC_SVR19_OFFSET 0xCC

#define AIC_SVR20 (*(volatile unsigned *)0xFFFFF0D0)
#define AIC_SVR20_OFFSET 0xD0

#define AIC_SVR21 (*(volatile unsigned *)0xFFFFF0D4)
#define AIC_SVR21_OFFSET 0xD4

#define AIC_SVR22 (*(volatile unsigned *)0xFFFFF0D8)
#define AIC_SVR22_OFFSET 0xD8

#define AIC_SVR23 (*(volatile unsigned *)0xFFFFF0DC)
#define AIC_SVR23_OFFSET 0xDC

#define AIC_SVR24 (*(volatile unsigned *)0xFFFFF0E0)
#define AIC_SVR24_OFFSET 0xE0

#define AIC_SVR25 (*(volatile unsigned *)0xFFFFF0E4)
#define AIC_SVR25_OFFSET 0xE4

#define AIC_SVR26 (*(volatile unsigned *)0xFFFFF0E8)
#define AIC_SVR26_OFFSET 0xE8

#define AIC_SVR27 (*(volatile unsigned *)0xFFFFF0EC)
#define AIC_SVR27_OFFSET 0xEC

#define AIC_SVR28 (*(volatile unsigned *)0xFFFFF0F0)
#define AIC_SVR28_OFFSET 0xF0

#define AIC_SVR29 (*(volatile unsigned *)0xFFFFF0F4)
#define AIC_SVR29_OFFSET 0xF4

#define AIC_SVR30 (*(volatile unsigned *)0xFFFFF0F8)
#define AIC_SVR30_OFFSET 0xF8

#define AIC_SVR31 (*(volatile unsigned *)0xFFFFF0FC)
#define AIC_SVR31_OFFSET 0xFC

#define AIC_IVR (*(volatile unsigned *)0xFFFFF100)
#define AIC_IVR_OFFSET 0x100

#define AIC_FVR (*(volatile unsigned *)0xFFFFF104)
#define AIC_FVR_OFFSET 0x104

#define AIC_ISR (*(volatile unsigned *)0xFFFFF108)
#define AIC_ISR_OFFSET 0x108

#define AIC_IPR (*(volatile unsigned *)0xFFFFF10C)
#define AIC_IPR_OFFSET 0x10C

#define AIC_IMR (*(volatile unsigned *)0xFFFFF110)
#define AIC_IMR_OFFSET 0x110

#define AIC_CISR (*(volatile unsigned *)0xFFFFF114)
#define AIC_CISR_OFFSET 0x114

#define AIC_IECR (*(volatile unsigned *)0xFFFFF120)
#define AIC_IECR_OFFSET 0x120

#define AIC_IDCR (*(volatile unsigned *)0xFFFFF124)
#define AIC_IDCR_OFFSET 0x124

#define AIC_ICCR (*(volatile unsigned *)0xFFFFF128)
#define AIC_ICCR_OFFSET 0x128

#define AIC_ISCR (*(volatile unsigned *)0xFFFFF12C)
#define AIC_ISCR_OFFSET 0x12C

#define AIC_EOICR (*(volatile unsigned *)0xFFFFF130)
#define AIC_EOICR_OFFSET 0x130

#define AIC_SPU (*(volatile unsigned *)0xFFFFF134)
#define AIC_SPU_OFFSET 0x134


#endif
