// AT91x408xx register and bit definitions.
//
// Copyright (c) 2005 Rowley Associates Limited.
//
// This file may be distributed under the terms of the License Agreement
// provided with this software.
//
// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE
// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.

#ifndef AT91x408xx_h
#define AT91x408xx_h

#define EBI_BASE 0xFFE00000

#define EBI_CSR0 (*(volatile unsigned *)0xFFE00000)
#define EBI_CSR0_OFFSET 0x0

#define EBI_CSR1 (*(volatile unsigned *)0xFFE00004)
#define EBI_CSR1_OFFSET 0x4

#define EBI_CSR2 (*(volatile unsigned *)0xFFE00008)
#define EBI_CSR2_OFFSET 0x8

#define EBI_CSR3 (*(volatile unsigned *)0xFFE0000C)
#define EBI_CSR3_OFFSET 0xC

#define EBI_CSR4 (*(volatile unsigned *)0xFFE00010)
#define EBI_CSR4_OFFSET 0x10

#define EBI_CSR5 (*(volatile unsigned *)0xFFE00014)
#define EBI_CSR5_OFFSET 0x14

#define EBI_CSR6 (*(volatile unsigned *)0xFFE00018)
#define EBI_CSR6_OFFSET 0x18

#define EBI_CSR7 (*(volatile unsigned *)0xFFE0001C)
#define EBI_CSR7_OFFSET 0x1C

#define EBI_RCR (*(volatile unsigned *)0xFFE00020)
#define EBI_RCR_OFFSET 0x20

#define EBI_MCR (*(volatile unsigned *)0xFFE00024)
#define EBI_MCR_OFFSET 0x24

#define SF_BASE 0xFFF00000

#define SF_CIDR (*(volatile unsigned *)0xFFF00000)
#define SF_CIDR_OFFSET 0x0

#define SF_EXID (*(volatile unsigned *)0xFFF00004)
#define SF_EXID_OFFSET 0x4

#define SF_RSR (*(volatile unsigned *)0xFFF00008)
#define SF_RSR_OFFSET 0x8

#define SF_MMR (*(volatile unsigned *)0xFFF0000C)
#define SF_MMR_OFFSET 0xC

#define SF_PMR (*(volatile unsigned *)0xFFF00018)
#define SF_PMR_OFFSET 0x18

#define USART1_BASE 0xFFFCC000

#define US_CR (*(volatile unsigned *)0xFFFCC000)
#define US_CR_OFFSET 0x0

#define US_MR (*(volatile unsigned *)0xFFFCC004)
#define US_MR_OFFSET 0x4

#define US_IER (*(volatile unsigned *)0xFFFCC008)
#define US_IER_OFFSET 0x8

#define US_IDR (*(volatile unsigned *)0xFFFCC00C)
#define US_IDR_OFFSET 0xC

#define US_IMR (*(volatile unsigned *)0xFFFCC010)
#define US_IMR_OFFSET 0x10

#define US_CSR (*(volatile unsigned *)0xFFFCC014)
#define US_CSR_OFFSET 0x14

#define US_RHR (*(volatile unsigned *)0xFFFCC018)
#define US_RHR_OFFSET 0x18

#define US_THR (*(volatile unsigned *)0xFFFCC01C)
#define US_THR_OFFSET 0x1C

#define US_BRGR (*(volatile unsigned *)0xFFFCC020)
#define US_BRGR_OFFSET 0x20

#define US_RTOR (*(volatile unsigned *)0xFFFCC024)
#define US_RTOR_OFFSET 0x24

#define US_TTGR (*(volatile unsigned *)0xFFFCC028)
#define US_TTGR_OFFSET 0x28

#define US_RPR (*(volatile unsigned *)0xFFFCC030)
#define US_RPR_OFFSET 0x30

#define US_RCR (*(volatile unsigned *)0xFFFCC034)
#define US_RCR_OFFSET 0x34

#define US_TPR (*(volatile unsigned *)0xFFFCC038)
#define US_TPR_OFFSET 0x38

#define US_TCR (*(volatile unsigned *)0xFFFCC03C)
#define US_TCR_OFFSET 0x3C

#define USART0_BASE 0xFFFD0000

#define US_CR (*(volatile unsigned *)0xFFFD0000)
#define US_CR_OFFSET 0x0

#define US_MR (*(volatile unsigned *)0xFFFD0004)
#define US_MR_OFFSET 0x4

#define US_IER (*(volatile unsigned *)0xFFFD0008)
#define US_IER_OFFSET 0x8

#define US_IDR (*(volatile unsigned *)0xFFFD000C)
#define US_IDR_OFFSET 0xC

#define US_IMR (*(volatile unsigned *)0xFFFD0010)
#define US_IMR_OFFSET 0x10

#define US_CSR (*(volatile unsigned *)0xFFFD0014)
#define US_CSR_OFFSET 0x14

#define US_RHR (*(volatile unsigned *)0xFFFD0018)
#define US_RHR_OFFSET 0x18

#define US_THR (*(volatile unsigned *)0xFFFD001C)
#define US_THR_OFFSET 0x1C

#define US_BRGR (*(volatile unsigned *)0xFFFD0020)
#define US_BRGR_OFFSET 0x20

#define US_RTOR (*(volatile unsigned *)0xFFFD0024)
#define US_RTOR_OFFSET 0x24

#define US_TTGR (*(volatile unsigned *)0xFFFD0028)
#define US_TTGR_OFFSET 0x28

#define US_RPR (*(volatile unsigned *)0xFFFD0030)
#define US_RPR_OFFSET 0x30

#define US_RCR (*(volatile unsigned *)0xFFFD0034)
#define US_RCR_OFFSET 0x34

#define US_TPR (*(volatile unsigned *)0xFFFD0038)
#define US_TPR_OFFSET 0x38

#define US_TCR (*(volatile unsigned *)0xFFFD003C)
#define US_TCR_OFFSET 0x3C

#define TC0_BASE 0xFFFE0000

#define TC0_CCR (*(volatile unsigned *)0xFFFE0000)
#define TC0_CCR_OFFSET 0x0

#define TC0_CMR (*(volatile unsigned *)0xFFFE0004)
#define TC0_CMR_OFFSET 0x4

#define TC0_CV (*(volatile unsigned *)0xFFFE0010)
#define TC0_CV_OFFSET 0x10

#define TC0_RA (*(volatile unsigned *)0xFFFE0014)
#define TC0_RA_OFFSET 0x14

#define TC0_RB (*(volatile unsigned *)0xFFFE0018)
#define TC0_RB_OFFSET 0x18

#define TC0_RC (*(volatile unsigned *)0xFFFE001C)
#define TC0_RC_OFFSET 0x1C

#define TC0_SR (*(volatile unsigned *)0xFFFE0020)
#define TC0_SR_OFFSET 0x20

#define TC0_IER (*(volatile unsigned *)0xFFFE0024)
#define TC0_IER_OFFSET 0x24

#define TC0_IDR (*(volatile unsigned *)0xFFFE0028)
#define TC0_IDR_OFFSET 0x28

#define TC0_IMR (*(volatile unsigned *)0xFFFE002C)
#define TC0_IMR_OFFSET 0x2C

#define TC1_BASE 0xFFFE0040

#define TC1_CCR (*(volatile unsigned *)0xFFFE0040)
#define TC1_CCR_OFFSET 0x0

#define TC1_CMR (*(volatile unsigned *)0xFFFE0044)
#define TC1_CMR_OFFSET 0x4

#define TC1_CV (*(volatile unsigned *)0xFFFE0050)
#define TC1_CV_OFFSET 0x10

#define TC1_RA (*(volatile unsigned *)0xFFFE0054)
#define TC1_RA_OFFSET 0x14

#define TC1_RB (*(volatile unsigned *)0xFFFE0058)
#define TC1_RB_OFFSET 0x18

#define TC1_RC (*(volatile unsigned *)0xFFFE005C)
#define TC1_RC_OFFSET 0x1C

#define TC1_SR (*(volatile unsigned *)0xFFFE0060)
#define TC1_SR_OFFSET 0x20

#define TC1_IER (*(volatile unsigned *)0xFFFE0064)
#define TC1_IER_OFFSET 0x24

#define TC1_IDR (*(volatile unsigned *)0xFFFE0068)
#define TC1_IDR_OFFSET 0x28

#define TC1_IMR (*(volatile unsigned *)0xFFFE006C)
#define TC1_IMR_OFFSET 0x2C

#define TC2_BASE 0xFFFE0080

#define TC2_CCR (*(volatile unsigned *)0xFFFE0080)
#define TC2_CCR_OFFSET 0x0

#define TC2_CMR (*(volatile unsigned *)0xFFFE0084)
#define TC2_CMR_OFFSET 0x4

#define TC2_CV (*(volatile unsigned *)0xFFFE0090)
#define TC2_CV_OFFSET 0x10

#define TC2_RA (*(volatile unsigned *)0xFFFE0094)
#define TC2_RA_OFFSET 0x14

#define TC2_RB (*(volatile unsigned *)0xFFFE0098)
#define TC2_RB_OFFSET 0x18

#define TC2_RC (*(volatile unsigned *)0xFFFE009C)
#define TC2_RC_OFFSET 0x1C

#define TC2_SR (*(volatile unsigned *)0xFFFE00A0)
#define TC2_SR_OFFSET 0x20

#define TC2_IER (*(volatile unsigned *)0xFFFE00A4)
#define TC2_IER_OFFSET 0x24

#define TC2_IDR (*(volatile unsigned *)0xFFFE00A8)
#define TC2_IDR_OFFSET 0x28

#define TC2_IMR (*(volatile unsigned *)0xFFFE00AC)
#define TC2_IMR_OFFSET 0x2C

#define TC_BASE 0xFFFE00C0

#define TC_BCR (*(volatile unsigned *)0xFFFE00C0)
#define TC_BCR_OFFSET 0x0

#define TC_BMR (*(volatile unsigned *)0xFFFE00C4)
#define TC_BMR_OFFSET 0x4

#define PIO_BASE 0xFFFF0000

#define PIO_PER (*(volatile unsigned *)0xFFFF0000)
#define PIO_PER_OFFSET 0x0

#define PIO_PDR (*(volatile unsigned *)0xFFFF0004)
#define PIO_PDR_OFFSET 0x4

#define PIO_PSR (*(volatile unsigned *)0xFFFF0008)
#define PIO_PSR_OFFSET 0x8

#define PIO_OER (*(volatile unsigned *)0xFFFF0010)
#define PIO_OER_OFFSET 0x10

#define PIO_ODR (*(volatile unsigned *)0xFFFF0014)
#define PIO_ODR_OFFSET 0x14

#define PIO_OSR (*(volatile unsigned *)0xFFFF0018)
#define PIO_OSR_OFFSET 0x18

#define PIO_IFER (*(volatile unsigned *)0xFFFF0020)
#define PIO_IFER_OFFSET 0x20

#define PIO_IFDR (*(volatile unsigned *)0xFFFF0024)
#define PIO_IFDR_OFFSET 0x24

#define PIO_IFSR (*(volatile unsigned *)0xFFFF0028)
#define PIO_IFSR_OFFSET 0x28

#define PIO_SODR (*(volatile unsigned *)0xFFFF0030)
#define PIO_SODR_OFFSET 0x30

#define PIO_CODR (*(volatile unsigned *)0xFFFF0034)
#define PIO_CODR_OFFSET 0x34

#define PIO_ODSR (*(volatile unsigned *)0xFFFF0038)
#define PIO_ODSR_OFFSET 0x38

#define PIO_PDSR (*(volatile unsigned *)0xFFFF003C)
#define PIO_PDSR_OFFSET 0x3C

#define PIO_IER (*(volatile unsigned *)0xFFFF0040)
#define PIO_IER_OFFSET 0x40

#define PIO_IDR (*(volatile unsigned *)0xFFFF0044)
#define PIO_IDR_OFFSET 0x44

#define PIO_IMR (*(volatile unsigned *)0xFFFF0048)
#define PIO_IMR_OFFSET 0x48

#define PIO_ISR (*(volatile unsigned *)0xFFFF004C)
#define PIO_ISR_OFFSET 0x4C

#define PS_BASE 0xFFFF4000

#define PS_CR (*(volatile unsigned *)0xFFFF4000)
#define PS_CR_OFFSET 0x0

#define PS_PCER (*(volatile unsigned *)0xFFFF4004)
#define PS_PCER_OFFSET 0x4

#define PS_PCDR (*(volatile unsigned *)0xFFFF4008)
#define PS_PCDR_OFFSET 0x8

#define PS_PCSR (*(volatile unsigned *)0xFFFF400C)
#define PS_PCSR_OFFSET 0xC

#define WD_BASE 0xFFFF8000

#define WD_OMR (*(volatile unsigned *)0xFFFF8000)
#define WD_OMR_OFFSET 0x0

#define WD_CMR (*(volatile unsigned *)0xFFFF8004)
#define WD_CMR_OFFSET 0x4

#define WD_CR (*(volatile unsigned *)0xFFFF8008)
#define WD_CR_OFFSET 0x8

#define WD_SR (*(volatile unsigned *)0xFFFF800C)
#define WD_SR_OFFSET 0xC

#define AIC_SMR_BASE 0xFFFFF000

#define AIC_SMR0 (*(volatile unsigned *)0xFFFFF000)
#define AIC_SMR0_OFFSET 0x0

#define AIC_SMR1 (*(volatile unsigned *)0xFFFFF004)
#define AIC_SMR1_OFFSET 0x4

#define AIC_SMR2 (*(volatile unsigned *)0xFFFFF008)
#define AIC_SMR2_OFFSET 0x8

#define AIC_SMR3 (*(volatile unsigned *)0xFFFFF00C)
#define AIC_SMR3_OFFSET 0xC

#define AIC_SMR4 (*(volatile unsigned *)0xFFFFF010)
#define AIC_SMR4_OFFSET 0x10

#define AIC_SMR5 (*(volatile unsigned *)0xFFFFF014)
#define AIC_SMR5_OFFSET 0x14

#define AIC_SMR6 (*(volatile unsigned *)0xFFFFF018)
#define AIC_SMR6_OFFSET 0x18

#define AIC_SMR7 (*(volatile unsigned *)0xFFFFF01C)
#define AIC_SMR7_OFFSET 0x1C

#define AIC_SMR8 (*(volatile unsigned *)0xFFFFF020)
#define AIC_SMR8_OFFSET 0x20

#define AIC_SMR9 (*(volatile unsigned *)0xFFFFF024)
#define AIC_SMR9_OFFSET 0x24

#define AIC_SMR10 (*(volatile unsigned *)0xFFFFF028)
#define AIC_SMR10_OFFSET 0x28

#define AIC_SMR11 (*(volatile unsigned *)0xFFFFF02C)
#define AIC_SMR11_OFFSET 0x2C

#define AIC_SMR12 (*(volatile unsigned *)0xFFFFF030)
#define AIC_SMR12_OFFSET 0x30

#define AIC_SMR13 (*(volatile unsigned *)0xFFFFF034)
#define AIC_SMR13_OFFSET 0x34

#define AIC_SMR14 (*(volatile unsigned *)0xFFFFF038)
#define AIC_SMR14_OFFSET 0x38

#define AIC_SMR15 (*(volatile unsigned *)0xFFFFF03C)
#define AIC_SMR15_OFFSET 0x3C

#define AIC_SMR16 (*(volatile unsigned *)0xFFFFF040)
#define AIC_SMR16_OFFSET 0x40

#define AIC_SMR17 (*(volatile unsigned *)0xFFFFF044)
#define AIC_SMR17_OFFSET 0x44

#define AIC_SMR18 (*(volatile unsigned *)0xFFFFF048)
#define AIC_SMR18_OFFSET 0x48

#define AIC_SMR19 (*(volatile unsigned *)0xFFFFF04C)
#define AIC_SMR19_OFFSET 0x4C

#define AIC_SMR20 (*(volatile unsigned *)0xFFFFF050)
#define AIC_SMR20_OFFSET 0x50

#define AIC_SMR21 (*(volatile unsigned *)0xFFFFF054)
#define AIC_SMR21_OFFSET 0x54

#define AIC_SMR22 (*(volatile unsigned *)0xFFFFF058)
#define AIC_SMR22_OFFSET 0x58

#define AIC_SMR23 (*(volatile unsigned *)0xFFFFF05C)
#define AIC_SMR23_OFFSET 0x5C

#define AIC_SMR24 (*(volatile unsigned *)0xFFFFF060)
#define AIC_SMR24_OFFSET 0x60

#define AIC_SMR25 (*(volatile unsigned *)0xFFFFF064)
#define AIC_SMR25_OFFSET 0x64

#define AIC_SMR26 (*(volatile unsigned *)0xFFFFF068)
#define AIC_SMR26_OFFSET 0x68

#define AIC_SMR27 (*(volatile unsigned *)0xFFFFF06C)
#define AIC_SMR27_OFFSET 0x6C

#define AIC_SMR28 (*(volatile unsigned *)0xFFFFF070)
#define AIC_SMR28_OFFSET 0x70

#define AIC_SMR29 (*(volatile unsigned *)0xFFFFF074)
#define AIC_SMR29_OFFSET 0x74

#define AIC_SMR30 (*(volatile unsigned *)0xFFFFF078)
#define AIC_SMR30_OFFSET 0x78

#define AIC_SMR31 (*(volatile unsigned *)0xFFFFF07C)
#define AIC_SMR31_OFFSET 0x7C

#define AIC_SVR_BASE 0xFFFFF080

#define AIC_SVR0 (*(volatile unsigned *)0xFFFFF080)
#define AIC_SVR0_OFFSET 0x0

#define AIC_SVR1 (*(volatile unsigned *)0xFFFFF084)
#define AIC_SVR1_OFFSET 0x4

#define AIC_SVR2 (*(volatile unsigned *)0xFFFFF088)
#define AIC_SVR2_OFFSET 0x8

#define AIC_SVR3 (*(volatile unsigned *)0xFFFFF08C)
#define AIC_SVR3_OFFSET 0xC

#define AIC_SVR4 (*(volatile unsigned *)0xFFFFF090)
#define AIC_SVR4_OFFSET 0x10

#define AIC_SVR5 (*(volatile unsigned *)0xFFFFF094)
#define AIC_SVR5_OFFSET 0x14

#define AIC_SVR6 (*(volatile unsigned *)0xFFFFF098)
#define AIC_SVR6_OFFSET 0x18

#define AIC_SVR7 (*(volatile unsigned *)0xFFFFF09C)
#define AIC_SVR7_OFFSET 0x1C

#define AIC_SVR8 (*(volatile unsigned *)0xFFFFF0A0)
#define AIC_SVR8_OFFSET 0x20

#define AIC_SVR9 (*(volatile unsigned *)0xFFFFF0A4)
#define AIC_SVR9_OFFSET 0x24

#define AIC_SVR10 (*(volatile unsigned *)0xFFFFF0A8)
#define AIC_SVR10_OFFSET 0x28

#define AIC_SVR11 (*(volatile unsigned *)0xFFFFF0AC)
#define AIC_SVR11_OFFSET 0x2C

#define AIC_SVR12 (*(volatile unsigned *)0xFFFFF0B0)
#define AIC_SVR12_OFFSET 0x30

#define AIC_SVR13 (*(volatile unsigned *)0xFFFFF0B4)
#define AIC_SVR13_OFFSET 0x34

#define AIC_SVR14 (*(volatile unsigned *)0xFFFFF0B8)
#define AIC_SVR14_OFFSET 0x38

#define AIC_SVR15 (*(volatile unsigned *)0xFFFFF0BC)
#define AIC_SVR15_OFFSET 0x3C

#define AIC_SVR16 (*(volatile unsigned *)0xFFFFF0C0)
#define AIC_SVR16_OFFSET 0x40

#define AIC_SVR17 (*(volatile unsigned *)0xFFFFF0C4)
#define AIC_SVR17_OFFSET 0x44

#define AIC_SMR18 (*(volatile unsigned *)0xFFFFF0C8)
#define AIC_SMR18_OFFSET 0x48

#define AIC_SMR19 (*(volatile unsigned *)0xFFFFF0CC)
#define AIC_SMR19_OFFSET 0x4C

#define AIC_SMR20 (*(volatile unsigned *)0xFFFFF0D0)
#define AIC_SMR20_OFFSET 0x50

#define AIC_SMR21 (*(volatile unsigned *)0xFFFFF0D4)
#define AIC_SMR21_OFFSET 0x54

#define AIC_SMR22 (*(volatile unsigned *)0xFFFFF0D8)
#define AIC_SMR22_OFFSET 0x58

#define AIC_SMR23 (*(volatile unsigned *)0xFFFFF0DC)
#define AIC_SMR23_OFFSET 0x5C

#define AIC_SMR24 (*(volatile unsigned *)0xFFFFF0E0)
#define AIC_SMR24_OFFSET 0x60

#define AIC_SMR25 (*(volatile unsigned *)0xFFFFF0E4)
#define AIC_SMR25_OFFSET 0x64

#define AIC_SMR26 (*(volatile unsigned *)0xFFFFF0E8)
#define AIC_SMR26_OFFSET 0x68

#define AIC_SMR27 (*(volatile unsigned *)0xFFFFF0EC)
#define AIC_SMR27_OFFSET 0x6C

#define AIC_SMR28 (*(volatile unsigned *)0xFFFFF0F0)
#define AIC_SMR28_OFFSET 0x70

#define AIC_SMR29 (*(volatile unsigned *)0xFFFFF0F4)
#define AIC_SMR29_OFFSET 0x74

#define AIC_SMR30 (*(volatile unsigned *)0xFFFFF0F8)
#define AIC_SMR30_OFFSET 0x78

#define AIC_SMR31 (*(volatile unsigned *)0xFFFFF0FC)
#define AIC_SMR31_OFFSET 0x7C

#define AIC_BASE 0xFFFFF100

#define AIC_IVR (*(volatile unsigned *)0xFFFFF100)
#define AIC_IVR_OFFSET 0x0

#define AIC_FVR (*(volatile unsigned *)0xFFFFF104)
#define AIC_FVR_OFFSET 0x4

#define AIC_ISR (*(volatile unsigned *)0xFFFFF108)
#define AIC_ISR_OFFSET 0x8

#define AIC_IPR (*(volatile unsigned *)0xFFFFF10C)
#define AIC_IPR_OFFSET 0xC

#define AIC_IMR (*(volatile unsigned *)0xFFFFF110)
#define AIC_IMR_OFFSET 0x10

#define AIC_CISR (*(volatile unsigned *)0xFFFFF114)
#define AIC_CISR_OFFSET 0x14

#define AIC_IECR (*(volatile unsigned *)0xFFFFF120)
#define AIC_IECR_OFFSET 0x20

#define AIC_IDCR (*(volatile unsigned *)0xFFFFF124)
#define AIC_IDCR_OFFSET 0x24

#define AIC_ICCR (*(volatile unsigned *)0xFFFFF128)
#define AIC_ICCR_OFFSET 0x28

#define AIC_ISCR (*(volatile unsigned *)0xFFFFF12C)
#define AIC_ISCR_OFFSET 0x2C

#define AIC_EOICR (*(volatile unsigned *)0xFFFFF130)
#define AIC_EOICR_OFFSET 0x30

#define AIC_SPU (*(volatile unsigned *)0xFFFFF134)
#define AIC_SPU_OFFSET 0x34


#endif
