The MIPS configurations of GNU as
support these
special options:
-G
num
gp
register. It is only accepted for targets
that use ECOFF format. The default value is 8.
-EB
-EL
as
can select big-endian or
little-endian output at run time (unlike the other GNU development
tools, which must be configured for one or the other). Use -EB
to select big-endian output, and -EL
for little-endian.
-mips1
-mips2
-mips3
-mips4
-mips5
-mips32
-mips32r2
-mips64
-mips64r2
-mips1
corresponds to the R2000 and R3000 processors,
-mips2
to the R6000 processor, -mips3
to the
R4000 processor, and -mips4
to the R8000 and
R10000 processors. -mips5
, -mips32
, -mips32r2
,
-mips64
, and -mips64r2
correspond to generic
MIPS V, MIPS32, MIPS32 RELEASE 2, MIPS64,
and MIPS64 RELEASE 2
ISA processors, respectively. You can also switch
instruction sets during the assembly; see Directives to override the ISA level.
-mgp32
-mfp32
-mgp32
controls the size of general-purpose registers
and -mfp32
controls the size of floating-point registers.
On some MIPS variants there is a 32-bit mode flag; when this flag is
set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
save the 32-bit registers on a context switch, so it is essential never
to use the 64-bit registers.
-mgp64
-mips16
-no-mips16
.set mips16
at the start of the assembly file. -no-mips16
turns off this option.
-mips3d
-no-mips3d
-no-mips3d
turns off this option.
-mdmx
-no-mdmx
-no-mdmx
turns off this option.
-mfix7000
-mno-fix7000
-mfix-vr4120
-no-mfix-vr4120
-m4010
-no-m4010
addciu
, ffc
,
etc.), and to not schedule nop
instructions around accesses to
the HI
and LO
registers. -no-m4010
turns off this
option.
-m4650
-no-m4650
mad
and madu
instruction, and to not schedule nop
instructions around accesses to the HI
and LO
registers.
-no-m4650
turns off this option.
-m3900
-no-m3900
-m4100
-no-m4100
-m
nnnn
, generate code for the MIPS
RNNNN chip. This tells the assembler to accept instructions
specific to that chip, and to schedule for that chip's hazards.
-march=
cpu
-m
cpu
, except that there are more value of cpu
understood. Valid cpu value are:
2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 10000, 12000, mips32-4k, sb1
-mtune=
cpu
-march=
cpu
.
-mabi=
abi
32
, n32
, o64
, 64
and eabi
.
-nocpp
as
, there is no need for -nocpp
, because the
GNU assembler itself never runs the C preprocessor.
--construct-floats
--no-construct-floats
--no-construct-floats
option disables the construction of
double width floating point constants by loading the two halves of the
value into the two single width floating point registers that make up
the double width register. This feature is useful if the processor
support the FR bit in its status register, and this bit is known (by
the programmer) to be set. This bit prevents the aliasing of the double
width register by the single width registers.
By default --construct-floats
is selected, allowing construction
of these floating point constants.
--trap
--no-break
as
automatically macro expands certain division and
multiplication instructions to check for overflow and division by zero. This
option causes as
to generate code to take a trap exception
rather than a break exception when an error is detected. The trap instructions
are only supported at Instruction Set Architecture level 2 and higher.
--break
--no-trap
-mpdr
-mno-pdr
.pdr
sections. Off by default on IRIX, on
elsewhere.