NXP LPC1000 CPU Support Package
This package contains project templates and system files for the NXP LPC1000.
CrossWorks Version 2 Installation Instructions
- To install this support package
-
- Click the Tools > Package Manager menu option to open the package manager window.
- Right click on the NXP LPC1000 CPU Support Package entry and select Install Selected Packages.
- Click Next to take you to the summary page.
- Click Next to install the package.
- Click Finish to close the package manager window.
- Click the Tools > Show Installed Packages.
- Click on the NXP LPC1000 CPU Support Package link to view the package and its contents.
- To manually install this support package
-
- If you have not done so already, follow the CMSIS 3 Support Package installation instructions.
- Download the file LPC1000.hzq using your web browser.
- Click the Tools > Manually Install Packages menu option.
- Select the file you have just downloaded to install the package.
- Click the Tools > Show Installed Packages.
- Click on the NXP LPC1000 CPU Support Package link to view the package and its contents.
- To install this support package using other versions
Release Notes
1.32
- Updated LPC15xx SYSCON register definitions.
1.31
- Corrected LPC15xx CAN register definitions.
- Fixed LPC15xx reset script.
1.30
- Deprecated LPC800 support, use the LPC800 CPU support package for new LPC800 projects.
- Deprecated LPC1100 support, use the LPC1100 CPU support package for new LPC1100 projects.
1.29
- Updated LPC11U6x register description file.
- Defined default Package Dependencies in project templates.
1.28
- Added support for LPC15xx devices.
- Added support for LPC11U6x devices.
- Updated LPC407x/8x CMSIS files.
- Added FLASH loaders for devices with 1K of RAM (these only work with CrossWorks V3 or later).
- Added ctl_sleep and ctl_woken to ctl_lpc*.c files. These functions can be used in CTL V3 to reduce the timer interrupt frequency when in low power mode.
1.27
- Added support for LPC4072 devices.
- Added SPIFI loader for LPC407x/8x devices.
- Corrected LPC117x/8x MCI register definitions.
- Fixed LPC800 loader.
1.26
- Updated LPC11Uxx SVD file to version 7.
- Updated LPC13Uxx SVD file to version 1.
- Updated LPC407x/8x SVD file to version 0.7.
- Added support for LPC1102 and LPC1104 devices.
- CTL projects now default to a process stack size of 256 bytes. Please note that existing CTL projects will need to specify a process stack size using the Runtime Memory Area Options > Process Stack Size project property in order to work with CrossWorks for ARM version 2.3.1 onwards.
- Increased default main stack size to 256 bytes.
- Updated system_LPC8xx.c file.
- Added Build Options > Use On-Chip RC Oscillator project property for LPC800 devices.
1.25
- Added support for LPC810, LPC811 and LPC812 devices.
1.24
- Added support for LPC1110FD20, LPC1111FDH20/002, LPC1112FD/102, LPC1114FDH28/102 and LPC1114FN28/102 devices.
- Added support for LPC11E36 and LPC11E37 devices
1.23
- Corrected part IDs for LPC11U37/401 and LPC11U37/501.
- Updated LPC11Axx SVD file to version 0.6.
- Added support for LPC1311/01 and LPC1313/01 devices.
1.22
- Added support for LPC407x/8x devices.
- Added support for LPC11A02, LPC11A04, LPC11A11, LPC11A12 and LPC11A13 devices.
- Fixed LPC177x/8x simulator generating hard fault exception when using AHBSRAM.
1.21
- Added support for LPC11U3x devices.
- LPC11xx and LPC13xx memory maps now use SVD files.
1.20
- LPC17xx devices now place heap and stacks in AHBSRAM by default.
- Added option to call EMCInit function in LPC177x/LPC178x startup code.
- Added support for LPC11A14 devices.
- Corrected definition of LPC11E14/401 SRAM size.
- Improved download performance for devices with 4K of RAM.
- Added support for LPC1114/102 devices.
1.19
- Corrected start address of AHBSRAM in LPC177x/LPC178x memory maps.
- Added support for LPC11Exx devices.
- Added support for LPC1100XL devices.
- Added support for LPC13Uxx devices.
- Added $(TargetsDir)/LPC1000/include/CMSIS to include path in project templates.
- Now uses CMSIS 3 core support package. Please note that existing projects will need to add $(TargetsDir)/LPC1000/include/CMSIS and $(TargetsDir)/CMSIS_3/CMSIS/Include to the Preprocessor Options > User Include Directories project property in order to build.
- Removed old CMSIS core library. Existing projects should remove references to $(TargetsDir)/LPC1000/lib/cmsis$(LibExt)$(LIB) from the Linker Options > Additional Input Files project property as the library is no longer required.
1.18
- Corrected flash size in LPC11U24/401 memory map.
- Fixed reset of LPC177x/8x devices when there is no valid program in flash.
1.17
- Added support for LPC11Uxx devices.
1.16
- Fixed debugging of IAP functions on LPC177x/8x devices running at 120MHz.
1.15
- Added support for LPC11D14/302 and LPC12D27/301 devices.
- Updated LPC11Cxx and LPC11xx support files.
- Added EABI versions of libraries.
1.14
- Corrected definition of LPC13xx USB device interrupt registers.
- Corrected definition of __NVIC_PRIO_BITS in LPC11xx.h CMSIS file.
- Simulator now works with latest reset script.
1.13
- Added support for LPC111x/102/202/302 (LPC1100L series), LPC11C22/301 and LPC11C24/301 devices.
- Compiling LPC1000.h with an invalid __TARGET_PROCESSOR definition now generates an error.
1.12
- Added support for LPC122x devices.
- Now using CMSIS version 2.0.
- Updated LPC177x and LPC178x support files.
1.11
- Reset scripts now work with devices without nSRST.
1.10
- Fixed externally built executable project template.
- Updated LPC177x and LPC178x support files.
1.9
- Added support for LPC177x and LPC178x devices.
1.8
- Fixed LPC1111/101 and LPC1112/101 loader.
- Added support for LPC11C12 and LPC11C14.
- Corrected definition of LPC17xx CAN BTR register.
- Corrected definition of LPC17xx EMAC MRDD register.
- Corrected definition of LPC17xx USB USBDevIntClr and USBDevIntSet registers.
- Corrected definition of LPC17xx I2SSTATE, I2SDMA1, I2SDMA2, I2SIRQ registers.
- Corrected definition of I2C MMCTRL register.
- Corrected definition of UART FIFOLVL register.
- Renamed LPC17xx ADTRIM register to AD0TRM.
- LPC17xx simulator will now finish executing CMSIS startup code.
1.7
- Corrected definition of PCONP register.
- Added IAP status code definitions to liblpc1000.h.
- Updated CMSIS files to latest version. Note that you will need to add the -fms-extensions compiler option to existing projects to avoid anonymous structure warnings.
- Now uses CMSIS startup code. Existing projects will need to add the $(TargetsDir)/LPC1000/include/CMSIS/system_LPC11xx.c, $(TargetsDir)/LPC1000/include/CMSIS/system_LPC13xx.c or $(TargetsDir)/LPC1000/include/CMSIS/system_LPC17xx.c file in order to build.
- Added LPC17xx peripheral bit-band definitions.
1.6
- Added support for LPC1763.
1.5
- Corrected the definition of the SCKLOC register in the LPC13xx header and memory map files.
- Added support for LPC1111/101, LPC1112/101, LPC1113/201 and LPC1114/201 devices.
- Boot loader initialization code is now run on reset.
- Added missing LPC1100 loader startup code.
1.4
- Added support for LPC11xx devices. Please note that LPC11xx support requires CrossWorks for ARM version 2.0.5 or later.
1.3
- Corrected the definition of the UxFIFOLVL register.
- Corrected the definition of the EXTERNAL bit in the DFSR register.
- Updated LPC17xx.h CMSIS header file to latest version.
- Fixed bug in LPC1300 startup code.
1.2
- Added support for LPC13xx devices.
- Added support for latest revisions of existing LPC17xx devices.
- Added support for LPC1759, LPC1767 and LPC1769.
- Corrected memory maps for LPC17xx devices with 32K of SRAM.
- The vector table offset register is now always configured to allow the start address of FLASH configuration programs to be moved away from 0x00000000 without modification of startup code.
1.1
- Startup code now configures CCLK to 100MHz with a 4MHz main clock.
- Startup code now configures CCLK to 100MHz rather than 72MHz with a 12MHz main clock.
1.0
- Initial Release.
Documentation
Known Problems
Flash download to devices with 1KB of SRAM (LPC810, LPC1110) is only supported with CrossWorks version 3 or later.
Using Micro Trace Buffer
To use the Micro Trace Buffer (MTB) on LPC8xx devices:
- Set the Target Trace Options > Trace Interface Type project property to MTB.
- Set the Target Trace Options > MTB RAM Address and Target Trace Options > MTB RAM Size project properties so that they describe an area in internal SRAM to store the MTB. The MTB address should be aligned to the size. The MTB can't be located in an area of RAM used by the program, you could ensure this by modifying the RAM segment description in the memory map file.
- Click Debug > Other Windows > Execution Trace to view the execution trace window.