NXP LPC3200 CPU Support Package

This package contains project templates and system files for the NXP LPC3200.

CrossWorks Version 4 Installation Instructions

This package can only be installed if you have the following CrossWorks license bolt-ons:

• ARM License

To install this support package

1. Click the Tools > Package Manager menu option to open the package manager window.
2. Right click on the NXP LPC3200 CPU Support Package entry and select Install Selected Packages.
3. Click Next to take you to the summary page.
4. Click Next to install the package.
5. Click Finish to close the package manager window.
6. Click the Tools > Show Installed Packages.
7. Click on the NXP LPC3200 CPU Support Package link to view the package and its contents.

To manually install this support package

1. If you have not done so already, follow the CrossWorks Tasking Library Package installation instructions.
2. Download the file LPC3200.hzq using your web browser.
3. Click the Tools > Manually Install Packages menu option.
4. Select the file you have just downloaded to install the package.
5. Click the Tools > Show Installed Packages.
6. Click on the NXP LPC3200 CPU Support Package link to view the package and its contents.

To install this support package using other versions

• CrossWorks Version 2 Installation Instructions
• CrossWorks Version 3 Installation Instructions

Release Notes

2.4

• Fixed HCLKPLL_CTRL bitfield sizes in memory map and header files.

2.3

• Added samples.
• Changed default debug handler for new projects to be None and added a coprocessor execute address property to enable VFP registers to be viewed.
• Added OnConnect function to target script to enable ETM usage.
• Changed default access to None for read-sensitive UART registers.

2.2

• Changed section placement files to support ARM EABI C++ exception scheme and thread local storage.
• Corrected address of P0_INTR_ER in memory map and header files.

2.1

• Added (optional) support for saving VFP state on interrupt.
• MMU TLB is now placed at the end of IRAM. The secondary boot loader executes at the end of IRAM hence allowing IRAM programs to be booted from NAND. The section placement files use a macro defined in the Target property group to determine the size of IRAM and as such you will need to reselect the Target if you have an existing project.

2.0

• Initial Release.

Documentation

Creating LPC3200 Projects

To create a new LPC3200 project

• Select the File > New > New Project menu item.
• Select the required Generic LPC32x0 from the Project Type list.
• Select the required project template type from the Templates list.
• Set the required project name and location directory.
• Click OK.

This will create a project that will run in the internal RAM (IRAM) of an LPC3200 board running from the main oscillator.

To build and debug an application

• Select the project to work on by using the Project > Set Active Project menu option.
• Select the configuration you require by using the Build > Set Active Build Configuration menu option.
• Build the project by using the Build > Build Project menu option.
• Connect to the appropriate target in the target window.
• Download and start debugging the current project by using Debug > Start Debugging.

LPC3200 Project Specifics

Target Processor

Once a project has been created you can select different target processors from the selected set by right clicking on the project node in the project explorer and selecting the Target Processor entry.

Selecting the target processor will specify the memory map that is used for the build and debug. You can view the selected memory map by right clicking on the project node in the project explorer and selecting View Memory Map or View Memory Map (as text). In the memory map files the memory segments defining the names, sizes and access types of the external memories are specified using macros which can be set using the Memory Map Macros project property.

Section Placement

CrossStudio for ARM supports LPC3200 projects running applications in a number of different memory configurations. You can select the memory configuration you require by right clicking on the project node in the project explorer and selecting the Placement entry.

For LPC3200 projects the set of placements are:

• IRAM application runs in internal SRAM.
• SDRAM application runs in SDRAM.
• NOR FLASH (XIP) application runs in NOR Flash with data in IRAM.
• NOR FLASH (copy to SDRAM) boot from NOR Flash and runs in SDRAM with data in IRAM.

Debug Handler

When you create a LPC3200 project a file is included in the build that implements additional (to JTAG) debug functionality. This file is used to:

• implement monitor mode debug. This enables interrupts to occur when stopped on a breakpoint and memory to be examined without stopping the processor.
• implement virtual to physical address translation in systems that change the memory map.
• invalidate the icache on writes to cacheable memory to enable software breakpoints to be set.
• implement access to coprocessor registers.

The project setup code creates a debug project property Debug Handler that enables you to choose additional (to JTAG) debug capabilities you require:

• None don't use the debug handler for breakpoints.
• Halt Mode use the debug handler but don't allow interrupts to execute on breakpoint.
• Monitor Mode Memory same as halt mode but memory access is done using the debug handler. To use this your application will have to periodically call the function dbg_poll()
• Monitor Mode full monitor mode debug.

Target Startup Code

The startup code LPC3200_Startup.s is common to all LPC3200 processors there are a set of preprocessor defines that configure the startup code and are documented in the startup file itself.

Target Reset Script

The reset scripts LPC3200_Target.js to stops the processor and turns off the MMU and caches in case the board has run a program.

LPC3200 NAND Flash Loader Files

The NAND flash loaders are board specific, however the files that are common to all NAND flash loaders are supplied in the LPC3200 CPU support package. The NAND flash loader works by shadowing code memory writes to the IRAM and SDRAM sections into the NAND flash. It also adds the secondary boot loader into the boot block of NAND flash.

• Loader_MemoryMap.xml the NAND flash loader memory map and placement.
• Loader_Startup.s reduced startup code for the NAND flash loader.
• mlclib.c small page MLC NAND flash functions.
• mlclib_large.c large page MLC NAND flash functions.
• nand_flash_boot_block.c the code to maintain the boot block.
• nand_flash_init.c the code to initialise the boot block.
• nand_flash_loader.c the NAND flash loader.
• sbloader.s the binary image of the secondary boot loader.
• secondary_loader.c the secondary boot loader.
• secondary_Loader_MemoryMap.xml the secondary boot loader memory map and placement.
• secondary_Loader_Startup.s reduced startup code for the secondary boot loader.

Memory Simulator

An LPC3200 memory simulator is provided that simulates the memories of the various LPC3200 devices. The memory simulation parameter (which is set by the Target Processor selection) contains macros that determine the sizes of the simulated memories and can be specified using the Memory Simulation Parameter Macros property.

Interrupt Handling

The file LPC3200.c implements the ctl_set_isr, ctl_unmask_isr and ctl_mask_isr functions by programming the MIC, SIC1 and SIC2 register groups. The number parameter to these functions is as documented in the interrupt enable registers in LPC32x0 user manual with 32 added to the SIC1 interrupts and 64 added to the SIC2 interrupts. Each interrupt handler should be assigned a unique priority number which is supplied as the priority parameter to the ctl_set_isr function. The priority determines the order in which interrupt status registers are checked, lower numbers are checked first. There is no facility to support nested interrupts i.e. re-enabling interrupts while executing an interrupt handler. By default the ARM IRQ interrupt is triggered when an interrupt occurs. However you can select to have the ARM FIQ interrupt triggered by adding the maximum number of interrupts (72) to the priority when you call ctl_set_isr.

The file LPC3200_irq_handler.s implements the irq_handler and fiq_handler exception handlers.

CTL Timer Support

The file LPC3200.c implements the ctl_start_timer function using the millisecond timer.

Header Files

Header files are generated from the memory map files and can be included using the file LPC3200.h this file also provide symbolic names for the interrupt numbers as used in ctl_set_isr. The LPC3200 project setup adds the directory $(TargetsDir)/LPC3200 to the User Include Directories project property so that you can just include targets/LPC3200.h into your source code.