Texas Instruments OMAP4 CPU Support Package
This package contains project templates and system files for the Texas Instruments OMAP4.
CrossWorks Version 1 Installation Instructions
- To install this support package
- Download the file OMAP4.hzq using your web browser.
- Click the Tools > Install Package menu option.
- Select the file you have just downloaded to install the package.
- To install this support package using other versions
- Startup code now places the mmu page table in the .mmu program section.
- Added CA9 MPCore peripherals to the registers display.
- Initial Release.
Creating OMAP4 Projects
To create a new OMAP4 project
- Select the File > New > New Project menu item.
- Select the appropriate Generic OMAP4 from the Categories list.
- Select the required project template type from the Templates list.
- Set the required project name and location directory.
- Click OK.
To build and debug an application the runs in OCM RAM
- Select the project to work on by using the Project > Set Active Project menu option.
- Select the OCM_RAM placement by clicking on the project node in the project explorer.
- Build the project by using the Build | Build Project menu option.
- Connect to the appropriate target in the target window.
- Download and start debugging the current project by using Debug > Start Debugging.
OMAP4 Project Specifics
Once a project has been created you can select different target processors from the selected set by right clicking on the project node in the project explorer and selecting the Target property.
Selecting the target processor will specify the memory map that is used for the build and debug. You can view the selected memory map by right clicking on the project node in the project explorer and selecting Edit Memory Map. In the memory map files the memory segments defining the names, sizes and access types of the external memories are specified using macros which can be set using the Memory Map Macros project property.
CrossStudio for ARM supports OMAP4 projects running applications in a number of different memory configurations. You can select the memory configuration you require by right clicking on the project node in the project explorer and selecting the Placement property.
For OMAP4 projects the set of placements are:
- application runs in internal SRAM on CPU0.
- application runs in external SDRAM on CPU0.
- application runs in internal SRAM on CPU1.
- application runs in external SDRAM on CPU1.
Note that a CPU1 project must be run as a debug dependent project of a CPU0 project.
Target Startup Code
In the startup code OMAP4_Startup.s there are a set of preprocessor defines that configure the startup code and are documented in the startup file itself.
Target Reset Script
The reset script OMAP4_Target.js resets the target using the icepick and stops it in the bootloader. You should always ensure that the board enters the bootloader after reset.
An OMAP4 memory simulator is provided that simulates the memories of the various OMAP4 devices. The memory simulation parameter (which is set by the Target Processor selection) contains macros that determine the sizes of the simulated memories and can be specified using the Memory Simulation Parameter Macros property.
The file OMAP4_ctl.c implements the ctl_set_isr, ctl_unmask_isr and ctl_mask_isr functions by programming the GIC register groups.
If the vector parameter passed to these functions is greater than or equal to 32 it corresponds to the interrupt line number plus 32 as defined in the OMAP4 reference manual. If the vector is less than 32 then it corresponds to the interrupt sources defined in the CA9 reference manual.
The priority parameter to the ctl_set_isr is the GIC priority i.e. lower numbers have higher priorities. If nested interrupts are enabled for the irq_handler then the priority is a pre-emption priority i.e. interrupt handlers can be interrupted by higher priority interrupt handlers. The startup code OMAP4_Startup.s implements the irq_handler exception handler.
The file OMAP4_ctl.c also implements the ctl_start_timer function using the CPU core private timer.