diff -rupN llvm/include/llvm/MC/MCELFStreamer.h llvm.patched/include/llvm/MC/MCELFStreamer.h --- llvm/include/llvm/MC/MCELFStreamer.h 2015-04-01 13:45:23.444727532 +0100 +++ llvm.patched/include/llvm/MC/MCELFStreamer.h 2015-04-01 13:45:34.744912906 +0100 @@ -115,7 +115,7 @@ private: MCELFStreamer *createARMELFStreamer(MCContext &Context, MCAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *Emitter, - bool RelaxAll, bool IsThumb); + bool RelaxAll, bool IsThumb, Triple::SubArchType subArch); } // end namespace llvm diff -rupN llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp llvm.patched/lib/CodeGen/TargetLoweringObjectFileImpl.cpp --- llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp 2015-04-01 13:45:24.424743611 +0100 +++ llvm.patched/lib/CodeGen/TargetLoweringObjectFileImpl.cpp 2015-04-01 13:45:35.928932329 +0100 @@ -228,14 +228,20 @@ const MCSection *TargetLoweringObjectFil /// getSectionPrefixForGlobal - Return the section prefix name used by options /// FunctionsSections and DataSections. static StringRef getSectionPrefixForGlobal(SectionKind Kind) { + static char prefixName[1024]; + extern const char *bssName, *textName, *dataName, *rodataName; if (Kind.isText()) return ".text."; if (Kind.isReadOnly()) return ".rodata."; if (Kind.isBSS()) return ".bss."; + if (Kind.isText()) { sprintf(prefixName, "%s.", textName); return prefixName; } + if (Kind.isReadOnly()) { sprintf(prefixName, "%s.", rodataName); return prefixName; } + if (Kind.isBSS()) { sprintf(prefixName, "%s.", bssName); return prefixName; } + if (Kind.isThreadData()) return ".tdata."; if (Kind.isThreadBSS()) return ".tbss."; - if (Kind.isDataNoRel()) return ".data."; + if (Kind.isDataNoRel()) { sprintf(prefixName, "%s.", dataName); return prefixName; } if (Kind.isDataRelLocal()) return ".data.rel.local."; if (Kind.isDataRel()) return ".data.rel."; if (Kind.isReadOnlyWithRelLocal()) return ".data.rel.ro.local."; diff -rupN llvm/lib/MC/MCObjectFileInfo.cpp llvm.patched/lib/MC/MCObjectFileInfo.cpp --- llvm/lib/MC/MCObjectFileInfo.cpp 2015-04-01 13:45:24.420743547 +0100 +++ llvm.patched/lib/MC/MCObjectFileInfo.cpp 2015-04-01 13:45:35.928932329 +0100 @@ -263,6 +263,11 @@ void MCObjectFileInfo::InitMachOMCObject TLSExtraDataSection = TLSTLVSection; } +const char *bssName = ".bss"; +const char *textName = ".text"; +const char *dataName = ".data"; +const char *rodataName = ".rodata"; + void MCObjectFileInfo::InitELFMCObjectFileInfo(Triple T) { switch (T.getArch()) { case Triple::mips: @@ -417,23 +422,23 @@ void MCObjectFileInfo::InitELFMCObjectFi // ELF BSSSection = - Ctx->getELFSection(".bss", ELF::SHT_NOBITS, + Ctx->getELFSection(bssName, ELF::SHT_NOBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC, SectionKind::getBSS()); TextSection = - Ctx->getELFSection(".text", ELF::SHT_PROGBITS, + Ctx->getELFSection(textName, ELF::SHT_PROGBITS, ELF::SHF_EXECINSTR | ELF::SHF_ALLOC, SectionKind::getText()); DataSection = - Ctx->getELFSection(".data", ELF::SHT_PROGBITS, + Ctx->getELFSection(dataName, ELF::SHT_PROGBITS, ELF::SHF_WRITE |ELF::SHF_ALLOC, SectionKind::getDataRel()); ReadOnlySection = - Ctx->getELFSection(".rodata", ELF::SHT_PROGBITS, + Ctx->getELFSection(rodataName, ELF::SHT_PROGBITS, ELF::SHF_ALLOC, SectionKind::getReadOnly()); diff -rupN llvm/lib/Target/ARM/ARM.td llvm.patched/lib/Target/ARM/ARM.td --- llvm/lib/Target/ARM/ARM.td 2015-04-01 13:45:24.356742497 +0100 +++ llvm.patched/lib/Target/ARM/ARM.td 2015-04-01 13:45:35.756929507 +0100 @@ -325,6 +325,10 @@ def : Processor<"mpcore", ARMV // V6M Processors. def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6MOps, FeatureNoARM, FeatureDB, FeatureMClass]>; +def : Processor<"cortex-m0plus", ARMV6Itineraries, [HasV6MOps, FeatureNoARM, + FeatureDB, FeatureMClass]>; +def : Processor<"cortex-m1", ARMV6Itineraries, [HasV6MOps, FeatureNoARM, + FeatureDB, FeatureMClass]>; // V6T2 Processors. def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops, @@ -384,6 +388,19 @@ def : ProcessorModel<"cortex-r5", Cort FeatureHasRAS, FeatureVFPOnlySP, FeatureD16, FeatureRClass]>; +// V7A Processors +def : ProcessorModel<"cortex-r4", CortexA8Model, + [ProcR5, HasV7Ops, FeatureDB, + FeatureDSPThumb2, + FeatureHasRAS, + FeatureRClass]>; + +def : ProcessorModel<"cortex-r4f", CortexA8Model, + [ProcR5, HasV7Ops, FeatureDB, + FeatureVFP3, FeatureDSPThumb2, + FeatureHasRAS, + FeatureD16, FeatureRClass]>; + // V7M Processors. def : ProcNoItin<"cortex-m3", [HasV7Ops, FeatureThumb2, FeatureNoARM, FeatureDB, diff -rupN llvm/lib/Target/ARM/MCTargetDesc/ARMArchName.def llvm.patched/lib/Target/ARM/MCTargetDesc/ARMArchName.def --- llvm/lib/Target/ARM/MCTargetDesc/ARMArchName.def 2015-04-01 13:45:24.364742627 +0100 +++ llvm.patched/lib/Target/ARM/MCTargetDesc/ARMArchName.def 2015-04-01 13:45:35.772929767 +0100 @@ -41,6 +41,7 @@ ARM_ARCH_NAME("armv7-r", ARMV7R, "7-R", ARM_ARCH_ALIAS("armv7r", ARMV7R) ARM_ARCH_NAME("armv7-m", ARMV7M, "7-M", v7) ARM_ARCH_ALIAS("armv7m", ARMV7M) +ARM_ARCH_NAME("armv7e-m", ARMV7EM, "7E-M", v7) ARM_ARCH_NAME("armv8-a", ARMV8A, "8-A", v8) ARM_ARCH_ALIAS("armv8a", ARMV8A) ARM_ARCH_NAME("iwmmxt", IWMMXT, "iwmmxt", v5TE) diff -rupN llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp llvm.patched/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp --- llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp 2015-04-01 13:45:24.364742627 +0100 +++ llvm.patched/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp 2015-04-01 13:45:35.772929767 +0100 @@ -432,9 +432,9 @@ private: size_t calculateContentSize() const; public: - ARMTargetELFStreamer(MCStreamer &S) + ARMTargetELFStreamer(MCStreamer &S, unsigned arch) : ARMTargetStreamer(S), CurrentVendor("aeabi"), FPU(ARM::INVALID_FPU), - Arch(ARM::INVALID_ARCH), EmittedArch(ARM::INVALID_ARCH), + Arch(arch), EmittedArch(ARM::INVALID_ARCH), AttributeSection(nullptr) {} }; @@ -793,6 +793,7 @@ void ARMTargetELFStreamer::emitArchDefau break; case ARM::ARMV7M: + case ARM::ARMV7EM: setAttributeItem(CPU_arch_profile, MicroControllerProfile, false); setAttributeItem(THUMB_ISA_use, AllowThumb32, false); break; @@ -1365,9 +1366,26 @@ MCStreamer *createARMNullStreamer(MCCont MCELFStreamer *createARMELFStreamer(MCContext &Context, MCAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *Emitter, - bool RelaxAll, bool IsThumb) { + bool RelaxAll, bool IsThumb, + Triple::SubArchType subArch) { ARMELFStreamer *S = new ARMELFStreamer(Context, TAB, OS, Emitter, IsThumb); - new ARMTargetELFStreamer(*S); + unsigned arch; + switch (subArch) + { + case Triple::ARMSubArch_v8: arch = ARM::ARMV8A; break; + case Triple::ARMSubArch_v7: arch = ARM::ARMV7; break; + case Triple::ARMSubArch_v7em: arch = ARM::ARMV7EM; break; + case Triple::ARMSubArch_v7m: arch = ARM::ARMV7M; break; + case Triple::ARMSubArch_v7s: arch = ARM::ARMV7M; break; + case Triple::ARMSubArch_v6: arch = ARM::ARMV6; break; + case Triple::ARMSubArch_v6m: arch = ARM::ARMV6M; break; + case Triple::ARMSubArch_v6t2: arch = ARM::ARMV6T2; break; + case Triple::ARMSubArch_v5: arch = ARM::ARMV5; break; + case Triple::ARMSubArch_v5te: arch = ARM::ARMV5TE; break; + case Triple::ARMSubArch_v4t: arch = ARM::ARMV4T; break; + default: arch = ARM::INVALID_ARCH; break; + } + new ARMTargetELFStreamer(*S, arch); // FIXME: This should eventually end up somewhere else where more // intelligent flag decisions can be made. For now we are just maintaining // the status quo for ARM and setting EF_ARM_EABI_VER5 as the default. diff -rupN llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm.patched/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp --- llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp 2015-04-01 13:45:24.364742627 +0100 +++ llvm.patched/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp 2015-04-01 13:45:35.776929833 +0100 @@ -314,7 +314,7 @@ static MCStreamer *createMCStreamer(cons return createARMWinCOFFStreamer(Ctx, MAB, *Emitter, OS); case Triple::ELF: return createARMELFStreamer(Ctx, MAB, OS, Emitter, false, - TheTriple.getArch() == Triple::thumb); + TheTriple.getArch() == Triple::thumb, TheTriple.getSubArch()); } } diff -rupN llvm/tools/clang/include/clang/Driver/CC1Options.td llvm.patched/tools/clang/include/clang/Driver/CC1Options.td --- llvm/tools/clang/include/clang/Driver/CC1Options.td 2015-04-01 13:45:23.832733899 +0100 +++ llvm.patched/tools/clang/include/clang/Driver/CC1Options.td 2015-04-01 13:45:35.416923929 +0100 @@ -600,6 +600,19 @@ def cl_denorms_are_zero : Flag<["-"], "c def fcuda_is_device : Flag<["-"], "fcuda-is-device">, HelpText<"Generate code for CUDA device">; +//===----------------------------------------------------------------------===// +// Section Naming Options +//===----------------------------------------------------------------------===// + +def mbss_EQ : Joined<["-"], "mbss=">, + HelpText<"name the .bss section">; +def mdata_EQ : Joined<["-"], "mdata=">, + HelpText<"name the .data section">; +def mrodata_EQ : Joined<["-"], "mrodata=">, + HelpText<"name the .rodata section">; +def mtext_EQ : Joined<["-"], "mtext=">, + HelpText<"name the .text section">; + } // let Flags = [CC1Option] diff -rupN llvm/tools/clang/lib/Basic/Targets.cpp llvm.patched/tools/clang/lib/Basic/Targets.cpp --- llvm/tools/clang/lib/Basic/Targets.cpp 2015-04-01 13:45:24.284741317 +0100 +++ llvm.patched/tools/clang/lib/Basic/Targets.cpp 2015-04-01 16:37:41.814765073 +0100 @@ -4002,7 +4002,7 @@ public: Features["hwdiv-arm"] = true; Features["crc"] = true; Features["crypto"] = true; - } else if (CPU == "cortex-r5" || + } else if (CPU == "cortex-r4" || CPU == "cortex-r4f" || CPU == "cortex-r5" || // Enable the hwdiv extension for all v8a AArch32 cores by // default. ArchName == "armv8a" || ArchName == "armv8" || @@ -4109,12 +4109,13 @@ public: .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A") .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", "7A") - .Cases("cortex-r4", "cortex-r5", "7R") + .Cases("cortex-r4", "cortex-r4f", "cortex-r5", "7R") .Case("swift", "7S") .Case("cyclone", "8A") .Case("cortex-m3", "7M") .Cases("cortex-m4", "cortex-m7", "7EM") .Case("cortex-m0", "6M") + .Cases("cortex-m0plus", "cortex-m1", "6M") .Cases("cortex-a53", "cortex-a57", "8A") .Default(nullptr); } @@ -4125,6 +4126,7 @@ public: "A") .Cases("cortex-a53", "cortex-a57", "A") .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m7", "M") + .Cases("cortex-m0plus", "cortex-m1", "M") .Cases("cortex-r4", "cortex-r5", "R") .Default(""); } diff -rupN llvm/tools/clang/lib/Frontend/CompilerInvocation.cpp llvm.patched/tools/clang/lib/Frontend/CompilerInvocation.cpp --- llvm/tools/clang/lib/Frontend/CompilerInvocation.cpp 2015-04-01 13:45:24.252740791 +0100 +++ llvm.patched/tools/clang/lib/Frontend/CompilerInvocation.cpp 2015-04-01 13:45:35.700928588 +0100 @@ -131,6 +131,11 @@ static void addDiagnosticArgs(ArgList &A } } +extern const char *bssName; +extern const char *textName; +extern const char *dataName; +extern const char *rodataName; + static bool ParseAnalyzerArgs(AnalyzerOptions &Opts, ArgList &Args, DiagnosticsEngine &Diags) { using namespace options; @@ -580,6 +585,18 @@ static bool ParseCodeGenArgs(CodeGenOpti bool NeedLocTracking = false; if (Arg *A = Args.getLastArg(OPT_Rpass_EQ)) { + if (Arg *A = Args.getLastArg(OPT_mbss_EQ)) { + bssName = A->getValue(); + } + if (Arg *A = Args.getLastArg(OPT_mdata_EQ)) { + dataName = A->getValue(); + } + if (Arg *A = Args.getLastArg(OPT_mrodata_EQ)) { + rodataName = A->getValue(); + } + if (Arg *A = Args.getLastArg(OPT_mtext_EQ)) { + textName = A->getValue(); + } Opts.OptimizationRemarkPattern = GenerateOptimizationRemarkRegex(Diags, Args, A); NeedLocTracking = true;