These options are defined for Nvidia PTX:
Ignored, but preserved for backward compatibility. Only 64-bit ABI is supported.
Generate code for the specified PTX ISA target architecture (e.g. sm_35). Valid architecture strings are sm_30, sm_35, sm_53, sm_70, sm_75 and sm_80. The default target architecture is sm_30.
This option sets the value of the preprocessor macro
__PTX_SM__; for instance, for sm_35, it has the value 350.
Alias of -march=.
Select the closest available -march= value that is not more capable. For instance, for -march-map=sm_50 select -march=sm_35, and for -march-map=sm_53 select -march=sm_53.
Generate code for the specified PTX ISA version (e.g. 7.0). Valid version strings include 3.1, 6.0, 6.3, and 7.0. The default PTX ISA version is 6.0, unless a higher version is required for specified PTX ISA target architecture via option -march=.
This option sets the values of the preprocessor macros
__PTX_ISA_VERSION_MINOR__; for instance, for 3.1 the macros have the values 3 and 1, respectively.
Link in code for a __main kernel. This is for stand-alone instead of offloading execution.
Apply partitioned execution optimizations. This is the default when any level of optimization is selected.
Generate code that does not use
.local memory directly for stack storage. Instead, a per-warp stack pointer is maintained explicitly. This enables variable-length stack allocation (with variable-length arrays or
alloca), and when global memory is used for underlying storage, makes it possible to access automatic variables from other threads, or with atomic instructions. This code generation variant is used for OpenMP offloading, but the option is exposed on its own for the purpose of testing the compiler; to generate code suitable for linking into programs using OpenMP offloading, use option -mgomp.
Switch to code generation variant that allows to execute all threads in each warp, while maintaining memory state and side effects as if only one thread in each warp was active outside of OpenMP SIMD regions. All atomic operations and calls to runtime (malloc, free, vprintf) are conditionally executed (iff current lane index equals the master lane index), and the register being assigned is copied via a shuffle instruction from the master lane. Outside of SIMD regions lane 0 is the master; inside, each thread sees itself as the master. Shared memory array
int __nvptx_uni stores all-zeros or all-ones bitmasks for each warp, indicating current mode (0 outside of SIMD regions). Each thread can bitwise-and the bitmask at position
tid.y with current lane index to compute the master lane index.
Generate code for use in OpenMP offloading: enables -msoft-stack and -muniform-simt options, and selects corresponding multilib variant.