Produce code for the Z80 processor. By default accepted undocumented operations with halves of index registers (
IYH) and instuction
IN F,(C). Other useful undocumented instructions produces warnings. Undocumented instructions may not work on some CPUs, use them on your own risk.
Produce code for the R800 processor.
Produce code for the Z180 processor.
Produce code for the eZ80 processor in Z80 memory mode by default.
Produce code for the eZ80 processor in ADL memory mode by default.
Mark all labels with specified prefix as local. But such label can be marked global explicitly in the code. This option do not change default local label prefix
.L, it is just adds new one.
Accept colonless labels. All names at line begin are treated as labels.
Accept assembler code produced by SDCC.
Single precision floating point numbers format. Default: ieee754 (32 bit).
Double precision floating point numbers format. Default: ieee754 (64 bit).
Accept documented instructions only.
Accept all known Z80 instructions.
Enable specified undocumented instruction(s).
Disable specified undocumented instruction(s).
Silently assemble undocumented Z80-instructions that have been adopted as documented R800-instructions .
Silently assemble all undocumented Z80-instructions.
Issue warnings for undocumented Z80-instructions that work on R800, do not assemble other undocumented instructions without warning.
Issue warnings for other undocumented Z80-instructions, do not treat any undocumented instructions as errors.
Treat all undocumented z80-instructions as errors.
Treat undocumented z80-instructions that do not work on R800 as errors.
Floating point numbers formats.
Single or double precision IEEE754 compatible format.
Half precision IEEE754 compatible format (16 bits).
Single precision IEEE754 compatible format (32 bits).
Double precision IEEE754 compatible format (64 bits).
32 bit floating point format from z80float library by Zeda.
48 bit floating point format from Math48 package by Anders Hejlsberg.
Known undocumented instructions.
All operations with halves of index registers (
SLL instruction. Same as
SLA r; INC r.
<op> (<ii>+<d>),<r>. For example: