The following table lists all available RISC-V specific directives.
Align to the given boundary, with the size given as log2 the number of bytes to align to.
Emits a half-word, word, or double-word value at the current position.
Emits a DTP-relative word (or double-word) at the current position. This is meant to be used by the compiler in shared libraries for DWARF debug info for thread local variables.
Sets the current section to the BSS section.
Emits a signed or unsigned LEB128 value at the current position. This only accepts constant expressions, because symbol addresses can change with relaxation, and we dont support relocations to modify LEB128 values at link time.
Modifies RISC-V specific assembler options inline with the assembly code. This is used when particular instruction sequences must be assembled with a specific set of options. For example, since we relax addressing sequences to shorter GP-relative sequences when possible the initial load of GP must not be relaxed and should be emitted as something like
.option push .option norelax la gp, __global_pointer$ .option pop
in order to produce after linker relaxation the expected
auipc gp, %pcrel_hi(__global_pointer$) addi gp, gp, %pcrel_lo(__global_pointer$)
instead of just
addi gp, gp, 0
Its not expected that options are changed in this manner during regular use, but there are a handful of esoteric cases like the one above where users need to disable particular features of the assembler for particular code sequences. The complete list of option arguments is shown below:
Pushes or pops the current option stack. These should be used whenever changing an option in line with assembly code in order to ensure the users command-line options are respected for the bulk of the file being assembled.
Enables or disables the generation of compressed instructions. Instructions are opportunistically compressed by the RISC-V assembler when possible, but sometimes this behavior is not desirable, especially when handling alignments.
Enables or disables position-independent code generation. Unless you really know what youre doing, this should only be at the top of a file.
Enables or disables relaxation. The RISC-V assembler and linker opportunistically relax some code sequences, but sometimes this behavior is not desirable.
Enables or disables the CSR checking.
arch, +extension[version] [,...,+extension_n[version_n]]
arch, -extension [,...,-extension_n]
Enables or disables the extensions for specific code region. For example, .option arch, +m2p0 means add m extension with version 2.0, and .option arch, -f, -d means remove extensions, f and d, from the architecture string. Note that, .option arch, +c, -c have the same behavior as .option rvc, norvc. However, they are also undesirable sometimes. Besides, .option arch, -i is illegal, since we cannot remove the base i extension anytime. If you want to reset the whole ISA string, you can also use .option arch, =rv32imac to overwrite the previous settings.
.insn type, operand [,...,operand_n]
.insn insn_length, value
This directive permits the numeric representation of an instructions and makes the assembler insert the operands according to one of the instruction formats for .insn (RISC-V-Formats). For example, the instruction add a0, a1, a2 could be written as .insn r 0x33, 0, 0, a0, a1, a2. But in fact, the instruction formats are difficult to use for some users, so most of them are using .word to encode the instruction directly, rather than using .insn. It is fine for now, but will be wrong when the mapping symbols are supported, since .word will not be shown as an instruction, it should be shown as data. Therefore, we also support two more formats of the .insn, the instruction add a0, a1, a2 could also be written as .insn 0x4, 0xc58533 or .insn 0xc58533. When the insn_length is set, then assembler will check if the value is a valid insn_length bytes instruction.
.attribute tag, value
Set the object attribute tag to value.
The tag is either an attribute number, or one of the following: