The ARM Simulator target interface provides access to CrossStudio's ARM instruction set simulator (ISS). The ISS simulates the ARM V4T, ARM V5TE, ARM V6-M and ARM V7-M instruction sets as defined in approrpriate ARM Architecure Reference Manuals. The ARM architecture, core type and memory endian to be simulated are specified by the projects' the code generation properties..

The ISS supports MCR and MRC access to the 16 primary registers of the System Control coprocessor (CP15) as defined in the ARM Architecture Reference Manual. The MMU is simulated but the cache isn't. The ISS supports MCR and MRC access to the Debug Communication Channel (CP14) as defined in the ARM7TDMI Technical Reference Manual. The ISS supports a limited subset of VFP instructions (CP10 and CP11) that enable C programs that use the VFP to execute.

The ISS implements a 3 word instruction pre-fetch buffer.

The memory system simulated by the ISS is implemented by the dynamic link library and associated parameter defined in the projects' simulator properties..

The ISS supports program loading and debugging with an unlimited number of breakpoints. The ISS supports instruction tracing, execution counts, exception vector trapping and exception vector triggering.