This documentation was generated automatically from the AVR Studio part description file AT90USB647.pdf
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sfrb WDTCSR = $60;
#define WDP0_BIT 0
#define WDP0_MASK 1
#define WDP1_BIT 1
#define WDP1_MASK 2
#define WDP2_BIT 2
#define WDP2_MASK 4
#define WDE_BIT 3
#define WDE_MASK 8
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog
#define WDCE_BIT 4
#define WDCE_MASK 16
#define WDP3_BIT 5
#define WDP3_MASK 32
#define WDIE_BIT 6
#define WDIE_MASK 64
#define WDIF_BIT 7
#define WDIF_MASK 128
sfrb PORTA = $02;
#define PORTA0_BIT 0
#define PORTA0_MASK 1
#define PORTA1_BIT 1
#define PORTA1_MASK 2
#define PORTA2_BIT 2
#define PORTA2_MASK 4
#define PORTA3_BIT 3
#define PORTA3_MASK 8
#define PORTA4_BIT 4
#define PORTA4_MASK 16
#define PORTA5_BIT 5
#define PORTA5_MASK 32
#define PORTA6_BIT 6
#define PORTA6_MASK 64
#define PORTA7_BIT 7
#define PORTA7_MASK 128
sfrb DDRA = $01;
#define DDA0_BIT 0
#define DDA0_MASK 1
#define DDA1_BIT 1
#define DDA1_MASK 2
#define DDA2_BIT 2
#define DDA2_MASK 4
#define DDA3_BIT 3
#define DDA3_MASK 8
#define DDA4_BIT 4
#define DDA4_MASK 16
#define DDA5_BIT 5
#define DDA5_MASK 32
#define DDA6_BIT 6
#define DDA6_MASK 64
#define DDA7_BIT 7
#define DDA7_MASK 128
sfrb PINA = $00;
#define PINA0_BIT 0
#define PINA0_MASK 1
#define PINA1_BIT 1
#define PINA1_MASK 2
#define PINA2_BIT 2
#define PINA2_MASK 4
#define PINA3_BIT 3
#define PINA3_MASK 8
#define PINA4_BIT 4
#define PINA4_MASK 16
#define PINA5_BIT 5
#define PINA5_MASK 32
#define PINA6_BIT 6
#define PINA6_MASK 64
#define PINA7_BIT 7
#define PINA7_MASK 128
sfrb PORTB = $05;
#define PORTB0_BIT 0
#define PORTB0_MASK 1
#define PORTB1_BIT 1
#define PORTB1_MASK 2
#define PORTB2_BIT 2
#define PORTB2_MASK 4
#define PORTB3_BIT 3
#define PORTB3_MASK 8
#define PORTB4_BIT 4
#define PORTB4_MASK 16
#define PORTB5_BIT 5
#define PORTB5_MASK 32
#define PORTB6_BIT 6
#define PORTB6_MASK 64
#define PORTB7_BIT 7
#define PORTB7_MASK 128
sfrb DDRB = $04;
#define DDB0_BIT 0
#define DDB0_MASK 1
#define DDB1_BIT 1
#define DDB1_MASK 2
#define DDB2_BIT 2
#define DDB2_MASK 4
#define DDB3_BIT 3
#define DDB3_MASK 8
#define DDB4_BIT 4
#define DDB4_MASK 16
#define DDB5_BIT 5
#define DDB5_MASK 32
#define DDB6_BIT 6
#define DDB6_MASK 64
#define DDB7_BIT 7
#define DDB7_MASK 128
sfrb PINB = $03;
#define PINB0_BIT 0
#define PINB0_MASK 1
#define PINB1_BIT 1
#define PINB1_MASK 2
#define PINB2_BIT 2
#define PINB2_MASK 4
#define PINB3_BIT 3
#define PINB3_MASK 8
#define PINB4_BIT 4
#define PINB4_MASK 16
#define PINB5_BIT 5
#define PINB5_MASK 32
#define PINB6_BIT 6
#define PINB6_MASK 64
#define PINB7_BIT 7
#define PINB7_MASK 128
sfrb PORTC = $08;
#define PORTC0_BIT 0
#define PORTC0_MASK 1
#define PORTC1_BIT 1
#define PORTC1_MASK 2
#define PORTC2_BIT 2
#define PORTC2_MASK 4
#define PORTC3_BIT 3
#define PORTC3_MASK 8
#define PORTC4_BIT 4
#define PORTC4_MASK 16
#define PORTC5_BIT 5
#define PORTC5_MASK 32
#define PORTC6_BIT 6
#define PORTC6_MASK 64
#define PORTC7_BIT 7
#define PORTC7_MASK 128
sfrb DDRC = $07;
#define DDC0_BIT 0
#define DDC0_MASK 1
#define DDC1_BIT 1
#define DDC1_MASK 2
#define DDC2_BIT 2
#define DDC2_MASK 4
#define DDC3_BIT 3
#define DDC3_MASK 8
#define DDC4_BIT 4
#define DDC4_MASK 16
#define DDC5_BIT 5
#define DDC5_MASK 32
#define DDC6_BIT 6
#define DDC6_MASK 64
#define DDC7_BIT 7
#define DDC7_MASK 128
sfrb PINC = $06;
#define PINC0_BIT 0
#define PINC0_MASK 1
#define PINC1_BIT 1
#define PINC1_MASK 2
#define PINC2_BIT 2
#define PINC2_MASK 4
#define PINC3_BIT 3
#define PINC3_MASK 8
#define PINC4_BIT 4
#define PINC4_MASK 16
#define PINC5_BIT 5
#define PINC5_MASK 32
#define PINC6_BIT 6
#define PINC6_MASK 64
#define PINC7_BIT 7
#define PINC7_MASK 128
sfrb PORTD = $0B;
#define PORTD0_BIT 0
#define PORTD0_MASK 1
#define PORTD1_BIT 1
#define PORTD1_MASK 2
#define PORTD2_BIT 2
#define PORTD2_MASK 4
#define PORTD3_BIT 3
#define PORTD3_MASK 8
#define PORTD4_BIT 4
#define PORTD4_MASK 16
#define PORTD5_BIT 5
#define PORTD5_MASK 32
#define PORTD6_BIT 6
#define PORTD6_MASK 64
#define PORTD7_BIT 7
#define PORTD7_MASK 128
sfrb DDRD = $0A;
#define DDD0_BIT 0
#define DDD0_MASK 1
#define DDD1_BIT 1
#define DDD1_MASK 2
#define DDD2_BIT 2
#define DDD2_MASK 4
#define DDD3_BIT 3
#define DDD3_MASK 8
#define DDD4_BIT 4
#define DDD4_MASK 16
#define DDD5_BIT 5
#define DDD5_MASK 32
#define DDD6_BIT 6
#define DDD6_MASK 64
#define DDD7_BIT 7
#define DDD7_MASK 128
sfrb PIND = $09;
#define PIND0_BIT 0
#define PIND0_MASK 1
#define PIND1_BIT 1
#define PIND1_MASK 2
#define PIND2_BIT 2
#define PIND2_MASK 4
#define PIND3_BIT 3
#define PIND3_MASK 8
#define PIND4_BIT 4
#define PIND4_MASK 16
#define PIND5_BIT 5
#define PIND5_MASK 32
#define PIND6_BIT 6
#define PIND6_MASK 64
#define PIND7_BIT 7
#define PIND7_MASK 128
sfrb PORTE = $0E;
#define PORTE0_BIT 0
#define PORTE0_MASK 1
#define PORTE1_BIT 1
#define PORTE1_MASK 2
#define PORTE2_BIT 2
#define PORTE2_MASK 4
#define PORTE3_BIT 3
#define PORTE3_MASK 8
#define PORTE4_BIT 4
#define PORTE4_MASK 16
#define PORTE5_BIT 5
#define PORTE5_MASK 32
#define PORTE6_BIT 6
#define PORTE6_MASK 64
#define PORTE7_BIT 7
#define PORTE7_MASK 128
sfrb DDRE = $0D;
#define DDE0_BIT 0
#define DDE0_MASK 1
#define DDE1_BIT 1
#define DDE1_MASK 2
#define DDE2_BIT 2
#define DDE2_MASK 4
#define DDE3_BIT 3
#define DDE3_MASK 8
#define DDE4_BIT 4
#define DDE4_MASK 16
#define DDE5_BIT 5
#define DDE5_MASK 32
#define DDE6_BIT 6
#define DDE6_MASK 64
#define DDE7_BIT 7
#define DDE7_MASK 128
sfrb PINE = $0C;
#define PINE0_BIT 0
#define PINE0_MASK 1
#define PINE1_BIT 1
#define PINE1_MASK 2
#define PINE2_BIT 2
#define PINE2_MASK 4
#define PINE3_BIT 3
#define PINE3_MASK 8
#define PINE4_BIT 4
#define PINE4_MASK 16
#define PINE5_BIT 5
#define PINE5_MASK 32
#define PINE6_BIT 6
#define PINE6_MASK 64
#define PINE7_BIT 7
#define PINE7_MASK 128
sfrb PORTF = $11;
#define PORTF0_BIT 0
#define PORTF0_MASK 1
#define PORTF1_BIT 1
#define PORTF1_MASK 2
#define PORTF2_BIT 2
#define PORTF2_MASK 4
#define PORTF3_BIT 3
#define PORTF3_MASK 8
#define PORTF4_BIT 4
#define PORTF4_MASK 16
#define PORTF5_BIT 5
#define PORTF5_MASK 32
#define PORTF6_BIT 6
#define PORTF6_MASK 64
#define PORTF7_BIT 7
#define PORTF7_MASK 128
sfrb DDRF = $10;
#define DDF0_BIT 0
#define DDF0_MASK 1
#define DDF1_BIT 1
#define DDF1_MASK 2
#define DDF2_BIT 2
#define DDF2_MASK 4
#define DDF3_BIT 3
#define DDF3_MASK 8
#define DDF4_BIT 4
#define DDF4_MASK 16
#define DDF5_BIT 5
#define DDF5_MASK 32
#define DDF6_BIT 6
#define DDF6_MASK 64
#define DDF7_BIT 7
#define DDF7_MASK 128
sfrb PINF = $0F;
#define PINF0_BIT 0
#define PINF0_MASK 1
#define PINF1_BIT 1
#define PINF1_MASK 2
#define PINF2_BIT 2
#define PINF2_MASK 4
#define PINF3_BIT 3
#define PINF3_MASK 8
#define PINF4_BIT 4
#define PINF4_MASK 16
#define PINF5_BIT 5
#define PINF5_MASK 32
#define PINF6_BIT 6
#define PINF6_MASK 64
#define PINF7_BIT 7
#define PINF7_MASK 128
sfrb SREG = $3F;
sfrb SPH = $3E;
#define SP8_BIT 0
#define SP8_MASK 1
#define SP9_BIT 1
#define SP9_MASK 2
#define SP10_BIT 2
#define SP10_MASK 4
#define SP11_BIT 3
#define SP11_MASK 8
#define SP12_BIT 4
#define SP12_MASK 16
#define SP13_BIT 5
#define SP13_MASK 32
#define SP14_BIT 6
#define SP14_MASK 64
#define SP15_BIT 7
#define SP15_MASK 128
sfrb SPL = $3D;
#define SP0_BIT 0
#define SP0_MASK 1
#define SP1_BIT 1
#define SP1_MASK 2
#define SP2_BIT 2
#define SP2_MASK 4
#define SP3_BIT 3
#define SP3_MASK 8
#define SP4_BIT 4
#define SP4_MASK 16
#define SP5_BIT 5
#define SP5_MASK 32
#define SP6_BIT 6
#define SP6_MASK 64
#define SP7_BIT 7
#define SP7_MASK 128
sfrb MCUCR = $35;
#define IVCE_BIT 0
#define IVCE_MASK 1
The IVCE bit must be written to logic one to enable change of the IVSEL bit.IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.Setting the IVCE bit will disable interrupts.
#define IVSEL_BIT 1
#define IVSEL_MASK 2
When the IVSEL bit is cleared (zero),the interrupt vectors are placed at the start of the Flash memory.When this bit is set (one),the interrupt vectors are moved to the beginning of the Boot Loader section of the flash.The actual address of the start of the boot flash section is determined by the BOOTSZ fuses.
#define PUD_BIT 4
#define PUD_MASK 16
When this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn,PORTxn}=0b01).
#define JTD_BIT 7
#define JTD_MASK 128
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed.
sfrb MCUSR = $34;
#define PORF_BIT 0
#define PORF_MASK 1
This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.
#define EXTRF_BIT 1
#define EXTRF_MASK 2
This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
#define BORF_BIT 2
#define BORF_MASK 4
This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
#define WDRF_BIT 3
#define WDRF_MASK 8
This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
#define JTRF_BIT 4
#define JTRF_MASK 16
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on reset, or by writing a logic zero to the flag. ? Bit 3 - WDRF: Watchdog Reset Flag
sfrb XMCRA = $74;
#define SRW00_BIT 0
#define SRW00_MASK 1
#define SRW01_BIT 1
#define SRW01_MASK 2
#define SRW10_BIT 2
#define SRW10_MASK 4
#define SRW11_BIT 3
#define SRW11_MASK 8
#define SRL0_BIT 4
#define SRL0_MASK 16
It is possible to configure different wait-states for different external memory addresses.
#define SRL1_BIT 5
#define SRL1_MASK 32
It is possible to configure different wait-states for different external memory addresses.
#define SRL2_BIT 6
#define SRL2_MASK 64
It is possible to configure different wait-states for different external memory addresses.
#define SRE_BIT 7
#define SRE_MASK 128
Writing SRE to one enables the External Memory Interface.
sfrb XMCRB = $75;
#define XMM0_BIT 0
#define XMM0_MASK 1
Port C pins released.
#define XMM1_BIT 1
#define XMM1_MASK 2
Port C pins released.
#define XMM2_BIT 2
#define XMM2_MASK 4
Port C pins released.
#define XMBK_BIT 7
#define XMBK_MASK 128
Port C pins release command.
sfrb OSCCAL = $66;
#define CAL0_BIT 0
#define CAL0_MASK 1
#define CAL1_BIT 1
#define CAL1_MASK 2
#define CAL2_BIT 2
#define CAL2_MASK 4
#define CAL3_BIT 3
#define CAL3_MASK 8
#define CAL4_BIT 4
#define CAL4_MASK 16
#define CAL5_BIT 5
#define CAL5_MASK 32
#define CAL6_BIT 6
#define CAL6_MASK 64
#define CAL7_BIT 7
#define CAL7_MASK 128
sfrb CLKPR = $61;
#define CLKPS0_BIT 0
#define CLKPS0_MASK 1
#define CLKPS1_BIT 1
#define CLKPS1_MASK 2
#define CLKPS2_BIT 2
#define CLKPS2_MASK 4
#define CLKPS3_BIT 3
#define CLKPS3_MASK 8
#define CLKPCE_BIT 7
#define CLKPCE_MASK 128
sfrb SMCR = $33;
#define SE_BIT 0
#define SE_MASK 1
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.To
#define SM0_BIT 1
#define SM0_MASK 2
These bits select between the five available sleep modes.
#define SM1_BIT 2
#define SM1_MASK 4
These bits select between the five available sleep modes.
#define SM2_BIT 3
#define SM2_MASK 8
These bits select between the five available sleep modes.
sfrb EIND = $3C;
#define EIND0_BIT 0
#define EIND0_MASK 1
For EICALL/EIJMP instructions.
sfrb RAMPZ = $3B;
#define RAMPZ0_BIT 0
#define RAMPZ0_MASK 1
The RAMPZ register is normally used to select which 64K RAM Page is accessed by the Z pointer.
sfrb GPIOR2 = $2B;
#define GPIOR20_BIT 0
#define GPIOR20_MASK 1
#define GPIOR21_BIT 1
#define GPIOR21_MASK 2
#define GPIOR22_BIT 2
#define GPIOR22_MASK 4
#define GPIOR23_BIT 3
#define GPIOR23_MASK 8
#define GPIOR24_BIT 4
#define GPIOR24_MASK 16
#define GPIOR25_BIT 5
#define GPIOR25_MASK 32
#define GPIOR26_BIT 6
#define GPIOR26_MASK 64
#define GPIOR27_BIT 7
#define GPIOR27_MASK 128
sfrb GPIOR1 = $2A;
#define GPIOR10_BIT 0
#define GPIOR10_MASK 1
#define GPIOR11_BIT 1
#define GPIOR11_MASK 2
#define GPIOR12_BIT 2
#define GPIOR12_MASK 4
#define GPIOR13_BIT 3
#define GPIOR13_MASK 8
#define GPIOR14_BIT 4
#define GPIOR14_MASK 16
#define GPIOR15_BIT 5
#define GPIOR15_MASK 32
#define GPIOR16_BIT 6
#define GPIOR16_MASK 64
#define GPIOR17_BIT 7
#define GPIOR17_MASK 128
sfrb GPIOR0 = $1E;
#define GPIOR00_BIT 0
#define GPIOR00_MASK 1
#define GPIOR01_BIT 1
#define GPIOR01_MASK 2
#define GPIOR02_BIT 2
#define GPIOR02_MASK 4
#define GPIOR03_BIT 3
#define GPIOR03_MASK 8
#define GPIOR04_BIT 4
#define GPIOR04_MASK 16
#define GPIOR05_BIT 5
#define GPIOR05_MASK 32
#define GPIOR06_BIT 6
#define GPIOR06_MASK 64
#define GPIOR07_BIT 7
#define GPIOR07_MASK 128
sfrb PRR1 = $65;
#define PRUSART1_BIT 0
#define PRUSART1_MASK 1
#define PRUSART2_BIT 1
#define PRUSART2_MASK 2
#define PRUSART3_BIT 2
#define PRUSART3_MASK 4
#define PRTIM3_BIT 3
#define PRTIM3_MASK 8
#define PRTIM4_BIT 4
#define PRTIM4_MASK 16
#define PRTIM5_BIT 5
#define PRTIM5_MASK 32
sfrb PRR0 = $64;
#define PRADC_BIT 0
#define PRADC_MASK 1
#define PRUSART0_BIT 1
#define PRUSART0_MASK 2
#define PRSPI_BIT 2
#define PRSPI_MASK 4
#define PRTIM1_BIT 3
#define PRTIM1_MASK 8
#define PRTIM0_BIT 5
#define PRTIM0_MASK 32
#define PRTIM2_BIT 6
#define PRTIM2_MASK 64
#define PRTWI_BIT 7
#define PRTWI_MASK 128
TWI: Simple yet powerful and flexible communications interface, only two bus lines needed. Both master and slave operation supported. Device can operate as transmitter or receiver. 7-bit address space allows up to 128 different slave addresses. Multi-master arbitration support Up to 400 kHz data transfer speed Slew-rate limited output drivers Noise suppression circuitry rejects spikes on bus lines Fully programmable slave address with general call support Address recognition causes wake-up when AVR is in sleep mode The Two-Wire Serial Interface (TWI) is ideally suited to typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bidirectional bus lines, one for clock (SCL) andone for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI pr
sfrb TWAMR = $BD;
#define TWAM0_BIT 1
#define TWAM0_MASK 2
#define TWAM1_BIT 2
#define TWAM1_MASK 4
#define TWAM2_BIT 3
#define TWAM2_MASK 8
#define TWAM3_BIT 4
#define TWAM3_MASK 16
#define TWAM4_BIT 5
#define TWAM4_MASK 32
#define TWAM5_BIT 6
#define TWAM5_MASK 64
#define TWAM6_BIT 7
#define TWAM6_MASK 128
sfrb TWBR = $B8;
#define TWBR0_BIT 0
#define TWBR0_MASK 1
#define TWBR1_BIT 1
#define TWBR1_MASK 2
#define TWBR2_BIT 2
#define TWBR2_MASK 4
#define TWBR3_BIT 3
#define TWBR3_MASK 8
#define TWBR4_BIT 4
#define TWBR4_MASK 16
#define TWBR5_BIT 5
#define TWBR5_MASK 32
#define TWBR6_BIT 6
#define TWBR6_MASK 64
#define TWBR7_BIT 7
#define TWBR7_MASK 128
sfrb TWCR = $BC;
#define TWIE_BIT 0
#define TWIE_MASK 1
When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT flag is high.
#define TWEN_BIT 2
#define TWEN_MASK 4
The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation.
#define TWWC_BIT 3
#define TWWC_MASK 8
The TWWC bit is set when attempting to write to the TWI Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR register when TWINT is high.
#define TWSTO_BIT 4
#define TWSTO_MASK 16
Writing the TWSTO bit to one in master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high impedance state.
#define TWSTA_BIT 5
#define TWSTA_MASK 32
The application writes the TWSTA bit to one when it desires to become a master on the 2-wire Serial Bus. The TWI hard-ware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master sta-tus. TWSTA is cleared by the TWI hardware when the START condition has been transmitted.
#define TWEA_BIT 6
#define TWEA_MASK 64
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is gener-ated on the TWI bus if the following conditions are met: 1. The device??s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in master receiver or slave receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again
#define TWINT_BIT 7
#define TWINT_MASK 128
This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag
sfrb TWSR = $B9;
#define TWPS0_BIT 0
#define TWPS0_MASK 1
Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See ??Bit Rate Generator Unit? on page 165 for calculating bit rates.
#define TWPS1_BIT 1
#define TWPS1_MASK 2
Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See ??Bit Rate Generator Unit? on page 165 for calculating bit rates.
#define TWS3_BIT 3
#define TWS3_MASK 8
Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co
#define TWS4_BIT 4
#define TWS4_MASK 16
Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co
#define TWS5_BIT 5
#define TWS5_MASK 32
Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c
#define TWS6_BIT 6
#define TWS6_MASK 64
Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co
#define TWS7_BIT 7
#define TWS7_MASK 128
Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c
sfrb TWDR = $BB;
#define TWD0_BIT 0
#define TWD0_MASK 1
#define TWD1_BIT 1
#define TWD1_MASK 2
#define TWD2_BIT 2
#define TWD2_MASK 4
#define TWD3_BIT 3
#define TWD3_MASK 8
#define TWD4_BIT 4
#define TWD4_MASK 16
#define TWD5_BIT 5
#define TWD5_MASK 32
#define TWD6_BIT 6
#define TWD6_MASK 64
#define TWD7_BIT 7
#define TWD7_MASK 128
sfrb TWAR = $BA;
#define TWGCE_BIT 0
#define TWGCE_MASK 1
#define TWA0_BIT 1
#define TWA0_MASK 2
#define TWA1_BIT 2
#define TWA1_MASK 4
#define TWA2_BIT 3
#define TWA2_MASK 8
#define TWA3_BIT 4
#define TWA3_MASK 16
#define TWA4_BIT 5
#define TWA4_MASK 32
#define TWA5_BIT 6
#define TWA5_MASK 64
#define TWA6_BIT 7
#define TWA6_MASK 128
The Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: ? Full-duplex, 3-wire Synchronous Data Transfer ? Master or Slave Operation ? LSB First or MSB First Data Transfer ? Four Programmable Bit Rates ? End of Transmission Interrupt Flag ? Write Collision Flag Protection ? Wakeup from Idle Mode (Slave Mode Only)
sfrb SPCR = $2C;
#define SPR0_BIT 0
#define SPR0_MASK 1
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.
#define SPR1_BIT 1
#define SPR1_MASK 2
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.
#define CPHA_BIT 2
#define CPHA_MASK 4
Refer to Figure 36 or Figure 37 for the functionality of this bit.
#define CPOL_BIT 3
#define CPOL_MASK 8
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.
#define MSTR_BIT 4
#define MSTR_MASK 16
This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.
#define DORD_BIT 5
#define DORD_MASK 32
When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.
#define SPE_BIT 6
#define SPE_MASK 64
When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.
#define SPIE_BIT 7
#define SPIE_MASK 128
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.
sfrb SPSR = $2D;
#define SPI2X_BIT 0
#define SPI2X_MASK 1
When this bit is written logic one the SPI speed (SCK Frequency)will be doubled when the SPI is in master mode .This means that the minimum SCK period will be 2 CPU clock periods.When the SPI is configured as Slave,the SPI is only guaranteed to work at f osc /4orlower. The SPI interface on the ATmega162 is also used for program memory and EEPROM downloading or uploading.
#define WCOL_BIT 6
#define WCOL_MASK 64
The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.
#define SPIF_BIT 7
#define SPIF_MASK 128
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).
sfrb SPDR = $2E;
#define SPDR0_BIT 0
#define SPDR0_MASK 1
#define SPDR1_BIT 1
#define SPDR1_MASK 2
#define SPDR2_BIT 2
#define SPDR2_MASK 4
#define SPDR3_BIT 3
#define SPDR3_MASK 8
#define SPDR4_BIT 4
#define SPDR4_MASK 16
#define SPDR5_BIT 5
#define SPDR5_MASK 32
#define SPDR6_BIT 6
#define SPDR6_MASK 64
#define SPDR7_BIT 7
#define SPDR7_MASK 128
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: ? Full Duplex Operation (Independent Serial Receive and Transmit Registers) ? Asynchronous or Synchronous Operation ? Master or Slave Clocked Synchronous Operation ? High Resolution Baud Rate Generator ? Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits ? Odd or Even Parity Generation and Parity Check Supported by Hardware ? Data OverRun Detection ? Framing Error Detection ? Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter ? Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete ? Multi-processor Communication Mode ? Double Speed Asynchronous Communica
sfrb UDR1 = $CE;
#define UDR1-0_BIT 0
#define UDR1-0_MASK 1
#define UDR1-1_BIT 1
#define UDR1-1_MASK 2
#define UDR1-2_BIT 2
#define UDR1-2_MASK 4
#define UDR1-3_BIT 3
#define UDR1-3_MASK 8
#define UDR1-4_BIT 4
#define UDR1-4_MASK 16
#define UDR1-5_BIT 5
#define UDR1-5_MASK 32
#define UDR1-6_BIT 6
#define UDR1-6_MASK 64
#define UDR1-7_BIT 7
#define UDR1-7_MASK 128
sfrb UCSR1A = $C8;
#define MPCM1_BIT 0
#define MPCM1_MASK 1
This bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see ??Multi-processor Communication Mode? on page 152.
#define U2X1_BIT 1
#define U2X1_MASK 2
This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.
#define UPE1_BIT 2
#define UPE1_MASK 4
This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A.
#define DOR1_BIT 3
#define DOR1_MASK 8
This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0.
#define FE1_BIT 4
#define FE1_MASK 16
This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.
#define UDRE1_BIT 5
#define UDRE1_MASK 32
This bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is re
#define TXC1_BIT 6
#define TXC1_MASK 64
This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the b
#define RXC1_BIT 7
#define RXC1_MASK 128
This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.
sfrb UCSR1B = $C9;
#define TXB81_BIT 0
#define TXB81_MASK 1
TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.
#define RXB81_BIT 1
#define RXB81_MASK 2
RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.
#define UCSZ12_BIT 2
#define UCSZ12_MASK 4
The UCSZ2 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use.
#define TXEN1_BIT 3
#define TXEN1_MASK 8
Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.
#define RXEN1_BIT 4
#define RXEN1_MASK 16
Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.
#define UDRIE1_BIT 5
#define UDRIE1_MASK 32
Writing this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.
#define TXCIE1_BIT 6
#define TXCIE1_MASK 64
Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.
#define RXCIE1_BIT 7
#define RXCIE1_MASK 128
Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.
sfrb UCSR1C = $CA;
#define UCPOL1_BIT 0
#define UCPOL1_MASK 1
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).
#define UCSZ10_BIT 1
#define UCSZ10_MASK 2
Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.
#define UCSZ11_BIT 2
#define UCSZ11_MASK 4
Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.
#define USBS1_BIT 3
#define USBS1_MASK 8
0: 1-bit. 1: 2-bit.
#define UPM10_BIT 4
#define UPM10_MASK 16
This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.
#define UPM11_BIT 5
#define UPM11_MASK 32
This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.
#define UMSEL10_BIT 6
#define UMSEL10_MASK 64
#define UMSEL11_BIT 7
#define UMSEL11_MASK 128
sfrb UBRR1H = $CD;
#define UBRR8_BIT 0
#define UBRR8_MASK 1
#define UBRR9_BIT 1
#define UBRR9_MASK 2
#define UBRR10_BIT 2
#define UBRR10_MASK 4
#define UBRR11_BIT 3
#define UBRR11_MASK 8
sfrb UBRR1L = $CC;
#define UBRR0_BIT 0
#define UBRR0_MASK 1
#define UBRR1_BIT 1
#define UBRR1_MASK 2
#define UBRR2_BIT 2
#define UBRR2_MASK 4
#define UBRR3_BIT 3
#define UBRR3_MASK 8
#define UBRR4_BIT 4
#define UBRR4_MASK 16
#define UBRR5_BIT 5
#define UBRR5_MASK 32
#define UBRR6_BIT 6
#define UBRR6_MASK 64
#define UBRR7_BIT 7
#define UBRR7_MASK 128
sfrb UEINT = $F4;
#define UEINT_0_BIT 0
#define UEINT_0_MASK 1
#define UEINT_1_BIT 1
#define UEINT_1_MASK 2
#define UEINT_2_BIT 2
#define UEINT_2_MASK 4
#define UEINT_3_BIT 3
#define UEINT_3_MASK 8
#define UEINT_4_BIT 4
#define UEINT_4_MASK 16
#define UEINT_5_BIT 5
#define UEINT_5_MASK 32
#define UEINT_6_BIT 6
#define UEINT_6_MASK 64
sfrb UEBCHX = $F3;
#define UEBCHX_0_BIT 0
#define UEBCHX_0_MASK 1
#define UEBCHX_1_BIT 1
#define UEBCHX_1_MASK 2
#define UEBCHX_2_BIT 2
#define UEBCHX_2_MASK 4
sfrb UEBCLX = $F2;
#define UEBCLX_0_BIT 0
#define UEBCLX_0_MASK 1
#define UEBCLX_1_BIT 1
#define UEBCLX_1_MASK 2
#define UEBCLX_2_BIT 2
#define UEBCLX_2_MASK 4
#define UEBCLX_3_BIT 3
#define UEBCLX_3_MASK 8
#define UEBCLX_4_BIT 4
#define UEBCLX_4_MASK 16
#define UEBCLX_5_BIT 5
#define UEBCLX_5_MASK 32
#define UEBCLX_6_BIT 6
#define UEBCLX_6_MASK 64
#define UEBCLX_7_BIT 7
#define UEBCLX_7_MASK 128
sfrb UEDATX = $F1;
#define UEDATX_0_BIT 0
#define UEDATX_0_MASK 1
#define UEDATX_1_BIT 1
#define UEDATX_1_MASK 2
#define UEDATX_2_BIT 2
#define UEDATX_2_MASK 4
#define UEDATX_3_BIT 3
#define UEDATX_3_MASK 8
#define UEDATX_4_BIT 4
#define UEDATX_4_MASK 16
#define UEDATX_5_BIT 5
#define UEDATX_5_MASK 32
#define UEDATX_6_BIT 6
#define UEDATX_6_MASK 64
#define UEDATX_7_BIT 7
#define UEDATX_7_MASK 128
sfrb UEIENX = $F0;
#define TXINE_BIT 0
#define TXINE_MASK 1
#define STALLEDE_BIT 1
#define STALLEDE_MASK 2
#define RXOUTE_BIT 2
#define RXOUTE_MASK 4
#define RXSTPE_BIT 3
#define RXSTPE_MASK 8
#define NAKOUTE_BIT 4
#define NAKOUTE_MASK 16
#define NAKINE_BIT 6
#define NAKINE_MASK 64
#define FLERRE_BIT 7
#define FLERRE_MASK 128
sfrb UESTA1X = $EF;
#define CURRBK0_BIT 0
#define CURRBK0_MASK 1
#define CURRBK1_BIT 1
#define CURRBK1_MASK 2
#define CTRLDIR_BIT 2
#define CTRLDIR_MASK 4
sfrb UESTA0X = $EE;
#define NBUSYBK0_BIT 0
#define NBUSYBK0_MASK 1
#define NBUSYBK1_BIT 1
#define NBUSYBK1_MASK 2
#define DTSEQ0_BIT 2
#define DTSEQ0_MASK 4
#define DTSEQ1_BIT 3
#define DTSEQ1_MASK 8
#define ZLPSEEN_BIT 4
#define ZLPSEEN_MASK 16
#define UNDERFI_BIT 5
#define UNDERFI_MASK 32
#define OVERFI_BIT 6
#define OVERFI_MASK 64
#define CFGOK_BIT 7
#define CFGOK_MASK 128
sfrb UECFG1X = $ED;
#define ALLOC_BIT 1
#define ALLOC_MASK 2
#define EPBK0_BIT 2
#define EPBK0_MASK 4
#define EPBK1_BIT 3
#define EPBK1_MASK 8
#define EPSIZE0_BIT 4
#define EPSIZE0_MASK 16
#define EPSIZE1_BIT 5
#define EPSIZE1_MASK 32
#define EPSIZE2_BIT 6
#define EPSIZE2_MASK 64
sfrb UECFG0X = $EC;
#define EPDIR_BIT 0
#define EPDIR_MASK 1
#define EPTYPE0_BIT 6
#define EPTYPE0_MASK 64
#define EPTYPE1_BIT 7
#define EPTYPE1_MASK 128
sfrb UECONX = $EB;
#define EPEN_BIT 0
#define EPEN_MASK 1
#define RSTDT_BIT 3
#define RSTDT_MASK 8
#define STALLRQC_BIT 4
#define STALLRQC_MASK 16
#define STALLRQ_BIT 5
#define STALLRQ_MASK 32
sfrb UERST = $EA;
#define EPRST0_BIT 0
#define EPRST0_MASK 1
#define EPRST1_BIT 1
#define EPRST1_MASK 2
#define EPRST2_BIT 2
#define EPRST2_MASK 4
#define EPRST3_BIT 3
#define EPRST3_MASK 8
#define EPRST4_BIT 4
#define EPRST4_MASK 16
#define EPRST5_BIT 5
#define EPRST5_MASK 32
#define EPRST6_BIT 6
#define EPRST6_MASK 64
sfrb UENUM = $E9;
#define UENUM_0_BIT 0
#define UENUM_0_MASK 1
#define UENUM_1_BIT 1
#define UENUM_1_MASK 2
#define UENUM_2_BIT 2
#define UENUM_2_MASK 4
sfrb UEINTX = $E8;
#define TXINI_BIT 0
#define TXINI_MASK 1
#define STALLEDI_BIT 1
#define STALLEDI_MASK 2
#define RXOUTI_BIT 2
#define RXOUTI_MASK 4
#define RXSTPI_BIT 3
#define RXSTPI_MASK 8
#define NAKOUTI_BIT 4
#define NAKOUTI_MASK 16
#define RWAL_BIT 5
#define RWAL_MASK 32
#define NAKINI_BIT 6
#define NAKINI_MASK 64
#define FIFOCON_BIT 7
#define FIFOCON_MASK 128
sfrb UDMFN = $E6;
#define FNCERR_BIT 4
#define FNCERR_MASK 16
sfrb UDFNUMH = $E5;
#define UDFNUMH_0_BIT 0
#define UDFNUMH_0_MASK 1
#define UDFNUMH_1_BIT 1
#define UDFNUMH_1_MASK 2
#define UDFNUMH_2_BIT 2
#define UDFNUMH_2_MASK 4
sfrb UDFNUML = $E4;
#define UDFNUML_0_BIT 0
#define UDFNUML_0_MASK 1
#define UDFNUML_1_BIT 1
#define UDFNUML_1_MASK 2
#define UDFNUML_2_BIT 2
#define UDFNUML_2_MASK 4
#define UDFNUML_3_BIT 3
#define UDFNUML_3_MASK 8
#define UDFNUML_4_BIT 4
#define UDFNUML_4_MASK 16
#define UDFNUML_5_BIT 5
#define UDFNUML_5_MASK 32
#define UDFNUML_6_BIT 6
#define UDFNUML_6_MASK 64
#define UDFNUML_7_BIT 7
#define UDFNUML_7_MASK 128
sfrb UDADDR = $E3;
#define UDADDR0_BIT 0
#define UDADDR0_MASK 1
#define UDADDR1_BIT 1
#define UDADDR1_MASK 2
#define UDADDR2_BIT 2
#define UDADDR2_MASK 4
#define UDADDR3_BIT 3
#define UDADDR3_MASK 8
#define UDADDR4_BIT 4
#define UDADDR4_MASK 16
#define UDADDR5_BIT 5
#define UDADDR5_MASK 32
#define UDADDR6_BIT 6
#define UDADDR6_MASK 64
#define ADDEN_BIT 7
#define ADDEN_MASK 128
sfrb UDIEN = $E2;
#define SUSPE_BIT 0
#define SUSPE_MASK 1
#define MSOFE_BIT 1
#define MSOFE_MASK 2
#define SOFE_BIT 2
#define SOFE_MASK 4
#define EORSTE_BIT 3
#define EORSTE_MASK 8
#define WAKEUPE_BIT 4
#define WAKEUPE_MASK 16
#define EORSME_BIT 5
#define EORSME_MASK 32
#define UPRSME_BIT 6
#define UPRSME_MASK 64
sfrb UDINT = $E1;
#define SUSPI_BIT 0
#define SUSPI_MASK 1
#define MSOFI_BIT 1
#define MSOFI_MASK 2
#define SOFI_BIT 2
#define SOFI_MASK 4
#define EORSTI_BIT 3
#define EORSTI_MASK 8
#define WAKEUPI_BIT 4
#define WAKEUPI_MASK 16
#define EORSMI_BIT 5
#define EORSMI_MASK 32
#define UPRSMI_BIT 6
#define UPRSMI_MASK 64
sfrb UDCON = $E0;
#define DETACH_BIT 0
#define DETACH_MASK 1
#define RMWKUP_BIT 1
#define RMWKUP_MASK 2
#define LSM_BIT 2
#define LSM_MASK 4
sfrb OTGINT = $DF;
#define SRPI_BIT 0
#define SRPI_MASK 1
#define VBERRI_BIT 1
#define VBERRI_MASK 2
#define BCERRI_BIT 2
#define BCERRI_MASK 4
#define ROLEEXI_BIT 3
#define ROLEEXI_MASK 8
#define HNPERRI_BIT 4
#define HNPERRI_MASK 16
#define STOI_BIT 5
#define STOI_MASK 32
sfrb OTGIEN = $DE;
#define SRPE_BIT 0
#define SRPE_MASK 1
#define VBERRE_BIT 1
#define VBERRE_MASK 2
#define BCERRE_BIT 2
#define BCERRE_MASK 4
#define ROLEEXE_BIT 3
#define ROLEEXE_MASK 8
#define HNPERRE_BIT 4
#define HNPERRE_MASK 16
#define STOE_BIT 5
#define STOE_MASK 32
sfrb OTGCON = $DD;
#define VBUSRQC_BIT 0
#define VBUSRQC_MASK 1
#define VBUSREQ_BIT 1
#define VBUSREQ_MASK 2
#define VBUSHWC_BIT 2
#define VBUSHWC_MASK 4
#define SRPSEL_BIT 3
#define SRPSEL_MASK 8
#define SRPREQ_BIT 4
#define SRPREQ_MASK 16
#define HNPREQ_BIT 5
#define HNPREQ_MASK 32
sfrb OTGTCON = $F9;
#define VALUE_2_0_BIT 0
#define VALUE_2_0_MASK 1
#define VALUE_2_1_BIT 1
#define VALUE_2_1_MASK 2
#define VALUE_2_BIT 2
#define VALUE_2_MASK 4
#define PAGE0_BIT 5
#define PAGE0_MASK 32
#define PAGE1_BIT 6
#define PAGE1_MASK 64
#define OTGTCON_7_BIT 7
#define OTGTCON_7_MASK 128
sfrb USBINT = $DA;
#define VBUSTI_BIT 0
#define VBUSTI_MASK 1
#define IDTI_BIT 1
#define IDTI_MASK 2
sfrb USBSTA = $D9;
#define VBUS_BIT 0
#define VBUS_MASK 1
#define ID_BIT 1
#define ID_MASK 2
#define SPEED_BIT 3
#define SPEED_MASK 8
sfrb USBCON = $D8;
#define VBUSTE_BIT 0
#define VBUSTE_MASK 1
#define IDTE_BIT 1
#define IDTE_MASK 2
#define OTGPADE_BIT 4
#define OTGPADE_MASK 16
#define FRZCLK_BIT 5
#define FRZCLK_MASK 32
#define HOST_BIT 6
#define HOST_MASK 64
#define USBE_BIT 7
#define USBE_MASK 128
sfrb UHWCON = $D7;
#define UVREGE_BIT 0
#define UVREGE_MASK 1
#define UVCONE_BIT 4
#define UVCONE_MASK 16
#define UIDE_BIT 6
#define UIDE_MASK 64
#define UIMOD_BIT 7
#define UIMOD_MASK 128
sfrb UPERRX = $F5;
#define DATATGL_BIT 0
#define DATATGL_MASK 1
#define DATAPID_BIT 1
#define DATAPID_MASK 2
#define PID_BIT 2
#define PID_MASK 4
#define TIMEOUT_BIT 3
#define TIMEOUT_MASK 8
#define CRC16_BIT 4
#define CRC16_MASK 16
#define COUNTER0_BIT 5
#define COUNTER0_MASK 32
#define COUNTER1_BIT 6
#define COUNTER1_MASK 64
sfrb UPINT = $F8;
#define PINT0_BIT 0
#define PINT0_MASK 1
#define PINT1_BIT 1
#define PINT1_MASK 2
#define PINT2_BIT 2
#define PINT2_MASK 4
#define PINT3_BIT 3
#define PINT3_MASK 8
#define PINT4_BIT 4
#define PINT4_MASK 16
RW
#define PINT5_BIT 5
#define PINT5_MASK 32
#define PINT6_BIT 6
#define PINT6_MASK 64
sfrb UPBCHX = $F7;
#define PBYCT8_BIT 0
#define PBYCT8_MASK 1
#define PBYCT9_BIT 1
#define PBYCT9_MASK 2
#define PBYCT10_BIT 2
#define PBYCT10_MASK 4
sfrb UPBCLX = $F6;
#define PBYCT0_BIT 0
#define PBYCT0_MASK 1
#define PBYCT1_BIT 1
#define PBYCT1_MASK 2
#define PBYCT2_BIT 2
#define PBYCT2_MASK 4
#define PBYCT3_BIT 3
#define PBYCT3_MASK 8
#define PBYCT4_BIT 4
#define PBYCT4_MASK 16
#define PBYCT5_BIT 5
#define PBYCT5_MASK 32
#define PBYCT6_BIT 6
#define PBYCT6_MASK 64
#define PBYCT7_BIT 7
#define PBYCT7_MASK 128
sfrb UPDATX = $AF;
#define PDAT0_BIT 0
#define PDAT0_MASK 1
#define PDAT1_BIT 1
#define PDAT1_MASK 2
#define PDAT2_BIT 2
#define PDAT2_MASK 4
#define PDAT3_BIT 3
#define PDAT3_MASK 8
#define PDAT4_BIT 4
#define PDAT4_MASK 16
#define PDAT5_BIT 5
#define PDAT5_MASK 32
#define PDAT6_BIT 6
#define PDAT6_MASK 64
#define PDAT7_BIT 7
#define PDAT7_MASK 128
sfrb UPIENX = $AE;
#define RXINE_BIT 0
#define RXINE_MASK 1
#define RXSTALLE_BIT 1
#define RXSTALLE_MASK 2
#define TXOUTE_BIT 2
#define TXOUTE_MASK 4
#define TXSTPE_BIT 3
#define TXSTPE_MASK 8
#define PERRE_BIT 4
#define PERRE_MASK 16
#define NAKEDE_BIT 6
#define NAKEDE_MASK 64
#define FLERRE_BIT 7
#define FLERRE_MASK 128
sfrb UPCFG2X = $AD;
#define UPCFG2X_0_BIT 0
#define UPCFG2X_0_MASK 1
#define UPCFG2X_1_BIT 1
#define UPCFG2X_1_MASK 2
#define UPCFG2X_2_BIT 2
#define UPCFG2X_2_MASK 4
#define UPCFG2X_3_BIT 3
#define UPCFG2X_3_MASK 8
#define UPCFG2X_4_BIT 4
#define UPCFG2X_4_MASK 16
#define UPCFG2X_5_BIT 5
#define UPCFG2X_5_MASK 32
#define UPCFG2X_6_BIT 6
#define UPCFG2X_6_MASK 64
#define UPCFG2X_7_BIT 7
#define UPCFG2X_7_MASK 128
sfrb UPSTAX = $AC;
#define NBUSYK0_BIT 0
#define NBUSYK0_MASK 1
#define NBUSYK1_BIT 1
#define NBUSYK1_MASK 2
#define DTSEQ0_BIT 2
#define DTSEQ0_MASK 4
#define DTSEQ1_BIT 3
#define DTSEQ1_MASK 8
#define UNDERFI_BIT 5
#define UNDERFI_MASK 32
#define OVERFI_BIT 6
#define OVERFI_MASK 64
#define CFGOK_BIT 7
#define CFGOK_MASK 128
sfrb UPCFG1X = $AB;
#define ALLOC_BIT 1
#define ALLOC_MASK 2
#define PBK0_BIT 2
#define PBK0_MASK 4
#define PBK1_BIT 3
#define PBK1_MASK 8
#define PSIZE0_BIT 4
#define PSIZE0_MASK 16
#define PSIZE1_BIT 5
#define PSIZE1_MASK 32
#define PSIZE2_BIT 6
#define PSIZE2_MASK 64
sfrb UPCFG0X = $AA;
#define PEPNUM0_BIT 0
#define PEPNUM0_MASK 1
#define PEPNUM1_BIT 1
#define PEPNUM1_MASK 2
#define PEPNUM2_BIT 2
#define PEPNUM2_MASK 4
#define PEPNUM3_BIT 3
#define PEPNUM3_MASK 8
#define PTOKEN0_BIT 4
#define PTOKEN0_MASK 16
#define PTOKEN1_BIT 5
#define PTOKEN1_MASK 32
#define PTYPE0_BIT 6
#define PTYPE0_MASK 64
#define PTYPE1_BIT 7
#define PTYPE1_MASK 128
sfrb UPCONX = $A9;
#define PEN_BIT 0
#define PEN_MASK 1
#define RSTDT_BIT 3
#define RSTDT_MASK 8
#define INMODE_BIT 5
#define INMODE_MASK 32
#define PFREEZE_BIT 6
#define PFREEZE_MASK 64
sfrb UPRST = $A8;
#define PRST0_BIT 0
#define PRST0_MASK 1
#define PRST1_BIT 1
#define PRST1_MASK 2
#define PRST2_BIT 2
#define PRST2_MASK 4
#define PRST3_BIT 3
#define PRST3_MASK 8
#define PRST4_BIT 4
#define PRST4_MASK 16
#define PRST5_BIT 5
#define PRST5_MASK 32
#define PRST6_BIT 6
#define PRST6_MASK 64
sfrb UPNUM = $A7;
#define PNUM0_BIT 0
#define PNUM0_MASK 1
#define PNUM1_BIT 1
#define PNUM1_MASK 2
#define PNUM2_BIT 2
#define PNUM2_MASK 4
sfrb UPINTX = $A6;
#define RXINI_BIT 0
#define RXINI_MASK 1
#define RXSTALLI_BIT 1
#define RXSTALLI_MASK 2
#define TXOUTI_BIT 2
#define TXOUTI_MASK 4
#define TXSTPI_BIT 3
#define TXSTPI_MASK 8
#define PERRI_BIT 4
#define PERRI_MASK 16
#define RWAL_BIT 5
#define RWAL_MASK 32
#define NAKEDI_BIT 6
#define NAKEDI_MASK 64
#define FIFOCON_BIT 7
#define FIFOCON_MASK 128
sfrb UPINRQX = $A5;
#define INRQ0_BIT 0
#define INRQ0_MASK 1
#define INRQ1_BIT 1
#define INRQ1_MASK 2
#define INRQ2_BIT 2
#define INRQ2_MASK 4
#define INRQ3_BIT 3
#define INRQ3_MASK 8
#define INRQ4_BIT 4
#define INRQ4_MASK 16
#define INRQ5_BIT 5
#define INRQ5_MASK 32
#define INRQ6_BIT 6
#define INRQ6_MASK 64
#define INRQ7_BIT 7
#define INRQ7_MASK 128
sfrb UHFLEN = $A4;
#define UHFLEN_0_BIT 0
#define UHFLEN_0_MASK 1
#define UHFLEN_1_BIT 1
#define UHFLEN_1_MASK 2
#define UHFLEN_2_BIT 2
#define UHFLEN_2_MASK 4
#define UHFLEN_3_BIT 3
#define UHFLEN_3_MASK 8
#define UHFLEN_4_BIT 4
#define UHFLEN_4_MASK 16
#define UHFLEN_5_BIT 5
#define UHFLEN_5_MASK 32
#define UHFLEN_6_BIT 6
#define UHFLEN_6_MASK 64
#define UHFLEN_7_BIT 7
#define UHFLEN_7_MASK 128
sfrb UHFNUMH = $A3;
#define UHFNUMH_0_BIT 0
#define UHFNUMH_0_MASK 1
#define UHFNUMH_1_BIT 1
#define UHFNUMH_1_MASK 2
#define UHFNUMH_2_BIT 2
#define UHFNUMH_2_MASK 4
sfrb UHFNUML = $A2;
#define UHFNUML_0_BIT 0
#define UHFNUML_0_MASK 1
#define UHFNUML_1_BIT 1
#define UHFNUML_1_MASK 2
#define UHFNUML_2_BIT 2
#define UHFNUML_2_MASK 4
#define UHFNUML_3_BIT 3
#define UHFNUML_3_MASK 8
#define UHFNUML_4_BIT 4
#define UHFNUML_4_MASK 16
#define UHFNUML_5_BIT 5
#define UHFNUML_5_MASK 32
#define UHFNUML_6_BIT 6
#define UHFNUML_6_MASK 64
#define UHFNUML_7_BIT 7
#define UHFNUML_7_MASK 128
sfrb UHADDR = $A1;
#define UHADDR_0_BIT 0
#define UHADDR_0_MASK 1
#define UHADDR_1_BIT 1
#define UHADDR_1_MASK 2
#define UHADDR_2_BIT 2
#define UHADDR_2_MASK 4
#define UHADDR_3_BIT 3
#define UHADDR_3_MASK 8
#define UHADDR_4_BIT 4
#define UHADDR_4_MASK 16
#define UHADDR_5_BIT 5
#define UHADDR_5_MASK 32
#define UHADDR_6_BIT 6
#define UHADDR_6_MASK 64
sfrb UHIEN = $A0;
#define DCONNE_BIT 0
#define DCONNE_MASK 1
#define DDISCE_BIT 1
#define DDISCE_MASK 2
#define RSTE_BIT 2
#define RSTE_MASK 4
#define RSMEDE_BIT 3
#define RSMEDE_MASK 8
#define RXRSME_BIT 4
#define RXRSME_MASK 16
#define HSOFE_BIT 5
#define HSOFE_MASK 32
#define HWUPE_BIT 6
#define HWUPE_MASK 64
sfrb UHINT = $9F;
#define DCONNI_BIT 0
#define DCONNI_MASK 1
#define DDISCI_BIT 1
#define DDISCI_MASK 2
#define RSTI_BIT 2
#define RSTI_MASK 4
#define RSMEDI_BIT 3
#define RSMEDI_MASK 8
#define RXRSMI_BIT 4
#define RXRSMI_MASK 16
#define HSOFI_BIT 5
#define HSOFI_MASK 32
#define UHUPI_BIT 6
#define UHUPI_MASK 64
sfrb UHCON = $9E;
#define SOFEN_BIT 0
#define SOFEN_MASK 1
#define RESET_BIT 1
#define RESET_MASK 2
#define RESUME_BIT 2
#define RESUME_MASK 4
The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppor
sfrb SPMCSR = $37;
#define SPMEN_BIT 0
#define SPMEN_MASK 1
This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than ??10001?, "01001", "00101", "00011" or "00001" in the lower five bits will have no effec
#define PGERS_BIT 1
#define PGERS_MASK 2
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.
#define PGWRT_BIT 2
#define PGWRT_MASK 4
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.
#define BLBSET_BIT 3
#define BLBSET_MASK 8
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See ??Reading the Fuse and Lock Bits from Software? on page 235 for details
#define RWWSRE_BIT 4
#define RWWSRE_MASK 16
When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lo
#define SIGRD_BIT 5
#define SIGRD_MASK 32
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read a byte from the signature row into the destination register. see ??Reading the Signature Row from Software? in the datasheet for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. This operation is reserved for future use and should not be used.
#define RWWSB_BIT 6
#define RWWSB_MASK 64
When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated.
#define SPMIE_BIT 7
#define SPMIE_MASK 128
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared.
EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See ??Preventing EEPROM Corruption? on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execute
sfrb EEARH = $22;
#define EEAR8_BIT 0
#define EEAR8_MASK 1
#define EEAR9_BIT 1
#define EEAR9_MASK 2
#define EEAR10_BIT 2
#define EEAR10_MASK 4
#define EEAR11_BIT 3
#define EEAR11_MASK 8
sfrb EEARL = $21;
#define EEAR0_BIT 0
#define EEAR0_MASK 1
#define EEAR1_BIT 1
#define EEAR1_MASK 2
#define EEAR2_BIT 2
#define EEAR2_MASK 4
#define EEAR3_BIT 3
#define EEAR3_MASK 8
#define EEAR4_BIT 4
#define EEAR4_MASK 16
#define EEAR5_BIT 5
#define EEAR5_MASK 32
#define EEAR6_BIT 6
#define EEAR6_MASK 64
#define EEAR7_BIT 7
#define EEAR7_MASK 128
sfrb EEDR = $20;
#define EEDR0_BIT 0
#define EEDR0_MASK 1
#define EEDR1_BIT 1
#define EEDR1_MASK 2
#define EEDR2_BIT 2
#define EEDR2_MASK 4
#define EEDR3_BIT 3
#define EEDR3_MASK 8
#define EEDR4_BIT 4
#define EEDR4_MASK 16
#define EEDR5_BIT 5
#define EEDR5_MASK 32
#define EEDR6_BIT 6
#define EEDR6_MASK 64
#define EEDR7_BIT 7
#define EEDR7_MASK 128
sfrb EECR = $1F;
#define EERE_BIT 0
#define EERE_MASK 1
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU
#define EEPE_BIT 1
#define EEPE_MASK 2
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See ??Boot Loader Support - Read While Write self-programming? on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed
#define EEMPE_BIT 2
#define EEMPE_MASK 4
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.
#define EERIE_BIT 3
#define EERIE_MASK 8
EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.
#define EEPM0_BIT 4
#define EEPM0_MASK 16
The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.
#define EEPM1_BIT 5
#define EEPM1_MASK 32
The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.
sfrb OCR0B = $28;
#define OCR0B_0_BIT 0
#define OCR0B_0_MASK 1
#define OCR0B_1_BIT 1
#define OCR0B_1_MASK 2
#define OCR0B_2_BIT 2
#define OCR0B_2_MASK 4
#define OCR0B_3_BIT 3
#define OCR0B_3_MASK 8
#define OCR0B_4_BIT 4
#define OCR0B_4_MASK 16
#define OCR0B_5_BIT 5
#define OCR0B_5_MASK 32
#define OCR0B_6_BIT 6
#define OCR0B_6_MASK 64
#define OCR0B_7_BIT 7
#define OCR0B_7_MASK 128
sfrb OCR0A = $27;
#define OCROA_0_BIT 0
#define OCROA_0_MASK 1
#define OCROA_1_BIT 1
#define OCROA_1_MASK 2
#define OCROA_2_BIT 2
#define OCROA_2_MASK 4
#define OCROA_3_BIT 3
#define OCROA_3_MASK 8
#define OCROA_4_BIT 4
#define OCROA_4_MASK 16
#define OCROA_5_BIT 5
#define OCROA_5_MASK 32
#define OCROA_6_BIT 6
#define OCROA_6_MASK 64
#define OCROA_7_BIT 7
#define OCROA_7_MASK 128
sfrb TCNT0 = $26;
#define TCNT0_0_BIT 0
#define TCNT0_0_MASK 1
#define TCNT0_1_BIT 1
#define TCNT0_1_MASK 2
#define TCNT0_2_BIT 2
#define TCNT0_2_MASK 4
#define TCNT0_3_BIT 3
#define TCNT0_3_MASK 8
#define TCNT0_4_BIT 4
#define TCNT0_4_MASK 16
#define TCNT0_5_BIT 5
#define TCNT0_5_MASK 32
#define TCNT0_6_BIT 6
#define TCNT0_6_MASK 64
#define TCNT0_7_BIT 7
#define TCNT0_7_MASK 128
sfrb TCCR0B = $25;
#define CS00_BIT 0
#define CS00_MASK 1
#define CS01_BIT 1
#define CS01_MASK 2
#define CS02_BIT 2
#define CS02_MASK 4
#define WGM02_BIT 3
#define WGM02_MASK 8
#define FOC0B_BIT 6
#define FOC0B_MASK 64
#define FOC0A_BIT 7
#define FOC0A_MASK 128
sfrb TCCR0A = $24;
#define WGM00_BIT 0
#define WGM00_MASK 1
#define WGM01_BIT 1
#define WGM01_MASK 2
#define COM0B0_BIT 4
#define COM0B0_MASK 16
#define COM0B1_BIT 5
#define COM0B1_MASK 32
#define COM0A0_BIT 6
#define COM0A0_MASK 64
#define COM0A1_BIT 7
#define COM0A1_MASK 128
sfrb TIMSK0 = $6E;
#define TOIE0_BIT 0
#define TOIE0_MASK 1
#define OCIE0A_BIT 1
#define OCIE0A_MASK 2
#define OCIE0B_BIT 2
#define OCIE0B_MASK 4
sfrb TIFR0 = $15;
#define TOV0_BIT 0
#define TOV0_MASK 1
#define OCF0A_BIT 1
#define OCF0A_MASK 2
#define OCF0B_BIT 2
#define OCF0B_MASK 4
sfrb GTCCR = $23;
#define PSRSYNC_BIT 0
#define PSRSYNC_MASK 1
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.
#define TSM_BIT 7
#define TSM_MASK 128
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneousl
The 8-bit Timer/Counter2 can select clock source from CK, prescaled CK, or external crystal input TOSC1. It can also be stopped as described in the section ??Timer/Counter2 Control Register - TCCR2?. The status flags (overflow and compare match) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Register TCCR2. The interrupt enable/disable settings are found in ??The Timer/Counter Interrupt Mask Register - TIMSK?. When Timer/Counter2 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. This module features a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. Timer/Counter2 can also be used as an 8-bit Pulse Width Modulator. In this mode, Timer/Counter2 and the output compare register serve as a glitch-free, stand-alone PWM with centered puls
sfrb TIMSK2 = $70;
#define TOIE2_BIT 0
#define TOIE2_MASK 1
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register ?? TIFR2.
#define OCIE2A_BIT 1
#define OCIE2A_MASK 2
When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the Timer/Counter 2 Interrupt Flag Register ?? TIFR2.
#define OCIE2B_BIT 2
#define OCIE2B_MASK 4
When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the Timer/Counter 2 Interrupt Flag Register ?? TIFR2.
sfrb TIFR2 = $17;
#define TOV2_BIT 0
#define TOV2_MASK 1
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.
#define OCF2A_BIT 1
#define OCF2A_MASK 2
The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A ?? Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed.
#define OCF2B_BIT 2
#define OCF2B_MASK 4
The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B ?? Output Compare Register2. OCF2B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 Compare match Interrupt Enable), and OCF2B are set (one), the Timer/Counter2 Compare match Interrupt is executed.
sfrb TCCR2A = $B0;
#define WGM20_BIT 0
#define WGM20_MASK 1
These bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information.
#define WGM21_BIT 1
#define WGM21_MASK 2
These bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information.
#define COM2B0_BIT 4
#define COM2B0_MASK 16
The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different functio
#define COM2B1_BIT 5
#define COM2B1_MASK 32
The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function
#define COM2A0_BIT 6
#define COM2A0_MASK 64
The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function
#define COM2A1_BIT 7
#define COM2A1_MASK 128
The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function
sfrb TCCR2B = $B1;
#define CS20_BIT 0
#define CS20_MASK 1
The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.
#define CS21_BIT 1
#define CS21_MASK 2
The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.
#define CS22_BIT 2
#define CS22_MASK 4
The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.
#define WGM22_BIT 3
#define WGM22_MASK 8
These bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information.
#define FOC2B_BIT 6
#define FOC2B_MASK 64
Writing a logical one to this bit, forces a change in the compare match output pin PD7 (OC2) according to the values already set in COM21 and COM20. If the COM21 and COM20 bits are written in the same cycle as FOC2, the new settings will not take effect until next compare match or forced output compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM21 and COM20 happens as if a Compare Match had occurred, but no interrupt is generated, and the Timer/Counter will not be cleared even if CTC2 is set. The corresponding I/O pin must be set as an output pin for the FOC2 bit to have effect on the pin. The FOC2 bit will always be read as zero. Setting the FOC2 bit has no effect in PWM mode
#define FOC2A_BIT 7
#define FOC2A_MASK 128
Writing a logical one to this bit, forces a change in the compare match output pin PD7 (OC2) according to the values already set in COM21 and COM20. If the COM21 and COM20 bits are written in the same cycle as FOC2, the new settings will not take effect until next compare match or forced output compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM21 and COM20 happens as if a Compare Match had occurred, but no interrupt is generated, and the Timer/Counter will not be cleared even if CTC2 is set. The corresponding I/O pin must be set as an output pin for the FOC2 bit to have effect on the pin. The FOC2 bit will always be read as zero. Setting the FOC2 bit has no effect in PWM mode
sfrb TCNT2 = $B2;
#define TCNT2-0_BIT 0
#define TCNT2-0_MASK 1
#define TCNT2-1_BIT 1
#define TCNT2-1_MASK 2
#define TCNT2-2_BIT 2
#define TCNT2-2_MASK 4
#define TCNT2-3_BIT 3
#define TCNT2-3_MASK 8
#define TCNT2-4_BIT 4
#define TCNT2-4_MASK 16
#define TCNT2-5_BIT 5
#define TCNT2-5_MASK 32
#define TCNT2-6_BIT 6
#define TCNT2-6_MASK 64
#define TCNT2-7_BIT 7
#define TCNT2-7_MASK 128
sfrb OCR2B = $B4;
#define OCR2-0_BIT 0
#define OCR2-0_MASK 1
#define OCR2-1_BIT 1
#define OCR2-1_MASK 2
#define OCR2-2_BIT 2
#define OCR2-2_MASK 4
#define OCR2-3_BIT 3
#define OCR2-3_MASK 8
#define OCR2-4_BIT 4
#define OCR2-4_MASK 16
#define OCR2-5_BIT 5
#define OCR2-5_MASK 32
#define OCR2-6_BIT 6
#define OCR2-6_MASK 64
#define OCR2-7_BIT 7
#define OCR2-7_MASK 128
sfrb OCR2A = $B3;
#define OCR2-0_BIT 0
#define OCR2-0_MASK 1
#define OCR2-1_BIT 1
#define OCR2-1_MASK 2
#define OCR2-2_BIT 2
#define OCR2-2_MASK 4
#define OCR2-3_BIT 3
#define OCR2-3_MASK 8
#define OCR2-4_BIT 4
#define OCR2-4_MASK 16
#define OCR2-5_BIT 5
#define OCR2-5_MASK 32
#define OCR2-6_BIT 6
#define OCR2-6_MASK 64
#define OCR2-7_BIT 7
#define OCR2-7_MASK 128
sfrb ASSR = $B6;
#define TCR2BUB_BIT 0
#define TCR2BUB_MASK 1
When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set. When TCCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new value.
#define TCR2AUB_BIT 1
#define TCR2AUB_MASK 2
When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new value.
#define OCR2BUB_BIT 2
#define OCR2BUB_MASK 4
When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value.
#define OCR2AUB_BIT 3
#define OCR2AUB_MASK 8
When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value.
#define TCN2UB_BIT 4
#define TCN2UB_MASK 16
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.
#define AS2_BIT 5
#define AS2_MASK 32
When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted.
#define EXCLK_BIT 6
#define EXCLK_MASK 64
When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero.
sfrb GTCCR = $23;
#define PSRASY_BIT 1
#define PSRASY_MASK 2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the ??Bit 7 ?? TSM: Timer/Counter Synchronization Mode? on page 107 for a description of the Timer/Counter Synchronization mode.
#define TSM_BIT 7
#define TSM_MASK 128
sfrb TCCR3A = $90;
#define WGM30_BIT 0
#define WGM30_MASK 1
Combined with the WGM33:2 bits found in the TCCR3B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.
#define WGM31_BIT 1
#define WGM31_MASK 2
Combined with the WGM33:2 bits found in the TCCR3B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.
#define COM3C0_BIT 2
#define COM3C0_MASK 4
The COM3C1 and COM3C0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.
#define COM3C1_BIT 3
#define COM3C1_MASK 8
The COM3C1 and COM3C0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.
#define COM3B0_BIT 4
#define COM3B0_MASK 16
The COM3B1 and COM3B0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.
#define COM3B1_BIT 5
#define COM3B1_MASK 32
The COM3B1 and COM3B0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.
#define COM3A0_BIT 6
#define COM3A0_MASK 64
The COM3A1 and COM3A0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.
#define COM3A1_BIT 7
#define COM3A1_MASK 128
The COM3A1 and COM3A0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.
sfrb TCCR3B = $91;
#define CS30_BIT 0
#define CS30_MASK 1
Select Prescaling Clock Source of Timer/Counter3. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.
#define CS31_BIT 1
#define CS31_MASK 2
Select Prescaling Clock Source of Timer/Counter3. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T3, falling edge. (1:1:1) = External Pin 1, rising edge.
#define CS32_BIT 2
#define CS32_MASK 4
Select Prescaling Clock Source of Timer/Counter3. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T3, falling edge. (1:1:1) = External Pin 1, rising edge.
#define WGM32_BIT 3
#define WGM32_MASK 8
Combined with the WGM33:2 bits found in the TCCR3B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.
#define WGM33_BIT 4
#define WGM33_MASK 16
Combined with the WGM33:2 bits found in the TCCR3B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.
#define ICES3_BIT 6
#define ICES3_MASK 64
While the ICES3 bit is cleared (zero), the Timer/Counter3 contents are transferred to the Input Capture Register - ICR3 - on the falling edge of the input capture pin - ICP. While the ICES3 bit is set (one), the Timer/Counter3 contents are transferred to the Input Capture Register - ICR3 - on the rising edge of the input capture pin - ICP.
#define ICNC3_BIT 7
#define ICNC3_MASK 128
When the ICNC3 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC3 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES3 bit. The actual sampling frequency is XTAL clock frequency.
sfrb TCCR3C = $92;
#define FOC3C_BIT 5
#define FOC3C_MASK 32
Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM3B1 and COM3B0.If the COM3B1 and COM3B0 bits are written in the same cycle as FOC3B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM3B1 and COM3B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC3B bit to have effect on the pin. The FOC3B bit will always be read as zero. The setting of the FOC3B bit has no effect in PWM mo
#define FOC3B_BIT 6
#define FOC3B_MASK 64
Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM3B1 and COM3B0.If the COM3B1 and COM3B0 bits are written in the same cycle as FOC3B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM3B1 and COM3B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC3B bit to have effect on the pin. The FOC3B bit will always be read as zero. The setting of the FOC3B bit has no effect in PWM mo
#define FOC3A_BIT 7
#define FOC3A_MASK 128
Writing a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM3A1 and COM3A0.If the COM3A1 and COM3A0 bits are written in the same cycle as FOC3A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM3A1 and COM3A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC3 in TCCR3B is set. The corresponding I/O pin must be set as an output pin for the FOC3A bit to have effect on the pin. The FOC3A bit will always be read as zero. The setting of the FOC3A bit has no effect in PWM m
sfrb TCNT3H = $95;
#define TCNT3H0_BIT 0
#define TCNT3H0_MASK 1
#define TCNT3H1_BIT 1
#define TCNT3H1_MASK 2
#define TCNT3H2_BIT 2
#define TCNT3H2_MASK 4
#define TCNT3H3_BIT 3
#define TCNT3H3_MASK 8
#define TCNT3H4_BIT 4
#define TCNT3H4_MASK 16
#define TCNT3H5_BIT 5
#define TCNT3H5_MASK 32
#define TCNT3H6_BIT 6
#define TCNT3H6_MASK 64
#define TCNT3H7_BIT 7
#define TCNT3H7_MASK 128
sfrb TCNT3L = $94;
#define TCNT3L0_BIT 0
#define TCNT3L0_MASK 1
#define TCNT3L1_BIT 1
#define TCNT3L1_MASK 2
#define TCNT3L2_BIT 2
#define TCNT3L2_MASK 4
#define TCNT3L3_BIT 3
#define TCNT3L3_MASK 8
#define TCNT3L4_BIT 4
#define TCNT3L4_MASK 16
#define TCNT3L5_BIT 5
#define TCNT3L5_MASK 32
#define TCNT3L6_BIT 6
#define TCNT3L6_MASK 64
#define TCNT3L7_BIT 7
#define TCNT3L7_MASK 128
sfrb OCR3AH = $99;
#define OCR3AH0_BIT 0
#define OCR3AH0_MASK 1
#define OCR3AH1_BIT 1
#define OCR3AH1_MASK 2
#define OCR3AH2_BIT 2
#define OCR3AH2_MASK 4
#define OCR3AH3_BIT 3
#define OCR3AH3_MASK 8
#define OCR3AH4_BIT 4
#define OCR3AH4_MASK 16
#define OCR3AH5_BIT 5
#define OCR3AH5_MASK 32
#define OCR3AH6_BIT 6
#define OCR3AH6_MASK 64
#define OCR3AH7_BIT 7
#define OCR3AH7_MASK 128
sfrb OCR3AL = $98;
#define OCR3AL0_BIT 0
#define OCR3AL0_MASK 1
#define OCR3AL1_BIT 1
#define OCR3AL1_MASK 2
#define OCR3AL2_BIT 2
#define OCR3AL2_MASK 4
#define OCR3AL3_BIT 3
#define OCR3AL3_MASK 8
#define OCR3AL4_BIT 4
#define OCR3AL4_MASK 16
#define OCR3AL5_BIT 5
#define OCR3AL5_MASK 32
#define OCR3AL6_BIT 6
#define OCR3AL6_MASK 64
#define OCR3AL7_BIT 7
#define OCR3AL7_MASK 128
sfrb OCR3BH = $9B;
#define OCR3BH0_BIT 0
#define OCR3BH0_MASK 1
#define OCR3BH1_BIT 1
#define OCR3BH1_MASK 2
#define OCR3BH2_BIT 2
#define OCR3BH2_MASK 4
#define OCR3BH3_BIT 3
#define OCR3BH3_MASK 8
#define OCR3BH4_BIT 4
#define OCR3BH4_MASK 16
#define OCR3BH5_BIT 5
#define OCR3BH5_MASK 32
#define OCR3BH6_BIT 6
#define OCR3BH6_MASK 64
#define OCR3BH7_BIT 7
#define OCR3BH7_MASK 128
sfrb OCR3BL = $9A;
#define OCR3BL0_BIT 0
#define OCR3BL0_MASK 1
#define OCR3BL1_BIT 1
#define OCR3BL1_MASK 2
#define OCR3BL2_BIT 2
#define OCR3BL2_MASK 4
#define OCR3BL3_BIT 3
#define OCR3BL3_MASK 8
#define OCR3BL4_BIT 4
#define OCR3BL4_MASK 16
#define OCR3BL5_BIT 5
#define OCR3BL5_MASK 32
#define OCR3BL6_BIT 6
#define OCR3BL6_MASK 64
#define OCR3BL7_BIT 7
#define OCR3BL7_MASK 128
sfrb OCR3CH = $9D;
#define OCR3CH0_BIT 0
#define OCR3CH0_MASK 1
#define OCR3CH1_BIT 1
#define OCR3CH1_MASK 2
#define OCR3CH2_BIT 2
#define OCR3CH2_MASK 4
#define OCR3CH3_BIT 3
#define OCR3CH3_MASK 8
#define OCR3CH4_BIT 4
#define OCR3CH4_MASK 16
#define OCR3CH5_BIT 5
#define OCR3CH5_MASK 32
#define OCR3CH6_BIT 6
#define OCR3CH6_MASK 64
#define OCR3CH7_BIT 7
#define OCR3CH7_MASK 128
sfrb OCR3CL = $9C;
#define OCR3CL0_BIT 0
#define OCR3CL0_MASK 1
#define OCR3CL1_BIT 1
#define OCR3CL1_MASK 2
#define OCR3CL2_BIT 2
#define OCR3CL2_MASK 4
#define OCR3CL3_BIT 3
#define OCR3CL3_MASK 8
#define OCR3CL4_BIT 4
#define OCR3CL4_MASK 16
#define OCR3CL5_BIT 5
#define OCR3CL5_MASK 32
#define OCR3CL6_BIT 6
#define OCR3CL6_MASK 64
#define OCR3CL7_BIT 7
#define OCR3CL7_MASK 128
sfrb ICR3H = $97;
#define ICR3H0_BIT 0
#define ICR3H0_MASK 1
#define ICR3H1_BIT 1
#define ICR3H1_MASK 2
#define ICR3H2_BIT 2
#define ICR3H2_MASK 4
#define ICR3H3_BIT 3
#define ICR3H3_MASK 8
#define ICR3H4_BIT 4
#define ICR3H4_MASK 16
#define ICR3H5_BIT 5
#define ICR3H5_MASK 32
#define ICR3H6_BIT 6
#define ICR3H6_MASK 64
#define ICR3H7_BIT 7
#define ICR3H7_MASK 128
sfrb ICR3L = $96;
#define ICR3L0_BIT 0
#define ICR3L0_MASK 1
#define ICR3L1_BIT 1
#define ICR3L1_MASK 2
#define ICR3L2_BIT 2
#define ICR3L2_MASK 4
#define ICR3L3_BIT 3
#define ICR3L3_MASK 8
#define ICR3L4_BIT 4
#define ICR3L4_MASK 16
#define ICR3L5_BIT 5
#define ICR3L5_MASK 32
#define ICR3L6_BIT 6
#define ICR3L6_MASK 64
#define ICR3L7_BIT 7
#define ICR3L7_MASK 128
sfrb TIMSK3 = $71;
#define TOIE3_BIT 0
#define TOIE3_MASK 1
When the TOIE3 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter3 occurs, i.e., when the TOV3 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define OCIE3A_BIT 1
#define OCIE3A_MASK 2
When the OCIE3A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter3 occurs, i.e., when the OCF3A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define OCIE3B_BIT 2
#define OCIE3B_MASK 4
When the OCIE3B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter3 occurs, i.e., when the OCF3B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define OCIE3C_BIT 3
#define OCIE3C_MASK 8
When the OCIE3C bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter3 occurs, i.e., when the OCF3B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define ICIE3_BIT 5
#define ICIE3_MASK 32
When the TICIE3 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF3 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
sfrb TIFR3 = $18;
#define TOV3_BIT 0
#define TOV3_MASK 1
The TOV3 is set (one) when an overflow occurs in Timer/Counter3. TOV3 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV3 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE3 (Timer/Counter3 Overflow Interrupt Enable), and TOV3 are set (one), the Timer/Counter3 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter3 changes counting direction at $0000.
#define OCF3A_BIT 1
#define OCF3A_MASK 2
The OCF3A bit is set (one) when compare match occurs between the Timer/Counter3 and the data in OCR3A - Output Compare Register 3A. OCF3A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF3A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE3A (Timer/Counter3 Compare match InterruptA Enable), and the OCF3A are set (one), the Timer/Counter3 Compare A match Interrupt is executed.
#define OCF3B_BIT 2
#define OCF3B_MASK 4
The OCF3B bit is set (one) when compare match occurs between the Timer/Counter3 and the data in OCR3B - Output Compare Register 3B. OCF3B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF3B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE3B (Timer/Counter3 Compare match InterruptB Enable), and the OCF3B are set (one), the Timer/Counter3 Compare B match Interrupt is executed.
#define OCF3C_BIT 3
#define OCF3C_MASK 8
The OCF3C bit is set (one) when compare match occurs between the Timer/Counter3 and the data in OCR3B - Output Compare Register 3B. OCF3B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF3B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE3B (Timer/Counter3 Compare match InterruptB Enable), and the OCF3B are set (one), the Timer/Counter3 Compare B match Interrupt is executed.
#define ICF3_BIT 5
#define ICF3_MASK 32
The ICF3 bit is set (one) to flag an input capture event, indicating that the Timer/Counter3 value has been transferred to the input capture register - ICR3. ICF3 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF3 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE3 (Timer/Counter3 Input Capture Interrupt Enable), and ICF3 are set (one), the Timer/Counter3 Capture Interrupt is executed.
sfrb TCCR1A = $80;
#define WGM10_BIT 0
#define WGM10_MASK 1
Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.
#define WGM11_BIT 1
#define WGM11_MASK 2
Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.
#define COM1C0_BIT 2
#define COM1C0_MASK 4
The COM1C1 and COM1C0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.
#define COM1C1_BIT 3
#define COM1C1_MASK 8
The COM1C1 and COM1C0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.
#define COM1B0_BIT 4
#define COM1B0_MASK 16
The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.
#define COM1B1_BIT 5
#define COM1B1_MASK 32
The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.
#define COM1A0_BIT 6
#define COM1A0_MASK 64
The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.
#define COM1A1_BIT 7
#define COM1A1_MASK 128
The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.
sfrb TCCR1B = $81;
#define CS10_BIT 0
#define CS10_MASK 1
Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.
#define CS11_BIT 1
#define CS11_MASK 2
Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.
#define CS12_BIT 2
#define CS12_MASK 4
Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.
#define WGM12_BIT 3
#define WGM12_MASK 8
Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.
#define WGM13_BIT 4
#define WGM13_MASK 16
Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.
#define ICES1_BIT 6
#define ICES1_MASK 64
While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.
#define ICNC1_BIT 7
#define ICNC1_MASK 128
When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.
sfrb TCCR1C = $82;
#define FOC1C_BIT 5
#define FOC1C_MASK 32
Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM1B1 and COM1B0.If the COM1B1 and COM1B0 bits are written in the same cycle as FOC1B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1B1 and COM1B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC1B bit to have effect on the pin. The FOC1B bit will always be read as zero. The setting of the FOC1B bit has no effect in PWM mo
#define FOC1B_BIT 6
#define FOC1B_MASK 64
Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM1B1 and COM1B0.If the COM1B1 and COM1B0 bits are written in the same cycle as FOC1B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1B1 and COM1B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC1B bit to have effect on the pin. The FOC1B bit will always be read as zero. The setting of the FOC1B bit has no effect in PWM mo
#define FOC1A_BIT 7
#define FOC1A_MASK 128
Writing a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM1A1 and COM1A0.If the COM1A1 and COM1A0 bits are written in the same cycle as FOC1A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1A1 and COM1A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC1 in TCCR1B is set. The corresponding I/O pin must be set as an output pin for the FOC1A bit to have effect on the pin. The FOC1A bit will always be read as zero. The setting of the FOC1A bit has no effect in PWM m
sfrb TCNT1H = $85;
#define TCNT1H0_BIT 0
#define TCNT1H0_MASK 1
#define TCNT1H1_BIT 1
#define TCNT1H1_MASK 2
#define TCNT1H2_BIT 2
#define TCNT1H2_MASK 4
#define TCNT1H3_BIT 3
#define TCNT1H3_MASK 8
#define TCNT1H4_BIT 4
#define TCNT1H4_MASK 16
#define TCNT1H5_BIT 5
#define TCNT1H5_MASK 32
#define TCNT1H6_BIT 6
#define TCNT1H6_MASK 64
#define TCNT1H7_BIT 7
#define TCNT1H7_MASK 128
sfrb TCNT1L = $84;
#define TCNT1L0_BIT 0
#define TCNT1L0_MASK 1
#define TCNT1L1_BIT 1
#define TCNT1L1_MASK 2
#define TCNT1L2_BIT 2
#define TCNT1L2_MASK 4
#define TCNT1L3_BIT 3
#define TCNT1L3_MASK 8
#define TCNT1L4_BIT 4
#define TCNT1L4_MASK 16
#define TCNT1L5_BIT 5
#define TCNT1L5_MASK 32
#define TCNT1L6_BIT 6
#define TCNT1L6_MASK 64
#define TCNT1L7_BIT 7
#define TCNT1L7_MASK 128
sfrb OCR1AH = $89;
#define OCR1AH0_BIT 0
#define OCR1AH0_MASK 1
#define OCR1AH1_BIT 1
#define OCR1AH1_MASK 2
#define OCR1AH2_BIT 2
#define OCR1AH2_MASK 4
#define OCR1AH3_BIT 3
#define OCR1AH3_MASK 8
#define OCR1AH4_BIT 4
#define OCR1AH4_MASK 16
#define OCR1AH5_BIT 5
#define OCR1AH5_MASK 32
#define OCR1AH6_BIT 6
#define OCR1AH6_MASK 64
#define OCR1AH7_BIT 7
#define OCR1AH7_MASK 128
sfrb OCR1AL = $88;
#define OCR1AL0_BIT 0
#define OCR1AL0_MASK 1
#define OCR1AL1_BIT 1
#define OCR1AL1_MASK 2
#define OCR1AL2_BIT 2
#define OCR1AL2_MASK 4
#define OCR1AL3_BIT 3
#define OCR1AL3_MASK 8
#define OCR1AL4_BIT 4
#define OCR1AL4_MASK 16
#define OCR1AL5_BIT 5
#define OCR1AL5_MASK 32
#define OCR1AL6_BIT 6
#define OCR1AL6_MASK 64
#define OCR1AL7_BIT 7
#define OCR1AL7_MASK 128
sfrb OCR1BH = $8B;
#define OCR1BH0_BIT 0
#define OCR1BH0_MASK 1
#define OCR1BH1_BIT 1
#define OCR1BH1_MASK 2
#define OCR1BH2_BIT 2
#define OCR1BH2_MASK 4
#define OCR1BH3_BIT 3
#define OCR1BH3_MASK 8
#define OCR1BH4_BIT 4
#define OCR1BH4_MASK 16
#define OCR1BH5_BIT 5
#define OCR1BH5_MASK 32
#define OCR1BH6_BIT 6
#define OCR1BH6_MASK 64
#define OCR1BH7_BIT 7
#define OCR1BH7_MASK 128
sfrb OCR1BL = $8A;
#define OCR1BL0_BIT 0
#define OCR1BL0_MASK 1
#define OCR1BL1_BIT 1
#define OCR1BL1_MASK 2
#define OCR1BL2_BIT 2
#define OCR1BL2_MASK 4
#define OCR1BL3_BIT 3
#define OCR1BL3_MASK 8
#define OCR1BL4_BIT 4
#define OCR1BL4_MASK 16
#define OCR1BL5_BIT 5
#define OCR1BL5_MASK 32
#define OCR1BL6_BIT 6
#define OCR1BL6_MASK 64
#define OCR1BL7_BIT 7
#define OCR1BL7_MASK 128
sfrb OCR1CH = $8D;
#define OCR1CH0_BIT 0
#define OCR1CH0_MASK 1
#define OCR1CH1_BIT 1
#define OCR1CH1_MASK 2
#define OCR1CH2_BIT 2
#define OCR1CH2_MASK 4
#define OCR1CH3_BIT 3
#define OCR1CH3_MASK 8
#define OCR1CH4_BIT 4
#define OCR1CH4_MASK 16
#define OCR1CH5_BIT 5
#define OCR1CH5_MASK 32
#define OCR1CH6_BIT 6
#define OCR1CH6_MASK 64
#define OCR1CH7_BIT 7
#define OCR1CH7_MASK 128
sfrb OCR1CL = $8C;
#define OCR1CL0_BIT 0
#define OCR1CL0_MASK 1
#define OCR1CL1_BIT 1
#define OCR1CL1_MASK 2
#define OCR1CL2_BIT 2
#define OCR1CL2_MASK 4
#define OCR1CL3_BIT 3
#define OCR1CL3_MASK 8
#define OCR1CL4_BIT 4
#define OCR1CL4_MASK 16
#define OCR1CL5_BIT 5
#define OCR1CL5_MASK 32
#define OCR1CL6_BIT 6
#define OCR1CL6_MASK 64
#define OCR1CL7_BIT 7
#define OCR1CL7_MASK 128
sfrb ICR1H = $87;
#define ICR1H0_BIT 0
#define ICR1H0_MASK 1
#define ICR1H1_BIT 1
#define ICR1H1_MASK 2
#define ICR1H2_BIT 2
#define ICR1H2_MASK 4
#define ICR1H3_BIT 3
#define ICR1H3_MASK 8
#define ICR1H4_BIT 4
#define ICR1H4_MASK 16
#define ICR1H5_BIT 5
#define ICR1H5_MASK 32
#define ICR1H6_BIT 6
#define ICR1H6_MASK 64
#define ICR1H7_BIT 7
#define ICR1H7_MASK 128
sfrb ICR1L = $86;
#define ICR1L0_BIT 0
#define ICR1L0_MASK 1
#define ICR1L1_BIT 1
#define ICR1L1_MASK 2
#define ICR1L2_BIT 2
#define ICR1L2_MASK 4
#define ICR1L3_BIT 3
#define ICR1L3_MASK 8
#define ICR1L4_BIT 4
#define ICR1L4_MASK 16
#define ICR1L5_BIT 5
#define ICR1L5_MASK 32
#define ICR1L6_BIT 6
#define ICR1L6_MASK 64
#define ICR1L7_BIT 7
#define ICR1L7_MASK 128
sfrb TIMSK1 = $6F;
#define TOIE1_BIT 0
#define TOIE1_MASK 1
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define OCIE1A_BIT 1
#define OCIE1A_MASK 2
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define OCIE1B_BIT 2
#define OCIE1B_MASK 4
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define OCIE1C_BIT 3
#define OCIE1C_MASK 8
When the OCIE1C bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define ICIE1_BIT 5
#define ICIE1_MASK 32
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
sfrb TIFR1 = $16;
#define TOV1_BIT 0
#define TOV1_MASK 1
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.
#define OCF1A_BIT 1
#define OCF1A_MASK 2
The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed.
#define OCF1B_BIT 2
#define OCF1B_MASK 4
The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.
#define OCF1C_BIT 3
#define OCF1C_MASK 8
The OCF1C bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.
#define ICF1_BIT 5
#define ICF1_MASK 32
The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.
JTAG Features: JTAG (IEEE std. 1149.1 compliant) Interface. Boundary-Scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard. Debugger Access to: ?? All Internal Peripheral Units ?? Internal and External RAM ?? The Internal Register File ??Program Counter ?? EEPROM and Flash Memories. Extensive On-Chip Debug Support for Break Conditions, Including: ??AVR Break Instruction ?? Break on Change of Program Memory Flow ??Single Step Break ??Program Memory Breakpoints on Single Address or Address Range ?? Data Memory Breakpoints on Single Address or Address Range. Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface. On-Chip Debugging Supported by AVR Stu
sfrb OCDR = $31;
#define OCDR0_BIT 0
#define OCDR0_MASK 1
#define OCDR1_BIT 1
#define OCDR1_MASK 2
#define OCDR2_BIT 2
#define OCDR2_MASK 4
#define OCDR3_BIT 3
#define OCDR3_MASK 8
#define OCDR4_BIT 4
#define OCDR4_MASK 16
#define OCDR5_BIT 5
#define OCDR5_MASK 32
#define OCDR6_BIT 6
#define OCDR6_MASK 64
#define OCDR7_BIT 7
#define OCDR7_MASK 128
sfrb MCUCR = $35;
#define JTD_BIT 7
#define JTD_MASK 128
When this bit is written to zero, the JTAG interface is enabled if the JTAGEN fuse is programmed. If this bit is written to one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface, a timed sequence must be followed: The application software must write this to the desired value twice within four cycles to change the bit.
sfrb MCUSR = $34;
#define JTRF_BIT 4
#define JTRF_MASK 16
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET.This bit is reset by a Power-on reset,or by writing a logic zero to the flag.
The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in ??Clock Systems and their Distribution? on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in ??Clock Systems and their Distribution? on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt
sfrb EICRA = $69;
#define ISC00_BIT 0
#define ISC00_MASK 1
#define ISC01_BIT 1
#define ISC01_MASK 2
#define ISC10_BIT 2
#define ISC10_MASK 4
#define ISC11_BIT 3
#define ISC11_MASK 8
#define ISC20_BIT 4
#define ISC20_MASK 16
#define ISC21_BIT 5
#define ISC21_MASK 32
#define ISC30_BIT 6
#define ISC30_MASK 64
#define ISC31_BIT 7
#define ISC31_MASK 128
sfrb EICRB = $6A;
#define ISC40_BIT 0
#define ISC40_MASK 1
#define ISC41_BIT 1
#define ISC41_MASK 2
#define ISC50_BIT 2
#define ISC50_MASK 4
#define ISC51_BIT 3
#define ISC51_MASK 8
#define ISC60_BIT 4
#define ISC60_MASK 16
#define ISC61_BIT 5
#define ISC61_MASK 32
#define ISC70_BIT 6
#define ISC70_MASK 64
#define ISC71_BIT 7
#define ISC71_MASK 128
sfrb EIMSK = $1D;
#define INT0_BIT 0
#define INT0_MASK 1
#define INT1_BIT 1
#define INT1_MASK 2
#define INT2_BIT 2
#define INT2_MASK 4
#define INT3_BIT 3
#define INT3_MASK 8
#define INT4_BIT 4
#define INT4_MASK 16
#define INT5_BIT 5
#define INT5_MASK 32
#define INT6_BIT 6
#define INT6_MASK 64
#define INT7_BIT 7
#define INT7_MASK 128
sfrb EIFR = $1C;
#define INTF0_BIT 0
#define INTF0_MASK 1
#define INTF1_BIT 1
#define INTF1_MASK 2
#define INTF2_BIT 2
#define INTF2_MASK 4
#define INTF3_BIT 3
#define INTF3_MASK 8
#define INTF4_BIT 4
#define INTF4_MASK 16
#define INTF5_BIT 5
#define INTF5_MASK 32
#define INTF6_BIT 6
#define INTF6_MASK 64
#define INTF7_BIT 7
#define INTF7_MASK 128
sfrb PCMSK0 = $6B;
#define PCINT0_BIT 0
#define PCINT0_MASK 1
#define PCINT1_BIT 1
#define PCINT1_MASK 2
#define PCINT2_BIT 2
#define PCINT2_MASK 4
#define PCINT3_BIT 3
#define PCINT3_MASK 8
#define PCINT4_BIT 4
#define PCINT4_MASK 16
#define PCINT5_BIT 5
#define PCINT5_MASK 32
#define PCINT6_BIT 6
#define PCINT6_MASK 64
#define PCINT7_BIT 7
#define PCINT7_MASK 128
sfrb PCIFR = $1B;
#define PCIF0_BIT 0
#define PCIF0_MASK 1
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
#define PCIF1_BIT 1
#define PCIF1_MASK 2
When a logic change on any PCINT14..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
#define PCIF2_BIT 2
#define PCIF2_MASK 4
When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
sfrb PCICR = $68;
#define PCIE0_BIT 0
#define PCIE0_MASK 1
#define PCIE1_BIT 1
#define PCIE1_MASK 2
#define PCIE2_BIT 2
#define PCIE2_MASK 4
AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode Noise
sfrb ADMUX = $7C;
#define MUX0_BIT 0
#define MUX0_MASK 1
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
#define MUX1_BIT 1
#define MUX1_MASK 2
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
#define MUX2_BIT 2
#define MUX2_MASK 4
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
#define MUX3_BIT 3
#define MUX3_MASK 8
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
#define MUX4_BIT 4
#define MUX4_MASK 16
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
#define ADLAR_BIT 5
#define ADLAR_MASK 32
The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see ??The ADC Data Register -ADCL and ADCH? on page 198.
#define REFS0_BIT 6
#define REFS0_MASK 64
These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.
#define REFS1_BIT 7
#define REFS1_MASK 128
These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.
sfrb ADCSRA = $7A;
#define ADPS0_BIT 0
#define ADPS0_MASK 1
These bits determine the division factor between the XTAL frequency and the input clock to the ADC.
#define ADPS1_BIT 1
#define ADPS1_MASK 2
These bits determine the division factor between the XTAL frequency and the input clock to the ADC.
#define ADPS2_BIT 2
#define ADPS2_MASK 4
These bits determine the division factor between the XTAL frequency and the input clock to the ADC.
#define ADIE_BIT 3
#define ADIE_MASK 8
When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.
#define ADIF_BIT 4
#define ADIF_MASK 16
This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.
#define ADATE_BIT 5
#define ADATE_MASK 32
When this bit is written to one,Auto Triggering of the ADC is enabled.The ADC will start a conversion on a positive edge of the selected trigger signal.The trigger source is selected by setting the ADC Trigger Select bits,ADTS in ADCSRB.
#define ADSC_BIT 6
#define ADSC_MASK 64
In Single Conversion Mode, a logical ??1?? must be written to this bit to start each conversion. In Free Running Mode, a logical ??1?? must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect
#define ADEN_BIT 7
#define ADEN_MASK 128
Writing a logical ??1?? to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
sfrb ADCH = $79;
#define ADCH0_BIT 0
#define ADCH0_MASK 1
#define ADCH1_BIT 1
#define ADCH1_MASK 2
#define ADCH2_BIT 2
#define ADCH2_MASK 4
#define ADCH3_BIT 3
#define ADCH3_MASK 8
#define ADCH4_BIT 4
#define ADCH4_MASK 16
#define ADCH5_BIT 5
#define ADCH5_MASK 32
#define ADCH6_BIT 6
#define ADCH6_MASK 64
#define ADCH7_BIT 7
#define ADCH7_MASK 128
sfrb ADCL = $78;
#define ADCL0_BIT 0
#define ADCL0_MASK 1
#define ADCL1_BIT 1
#define ADCL1_MASK 2
#define ADCL2_BIT 2
#define ADCL2_MASK 4
#define ADCL3_BIT 3
#define ADCL3_MASK 8
#define ADCL4_BIT 4
#define ADCL4_MASK 16
#define ADCL5_BIT 5
#define ADCL5_MASK 32
#define ADCL6_BIT 6
#define ADCL6_MASK 64
#define ADCL7_BIT 7
#define ADCL7_MASK 128
sfrb ADCSRB = $7B;
#define ADTS0_BIT 0
#define ADTS0_MASK 1
If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set .
#define ADTS1_BIT 1
#define ADTS1_MASK 2
If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set .
#define ADTS2_BIT 2
#define ADTS2_MASK 4
If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set .
#define ADHSM_BIT 7
#define ADHSM_MASK 128
Writing this bit to one enables the ADC High Speed Mode.This mode enables higher conversion rate at the expense of higher power consumption.
sfrb DIDR0 = $7E;
#define ADC0D_BIT 0
#define ADC0D_MASK 1
When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.
#define ADC1D_BIT 1
#define ADC1D_MASK 2
When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.
#define ADC2D_BIT 2
#define ADC2D_MASK 4
When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.
#define ADC3D_BIT 3
#define ADC3D_MASK 8
When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.
#define ADC4D_BIT 4
#define ADC4D_MASK 16
When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.
#define ADC5D_BIT 5
#define ADC5D_MASK 32
When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.
#define ADC6D_BIT 6
#define ADC6D_MASK 64
When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.
#define ADC7D_BIT 7
#define ADC7D_MASK 128
When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.
sfrb ADCSRB = $7B;
#define ACME_BIT 6
#define ACME_MASK 64
When this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see ??Analog Comparator Multiplexed Input? on page 186.
sfrb ACSR = $30;
#define ACIS0_BIT 0
#define ACIS0_MASK 1
These bits determine which comparator events that trigger the Analog Comparator interrupt.
#define ACIS1_BIT 1
#define ACIS1_MASK 2
These bits determine which comparator events that trigger the Analog Comparator interrupt.
#define ACIC_BIT 2
#define ACIC_MASK 4
When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the analog comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set
#define ACIE_BIT 3
#define ACIE_MASK 8
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.
#define ACI_BIT 4
#define ACI_MASK 16
This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
#define ACO_BIT 5
#define ACO_MASK 32
The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.
#define ACBG_BIT 6
#define ACBG_MASK 64
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See ??Internal Voltage Reference? on page 42.
#define ACD_BIT 7
#define ACD_MASK 128
When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
sfrb PLLCSR = $29;
#define PLOCK_BIT 0
#define PLOCK_MASK 1
#define PLLE_BIT 1
#define PLLE_MASK 2
#define PLLP0_BIT 2
#define PLLP0_MASK 4
#define PLLP1_BIT 3
#define PLLP1_MASK 8
#define PLLP2_BIT 4
#define PLLP2_MASK 16