This documentation was generated automatically from the AVR Studio part description file AT90PWM2.pdf
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sfrb PORTB = $05;
#define PORTB0_BIT 0
#define PORTB0_MASK 1
#define PORTB1_BIT 1
#define PORTB1_MASK 2
#define PORTB2_BIT 2
#define PORTB2_MASK 4
#define PORTB3_BIT 3
#define PORTB3_MASK 8
#define PORTB4_BIT 4
#define PORTB4_MASK 16
#define PORTB5_BIT 5
#define PORTB5_MASK 32
#define PORTB6_BIT 6
#define PORTB6_MASK 64
#define PORTB7_BIT 7
#define PORTB7_MASK 128
sfrb DDRB = $04;
#define DDB0_BIT 0
#define DDB0_MASK 1
#define DDB1_BIT 1
#define DDB1_MASK 2
#define DDB2_BIT 2
#define DDB2_MASK 4
#define DDB3_BIT 3
#define DDB3_MASK 8
#define DDB4_BIT 4
#define DDB4_MASK 16
#define DDB5_BIT 5
#define DDB5_MASK 32
#define DDB6_BIT 6
#define DDB6_MASK 64
#define DDB7_BIT 7
#define DDB7_MASK 128
sfrb PINB = $03;
#define PINB0_BIT 0
#define PINB0_MASK 1
#define PINB1_BIT 1
#define PINB1_MASK 2
#define PINB2_BIT 2
#define PINB2_MASK 4
#define PINB3_BIT 3
#define PINB3_MASK 8
#define PINB4_BIT 4
#define PINB4_MASK 16
#define PINB5_BIT 5
#define PINB5_MASK 32
#define PINB6_BIT 6
#define PINB6_MASK 64
#define PINB7_BIT 7
#define PINB7_MASK 128
sfrb PORTD = $0B;
#define PORTD0_BIT 0
#define PORTD0_MASK 1
#define PORTD1_BIT 1
#define PORTD1_MASK 2
#define PORTD2_BIT 2
#define PORTD2_MASK 4
#define PORTD3_BIT 3
#define PORTD3_MASK 8
#define PORTD4_BIT 4
#define PORTD4_MASK 16
#define PORTD5_BIT 5
#define PORTD5_MASK 32
#define PORTD6_BIT 6
#define PORTD6_MASK 64
#define PORTD7_BIT 7
#define PORTD7_MASK 128
sfrb DDRD = $0A;
#define DDD0_BIT 0
#define DDD0_MASK 1
#define DDD1_BIT 1
#define DDD1_MASK 2
#define DDD2_BIT 2
#define DDD2_MASK 4
#define DDD3_BIT 3
#define DDD3_MASK 8
#define DDD4_BIT 4
#define DDD4_MASK 16
#define DDD5_BIT 5
#define DDD5_MASK 32
#define DDD6_BIT 6
#define DDD6_MASK 64
#define DDD7_BIT 7
#define DDD7_MASK 128
sfrb PIND = $09;
#define PIND0_BIT 0
#define PIND0_MASK 1
#define PIND1_BIT 1
#define PIND1_MASK 2
#define PIND2_BIT 2
#define PIND2_MASK 4
#define PIND3_BIT 3
#define PIND3_MASK 8
#define PIND4_BIT 4
#define PIND4_MASK 16
#define PIND5_BIT 5
#define PIND5_MASK 32
#define PIND6_BIT 6
#define PIND6_MASK 64
#define PIND7_BIT 7
#define PIND7_MASK 128
The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppor
sfrb SPMCSR = $37;
#define SPMEN_BIT 0
#define SPMEN_MASK 1
This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than “10001”, "01001", "00101", "00011" or "00001" in the lower five bits will have no effec
#define PGERS_BIT 1
#define PGERS_MASK 2
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.
#define PGWRT_BIT 2
#define PGWRT_MASK 4
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.
#define BLBSET_BIT 3
#define BLBSET_MASK 8
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 235 for details
#define RWWSRE_BIT 4
#define RWWSRE_MASK 16
When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lo
#define RWWSB_BIT 6
#define RWWSB_MASK 64
When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated.
#define SPMIE_BIT 7
#define SPMIE_MASK 128
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared.
EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execute
sfrb EEARH = $22;
#define EEAR8_BIT 0
#define EEAR8_MASK 1
#define EEAR9_BIT 1
#define EEAR9_MASK 2
#define EEAR10_BIT 2
#define EEAR10_MASK 4
#define EEAR11_BIT 3
#define EEAR11_MASK 8
sfrb EEARL = $21;
#define EEARL0_BIT 0
#define EEARL0_MASK 1
#define EEARL1_BIT 1
#define EEARL1_MASK 2
#define EEARL2_BIT 2
#define EEARL2_MASK 4
#define EEARL3_BIT 3
#define EEARL3_MASK 8
#define EEARL4_BIT 4
#define EEARL4_MASK 16
#define EEARL5_BIT 5
#define EEARL5_MASK 32
#define EEARL6_BIT 6
#define EEARL6_MASK 64
#define EEARL7_BIT 7
#define EEARL7_MASK 128
sfrb EEDR = $20;
#define EEDR0_BIT 0
#define EEDR0_MASK 1
#define EEDR1_BIT 1
#define EEDR1_MASK 2
#define EEDR2_BIT 2
#define EEDR2_MASK 4
#define EEDR3_BIT 3
#define EEDR3_MASK 8
#define EEDR4_BIT 4
#define EEDR4_MASK 16
#define EEDR5_BIT 5
#define EEDR5_MASK 32
#define EEDR6_BIT 6
#define EEDR6_MASK 64
#define EEDR7_BIT 7
#define EEDR7_MASK 128
sfrb EECR = $1F;
#define EERE_BIT 0
#define EERE_MASK 1
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU
#define EEWE_BIT 1
#define EEWE_MASK 2
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed
#define EEMWE_BIT 2
#define EEMWE_MASK 4
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.
#define EERIE_BIT 3
#define EERIE_MASK 8
EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.
Power Stage Controller
sfrb PICR0H = 0xDF;
#define PICR0_8_BIT 0
#define PICR0_8_MASK 1
#define PICR0_9_BIT 1
#define PICR0_9_MASK 2
#define PICR0_10_BIT 2
#define PICR0_10_MASK 4
#define PICR0_11_BIT 3
#define PICR0_11_MASK 8
sfrb PICR0L = 0xDE;
#define PICR0_0_BIT 0
#define PICR0_0_MASK 1
#define PICR0_1_BIT 1
#define PICR0_1_MASK 2
#define PICR0_2_BIT 2
#define PICR0_2_MASK 4
#define PICR0_3_BIT 3
#define PICR0_3_MASK 8
#define PICR0_4_BIT 4
#define PICR0_4_MASK 16
#define PICR0_5_BIT 5
#define PICR0_5_MASK 32
#define PICR0_6_BIT 6
#define PICR0_6_MASK 64
#define PICR0_7_BIT 7
#define PICR0_7_MASK 128
sfrb PFRC0B = 0xDD;
#define PRFM0B0_BIT 0
#define PRFM0B0_MASK 1
#define PRFM0B1_BIT 1
#define PRFM0B1_MASK 2
#define PRFM0B2_BIT 2
#define PRFM0B2_MASK 4
#define PRFM0B3_BIT 3
#define PRFM0B3_MASK 8
#define PFLTE0B_BIT 4
#define PFLTE0B_MASK 16
#define PELEV0B_BIT 5
#define PELEV0B_MASK 32
#define PISEL0B_BIT 6
#define PISEL0B_MASK 64
#define PCAE0B_BIT 7
#define PCAE0B_MASK 128
sfrb PFRC0A = 0xDC;
#define PRFM0A0_BIT 0
#define PRFM0A0_MASK 1
#define PRFM0A1_BIT 1
#define PRFM0A1_MASK 2
#define PRFM0A2_BIT 2
#define PRFM0A2_MASK 4
#define PRFM0A3_BIT 3
#define PRFM0A3_MASK 8
#define PFLTE0A_BIT 4
#define PFLTE0A_MASK 16
#define PELEV0A_BIT 5
#define PELEV0A_MASK 32
#define PISEL0A_BIT 6
#define PISEL0A_MASK 64
#define PCAE0A_BIT 7
#define PCAE0A_MASK 128
sfrb PCTL0 = 0xDB;
#define PRUN0_BIT 0
#define PRUN0_MASK 1
#define PCCYC0_BIT 1
#define PCCYC0_MASK 2
#define PARUN0_BIT 2
#define PARUN0_MASK 4
#define PAOC0A_BIT 3
#define PAOC0A_MASK 8
#define PAOC0B_BIT 4
#define PAOC0B_MASK 16
#define PBFM0_BIT 5
#define PBFM0_MASK 32
#define PPRE00_BIT 6
#define PPRE00_MASK 64
#define PPRE01_BIT 7
#define PPRE01_MASK 128
sfrb PCNF0 = 0xDA;
#define PCLKSEL0_BIT 1
#define PCLKSEL0_MASK 2
#define POP0_BIT 2
#define POP0_MASK 4
#define PMODE00_BIT 3
#define PMODE00_MASK 8
#define PMODE01_BIT 4
#define PMODE01_MASK 16
#define PLOCK0_BIT 5
#define PLOCK0_MASK 32
#define PALOCK0_BIT 6
#define PALOCK0_MASK 64
#define PFIFTY0_BIT 7
#define PFIFTY0_MASK 128
sfrb OCR0RBH = 0xD9;
#define OCR0RB_8_BIT 0
#define OCR0RB_8_MASK 1
#define OCR0RB_9_BIT 1
#define OCR0RB_9_MASK 2
#define OCR0RB_00_BIT 2
#define OCR0RB_00_MASK 4
#define OCR0RB_01_BIT 3
#define OCR0RB_01_MASK 8
#define OCR0RB_02_BIT 4
#define OCR0RB_02_MASK 16
#define OCR0RB_03_BIT 5
#define OCR0RB_03_MASK 32
#define OCR0RB_04_BIT 6
#define OCR0RB_04_MASK 64
#define OCR0RB_05_BIT 7
#define OCR0RB_05_MASK 128
sfrb OCR0RBL = 0xD8;
#define OCR0RB_0_BIT 0
#define OCR0RB_0_MASK 1
#define OCR0RB_1_BIT 1
#define OCR0RB_1_MASK 2
#define OCR0RB_2_BIT 2
#define OCR0RB_2_MASK 4
#define OCR0RB_3_BIT 3
#define OCR0RB_3_MASK 8
#define OCR0RB_4_BIT 4
#define OCR0RB_4_MASK 16
#define OCR0RB_5_BIT 5
#define OCR0RB_5_MASK 32
#define OCR0RB_6_BIT 6
#define OCR0RB_6_MASK 64
#define OCR0RB_7_BIT 7
#define OCR0RB_7_MASK 128
sfrb OCR0SBH = 0xD7;
#define OCR0SB_8_BIT 0
#define OCR0SB_8_MASK 1
#define OCR0SB_9_BIT 1
#define OCR0SB_9_MASK 2
#define OCR0SB_00_BIT 2
#define OCR0SB_00_MASK 4
#define OCR0SB_01_BIT 3
#define OCR0SB_01_MASK 8
sfrb OCR0SBL = 0xD6;
#define OCR0SB_0_BIT 0
#define OCR0SB_0_MASK 1
#define OCR0SB_1_BIT 1
#define OCR0SB_1_MASK 2
#define OCR0SB_2_BIT 2
#define OCR0SB_2_MASK 4
#define OCR0SB_3_BIT 3
#define OCR0SB_3_MASK 8
#define OCR0SB_4_BIT 4
#define OCR0SB_4_MASK 16
#define OCR0SB_5_BIT 5
#define OCR0SB_5_MASK 32
#define OCR0SB_6_BIT 6
#define OCR0SB_6_MASK 64
#define OCR0SB_7_BIT 7
#define OCR0SB_7_MASK 128
sfrb OCR0RAH = 0xD5;
#define OCR0RA_8_BIT 0
#define OCR0RA_8_MASK 1
#define OCR0RA_9_BIT 1
#define OCR0RA_9_MASK 2
#define OCR0RA_00_BIT 2
#define OCR0RA_00_MASK 4
#define OCR0RA_01_BIT 3
#define OCR0RA_01_MASK 8
sfrb OCR0RAL = 0xD4;
#define OCR0RA_0_BIT 0
#define OCR0RA_0_MASK 1
#define OCR0RA_1_BIT 1
#define OCR0RA_1_MASK 2
#define OCR0RA_2_BIT 2
#define OCR0RA_2_MASK 4
#define OCR0RA_3_BIT 3
#define OCR0RA_3_MASK 8
#define OCR0RA_4_BIT 4
#define OCR0RA_4_MASK 16
#define OCR0RA_5_BIT 5
#define OCR0RA_5_MASK 32
#define OCR0RA_6_BIT 6
#define OCR0RA_6_MASK 64
#define OCR0RA_7_BIT 7
#define OCR0RA_7_MASK 128
sfrb OCR0SAH = 0xD3;
#define OCR0SA_8_BIT 0
#define OCR0SA_8_MASK 1
#define OCR0SA_9_BIT 1
#define OCR0SA_9_MASK 2
#define OCR0SA_00_BIT 2
#define OCR0SA_00_MASK 4
#define OCR0SA_01_BIT 3
#define OCR0SA_01_MASK 8
sfrb OCR0SAL = 0xD2;
#define OCR0SA_0_BIT 0
#define OCR0SA_0_MASK 1
#define OCR0SA_1_BIT 1
#define OCR0SA_1_MASK 2
#define OCR0SA_2_BIT 2
#define OCR0SA_2_MASK 4
#define OCR0SA_3_BIT 3
#define OCR0SA_3_MASK 8
#define OCR0SA_4_BIT 4
#define OCR0SA_4_MASK 16
#define OCR0SA_5_BIT 5
#define OCR0SA_5_MASK 32
#define OCR0SA_6_BIT 6
#define OCR0SA_6_MASK 64
#define OCR0SA_7_BIT 7
#define OCR0SA_7_MASK 128
sfrb PSOC0 = 0xD0;
#define POEN0A_BIT 0
#define POEN0A_MASK 1
#define POEN0B_BIT 2
#define POEN0B_MASK 4
#define PSYNC00_BIT 4
#define PSYNC00_MASK 16
#define PSYNC01_BIT 5
#define PSYNC01_MASK 32
sfrb PIM0 = $A1;
#define PEOPE0_BIT 0
#define PEOPE0_MASK 1
#define PEVE0A_BIT 3
#define PEVE0A_MASK 8
#define PEVE0B_BIT 4
#define PEVE0B_MASK 16
#define PSEIE0_BIT 5
#define PSEIE0_MASK 32
sfrb PIFR0 = $A0;
#define PEOP0_BIT 0
#define PEOP0_MASK 1
#define PRN00_BIT 1
#define PRN00_MASK 2
#define PRN01_BIT 2
#define PRN01_MASK 4
#define PEV0A_BIT 3
#define PEV0A_MASK 8
#define PEV0B_BIT 4
#define PEV0B_MASK 16
#define PSEI0_BIT 5
#define PSEI0_MASK 32
Power Stage Controller
sfrb PICR2H = 0xFF;
#define PICR2_8_BIT 0
#define PICR2_8_MASK 1
#define PICR2_9_BIT 1
#define PICR2_9_MASK 2
#define PICR2_10_BIT 2
#define PICR2_10_MASK 4
#define PICR2_11_BIT 3
#define PICR2_11_MASK 8
sfrb PICR2L = 0xFE;
#define PICR2_0_BIT 0
#define PICR2_0_MASK 1
#define PICR2_1_BIT 1
#define PICR2_1_MASK 2
#define PICR2_2_BIT 2
#define PICR2_2_MASK 4
#define PICR2_3_BIT 3
#define PICR2_3_MASK 8
#define PICR2_4_BIT 4
#define PICR2_4_MASK 16
#define PICR2_5_BIT 5
#define PICR2_5_MASK 32
#define PICR2_6_BIT 6
#define PICR2_6_MASK 64
#define PICR2_7_BIT 7
#define PICR2_7_MASK 128
sfrb PFRC2B = 0xFD;
#define PRFM2B0_BIT 0
#define PRFM2B0_MASK 1
#define PRFM2B1_BIT 1
#define PRFM2B1_MASK 2
#define PRFM2B2_BIT 2
#define PRFM2B2_MASK 4
#define PRFM2B3_BIT 3
#define PRFM2B3_MASK 8
#define PFLTE2B_BIT 4
#define PFLTE2B_MASK 16
#define PELEV2B_BIT 5
#define PELEV2B_MASK 32
#define PISEL2B_BIT 6
#define PISEL2B_MASK 64
#define PCAE2B_BIT 7
#define PCAE2B_MASK 128
sfrb PFRC2A = 0xFC;
#define PRFM2A0_BIT 0
#define PRFM2A0_MASK 1
#define PRFM2A1_BIT 1
#define PRFM2A1_MASK 2
#define PRFM2A2_BIT 2
#define PRFM2A2_MASK 4
#define PRFM2A3_BIT 3
#define PRFM2A3_MASK 8
#define PFLTE2A_BIT 4
#define PFLTE2A_MASK 16
#define PELEV2A_BIT 5
#define PELEV2A_MASK 32
#define PISEL2A_BIT 6
#define PISEL2A_MASK 64
#define PCAE2A_BIT 7
#define PCAE2A_MASK 128
sfrb PCTL2 = 0xFB;
#define PRUN2_BIT 0
#define PRUN2_MASK 1
#define PCCYC2_BIT 1
#define PCCYC2_MASK 2
#define PARUN2_BIT 2
#define PARUN2_MASK 4
#define PAOC2A_BIT 3
#define PAOC2A_MASK 8
#define PAOC2B_BIT 4
#define PAOC2B_MASK 16
#define PBFM2_BIT 5
#define PBFM2_MASK 32
#define PPRE20_BIT 6
#define PPRE20_MASK 64
#define PPRE21_BIT 7
#define PPRE21_MASK 128
sfrb PCNF2 = 0xFA;
#define POME2_BIT 0
#define POME2_MASK 1
#define PCLKSEL2_BIT 1
#define PCLKSEL2_MASK 2
#define POP2_BIT 2
#define POP2_MASK 4
#define PMODE20_BIT 3
#define PMODE20_MASK 8
#define PMODE21_BIT 4
#define PMODE21_MASK 16
#define PLOCK2_BIT 5
#define PLOCK2_MASK 32
#define PALOCK2_BIT 6
#define PALOCK2_MASK 64
#define PFIFTY2_BIT 7
#define PFIFTY2_MASK 128
sfrb OCR2RBH = 0xF9;
#define OCR2RB_8_BIT 0
#define OCR2RB_8_MASK 1
#define OCR2RB_9_BIT 1
#define OCR2RB_9_MASK 2
#define OCR2RB_10_BIT 2
#define OCR2RB_10_MASK 4
#define OCR2RB_11_BIT 3
#define OCR2RB_11_MASK 8
#define OCR2RB_12_BIT 4
#define OCR2RB_12_MASK 16
#define OCR2RB_13_BIT 5
#define OCR2RB_13_MASK 32
#define OCR2RB_14_BIT 6
#define OCR2RB_14_MASK 64
#define OCR2RB_15_BIT 7
#define OCR2RB_15_MASK 128
sfrb OCR2RBL = 0xF8;
#define OCR2RB_0_BIT 0
#define OCR2RB_0_MASK 1
#define OCR2RB_1_BIT 1
#define OCR2RB_1_MASK 2
#define OCR2RB_2_BIT 2
#define OCR2RB_2_MASK 4
#define OCR2RB_3_BIT 3
#define OCR2RB_3_MASK 8
#define OCR2RB_4_BIT 4
#define OCR2RB_4_MASK 16
#define OCR2RB_5_BIT 5
#define OCR2RB_5_MASK 32
#define OCR2RB_6_BIT 6
#define OCR2RB_6_MASK 64
#define OCR2RB_7_BIT 7
#define OCR2RB_7_MASK 128
sfrb OCR2SBH = 0xF7;
#define OCR2SB_8_BIT 0
#define OCR2SB_8_MASK 1
#define OCR2SB_9_BIT 1
#define OCR2SB_9_MASK 2
#define OCR2SB_10_BIT 2
#define OCR2SB_10_MASK 4
#define OCR2SB_11_BIT 3
#define OCR2SB_11_MASK 8
sfrb OCR2SBL = 0xF6;
#define OCR2SB_0_BIT 0
#define OCR2SB_0_MASK 1
#define OCR2SB_1_BIT 1
#define OCR2SB_1_MASK 2
#define OCR2SB_2_BIT 2
#define OCR2SB_2_MASK 4
#define OCR2SB_3_BIT 3
#define OCR2SB_3_MASK 8
#define OCR2SB_4_BIT 4
#define OCR2SB_4_MASK 16
#define OCR2SB_5_BIT 5
#define OCR2SB_5_MASK 32
#define OCR2SB_6_BIT 6
#define OCR2SB_6_MASK 64
#define OCR2SB_7_BIT 7
#define OCR2SB_7_MASK 128
sfrb OCR2RAH = 0xF5;
#define OCR2RA_8_BIT 0
#define OCR2RA_8_MASK 1
#define OCR2RA_9_BIT 1
#define OCR2RA_9_MASK 2
#define OCR2RA_10_BIT 2
#define OCR2RA_10_MASK 4
#define OCR2RA_11_BIT 3
#define OCR2RA_11_MASK 8
sfrb OCR2RAL = 0xF4;
#define OCR2RA_0_BIT 0
#define OCR2RA_0_MASK 1
#define OCR2RA_1_BIT 1
#define OCR2RA_1_MASK 2
#define OCR2RA_2_BIT 2
#define OCR2RA_2_MASK 4
#define OCR2RA_3_BIT 3
#define OCR2RA_3_MASK 8
#define OCR2RA_4_BIT 4
#define OCR2RA_4_MASK 16
#define OCR2RA_5_BIT 5
#define OCR2RA_5_MASK 32
#define OCR2RA_6_BIT 6
#define OCR2RA_6_MASK 64
#define OCR2RA_7_BIT 7
#define OCR2RA_7_MASK 128
sfrb OCR2SAH = 0xF3;
#define OCR2SA_8_BIT 0
#define OCR2SA_8_MASK 1
#define OCR2SA_9_BIT 1
#define OCR2SA_9_MASK 2
#define OCR2SA_10_BIT 2
#define OCR2SA_10_MASK 4
#define OCR2SA_11_BIT 3
#define OCR2SA_11_MASK 8
sfrb OCR2SAL = 0xF2;
#define OCR2SA_0_BIT 0
#define OCR2SA_0_MASK 1
#define OCR2SA_1_BIT 1
#define OCR2SA_1_MASK 2
#define OCR2SA_2_BIT 2
#define OCR2SA_2_MASK 4
#define OCR2SA_3_BIT 3
#define OCR2SA_3_MASK 8
#define OCR2SA_4_BIT 4
#define OCR2SA_4_MASK 16
#define OCR2SA_5_BIT 5
#define OCR2SA_5_MASK 32
#define OCR2SA_6_BIT 6
#define OCR2SA_6_MASK 64
#define OCR2SA_7_BIT 7
#define OCR2SA_7_MASK 128
sfrb POM2 = 0xF1;
#define POMV2A0_BIT 0
#define POMV2A0_MASK 1
#define POMV2A1_BIT 1
#define POMV2A1_MASK 2
#define POMV2A2_BIT 2
#define POMV2A2_MASK 4
#define POMV2A3_BIT 3
#define POMV2A3_MASK 8
#define POMV2B0_BIT 4
#define POMV2B0_MASK 16
#define POMV2B1_BIT 5
#define POMV2B1_MASK 32
#define POMV2B2_BIT 6
#define POMV2B2_MASK 64
#define POMV2B3_BIT 7
#define POMV2B3_MASK 128
sfrb PSOC2 = 0xF0;
#define POEN2A_BIT 0
#define POEN2A_MASK 1
#define POEN2C_BIT 1
#define POEN2C_MASK 2
#define POEN2B_BIT 2
#define POEN2B_MASK 4
#define POEN2D_BIT 3
#define POEN2D_MASK 8
#define PSYNC2_0_BIT 4
#define PSYNC2_0_MASK 16
#define PSYNC2_1_BIT 5
#define PSYNC2_1_MASK 32
#define POS22_BIT 6
#define POS22_MASK 64
#define POS23_BIT 7
#define POS23_MASK 128
sfrb PIM2 = $A5;
#define PEOPE2_BIT 0
#define PEOPE2_MASK 1
#define PEVE2A_BIT 3
#define PEVE2A_MASK 8
#define PEVE2B_BIT 4
#define PEVE2B_MASK 16
#define PSEIE2_BIT 5
#define PSEIE2_MASK 32
sfrb PIFR2 = $A4;
#define PEOP2_BIT 0
#define PEOP2_MASK 1
#define PRN20_BIT 1
#define PRN20_MASK 2
#define PRN21_BIT 2
#define PRN21_MASK 4
#define PEV2A_BIT 3
#define PEV2A_MASK 8
#define PEV2B_BIT 4
#define PEV2B_MASK 16
#define PSEI2_BIT 5
#define PSEI2_MASK 32
sfrb EUDR = 0xCE;
#define EUDR0_BIT 0
#define EUDR0_MASK 1
#define EUDR1_BIT 1
#define EUDR1_MASK 2
#define EUDR2_BIT 2
#define EUDR2_MASK 4
#define EUDR3_BIT 3
#define EUDR3_MASK 8
#define EUDR4_BIT 4
#define EUDR4_MASK 16
#define EUDR5_BIT 5
#define EUDR5_MASK 32
#define EUDR6_BIT 6
#define EUDR6_MASK 64
#define EUDR7_BIT 7
#define EUDR7_MASK 128
sfrb EUCSRA = 0xC8;
#define URxS0_BIT 0
#define URxS0_MASK 1
#define URxS1_BIT 1
#define URxS1_MASK 2
#define URxS2_BIT 2
#define URxS2_MASK 4
#define URxS3_BIT 3
#define URxS3_MASK 8
#define UTxS0_BIT 4
#define UTxS0_MASK 16
#define UTxS1_BIT 5
#define UTxS1_MASK 32
#define UTxS2_BIT 6
#define UTxS2_MASK 64
#define UTxS3_BIT 7
#define UTxS3_MASK 128
.
sfrb EUCSRB = 0xC9;
#define BODR_BIT 0
#define BODR_MASK 1
#define EMCH_BIT 1
#define EMCH_MASK 2
#define EUSBS_BIT 3
#define EUSBS_MASK 8
#define EUSART_BIT 4
#define EUSART_MASK 16
sfrb EUCSRC = 0xCA;
#define STP0_BIT 0
#define STP0_MASK 1
#define STP1_BIT 1
#define STP1_MASK 2
#define F1617_BIT 2
#define F1617_MASK 4
#define FEM_BIT 3
#define FEM_MASK 8
sfrb MUBRRH = 0xCD;
#define MUBRR8_BIT 0
#define MUBRR8_MASK 1
#define MUBRR9_BIT 1
#define MUBRR9_MASK 2
#define MUBRR10_BIT 2
#define MUBRR10_MASK 4
#define MUBRR11_BIT 3
#define MUBRR11_MASK 8
#define MUBRR12_BIT 4
#define MUBRR12_MASK 16
#define MUBRR13_BIT 5
#define MUBRR13_MASK 32
#define MUBRR14_BIT 6
#define MUBRR14_MASK 64
#define MUBRR15_BIT 7
#define MUBRR15_MASK 128
sfrb MUBRRL = 0xCC;
#define MUBRR0_BIT 0
#define MUBRR0_MASK 1
#define MUBRR1_BIT 1
#define MUBRR1_MASK 2
#define MUBRR2_BIT 2
#define MUBRR2_MASK 4
#define MUBRR3_BIT 3
#define MUBRR3_MASK 8
#define MUBRR4_BIT 4
#define MUBRR4_MASK 16
#define MUBRR5_BIT 5
#define MUBRR5_MASK 32
#define MUBRR6_BIT 6
#define MUBRR6_MASK 64
#define MUBRR7_BIT 7
#define MUBRR7_MASK 128
sfrb AC0CON = $AD;
#define AC0M0_BIT 0
#define AC0M0_MASK 1
#define AC0M1_BIT 1
#define AC0M1_MASK 2
#define AC0M2_BIT 2
#define AC0M2_MASK 4
#define AC0IS0_BIT 4
#define AC0IS0_MASK 16
#define AC0IS1_BIT 5
#define AC0IS1_MASK 32
#define AC0IE_BIT 6
#define AC0IE_MASK 64
#define AC0EN_BIT 7
#define AC0EN_MASK 128
sfrb AC1CON = $AE;
#define AC1M0_BIT 0
#define AC1M0_MASK 1
#define AC1M1_BIT 1
#define AC1M1_MASK 2
#define AC1M2_BIT 2
#define AC1M2_MASK 4
#define AC1ICE_BIT 3
#define AC1ICE_MASK 8
#define AC1IS0_BIT 4
#define AC1IS0_MASK 16
#define AC1IS1_BIT 5
#define AC1IS1_MASK 32
#define AC1IE_BIT 6
#define AC1IE_MASK 64
#define AC1EN_BIT 7
#define AC1EN_MASK 128
sfrb AC2CON = $AF;
#define AC2M0_BIT 0
#define AC2M0_MASK 1
#define AC2M1_BIT 1
#define AC2M1_MASK 2
#define AC2M2_BIT 2
#define AC2M2_MASK 4
#define AC2SADE_BIT 3
#define AC2SADE_MASK 8
#define AC2IS0_BIT 4
#define AC2IS0_MASK 16
#define AC2IS1_BIT 5
#define AC2IS1_MASK 32
#define AC2IE_BIT 6
#define AC2IE_MASK 64
#define AC2EN_BIT 7
#define AC2EN_MASK 128
Digital to Analog Converter
sfrb DACH = $AC;
#define DACH0_BIT 0
#define DACH0_MASK 1
#define DACH1_BIT 1
#define DACH1_MASK 2
#define DACH2_BIT 2
#define DACH2_MASK 4
#define DACH3_BIT 3
#define DACH3_MASK 8
#define DACH4_BIT 4
#define DACH4_MASK 16
#define DACH5_BIT 5
#define DACH5_MASK 32
#define DACH6_BIT 6
#define DACH6_MASK 64
#define DACH7_BIT 7
#define DACH7_MASK 128
sfrb DACL = $AB;
#define DACL1_BIT 1
#define DACL1_MASK 2
#define DACL2_BIT 2
#define DACL2_MASK 4
#define DACL3_BIT 3
#define DACL3_MASK 8
#define DACL4_BIT 4
#define DACL4_MASK 16
#define DACL5_BIT 5
#define DACL5_MASK 32
#define DACL6_BIT 6
#define DACL6_MASK 64
#define DACL7_BIT 7
#define DACL7_MASK 128
sfrb DACON = $AA;
#define DAEN_BIT 0
#define DAEN_MASK 1
#define DAOE_BIT 1
#define DAOE_MASK 2
#define DALA_BIT 2
#define DALA_MASK 4
#define DATS0_BIT 4
#define DATS0_MASK 16
#define DATS1_BIT 5
#define DATS1_MASK 32
#define DATS2_BIT 6
#define DATS2_MASK 64
#define DAATE_BIT 7
#define DAATE_MASK 128
sfrb SREG = $3F;
sfrb SPH = $3E;
#define SP8_BIT 0
#define SP8_MASK 1
#define SP9_BIT 1
#define SP9_MASK 2
#define SP10_BIT 2
#define SP10_MASK 4
#define SP11_BIT 3
#define SP11_MASK 8
#define SP12_BIT 4
#define SP12_MASK 16
#define SP13_BIT 5
#define SP13_MASK 32
#define SP14_BIT 6
#define SP14_MASK 64
#define SP15_BIT 7
#define SP15_MASK 128
sfrb SPL = $3D;
#define SP0_BIT 0
#define SP0_MASK 1
#define SP1_BIT 1
#define SP1_MASK 2
#define SP2_BIT 2
#define SP2_MASK 4
#define SP3_BIT 3
#define SP3_MASK 8
#define SP4_BIT 4
#define SP4_MASK 16
#define SP5_BIT 5
#define SP5_MASK 32
#define SP6_BIT 6
#define SP6_MASK 64
#define SP7_BIT 7
#define SP7_MASK 128
sfrb MCUCR = $35;
#define IVCE_BIT 0
#define IVCE_MASK 1
The IVCE bit must be written to logic one to enable change of the IVSEL bit.IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.Setting the IVCE bit will disable interrupts.
#define IVSEL_BIT 1
#define IVSEL_MASK 2
When the IVSEL bit is cleared (zero),the interrupt vectors are placed at the start of the Flash memory.When this bit is set (one),the interrupt vectors are moved to the beginning of the Boot Loader section of the flash.The actual address of the start of the boot flash section is determined by the BOOTSZ fuses.
#define PUD_BIT 4
#define PUD_MASK 16
When this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn,PORTxn}=0b01).
#define SPIPS_BIT 7
#define SPIPS_MASK 128
sfrb MCUSR = $34;
#define PORF_BIT 0
#define PORF_MASK 1
This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.
#define EXTRF_BIT 1
#define EXTRF_MASK 2
This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
#define BORF_BIT 2
#define BORF_MASK 4
This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
#define WDRF_BIT 3
#define WDRF_MASK 8
This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
sfrb OSCCAL = $66;
#define CAL0_BIT 0
#define CAL0_MASK 1
#define CAL1_BIT 1
#define CAL1_MASK 2
#define CAL2_BIT 2
#define CAL2_MASK 4
#define CAL3_BIT 3
#define CAL3_MASK 8
#define CAL4_BIT 4
#define CAL4_MASK 16
#define CAL5_BIT 5
#define CAL5_MASK 32
#define CAL6_BIT 6
#define CAL6_MASK 64
sfrb CLKPR = $61;
#define CLKPS0_BIT 0
#define CLKPS0_MASK 1
#define CLKPS1_BIT 1
#define CLKPS1_MASK 2
#define CLKPS2_BIT 2
#define CLKPS2_MASK 4
#define CLKPS3_BIT 3
#define CLKPS3_MASK 8
#define CPKPCE_BIT 7
#define CPKPCE_MASK 128
sfrb SMCR = $33;
#define SE_BIT 0
#define SE_MASK 1
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.To
#define SM0_BIT 1
#define SM0_MASK 2
These bits select between the five available sleep modes.
#define SM1_BIT 2
#define SM1_MASK 4
These bits select between the five available sleep modes.
#define SM2_BIT 3
#define SM2_MASK 8
These bits select between the five available sleep modes.
sfrb GPIOR3 = $1B;
#define GPIOR30_BIT 0
#define GPIOR30_MASK 1
#define GPIOR31_BIT 1
#define GPIOR31_MASK 2
#define GPIOR32_BIT 2
#define GPIOR32_MASK 4
#define GPIOR33_BIT 3
#define GPIOR33_MASK 8
#define GPIOR34_BIT 4
#define GPIOR34_MASK 16
#define GPIOR35_BIT 5
#define GPIOR35_MASK 32
#define GPIOR36_BIT 6
#define GPIOR36_MASK 64
#define GPIOR37_BIT 7
#define GPIOR37_MASK 128
sfrb GPIOR2 = $1A;
#define GPIOR20_BIT 0
#define GPIOR20_MASK 1
#define GPIOR21_BIT 1
#define GPIOR21_MASK 2
#define GPIOR22_BIT 2
#define GPIOR22_MASK 4
#define GPIOR23_BIT 3
#define GPIOR23_MASK 8
#define GPIOR24_BIT 4
#define GPIOR24_MASK 16
#define GPIOR25_BIT 5
#define GPIOR25_MASK 32
#define GPIOR26_BIT 6
#define GPIOR26_MASK 64
#define GPIOR27_BIT 7
#define GPIOR27_MASK 128
sfrb GPIOR1 = $19;
#define GPIOR10_BIT 0
#define GPIOR10_MASK 1
#define GPIOR11_BIT 1
#define GPIOR11_MASK 2
#define GPIOR12_BIT 2
#define GPIOR12_MASK 4
#define GPIOR13_BIT 3
#define GPIOR13_MASK 8
#define GPIOR14_BIT 4
#define GPIOR14_MASK 16
#define GPIOR15_BIT 5
#define GPIOR15_MASK 32
#define GPIOR16_BIT 6
#define GPIOR16_MASK 64
#define GPIOR17_BIT 7
#define GPIOR17_MASK 128
sfrb GPIOR0 = $1E;
#define GPIOR00_BIT 0
#define GPIOR00_MASK 1
#define GPIOR01_BIT 1
#define GPIOR01_MASK 2
#define GPIOR02_BIT 2
#define GPIOR02_MASK 4
#define GPIOR03_BIT 3
#define GPIOR03_MASK 8
#define GPIOR04_BIT 4
#define GPIOR04_MASK 16
#define GPIOR05_BIT 5
#define GPIOR05_MASK 32
#define GPIOR06_BIT 6
#define GPIOR06_MASK 64
#define GPIOR07_BIT 7
#define GPIOR07_MASK 128
sfrb PLLCSR = $29;
#define PLOCK_BIT 0
#define PLOCK_MASK 1
#define PLLE_BIT 1
#define PLLE_MASK 2
#define PCKE_BIT 2
#define PCKE_MASK 4
sfrb PORTE = $0E;
#define PORTE0_BIT 0
#define PORTE0_MASK 1
#define PORTE1_BIT 1
#define PORTE1_MASK 2
#define PORTE2_BIT 2
#define PORTE2_MASK 4
sfrb DDRE = $0D;
#define DDE0_BIT 0
#define DDE0_MASK 1
#define DDE1_BIT 1
#define DDE1_MASK 2
#define DDE2_BIT 2
#define DDE2_MASK 4
sfrb PINE = $0C;
#define PINE0_BIT 0
#define PINE0_MASK 1
#define PINE1_BIT 1
#define PINE1_MASK 2
#define PINE2_BIT 2
#define PINE2_MASK 4
sfrb TIMSK0 = $6E;
#define TOIE0_BIT 0
#define TOIE0_MASK 1
#define OCIE0A_BIT 1
#define OCIE0A_MASK 2
#define OCIE0B_BIT 2
#define OCIE0B_MASK 4
sfrb TIFR0 = $15;
#define TOV0_BIT 0
#define TOV0_MASK 1
#define OCF0A_BIT 1
#define OCF0A_MASK 2
#define OCF0B_BIT 2
#define OCF0B_MASK 4
sfrb TCCR0A = $24;
#define WGM00_BIT 0
#define WGM00_MASK 1
#define WGM01_BIT 1
#define WGM01_MASK 2
#define COM0B0_BIT 4
#define COM0B0_MASK 16
#define COM0B1_BIT 5
#define COM0B1_MASK 32
#define COM0A0_BIT 6
#define COM0A0_MASK 64
#define COM0A1_BIT 7
#define COM0A1_MASK 128
sfrb TCCR0B = $25;
#define CS00_BIT 0
#define CS00_MASK 1
#define CS01_BIT 1
#define CS01_MASK 2
#define CS02_BIT 2
#define CS02_MASK 4
#define WGM02_BIT 3
#define WGM02_MASK 8
#define FOC0B_BIT 6
#define FOC0B_MASK 64
#define FOC0A_BIT 7
#define FOC0A_MASK 128
sfrb TCNT0 = $26;
#define TCNT0_0_BIT 0
#define TCNT0_0_MASK 1
#define TCNT0_1_BIT 1
#define TCNT0_1_MASK 2
#define TCNT0_2_BIT 2
#define TCNT0_2_MASK 4
#define TCNT0_3_BIT 3
#define TCNT0_3_MASK 8
#define TCNT0_4_BIT 4
#define TCNT0_4_MASK 16
#define TCNT0_5_BIT 5
#define TCNT0_5_MASK 32
#define TCNT0_6_BIT 6
#define TCNT0_6_MASK 64
#define TCNT0_7_BIT 7
#define TCNT0_7_MASK 128
sfrb OCR0A = $27;
#define OCR0_0_BIT 0
#define OCR0_0_MASK 1
#define OCR0_1_BIT 1
#define OCR0_1_MASK 2
#define OCR0_2_BIT 2
#define OCR0_2_MASK 4
#define OCR0_3_BIT 3
#define OCR0_3_MASK 8
#define OCR0_4_BIT 4
#define OCR0_4_MASK 16
#define OCR0_5_BIT 5
#define OCR0_5_MASK 32
#define OCR0_6_BIT 6
#define OCR0_6_MASK 64
#define OCR0_7_BIT 7
#define OCR0_7_MASK 128
sfrb OCR0B = $28;
#define OCR0_0_BIT 0
#define OCR0_0_MASK 1
#define OCR0_1_BIT 1
#define OCR0_1_MASK 2
#define OCR0_2_BIT 2
#define OCR0_2_MASK 4
#define OCR0_3_BIT 3
#define OCR0_3_MASK 8
#define OCR0_4_BIT 4
#define OCR0_4_MASK 16
#define OCR0_5_BIT 5
#define OCR0_5_MASK 32
#define OCR0_6_BIT 6
#define OCR0_6_MASK 64
#define OCR0_7_BIT 7
#define OCR0_7_MASK 128
sfrb GTCCR = $23;
#define PSR10_BIT 0
#define PSR10_MASK 1
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.
#define ICPSEL1_BIT 6
#define ICPSEL1_MASK 64
#define TSM_BIT 7
#define TSM_MASK 128
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneousl
sfrb TIMSK1 = $6F;
#define TOIE1_BIT 0
#define TOIE1_MASK 1
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define OCIE1A_BIT 1
#define OCIE1A_MASK 2
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define OCIE1B_BIT 2
#define OCIE1B_MASK 4
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define ICIE1_BIT 5
#define ICIE1_MASK 32
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
sfrb TIFR1 = $16;
#define TOV1_BIT 0
#define TOV1_MASK 1
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.
#define OCF1A_BIT 1
#define OCF1A_MASK 2
The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed.
#define OCF1B_BIT 2
#define OCF1B_MASK 4
The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.
#define ICF1_BIT 5
#define ICF1_MASK 32
The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.
sfrb TCCR1A = $80;
#define WGM10_BIT 0
#define WGM10_MASK 1
Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.
#define WGM11_BIT 1
#define WGM11_MASK 2
Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.
#define COM1B0_BIT 4
#define COM1B0_MASK 16
The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.
#define COM1B1_BIT 5
#define COM1B1_MASK 32
The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.
#define COM1A0_BIT 6
#define COM1A0_MASK 64
The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.
#define COM1A1_BIT 7
#define COM1A1_MASK 128
The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.
sfrb TCCR1B = $81;
#define CS10_BIT 0
#define CS10_MASK 1
Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.
#define CS11_BIT 1
#define CS11_MASK 2
Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.
#define CS12_BIT 2
#define CS12_MASK 4
Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.
#define WGM12_BIT 3
#define WGM12_MASK 8
Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.
#define WGM13_BIT 4
#define WGM13_MASK 16
Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.
#define ICES1_BIT 6
#define ICES1_MASK 64
While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.
#define ICNC1_BIT 7
#define ICNC1_MASK 128
When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.
sfrb TCCR1C = $82;
#define FOC1B_BIT 6
#define FOC1B_MASK 64
#define FOC1A_BIT 7
#define FOC1A_MASK 128
sfrb TCNT1H = $85;
#define TCNT1H0_BIT 0
#define TCNT1H0_MASK 1
#define TCNT1H1_BIT 1
#define TCNT1H1_MASK 2
#define TCNT1H2_BIT 2
#define TCNT1H2_MASK 4
#define TCNT1H3_BIT 3
#define TCNT1H3_MASK 8
#define TCNT1H4_BIT 4
#define TCNT1H4_MASK 16
#define TCNT1H5_BIT 5
#define TCNT1H5_MASK 32
#define TCNT1H6_BIT 6
#define TCNT1H6_MASK 64
#define TCNT1H7_BIT 7
#define TCNT1H7_MASK 128
sfrb TCNT1L = $84;
#define TCNT1L0_BIT 0
#define TCNT1L0_MASK 1
#define TCNT1L1_BIT 1
#define TCNT1L1_MASK 2
#define TCNT1L2_BIT 2
#define TCNT1L2_MASK 4
#define TCNT1L3_BIT 3
#define TCNT1L3_MASK 8
#define TCNT1L4_BIT 4
#define TCNT1L4_MASK 16
#define TCNT1L5_BIT 5
#define TCNT1L5_MASK 32
#define TCNT1L6_BIT 6
#define TCNT1L6_MASK 64
#define TCNT1L7_BIT 7
#define TCNT1L7_MASK 128
sfrb OCR1AH = $89;
#define OCR1AH0_BIT 0
#define OCR1AH0_MASK 1
#define OCR1AH1_BIT 1
#define OCR1AH1_MASK 2
#define OCR1AH2_BIT 2
#define OCR1AH2_MASK 4
#define OCR1AH3_BIT 3
#define OCR1AH3_MASK 8
#define OCR1AH4_BIT 4
#define OCR1AH4_MASK 16
#define OCR1AH5_BIT 5
#define OCR1AH5_MASK 32
#define OCR1AH6_BIT 6
#define OCR1AH6_MASK 64
#define OCR1AH7_BIT 7
#define OCR1AH7_MASK 128
sfrb OCR1AL = $88;
#define OCR1AL0_BIT 0
#define OCR1AL0_MASK 1
#define OCR1AL1_BIT 1
#define OCR1AL1_MASK 2
#define OCR1AL2_BIT 2
#define OCR1AL2_MASK 4
#define OCR1AL3_BIT 3
#define OCR1AL3_MASK 8
#define OCR1AL4_BIT 4
#define OCR1AL4_MASK 16
#define OCR1AL5_BIT 5
#define OCR1AL5_MASK 32
#define OCR1AL6_BIT 6
#define OCR1AL6_MASK 64
#define OCR1AL7_BIT 7
#define OCR1AL7_MASK 128
sfrb OCR1BH = $8B;
#define OCR1BH0_BIT 0
#define OCR1BH0_MASK 1
#define OCR1BH1_BIT 1
#define OCR1BH1_MASK 2
#define OCR1BH2_BIT 2
#define OCR1BH2_MASK 4
#define OCR1BH3_BIT 3
#define OCR1BH3_MASK 8
#define OCR1BH4_BIT 4
#define OCR1BH4_MASK 16
#define OCR1BH5_BIT 5
#define OCR1BH5_MASK 32
#define OCR1BH6_BIT 6
#define OCR1BH6_MASK 64
#define OCR1BH7_BIT 7
#define OCR1BH7_MASK 128
sfrb OCR1BL = $8A;
#define OCR1BL0_BIT 0
#define OCR1BL0_MASK 1
#define OCR1BL1_BIT 1
#define OCR1BL1_MASK 2
#define OCR1BL2_BIT 2
#define OCR1BL2_MASK 4
#define OCR1BL3_BIT 3
#define OCR1BL3_MASK 8
#define OCR1BL4_BIT 4
#define OCR1BL4_MASK 16
#define OCR1BL5_BIT 5
#define OCR1BL5_MASK 32
#define OCR1BL6_BIT 6
#define OCR1BL6_MASK 64
#define OCR1BL7_BIT 7
#define OCR1BL7_MASK 128
sfrb ICR1H = $87;
#define ICR1H0_BIT 0
#define ICR1H0_MASK 1
#define ICR1H1_BIT 1
#define ICR1H1_MASK 2
#define ICR1H2_BIT 2
#define ICR1H2_MASK 4
#define ICR1H3_BIT 3
#define ICR1H3_MASK 8
#define ICR1H4_BIT 4
#define ICR1H4_MASK 16
#define ICR1H5_BIT 5
#define ICR1H5_MASK 32
#define ICR1H6_BIT 6
#define ICR1H6_MASK 64
#define ICR1H7_BIT 7
#define ICR1H7_MASK 128
sfrb ICR1L = $86;
#define ICR1L0_BIT 0
#define ICR1L0_MASK 1
#define ICR1L1_BIT 1
#define ICR1L1_MASK 2
#define ICR1L2_BIT 2
#define ICR1L2_MASK 4
#define ICR1L3_BIT 3
#define ICR1L3_MASK 8
#define ICR1L4_BIT 4
#define ICR1L4_MASK 16
#define ICR1L5_BIT 5
#define ICR1L5_MASK 32
#define ICR1L6_BIT 6
#define ICR1L6_MASK 64
#define ICR1L7_BIT 7
#define ICR1L7_MASK 128
sfrb GTCCR = $23;
#define PSRSYNC_BIT 0
#define PSRSYNC_MASK 1
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.
#define TSM_BIT 7
#define TSM_MASK 128
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneous
AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode Noi
sfrb ADMUX = $7C;
#define MUX0_BIT 0
#define MUX0_MASK 1
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
#define MUX1_BIT 1
#define MUX1_MASK 2
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
#define MUX2_BIT 2
#define MUX2_MASK 4
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
#define MUX3_BIT 3
#define MUX3_MASK 8
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
#define ADLAR_BIT 5
#define ADLAR_MASK 32
The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198.
#define REFS0_BIT 6
#define REFS0_MASK 64
These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.
#define REFS1_BIT 7
#define REFS1_MASK 128
These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.
sfrb ADCSRA = $7A;
#define ADPS0_BIT 0
#define ADPS0_MASK 1
These bits determine the division factor between the XTAL frequency and the input clock to the ADC.
#define ADPS1_BIT 1
#define ADPS1_MASK 2
These bits determine the division factor between the XTAL frequency and the input clock to the ADC.
#define ADPS2_BIT 2
#define ADPS2_MASK 4
These bits determine the division factor between the XTAL frequency and the input clock to the ADC.
#define ADIE_BIT 3
#define ADIE_MASK 8
When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.
#define ADIF_BIT 4
#define ADIF_MASK 16
This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.
#define ADATE_BIT 5
#define ADATE_MASK 32
When this bit is written to one,Auto Triggering of the ADC is enabled.The ADC will start a conversion on a positive edge of the selected trigger signal.The trigger source is selected by setting the ADC Trigger Select bits,ADTS in ADCSRB.
#define ADSC_BIT 6
#define ADSC_MASK 64
In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect
#define ADEN_BIT 7
#define ADEN_MASK 128
Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
sfrb ADCH = $79;
#define ADCH0_BIT 0
#define ADCH0_MASK 1
#define ADCH1_BIT 1
#define ADCH1_MASK 2
#define ADCH2_BIT 2
#define ADCH2_MASK 4
#define ADCH3_BIT 3
#define ADCH3_MASK 8
#define ADCH4_BIT 4
#define ADCH4_MASK 16
#define ADCH5_BIT 5
#define ADCH5_MASK 32
#define ADCH6_BIT 6
#define ADCH6_MASK 64
#define ADCH7_BIT 7
#define ADCH7_MASK 128
sfrb ADCL = $78;
#define ADCL0_BIT 0
#define ADCL0_MASK 1
#define ADCL1_BIT 1
#define ADCL1_MASK 2
#define ADCL2_BIT 2
#define ADCL2_MASK 4
#define ADCL3_BIT 3
#define ADCL3_MASK 8
#define ADCL4_BIT 4
#define ADCL4_MASK 16
#define ADCL5_BIT 5
#define ADCL5_MASK 32
#define ADCL6_BIT 6
#define ADCL6_MASK 64
#define ADCL7_BIT 7
#define ADCL7_MASK 128
sfrb ADCSRB = $7B;
#define ADTS0_BIT 0
#define ADTS0_MASK 1
#define ADTS1_BIT 1
#define ADTS1_MASK 2
#define ADTS2_BIT 2
#define ADTS2_MASK 4
#define ADASCR_BIT 3
#define ADASCR_MASK 8
#define ADAP_BIT 4
#define ADAP_MASK 16
sfrb DIDR0 = $7E;
#define ADC0D_BIT 0
#define ADC0D_MASK 1
When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.
#define ADC1D_BIT 1
#define ADC1D_MASK 2
When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.
#define ADC2D_BIT 2
#define ADC2D_MASK 4
When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.
#define ADC3D_BIT 3
#define ADC3D_MASK 8
When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.
#define ADC4D_BIT 4
#define ADC4D_MASK 16
When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.
#define ADC5D_BIT 5
#define ADC5D_MASK 32
When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.
#define ADC6D_BIT 6
#define ADC6D_MASK 64
When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.
#define ADC7D_BIT 7
#define ADC7D_MASK 128
When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.
sfrb UDR = 0xC6;
#define UDR0_BIT 0
#define UDR0_MASK 1
#define UDR1_BIT 1
#define UDR1_MASK 2
#define UDR2_BIT 2
#define UDR2_MASK 4
#define UDR3_BIT 3
#define UDR3_MASK 8
#define UDR4_BIT 4
#define UDR4_MASK 16
#define UDR5_BIT 5
#define UDR5_MASK 32
#define UDR6_BIT 6
#define UDR6_MASK 64
#define UDR7_BIT 7
#define UDR7_MASK 128
sfrb UCSRA = 0xC0;
#define MPCM_BIT 0
#define MPCM_MASK 1
#define U2X_BIT 1
#define U2X_MASK 2
#define UPE_BIT 2
#define UPE_MASK 4
#define DOR_BIT 3
#define DOR_MASK 8
#define FE_BIT 4
#define FE_MASK 16
#define UDRE_BIT 5
#define UDRE_MASK 32
#define TXC_BIT 6
#define TXC_MASK 64
#define RXC_BIT 7
#define RXC_MASK 128
sfrb UCSRB = 0xC1;
#define TXB8_BIT 0
#define TXB8_MASK 1
#define RXB8_BIT 1
#define RXB8_MASK 2
#define UCSZ2_BIT 2
#define UCSZ2_MASK 4
#define TXEN_BIT 3
#define TXEN_MASK 8
#define RXEN_BIT 4
#define RXEN_MASK 16
#define UDRIE_BIT 5
#define UDRIE_MASK 32
#define TXCIE_BIT 6
#define TXCIE_MASK 64
#define RXCIE_BIT 7
#define RXCIE_MASK 128
sfrb UCSRC = 0xC2;
#define UCPOL_BIT 0
#define UCPOL_MASK 1
#define UCSZ0_BIT 1
#define UCSZ0_MASK 2
#define UCSZ1_BIT 2
#define UCSZ1_MASK 4
#define USBS_BIT 3
#define USBS_MASK 8
#define UPM0_BIT 4
#define UPM0_MASK 16
#define UPM1_BIT 5
#define UPM1_MASK 32
#define UMSEL0_BIT 6
#define UMSEL0_MASK 64
sfrb UBRRH = 0xC5;
#define UBRR8_BIT 0
#define UBRR8_MASK 1
#define UBRR9_BIT 1
#define UBRR9_MASK 2
#define UBRR10_BIT 2
#define UBRR10_MASK 4
#define UBRR11_BIT 3
#define UBRR11_MASK 8
sfrb UBRRL = 0xC4;
#define UBRR0_BIT 0
#define UBRR0_MASK 1
#define UBRR1_BIT 1
#define UBRR1_MASK 2
#define UBRR2_BIT 2
#define UBRR2_MASK 4
#define UBRR3_BIT 3
#define UBRR3_MASK 8
#define UBRR4_BIT 4
#define UBRR4_MASK 16
#define UBRR5_BIT 5
#define UBRR5_MASK 32
#define UBRR6_BIT 6
#define UBRR6_MASK 64
#define UBRR7_BIT 7
#define UBRR7_MASK 128
The Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Four Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wakeup from Idle Mode (Slave Mode Only)
sfrb SPCR = $2C;
#define SPR0_BIT 0
#define SPR0_MASK 1
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.
#define SPR1_BIT 1
#define SPR1_MASK 2
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.
#define CPHA_BIT 2
#define CPHA_MASK 4
Refer to Figure 36 or Figure 37 for the functionality of this bit.
#define CPOL_BIT 3
#define CPOL_MASK 8
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.
#define MSTR_BIT 4
#define MSTR_MASK 16
This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.
#define DORD_BIT 5
#define DORD_MASK 32
When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.
#define SPE_BIT 6
#define SPE_MASK 64
When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.
#define SPIE_BIT 7
#define SPIE_MASK 128
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.
sfrb SPSR = $2D;
#define SPI2X_BIT 0
#define SPI2X_MASK 1
When this bit is written logic one the SPI speed (SCK Frequency)will be doubled when the SPI is in master mode .This means that the minimum SCK period will be 2 CPU clock periods.When the SPI is configured as Slave,the SPI is only guaranteed to work at f osc /4orlower. The SPI interface on the ATmega162 is also used for program memory and EEPROM downloading or uploading.
#define WCOL_BIT 6
#define WCOL_MASK 64
The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.
#define SPIF_BIT 7
#define SPIF_MASK 128
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).
sfrb SPDR = $2E;
#define SPDR0_BIT 0
#define SPDR0_MASK 1
#define SPDR1_BIT 1
#define SPDR1_MASK 2
#define SPDR2_BIT 2
#define SPDR2_MASK 4
#define SPDR3_BIT 3
#define SPDR3_MASK 8
#define SPDR4_BIT 4
#define SPDR4_MASK 16
#define SPDR5_BIT 5
#define SPDR5_MASK 32
#define SPDR6_BIT 6
#define SPDR6_MASK 64
#define SPDR7_BIT 7
#define SPDR7_MASK 128
sfrb WDTCSR = $60;
#define WDP0_BIT 0
#define WDP0_MASK 1
#define WDP1_BIT 1
#define WDP1_MASK 2
#define WDP2_BIT 2
#define WDP2_MASK 4
#define WDE_BIT 3
#define WDE_MASK 8
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog
#define WDCE_BIT 4
#define WDCE_MASK 16
#define WDP3_BIT 5
#define WDP3_MASK 32
#define WDIE_BIT 6
#define WDIE_MASK 64
#define WDIF_BIT 7
#define WDIF_MASK 128
The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in “Clock Systems and their Distribution” on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt
sfrb EICRA = $69;
#define ISC00_BIT 0
#define ISC00_MASK 1
#define ISC01_BIT 1
#define ISC01_MASK 2
#define ISC10_BIT 2
#define ISC10_MASK 4
#define ISC11_BIT 3
#define ISC11_MASK 8
#define ISC20_BIT 4
#define ISC20_MASK 16
#define ISC21_BIT 5
#define ISC21_MASK 32
sfrb EIMSK = $1D;
#define INT0_BIT 0
#define INT0_MASK 1
#define INT1_BIT 1
#define INT1_MASK 2
#define INT2_BIT 2
#define INT2_MASK 4
sfrb EIFR = $1C;
#define INTF0_BIT 0
#define INTF0_MASK 1
#define INTF1_BIT 1
#define INTF1_MASK 2
#define INTF2_BIT 2
#define INTF2_MASK 4