This documentation was generated automatically from the AVR Studio part description file AT90S8535.pdf
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The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in “Timer/Counter0 Control Register - TCCR0” on page 35. The overflow status flag is found in “The Timer/Counter Interrupt Flag Register - TIFR” on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in “The Timer/Counter Interrupt Mask Regis-ter - TIMSK” on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions
sfrb TIMSK = $39;
#define TOIE0_BIT 0
#define TOIE0_MASK 1
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
sfrb TIFR = $38;
#define TOV0_BIT 0
#define TOV0_MASK 1
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.
sfrb TCCR0 = $33;
#define CS00_BIT 0
#define CS00_MASK 1
#define CS01_BIT 1
#define CS01_MASK 2
#define CS02_BIT 2
#define CS02_MASK 4
sfrb TCNT0 = $32;
#define TCNT00_BIT 0
#define TCNT00_MASK 1
#define TCNT01_BIT 1
#define TCNT01_MASK 2
#define TCNT02_BIT 2
#define TCNT02_MASK 4
#define TCNT03_BIT 3
#define TCNT03_MASK 8
#define TCNT04_BIT 4
#define TCNT04_MASK 16
#define TCNT05_BIT 5
#define TCNT05_MASK 32
#define TCNT06_BIT 6
#define TCNT06_MASK 64
#define TCNT07_BIT 7
#define TCNT07_MASK 128
The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in the specification for the Timer/Counter1 Control Registers - TCCR1A and TCCR1B. The different status flags (overflow, compare match and capture event) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter1 Control Registers - TCCR1A and TCCR1B. The interrupt enable/disable settings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register - TIMS
sfrb TIMSK = $39;
#define TOIE1_BIT 2
#define TOIE1_MASK 4
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define OCIE1B_BIT 3
#define OCIE1B_MASK 8
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define OCIE1A_BIT 4
#define OCIE1A_MASK 16
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define TICIE1_BIT 5
#define TICIE1_MASK 32
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
sfrb TIFR = $38;
#define TOV1_BIT 2
#define TOV1_MASK 4
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.
#define OCF1B_BIT 3
#define OCF1B_MASK 8
The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.
#define OCF1A_BIT 4
#define OCF1A_MASK 16
The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed.
#define ICF1_BIT 5
#define ICF1_MASK 32
The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.
sfrb TCCR1A = $2F;
#define PWM10_BIT 0
#define PWM10_MASK 1
#define PWM11_BIT 1
#define PWM11_MASK 2
#define COM1B0_BIT 4
#define COM1B0_MASK 16
The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB.
#define COM1B1_BIT 5
#define COM1B1_MASK 32
The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB.
#define COM1A0_BIT 6
#define COM1A0_MASK 64
The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in Table 9.
#define COM1A1_BIT 7
#define COM1A1_MASK 128
The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in Table 9.
sfrb TCCR1B = $2E;
#define CS10_BIT 0
#define CS10_MASK 1
#define CS11_BIT 1
#define CS11_MASK 2
#define CS12_BIT 2
#define CS12_MASK 4
#define CTC1_BIT 3
#define CTC1_MASK 8
When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match. Since the compare match is detected in the CPU clock cycle following the match, this function will behave differently when a prescal-ing higher than 1 is used for the timer. When a prescaling of 1 is used, and the compareA register is set to C, the timer will count as follows if CTC1 is set: ...|C-2 |C-1 |C |0|1 |... When the prescaler is set to divide by 8, the timer will count like this: ... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0, 0, 0, 0, 0, 0, 0 | ... In PWM mode, this bit has no effect
#define ICES1_BIT 6
#define ICES1_MASK 64
While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.
#define ICNC1_BIT 7
#define ICNC1_MASK 128
When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.
sfrb TCNT1H = $2D;
#define TCNT1H0_BIT 0
#define TCNT1H0_MASK 1
#define TCNT1H1_BIT 1
#define TCNT1H1_MASK 2
#define TCNT1H2_BIT 2
#define TCNT1H2_MASK 4
#define TCNT1H3_BIT 3
#define TCNT1H3_MASK 8
#define TCNT1H4_BIT 4
#define TCNT1H4_MASK 16
#define TCNT1H5_BIT 5
#define TCNT1H5_MASK 32
#define TCNT1H6_BIT 6
#define TCNT1H6_MASK 64
#define TCNT1H7_BIT 7
#define TCNT1H7_MASK 128
sfrb TCNT1L = $2C;
#define TCNT1L0_BIT 0
#define TCNT1L0_MASK 1
#define TCNT1L1_BIT 1
#define TCNT1L1_MASK 2
#define TCNT1L2_BIT 2
#define TCNT1L2_MASK 4
#define TCNT1L3_BIT 3
#define TCNT1L3_MASK 8
#define TCNT1L4_BIT 4
#define TCNT1L4_MASK 16
#define TCNT1L5_BIT 5
#define TCNT1L5_MASK 32
#define TCNT1L6_BIT 6
#define TCNT1L6_MASK 64
#define TCNT1L7_BIT 7
#define TCNT1L7_MASK 128
sfrb OCR1AH = $2B;
#define OCR1AH0_BIT 0
#define OCR1AH0_MASK 1
#define OCR1AH1_BIT 1
#define OCR1AH1_MASK 2
#define OCR1AH2_BIT 2
#define OCR1AH2_MASK 4
#define OCR1AH3_BIT 3
#define OCR1AH3_MASK 8
#define OCR1AH4_BIT 4
#define OCR1AH4_MASK 16
#define OCR1AH5_BIT 5
#define OCR1AH5_MASK 32
#define OCR1AH6_BIT 6
#define OCR1AH6_MASK 64
#define OCR1AH7_BIT 7
#define OCR1AH7_MASK 128
sfrb OCR1AL = $2A;
#define OCR1AL0_BIT 0
#define OCR1AL0_MASK 1
#define OCR1AL1_BIT 1
#define OCR1AL1_MASK 2
#define OCR1AL2_BIT 2
#define OCR1AL2_MASK 4
#define OCR1AL3_BIT 3
#define OCR1AL3_MASK 8
#define OCR1AL4_BIT 4
#define OCR1AL4_MASK 16
#define OCR1AL5_BIT 5
#define OCR1AL5_MASK 32
#define OCR1AL6_BIT 6
#define OCR1AL6_MASK 64
#define OCR1AL7_BIT 7
#define OCR1AL7_MASK 128
sfrb OCR1BH = $29;
#define OCR1BH0_BIT 0
#define OCR1BH0_MASK 1
#define OCR1BH1_BIT 1
#define OCR1BH1_MASK 2
#define OCR1BH2_BIT 2
#define OCR1BH2_MASK 4
#define OCR1BH3_BIT 3
#define OCR1BH3_MASK 8
#define OCR1BH4_BIT 4
#define OCR1BH4_MASK 16
#define OCR1BH5_BIT 5
#define OCR1BH5_MASK 32
#define OCR1BH6_BIT 6
#define OCR1BH6_MASK 64
#define OCR1BH7_BIT 7
#define OCR1BH7_MASK 128
sfrb OCR1BL = $28;
#define OCR1BL0_BIT 0
#define OCR1BL0_MASK 1
#define OCR1BL1_BIT 1
#define OCR1BL1_MASK 2
#define OCR1BL2_BIT 2
#define OCR1BL2_MASK 4
#define OCR1BL3_BIT 3
#define OCR1BL3_MASK 8
#define OCR1BL4_BIT 4
#define OCR1BL4_MASK 16
#define OCR1BL5_BIT 5
#define OCR1BL5_MASK 32
#define OCR1BL6_BIT 6
#define OCR1BL6_MASK 64
#define OCR1BL7_BIT 7
#define OCR1BL7_MASK 128
sfrb ICR1H = $27;
#define ICR1H0_BIT 0
#define ICR1H0_MASK 1
#define ICR1H1_BIT 1
#define ICR1H1_MASK 2
#define ICR1H2_BIT 2
#define ICR1H2_MASK 4
#define ICR1H3_BIT 3
#define ICR1H3_MASK 8
#define ICR1H4_BIT 4
#define ICR1H4_MASK 16
#define ICR1H5_BIT 5
#define ICR1H5_MASK 32
#define ICR1H6_BIT 6
#define ICR1H6_MASK 64
#define ICR1H7_BIT 7
#define ICR1H7_MASK 128
sfrb ICR1L = $26;
#define ICR1L0_BIT 0
#define ICR1L0_MASK 1
#define ICR1L1_BIT 1
#define ICR1L1_MASK 2
#define ICR1L2_BIT 2
#define ICR1L2_MASK 4
#define ICR1L3_BIT 3
#define ICR1L3_MASK 8
#define ICR1L4_BIT 4
#define ICR1L4_MASK 16
#define ICR1L5_BIT 5
#define ICR1L5_MASK 32
#define ICR1L6_BIT 6
#define ICR1L6_MASK 64
#define ICR1L7_BIT 7
#define ICR1L7_MASK 128
sfrb TCCR2 = $25;
#define CS20_BIT 0
#define CS20_MASK 1
The three clock select bits select the clock source to be used by the Timer/Counter.
#define CS21_BIT 1
#define CS21_MASK 2
The three clock select bits select the clock source to be used by the Timer/Counter.
#define CS22_BIT 2
#define CS22_MASK 4
The three clock select bits select the clock source to be used by the Timer/Counter.
#define CTC2_BIT 3
#define CTC2_MASK 8
Please refer to manual.
#define COM20_BIT 4
#define COM20_MASK 16
These bits control the output compare pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 64 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM)
#define COM21_BIT 5
#define COM21_MASK 32
These bits control the output compare pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 64 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM).
#define PWM2_BIT 6
#define PWM2_MASK 64
When set (one), this bit enables PWM mode for Timer/Counter2.
sfrb TCNT2 = $24;
#define TCNT2_0_BIT 0
#define TCNT2_0_MASK 1
#define TCNT2_1_BIT 1
#define TCNT2_1_MASK 2
#define TCNT2_2_BIT 2
#define TCNT2_2_MASK 4
#define TCNT2_3_BIT 3
#define TCNT2_3_MASK 8
#define TCNT2_4_BIT 4
#define TCNT2_4_MASK 16
#define TCNT2_5_BIT 5
#define TCNT2_5_MASK 32
#define TCNT2_6_BIT 6
#define TCNT2_6_MASK 64
#define TCNT2_7_BIT 7
#define TCNT2_7_MASK 128
sfrb OCR2 = $23;
#define OCR2_0_BIT 0
#define OCR2_0_MASK 1
#define OCR2_1_BIT 1
#define OCR2_1_MASK 2
#define OCR2_2_BIT 2
#define OCR2_2_MASK 4
#define OCR2_3_BIT 3
#define OCR2_3_MASK 8
#define OCR2_4_BIT 4
#define OCR2_4_MASK 16
#define OCR2_5_BIT 5
#define OCR2_5_MASK 32
#define OCR2_6_BIT 6
#define OCR2_6_MASK 64
#define OCR2_7_BIT 7
#define OCR2_7_MASK 128
sfrb ASSR = $22;
#define TCR2UB_BIT 0
#define TCR2UB_MASK 1
When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set (one). When TCCR2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical “0” in this bit indicates that TCCR2 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter2 registers while its Update Busy flag is set (one), the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2 and TCCR2 are different. When reading TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary storage register is rea
#define OCR2UB_BIT 1
#define OCR2UB_MASK 2
When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set (one). When OCR2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical “0” in this bit indicates that OCR2 is ready to be updated with a new value.
#define TCN2UB_BIT 2
#define TCN2UB_MASK 4
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set (one). When TCNT2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical “0” in this bit indicates that TCNT2 is ready to be updated with a new value.
#define AS2_BIT 3
#define AS2_MASK 8
When AS2 is set (one), Timer/Counter2 is clocked from the TOSC1 pin. Pins PC6 and PC7 become connected to a crystal oscillator and cannot be used as general I/O pins. When cleared (zero), Timer/Counter2 is clocked from the internal system clock, CK. When the value of this bit is changed, the contents of TCNT2, OCR2 and TCCR2 might get corrupted.
sfrb TIMSK = $39;
#define TOIE2_BIT 6
#define TOIE2_MASK 64
When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter2 occurs (i.e., when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
#define OCIE2_BIT 7
#define OCIE2_MASK 128
When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match inter-rupt is enabled. The corresponding interrupt (at vector $003) is executed if a compare match in Timer/Counter2 occurs (i.e., when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
sfrb TIFR = $38;
#define TOV2_BIT 6
#define TOV2_MASK 64
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE2 (Timer/Counter2 Overf low Interrupt Enable) and TOV2 are set (one), the Timer/Counter2 Overflow Interrupt is executed. In up/down PWM mode, this bit is set when Timer/Counter1 advances from $0000.
#define OCF2_BIT 7
#define OCF2_MASK 128
The OCF2 bit is set (one) when compare match occurs between the Timer/Counter2 and the data in OCR2 (Output Compare Register2). OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE2 (Timer/Counter2 Compare Match Interrupt Enable) and the OCF2 are set (one), the Timer/Counter2 Compare Match Interrupt is executed.
sfrb UDR = $0C;
#define UDR0_BIT 0
#define UDR0_MASK 1
#define UDR1_BIT 1
#define UDR1_MASK 2
#define UDR2_BIT 2
#define UDR2_MASK 4
#define UDR3_BIT 3
#define UDR3_MASK 8
#define UDR4_BIT 4
#define UDR4_MASK 16
#define UDR5_BIT 5
#define UDR5_MASK 32
#define UDR6_BIT 6
#define UDR6_MASK 64
#define UDR7_BIT 7
#define UDR7_MASK 128
sfrb USR = $0B;
#define OR_BIT 3
#define OR_MASK 8
This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR register is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDRE is read. The OR bit is cleared (zero) when data is received and transferred to UDR.
#define FE_BIT 4
#define FE_MASK 16
This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.
#define UDRE_BIT 5
#define UDRE_MASK 32
This bit is set (one) when a character written to UDR is transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be executed as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven data transmittal is used, the UART Data Register Empty Interrupt routine must write UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt routine terminates. UDRE is set (one) during reset to indicate that the transmitter is ready
#define TXC_BIT 6
#define TXC_MASK 64
This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bit
#define RXC_BIT 7
#define RXC_MASK 128
This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the UART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR. When interrupt-driven data reception is used, the UART Receive Complete Interrupt routine must read UDR in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.
sfrb UCR = $0A;
#define TXB8_BIT 0
#define TXB8_MASK 1
When CHR9 is set (one), TXB8 is the 9th data bit in the character to be transmitted.
#define RXB8_BIT 1
#define RXB8_MASK 2
When CHR9 is set (one), RXB8 is the 9th data bit of the received character.
#define CHR9_BIT 2
#define CHR9_MASK 4
When this bit is set (one) transmitted and received characters are 9 bit long plus start and stop bits. The 9th bit is read and written by using the RXB8 and TXB8 bits in UCR, respectively. The 9th data bit can be used as an extra stop bit or a parity bit.
#define TXEN_BIT 3
#define TXEN_MASK 8
This bit enables the UART transmitter when set (one). When disabling the transmitter while transmitting a character, the transmitter is not disabled before the character in the shift register plus any following character in UDR has been completely transmitted.
#define RXEN_BIT 4
#define RXEN_MASK 16
This bit enables the UART receiver when set (one). When the receiver is disabled, the TXC, OR and FE status flags cannot become set. If these flags are set, turning off RXEN does not cause them to be cleared.
#define UDRIE_BIT 5
#define UDRIE_MASK 32
When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data Register Empty interrupt routine to be executed provided that global interrupts are enabled.
#define TXCIE_BIT 6
#define TXCIE_MASK 64
When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Complete interrupt routine to be executed provided that global interrupts are enabled.
#define RXCIE_BIT 7
#define RXCIE_MASK 128
When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Complete interrupt routine to be executed provided that global interrupts are enabled.
sfrb UBRR = $09;
#define UBRR0_BIT 0
#define UBRR0_MASK 1
#define UBRR1_BIT 1
#define UBRR1_MASK 2
#define UBRR2_BIT 2
#define UBRR2_MASK 4
#define UBRR3_BIT 3
#define UBRR3_MASK 8
#define UBRR4_BIT 4
#define UBRR4_MASK 16
#define UBRR5_BIT 5
#define UBRR5_MASK 32
#define UBRR6_BIT 6
#define UBRR6_MASK 64
#define UBRR7_BIT 7
#define UBRR7_MASK 128
The Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Four Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wakeup from Idle Mode (Slave Mode Only)
sfrb SPCR = $0D;
#define SPR0_BIT 0
#define SPR0_MASK 1
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.
#define SPR1_BIT 1
#define SPR1_MASK 2
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.
#define CPHA_BIT 2
#define CPHA_MASK 4
Refer to Figure 36 or Figure 37 for the functionality of this bit.
#define CPOL_BIT 3
#define CPOL_MASK 8
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.
#define MSTR_BIT 4
#define MSTR_MASK 16
This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.
#define DORD_BIT 5
#define DORD_MASK 32
When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.
#define SPE_BIT 6
#define SPE_MASK 64
When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.
#define SPIE_BIT 7
#define SPIE_MASK 128
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.
sfrb SPSR = $0E;
#define WCOL_BIT 6
#define WCOL_MASK 64
The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.
#define SPIF_BIT 7
#define SPIF_MASK 128
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).
sfrb SPDR = $0F;
#define SPDR0_BIT 0
#define SPDR0_MASK 1
#define SPDR1_BIT 1
#define SPDR1_MASK 2
#define SPDR2_BIT 2
#define SPDR2_MASK 4
#define SPDR3_BIT 3
#define SPDR3_MASK 8
#define SPDR4_BIT 4
#define SPDR4_MASK 16
#define SPDR5_BIT 5
#define SPDR5_MASK 32
#define SPDR6_BIT 6
#define SPDR6_MASK 64
#define SPDR7_BIT 7
#define SPDR7_MASK 128
sfrb PORTA = $1B;
#define PORTA0_BIT 0
#define PORTA0_MASK 1
#define PORTA1_BIT 1
#define PORTA1_MASK 2
#define PORTA2_BIT 2
#define PORTA2_MASK 4
#define PORTA3_BIT 3
#define PORTA3_MASK 8
#define PORTA4_BIT 4
#define PORTA4_MASK 16
#define PORTA5_BIT 5
#define PORTA5_MASK 32
#define PORTA6_BIT 6
#define PORTA6_MASK 64
#define PORTA7_BIT 7
#define PORTA7_MASK 128
sfrb DDRA = $1A;
#define DDA0_BIT 0
#define DDA0_MASK 1
#define DDA1_BIT 1
#define DDA1_MASK 2
#define DDA2_BIT 2
#define DDA2_MASK 4
#define DDA3_BIT 3
#define DDA3_MASK 8
#define DDA4_BIT 4
#define DDA4_MASK 16
#define DDA5_BIT 5
#define DDA5_MASK 32
#define DDA6_BIT 6
#define DDA6_MASK 64
#define DDA7_BIT 7
#define DDA7_MASK 128
sfrb PINA = $19;
#define PINA0_BIT 0
#define PINA0_MASK 1
#define PINA1_BIT 1
#define PINA1_MASK 2
#define PINA2_BIT 2
#define PINA2_MASK 4
#define PINA3_BIT 3
#define PINA3_MASK 8
#define PINA4_BIT 4
#define PINA4_MASK 16
#define PINA5_BIT 5
#define PINA5_MASK 32
#define PINA6_BIT 6
#define PINA6_MASK 64
#define PINA7_BIT 7
#define PINA7_MASK 128
sfrb PORTB = $18;
#define PORTB0_BIT 0
#define PORTB0_MASK 1
#define PORTB1_BIT 1
#define PORTB1_MASK 2
#define PORTB2_BIT 2
#define PORTB2_MASK 4
#define PORTB3_BIT 3
#define PORTB3_MASK 8
#define PORTB4_BIT 4
#define PORTB4_MASK 16
#define PORTB5_BIT 5
#define PORTB5_MASK 32
#define PORTB6_BIT 6
#define PORTB6_MASK 64
#define PORTB7_BIT 7
#define PORTB7_MASK 128
sfrb DDRB = $17;
#define DDB0_BIT 0
#define DDB0_MASK 1
#define DDB1_BIT 1
#define DDB1_MASK 2
#define DDB2_BIT 2
#define DDB2_MASK 4
#define DDB3_BIT 3
#define DDB3_MASK 8
#define DDB4_BIT 4
#define DDB4_MASK 16
#define DDB5_BIT 5
#define DDB5_MASK 32
#define DDB6_BIT 6
#define DDB6_MASK 64
#define DDB7_BIT 7
#define DDB7_MASK 128
sfrb PINB = $16;
#define PINB0_BIT 0
#define PINB0_MASK 1
#define PINB1_BIT 1
#define PINB1_MASK 2
#define PINB2_BIT 2
#define PINB2_MASK 4
#define PINB3_BIT 3
#define PINB3_MASK 8
#define PINB4_BIT 4
#define PINB4_MASK 16
#define PINB5_BIT 5
#define PINB5_MASK 32
#define PINB6_BIT 6
#define PINB6_MASK 64
#define PINB7_BIT 7
#define PINB7_MASK 128
sfrb PORTC = $15;
#define PORTC0_BIT 0
#define PORTC0_MASK 1
#define PORTC1_BIT 1
#define PORTC1_MASK 2
#define PORTC2_BIT 2
#define PORTC2_MASK 4
#define PORTC3_BIT 3
#define PORTC3_MASK 8
#define PORTC4_BIT 4
#define PORTC4_MASK 16
#define PORTC5_BIT 5
#define PORTC5_MASK 32
#define PORTC6_BIT 6
#define PORTC6_MASK 64
#define PORTC7_BIT 7
#define PORTC7_MASK 128
sfrb DDRC = $14;
#define DDC0_BIT 0
#define DDC0_MASK 1
#define DDC1_BIT 1
#define DDC1_MASK 2
#define DDC2_BIT 2
#define DDC2_MASK 4
#define DDC3_BIT 3
#define DDC3_MASK 8
#define DDC4_BIT 4
#define DDC4_MASK 16
#define DDC5_BIT 5
#define DDC5_MASK 32
#define DDC6_BIT 6
#define DDC6_MASK 64
#define DDC7_BIT 7
#define DDC7_MASK 128
sfrb PINC = $13;
#define PINC0_BIT 0
#define PINC0_MASK 1
#define PINC1_BIT 1
#define PINC1_MASK 2
#define PINC2_BIT 2
#define PINC2_MASK 4
#define PINC3_BIT 3
#define PINC3_MASK 8
#define PINC4_BIT 4
#define PINC4_MASK 16
#define PINC5_BIT 5
#define PINC5_MASK 32
#define PINC6_BIT 6
#define PINC6_MASK 64
#define PINC7_BIT 7
#define PINC7_MASK 128
sfrb PORTD = $12;
#define PORTD0_BIT 0
#define PORTD0_MASK 1
#define PORTD1_BIT 1
#define PORTD1_MASK 2
#define PORTD2_BIT 2
#define PORTD2_MASK 4
#define PORTD3_BIT 3
#define PORTD3_MASK 8
#define PORTD4_BIT 4
#define PORTD4_MASK 16
#define PORTD5_BIT 5
#define PORTD5_MASK 32
#define PORTD6_BIT 6
#define PORTD6_MASK 64
#define PORTD7_BIT 7
#define PORTD7_MASK 128
sfrb DDRD = $11;
#define DDD0_BIT 0
#define DDD0_MASK 1
#define DDD1_BIT 1
#define DDD1_MASK 2
#define DDD2_BIT 2
#define DDD2_MASK 4
#define DDD3_BIT 3
#define DDD3_MASK 8
#define DDD4_BIT 4
#define DDD4_MASK 16
#define DDD5_BIT 5
#define DDD5_MASK 32
#define DDD6_BIT 6
#define DDD6_MASK 64
#define DDD7_BIT 7
#define DDD7_MASK 128
sfrb PIND = $10;
#define PIND0_BIT 0
#define PIND0_MASK 1
#define PIND1_BIT 1
#define PIND1_MASK 2
#define PIND2_BIT 2
#define PIND2_MASK 4
#define PIND3_BIT 3
#define PIND3_MASK 8
#define PIND4_BIT 4
#define PIND4_MASK 16
#define PIND5_BIT 5
#define PIND5_MASK 32
#define PIND6_BIT 6
#define PIND6_MASK 64
#define PIND7_BIT 7
#define PIND7_MASK 128
The analog comparator compares the input values on the positive input PB2 (AIN0) and negative input PB3 (AIN1). When the voltage on the positive input PB2 (AIN0) is higher than the voltage on the negative input PB3 (AIN1), the Analog Com-parator Output, ACO is set (one). The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Inter-rupt triggering on comparator output rise, fall or toggle
sfrb ACSR = $08;
#define ACIS0_BIT 0
#define ACIS0_MASK 1
These bits determine which comparator events that trigger the Analog Comparator interrupt.
#define ACIS1_BIT 1
#define ACIS1_MASK 2
These bits determine which comparator events that trigger the Analog Comparator interrupt.
#define ACIC_BIT 2
#define ACIC_MASK 4
When set (one), this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When cleared (zero), no connection between the analog comparator and the Input Capture function is given. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one)
#define ACIE_BIT 3
#define ACIE_MASK 8
When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the analog comparator interrupt is activated. When Cleared (Zero), the interrupt is disabled.
#define ACI_BIT 4
#define ACI_MASK 16
This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. Observe however, that if another bit in this register is modified using the SBI or CBI instruction, ACI will be cleared if it has become set before the operation
#define ACO_BIT 5
#define ACO_MASK 32
When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
#define ACD_BIT 7
#define ACD_MASK 128
When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode Noise
sfrb ADMUX = $07;
#define MUX0_BIT 0
#define MUX0_MASK 1
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
#define MUX1_BIT 1
#define MUX1_MASK 2
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
#define MUX2_BIT 2
#define MUX2_MASK 4
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
sfrb ADCSR = $06;
#define ADPS0_BIT 0
#define ADPS0_MASK 1
These bits determine the division factor between the XTAL frequency and the input clock to the ADC.
#define ADPS1_BIT 1
#define ADPS1_MASK 2
These bits determine the division factor between the XTAL frequency and the input clock to the ADC.
#define ADPS2_BIT 2
#define ADPS2_MASK 4
These bits determine the division factor between the XTAL frequency and the input clock to the ADC.
#define ADIE_BIT 3
#define ADIE_MASK 8
When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.
#define ADIF_BIT 4
#define ADIF_MASK 16
This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.
#define ADFR_BIT 5
#define ADFR_MASK 32
When this bit is set (one) the ADC operates in Free Running Mode. In this mode, the ADC samples and updates the data registers continuously. Clearing this bit (zero) will terminate Free Running Mode.
#define ADSC_BIT 6
#define ADSC_MASK 64
In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect
#define ADEN_BIT 7
#define ADEN_MASK 128
Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
sfrb ADCH = $05;
#define ADC8_BIT 0
#define ADC8_MASK 1
#define ADC9_BIT 1
#define ADC9_MASK 2
sfrb ADCL = $04;
#define ADC0_BIT 0
#define ADC0_MASK 1
#define ADC1_BIT 1
#define ADC1_MASK 2
#define ADC2_BIT 2
#define ADC2_MASK 4
#define ADC3_BIT 3
#define ADC3_MASK 8
#define ADC4_BIT 4
#define ADC4_MASK 16
#define ADC5_BIT 5
#define ADC5_MASK 32
#define ADC6_BIT 6
#define ADC6_MASK 64
#define ADC7_BIT 7
#define ADC7_MASK 128
sfrb WDTCR = $21;
#define WDP0_BIT 0
#define WDP0_MASK 1
#define WDP1_BIT 1
#define WDP1_MASK 2
#define WDP2_BIT 2
#define WDP2_MASK 4
#define WDE_BIT 3
#define WDE_MASK 8
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog
#define WDTOE_BIT 4
#define WDTOE_MASK 16
This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.
EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execute
sfrb EEARH = $1F;
#define EEAR8_BIT 0
#define EEAR8_MASK 1
sfrb EEARL = $1E;
#define EEAR0_BIT 0
#define EEAR0_MASK 1
#define EEAR1_BIT 1
#define EEAR1_MASK 2
#define EEAR2_BIT 2
#define EEAR2_MASK 4
#define EEAR3_BIT 3
#define EEAR3_MASK 8
#define EEAR4_BIT 4
#define EEAR4_MASK 16
#define EEAR5_BIT 5
#define EEAR5_MASK 32
#define EEAR6_BIT 6
#define EEAR6_MASK 64
#define EEAR7_BIT 7
#define EEAR7_MASK 128
sfrb EEDR = $1D;
#define EEDR0_BIT 0
#define EEDR0_MASK 1
#define EEDR1_BIT 1
#define EEDR1_MASK 2
#define EEDR2_BIT 2
#define EEDR2_MASK 4
#define EEDR3_BIT 3
#define EEDR3_MASK 8
#define EEDR4_BIT 4
#define EEDR4_MASK 16
#define EEDR5_BIT 5
#define EEDR5_MASK 32
#define EEDR6_BIT 6
#define EEDR6_MASK 64
#define EEDR7_BIT 7
#define EEDR7_MASK 128
sfrb EECR = $1C;
#define EERE_BIT 0
#define EERE_MASK 1
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU
#define EEWE_BIT 1
#define EEWE_MASK 2
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed
#define EEMWE_BIT 2
#define EEMWE_MASK 4
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.
#define EERIE_BIT 3
#define EERIE_MASK 8
EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.
sfrb SREG = $3F;
sfrb SPH = $3E;
#define SP8_BIT 0
#define SP8_MASK 1
#define SP9_BIT 1
#define SP9_MASK 2
sfrb SPL = $3D;
#define SP0_BIT 0
#define SP0_MASK 1
#define SP1_BIT 1
#define SP1_MASK 2
#define SP2_BIT 2
#define SP2_MASK 4
#define SP3_BIT 3
#define SP3_MASK 8
#define SP4_BIT 4
#define SP4_MASK 16
#define SP5_BIT 5
#define SP5_MASK 32
#define SP6_BIT 6
#define SP6_MASK 64
#define SP7_BIT 7
#define SP7_MASK 128
sfrb MCUCR = $35;
#define ISC00_BIT 0
#define ISC00_MASK 1
#define ISC01_BIT 1
#define ISC01_MASK 2
#define ISC10_BIT 2
#define ISC10_MASK 4
#define ISC11_BIT 3
#define ISC11_MASK 8
#define SM0_BIT 4
#define SM0_MASK 16
SM1 and SM0 selects between different sleep modes. Please refer to the manual for further details.
#define SM1_BIT 5
#define SM1_MASK 32
SM1 and SM0 selects between different sleep modes. Please refer to the manual for further details.
#define SE_BIT 6
#define SE_MASK 64
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.
sfrb MCUSR = $34;
#define PORF_BIT 0
#define PORF_MASK 1
#define EXTRF_BIT 1
#define EXTRF_MASK 2
sfrb GIMSK = $3B;
#define INT0_BIT 6
#define INT0_MASK 64
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bits
#define INT1_BIT 7
#define INT1_MASK 128
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory address $002. See also “External Interrupts”.
sfrb GIFR = $3A;
#define INTF0_BIT 6
#define INTF0_MASK 64
When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
#define INTF1_BIT 7
#define INTF1_MASK 128
When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $002. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.