This documentation was generated automatically from the AVR Studio part description file ATmega161.pdf
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sfrb ACSR = $08;
#define ACIS0_BIT 0
#define ACIS0_MASK 1
These bits determine which comparator events that trigger the Analog Comparator interrupt.
#define ACIS1_BIT 1
#define ACIS1_MASK 2
These bits determine which comparator events that trigger the Analog Comparator interrupt.
#define ACIC_BIT 2
#define ACIC_MASK 4
When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the analog comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set
#define ACIE_BIT 3
#define ACIE_MASK 8
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.
#define ACI_BIT 4
#define ACI_MASK 16
This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
#define ACO_BIT 5
#define ACO_MASK 32
The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.
#define AINBG_BIT 6
#define AINBG_MASK 64
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42.
#define ACD_BIT 7
#define ACD_MASK 128
When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the device and peripheral devices or between several AVR devices. The SPI includes the following features: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode
sfrb SPDR = $0F;
#define SPDR0_BIT 0
#define SPDR0_MASK 1
#define SPDR1_BIT 1
#define SPDR1_MASK 2
#define SPDR2_BIT 2
#define SPDR2_MASK 4
#define SPDR3_BIT 3
#define SPDR3_MASK 8
#define SPDR4_BIT 4
#define SPDR4_MASK 16
#define SPDR5_BIT 5
#define SPDR5_MASK 32
#define SPDR6_BIT 6
#define SPDR6_MASK 64
#define SPDR7_BIT 7
#define SPDR7_MASK 128
sfrb SPSR = $0E;
#define SPI2X_BIT 0
#define SPI2X_MASK 1
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in master mode (see Table 71). This means that the minimum SCK period will be 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f ck / 4 or lower. The SPI interface on the ATmega104 is also used for program memory and EEPROM downloading or uploading. See page 253 for serial programming and verification.
#define WCOL_BIT 6
#define WCOL_MASK 64
The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.
#define SPIF_BIT 7
#define SPIF_MASK 128
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).
sfrb SPCR = $0D;
#define SPR0_BIT 0
#define SPR0_MASK 1
#define SPR1_BIT 1
#define SPR1_MASK 2
#define CPHA_BIT 2
#define CPHA_MASK 4
Refer to Figure 36 or Figure 37 for the functionality of this bit.
#define CPOL_BIT 3
#define CPOL_MASK 8
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.
#define MSTR_BIT 4
#define MSTR_MASK 16
This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.
#define DORD_BIT 5
#define DORD_MASK 32
When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.
#define SPE_BIT 6
#define SPE_MASK 64
When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.
#define SPIE_BIT 7
#define SPIE_MASK 128
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Com
sfrb UDR0 = $0C;
#define UDR00_BIT 0
#define UDR00_MASK 1
#define UDR01_BIT 1
#define UDR01_MASK 2
#define UDR02_BIT 2
#define UDR02_MASK 4
#define UDR03_BIT 3
#define UDR03_MASK 8
#define UDR04_BIT 4
#define UDR04_MASK 16
#define UDR05_BIT 5
#define UDR05_MASK 32
#define UDR06_BIT 6
#define UDR06_MASK 64
#define UDR07_BIT 7
#define UDR07_MASK 128
sfrb UCSR0A = $0B;
#define MPCM0_BIT 0
#define MPCM0_MASK 1
This bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 152.
#define U2X0_BIT 1
#define U2X0_MASK 2
This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.
#define OR0_BIT 3
#define OR0_MASK 8
This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR0 register is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0.
#define FE0_BIT 4
#define FE0_MASK 16
This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.
#define UDRE0_BIT 5
#define UDRE0_MASK 32
This bit is set (one) when a character written to UDR0 is transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDR0 in order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is r
#define TXC0_BIT 6
#define TXC0_MASK 64
This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to t
#define RXC0_BIT 7
#define RXC0_MASK 128
This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regardless of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDR0 in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.
sfrb UCSR0B = $0A;
#define TXB80_BIT 0
#define TXB80_MASK 1
TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.
#define RXB80_BIT 1
#define RXB80_MASK 2
RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.
#define CHR90_BIT 2
#define CHR90_MASK 4
#define TXEN0_BIT 3
#define TXEN0_MASK 8
Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.
#define RXEN0_BIT 4
#define RXEN0_MASK 16
Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.
#define UDR0IE0_BIT 5
#define UDR0IE0_MASK 32
Writing this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.
#define TXCIE0_BIT 6
#define TXCIE0_MASK 64
Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.
#define RXCIE0_BIT 7
#define RXCIE0_MASK 128
Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.
sfrb UBRR0 = $09;
#define UBRR00_BIT 0
#define UBRR00_MASK 1
#define UBRR01_BIT 1
#define UBRR01_MASK 2
#define UBRR02_BIT 2
#define UBRR02_MASK 4
#define UBRR03_BIT 3
#define UBRR03_MASK 8
#define UBRR04_BIT 4
#define UBRR04_MASK 16
#define UBRR05_BIT 5
#define UBRR05_MASK 32
#define UBRR06_BIT 6
#define UBRR06_MASK 64
#define UBRR07_BIT 7
#define UBRR07_MASK 128
sfrb UBRRHI = $20;
#define UBRRHI00_BIT 0
#define UBRRHI00_MASK 1
#define UBRRHI01_BIT 1
#define UBRRHI01_MASK 2
#define UBRRHI02_BIT 2
#define UBRRHI02_MASK 4
#define UBRRHI03_BIT 3
#define UBRRHI03_MASK 8
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Com
sfrb UDR1 = $03;
#define UDR10_BIT 0
#define UDR10_MASK 1
#define UDR11_BIT 1
#define UDR11_MASK 2
#define UDR12_BIT 2
#define UDR12_MASK 4
#define UDR13_BIT 3
#define UDR13_MASK 8
#define UDR14_BIT 4
#define UDR14_MASK 16
#define UDR15_BIT 5
#define UDR15_MASK 32
#define UDR16_BIT 6
#define UDR16_MASK 64
#define UDR17_BIT 7
#define UDR17_MASK 128
sfrb UCSR1A = $02;
#define MPCM1_BIT 0
#define MPCM1_MASK 1
This bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 152.
#define U2X1_BIT 1
#define U2X1_MASK 2
This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.
#define OR1_BIT 3
#define OR1_MASK 8
This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR1 register is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR1E is read. The OR bit is cleared (zero) when data is received and transferred to UDR1.
#define FE1_BIT 4
#define FE1_MASK 16
This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.
#define UDRE1_BIT 5
#define UDRE1_MASK 32
This bit is set (one) when a character written to UDR1 is transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR1IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR1E is set. UDR1E is cleared by writing UDR1. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDR1 in order to clear UDR1E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR1E is set (one) during reset to indicate that the transmitter is
#define TXC1_BIT 6
#define TXC1_MASK 64
This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR1. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to
#define RXC1_BIT 7
#define RXC1_MASK 128
This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR1. The bit is set regardless of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR1. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDR1 in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.
sfrb UCSR1B = $01;
#define TXB81_BIT 0
#define TXB81_MASK 1
TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR1.
#define RXB81_BIT 1
#define RXB81_MASK 2
RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR1.
#define CHR91_BIT 2
#define CHR91_MASK 4
#define TXEN1_BIT 3
#define TXEN1_MASK 8
Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.
#define RXEN1_BIT 4
#define RXEN1_MASK 16
Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.
#define UDR1IE1_BIT 5
#define UDR1IE1_MASK 32
Writing this bit to one enables interrupt on the UDR1E flag. A Data Register Empty interrupt will be generated only if the UDR1IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR1E bit in UCSR1A is set.
#define TXCIE1_BIT 6
#define TXCIE1_MASK 64
Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR1A is set.
#define RXCIE1_BIT 7
#define RXCIE1_MASK 128
Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR1A is set.
sfrb UBRR1 = $00;
#define UBRR10_BIT 0
#define UBRR10_MASK 1
#define UBRR11_BIT 1
#define UBRR11_MASK 2
#define UBRR12_BIT 2
#define UBRR12_MASK 4
#define UBRR13_BIT 3
#define UBRR13_MASK 8
#define UBRR14_BIT 4
#define UBRR14_MASK 16
#define UBRR15_BIT 5
#define UBRR15_MASK 32
#define UBRR16_BIT 6
#define UBRR16_MASK 64
#define UBRR17_BIT 7
#define UBRR17_MASK 128
sfrb UBRRHI = $20;
#define UBRRHI10_BIT 4
#define UBRRHI10_MASK 16
#define UBRRHI11_BIT 5
#define UBRRHI11_MASK 32
#define UBRRHI12_BIT 6
#define UBRRHI12_MASK 64
#define UBRRHI13_BIT 7
#define UBRRHI13_MASK 128
sfrb PORTA = $1B;
#define PORTA0_BIT 0
#define PORTA0_MASK 1
#define PORTA1_BIT 1
#define PORTA1_MASK 2
#define PORTA2_BIT 2
#define PORTA2_MASK 4
#define PORTA3_BIT 3
#define PORTA3_MASK 8
#define PORTA4_BIT 4
#define PORTA4_MASK 16
#define PORTA5_BIT 5
#define PORTA5_MASK 32
#define PORTA6_BIT 6
#define PORTA6_MASK 64
#define PORTA7_BIT 7
#define PORTA7_MASK 128
sfrb DDRA = $1A;
#define DDA0_BIT 0
#define DDA0_MASK 1
#define DDA1_BIT 1
#define DDA1_MASK 2
#define DDA2_BIT 2
#define DDA2_MASK 4
#define DDA3_BIT 3
#define DDA3_MASK 8
#define DDA4_BIT 4
#define DDA4_MASK 16
#define DDA5_BIT 5
#define DDA5_MASK 32
#define DDA6_BIT 6
#define DDA6_MASK 64
#define DDA7_BIT 7
#define DDA7_MASK 128
sfrb PINA = $19;
#define PINA0_BIT 0
#define PINA0_MASK 1
#define PINA1_BIT 1
#define PINA1_MASK 2
#define PINA2_BIT 2
#define PINA2_MASK 4
#define PINA3_BIT 3
#define PINA3_MASK 8
#define PINA4_BIT 4
#define PINA4_MASK 16
#define PINA5_BIT 5
#define PINA5_MASK 32
#define PINA6_BIT 6
#define PINA6_MASK 64
#define PINA7_BIT 7
#define PINA7_MASK 128
sfrb PORTB = $18;
#define PORTB0_BIT 0
#define PORTB0_MASK 1
#define PORTB1_BIT 1
#define PORTB1_MASK 2
#define PORTB2_BIT 2
#define PORTB2_MASK 4
#define PORTB3_BIT 3
#define PORTB3_MASK 8
#define PORTB4_BIT 4
#define PORTB4_MASK 16
#define PORTB5_BIT 5
#define PORTB5_MASK 32
#define PORTB6_BIT 6
#define PORTB6_MASK 64
#define PORTB7_BIT 7
#define PORTB7_MASK 128
sfrb DDRB = $17;
#define DDB0_BIT 0
#define DDB0_MASK 1
#define DDB1_BIT 1
#define DDB1_MASK 2
#define DDB2_BIT 2
#define DDB2_MASK 4
#define DDB3_BIT 3
#define DDB3_MASK 8
#define DDB4_BIT 4
#define DDB4_MASK 16
#define DDB5_BIT 5
#define DDB5_MASK 32
#define DDB6_BIT 6
#define DDB6_MASK 64
#define DDB7_BIT 7
#define DDB7_MASK 128
sfrb PINB = $16;
#define PINB0_BIT 0
#define PINB0_MASK 1
#define PINB1_BIT 1
#define PINB1_MASK 2
#define PINB2_BIT 2
#define PINB2_MASK 4
#define PINB3_BIT 3
#define PINB3_MASK 8
#define PINB4_BIT 4
#define PINB4_MASK 16
#define PINB5_BIT 5
#define PINB5_MASK 32
#define PINB6_BIT 6
#define PINB6_MASK 64
#define PINB7_BIT 7
#define PINB7_MASK 128
sfrb PORTC = $15;
#define PORTC0_BIT 0
#define PORTC0_MASK 1
#define PORTC1_BIT 1
#define PORTC1_MASK 2
#define PORTC2_BIT 2
#define PORTC2_MASK 4
#define PORTC3_BIT 3
#define PORTC3_MASK 8
#define PORTC4_BIT 4
#define PORTC4_MASK 16
#define PORTC5_BIT 5
#define PORTC5_MASK 32
#define PORTC6_BIT 6
#define PORTC6_MASK 64
#define PORTC7_BIT 7
#define PORTC7_MASK 128
sfrb DDRC = $14;
#define DDC0_BIT 0
#define DDC0_MASK 1
#define DDC1_BIT 1
#define DDC1_MASK 2
#define DDC2_BIT 2
#define DDC2_MASK 4
#define DDC3_BIT 3
#define DDC3_MASK 8
#define DDC4_BIT 4
#define DDC4_MASK 16
#define DDC5_BIT 5
#define DDC5_MASK 32
#define DDC6_BIT 6
#define DDC6_MASK 64
#define DDC7_BIT 7
#define DDC7_MASK 128
sfrb PINC = $13;
#define PINC0_BIT 0
#define PINC0_MASK 1
#define PINC1_BIT 1
#define PINC1_MASK 2
#define PINC2_BIT 2
#define PINC2_MASK 4
#define PINC3_BIT 3
#define PINC3_MASK 8
#define PINC4_BIT 4
#define PINC4_MASK 16
#define PINC5_BIT 5
#define PINC5_MASK 32
#define PINC6_BIT 6
#define PINC6_MASK 64
#define PINC7_BIT 7
#define PINC7_MASK 128
sfrb PORTD = $12;
#define PORTD0_BIT 0
#define PORTD0_MASK 1
#define PORTD1_BIT 1
#define PORTD1_MASK 2
#define PORTD2_BIT 2
#define PORTD2_MASK 4
#define PORTD3_BIT 3
#define PORTD3_MASK 8
#define PORTD4_BIT 4
#define PORTD4_MASK 16
#define PORTD5_BIT 5
#define PORTD5_MASK 32
#define PORTD6_BIT 6
#define PORTD6_MASK 64
#define PORTD7_BIT 7
#define PORTD7_MASK 128
sfrb DDRD = $11;
#define DDD0_BIT 0
#define DDD0_MASK 1
#define DDD1_BIT 1
#define DDD1_MASK 2
#define DDD2_BIT 2
#define DDD2_MASK 4
#define DDD3_BIT 3
#define DDD3_MASK 8
#define DDD4_BIT 4
#define DDD4_MASK 16
#define DDD5_BIT 5
#define DDD5_MASK 32
#define DDD6_BIT 6
#define DDD6_MASK 64
#define DDD7_BIT 7
#define DDD7_MASK 128
sfrb PIND = $10;
#define PIND0_BIT 0
#define PIND0_MASK 1
#define PIND1_BIT 1
#define PIND1_MASK 2
#define PIND2_BIT 2
#define PIND2_MASK 4
#define PIND3_BIT 3
#define PIND3_MASK 8
#define PIND4_BIT 4
#define PIND4_MASK 16
#define PIND5_BIT 5
#define PIND5_MASK 32
#define PIND6_BIT 6
#define PIND6_MASK 64
#define PIND7_BIT 7
#define PIND7_MASK 128
sfrb PORTE = $07;
#define PORTE0_BIT 0
#define PORTE0_MASK 1
#define PORTE1_BIT 1
#define PORTE1_MASK 2
#define PORTE2_BIT 2
#define PORTE2_MASK 4
sfrb DDRE = $06;
#define DDE0_BIT 0
#define DDE0_MASK 1
#define DDE1_BIT 1
#define DDE1_MASK 2
#define DDE2_BIT 2
#define DDE2_MASK 4
sfrb PINE = $05;
#define PINE0_BIT 0
#define PINE0_MASK 1
#define PINE1_BIT 1
#define PINE1_MASK 2
#define PINE2_BIT 2
#define PINE2_MASK 4
EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execute
sfrb EEARH = $1F;
#define EEAR8_BIT 0
#define EEAR8_MASK 1
sfrb EEARL = $1E;
#define EEAR0_BIT 0
#define EEAR0_MASK 1
#define EEAR1_BIT 1
#define EEAR1_MASK 2
#define EEAR2_BIT 2
#define EEAR2_MASK 4
#define EEAR3_BIT 3
#define EEAR3_MASK 8
#define EEAR4_BIT 4
#define EEAR4_MASK 16
#define EEAR5_BIT 5
#define EEAR5_MASK 32
#define EEAR6_BIT 6
#define EEAR6_MASK 64
#define EEAR7_BIT 7
#define EEAR7_MASK 128
sfrb EEDR = $1D;
#define EEDR0_BIT 0
#define EEDR0_MASK 1
#define EEDR1_BIT 1
#define EEDR1_MASK 2
#define EEDR2_BIT 2
#define EEDR2_MASK 4
#define EEDR3_BIT 3
#define EEDR3_MASK 8
#define EEDR4_BIT 4
#define EEDR4_MASK 16
#define EEDR5_BIT 5
#define EEDR5_MASK 32
#define EEDR6_BIT 6
#define EEDR6_MASK 64
#define EEDR7_BIT 7
#define EEDR7_MASK 128
sfrb EECR = $1C;
#define EERE_BIT 0
#define EERE_MASK 1
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU
#define EEWE_BIT 1
#define EEWE_MASK 2
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed
#define EEMWE_BIT 2
#define EEMWE_MASK 4
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.
#define EERIE_BIT 3
#define EERIE_MASK 8
EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.
sfrb GIMSK = $3B;
#define INT2_BIT 5
#define INT2_MASK 32
#define INT0_BIT 6
#define INT0_MASK 64
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bits
#define INT1_BIT 7
#define INT1_MASK 128
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory address $002. See also “External Interrupts”.
sfrb GIFR = $3A;
#define INTF2_BIT 5
#define INTF2_MASK 32
When an event on the INT2 pin triggers an interrupt request,INTF2 becomes set (one).If the I bit in SREG and the INT2 bit in GICR are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt rou tine is executed.Alternatively,the flag can be cleared by writing a logical one to it.Note that when entering some sleep modes with the INT2 interrupt disabled,the input buffer on this pin will be disabled.This may cause a logic change in inter nal signals which will set the INTF2 flag
#define INTF0_BIT 6
#define INTF0_MASK 64
When an event on the INT0 pin triggers an interrupt request,INTF0 becomes set (one).If the I bit in SREG and the INT0 bit in GICR are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt rou tine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt.
#define INTF1_BIT 7
#define INTF1_MASK 128
When an event on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I bit in SREG and the INT1 bit in GICR are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT1 is configured as a level interrupt.
sfrb SREG = $3F;
sfrb SPH = $3E;
#define SP8_BIT 0
#define SP8_MASK 1
#define SP9_BIT 1
#define SP9_MASK 2
#define SP10_BIT 2
#define SP10_MASK 4
#define SP11_BIT 3
#define SP11_MASK 8
#define SP12_BIT 4
#define SP12_MASK 16
#define SP13_BIT 5
#define SP13_MASK 32
#define SP14_BIT 6
#define SP14_MASK 64
#define SP15_BIT 7
#define SP15_MASK 128
sfrb SPL = $3D;
#define SP0_BIT 0
#define SP0_MASK 1
#define SP1_BIT 1
#define SP1_MASK 2
#define SP2_BIT 2
#define SP2_MASK 4
#define SP3_BIT 3
#define SP3_MASK 8
#define SP4_BIT 4
#define SP4_MASK 16
#define SP5_BIT 5
#define SP5_MASK 32
#define SP6_BIT 6
#define SP6_MASK 64
#define SP7_BIT 7
#define SP7_MASK 128
sfrb MCUCR = $35;
#define ISC00_BIT 0
#define ISC00_MASK 1
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt.
#define ISC01_BIT 1
#define ISC01_MASK 2
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt.
#define ISC10_BIT 2
#define ISC10_MASK 4
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-bit and the corresponding interrupt mask in the GICR are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt.
#define ISC11_BIT 3
#define ISC11_MASK 8
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-bit and the corresponding interrupt mask in the GICR are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt.
#define SM1_BIT 4
#define SM1_MASK 16
The description is to long for the tooltip help, please refer to the manual
#define SE_BIT 5
#define SE_MASK 32
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.To avoid the MCU entering the sleep mode unless it is the programmers purpose,it is recommended to write the Sleep Enable (SE)bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up.
#define SRW10_BIT 6
#define SRW10_MASK 64
For a detailed description in non ATmega103 Compatibility mode, see common description for the SRWn bits below (XMRA description). In ATmega103 Compatibility mode, writing SRW10 to one enables the wait state and one extra cycle is added during read/write strobe as shown in Figure 14.
#define SRE_BIT 7
#define SRE_MASK 128
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are acti-vated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction regis-ters. Writing SRE to zero, disables the External Memory Interface and the normal pin and data direction settings are used.
sfrb MCUSR = $34;
#define PORF_BIT 0
#define PORF_MASK 1
This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.
#define EXTRF_BIT 1
#define EXTRF_MASK 2
This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
#define BORF_BIT 2
#define BORF_MASK 4
This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
#define WDRF_BIT 3
#define WDRF_MASK 8
This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
sfrb EMCUCR = $36;
#define ISC2_BIT 0
#define ISC2_MASK 1
The asynchronous external interrupt 2 is activated by the external pin INT2 if the SREG I-bit and the corresponding interrupt mask in GICR are set.If ISC2 is written to zero,a falling edge on INT2 activates the interrupt.If ISC2 is written to one,a rising edge on INT2 activates the interrupt.Edges on INT2 are registered asynchronously.Pulses on INT2 wider than the minimum pulse given width will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.When changing the ISC2 bit,an interrupt can occur.Therefore,it is recommended to first disable INT2 by clearing its Interrupt Enable bit in the GICR register.Then,the ISC2 bit can be changed.Finally, the INT2 interruptflag should becleared by writing a logical one to its Interrupt Flagbit (INTF2)in the GIFR register before the interrupt is re-enabled.
#define SRW11_BIT 1
#define SRW11_MASK 2
The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the external memory address space.
#define SRW00_BIT 2
#define SRW00_MASK 4
The SRW00 and SRW01 bits control the number of wait-states for the upper sector of the external memory address space.
#define SRW01_BIT 3
#define SRW01_MASK 8
The SRW00 and SRW01 bits control the number of wait-states for the upper sector of the external memory address space.
#define SRL0_BIT 4
#define SRL0_MASK 16
It is possible to configure different wait-states for different external memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits.The SRL2,SRL1,and SRL0 bits select the splitting of these sectors. By default,the SRL2,SRL1,and SRL0 bits are set to zero and the entire external memory address space is treated as one sector.When the entire SRAM address space is configured as one sector,the wait-states are configured by the SRW11 and SRW10 bits.
#define SRL1_BIT 5
#define SRL1_MASK 32
It is possible to configure different wait-states for different external memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits.The SRL2,SRL1,and SRL0 bits select the splitting of these sectors. By default,the SRL2,SRL1,and SRL0 bits are set to zero and the entire external memory address space is treated as one sector.When the entire SRAM address space is configured as one sector,the wait-states are configured by the SRW11 and SRW10 bits.
#define SRL2_BIT 6
#define SRL2_MASK 64
It is possible to configure different wait-states for different external memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits.The SRL2,SRL1,and SRL0 bits select the splitting of these sectors. By default,the SRL2,SRL1,and SRL0 bits are set to zero and the entire external memory address space is treated as one sector.When the entire SRAM address space is configured as one sector,the wait-states are configured by the SRW11 and SRW10 bits.
#define SM0_BIT 7
#define SM0_MASK 128
The Sleep Mode Select bits select between the five available sleep modes. See Datasheet.
sfrb SPMCR = $37;
#define SPMEN_BIT 0
#define SPMEN_MASK 1
#define PGERS_BIT 1
#define PGERS_MASK 2
#define PGWRT_BIT 2
#define PGWRT_MASK 4
#define BLBSET_BIT 3
#define BLBSET_MASK 8
sfrb TCCR0 = $33;
#define CS00_BIT 0
#define CS00_MASK 1
The three clock select bits select the clock source to be used by the Timer/Counter,
#define CS01_BIT 1
#define CS01_MASK 2
The three clock select bits select the clock source to be used by the Timer/Counter,
#define CS02_BIT 2
#define CS02_MASK 4
The three clock select bits select the clock source to be used by the Timer/Counter,
#define WGM01_BIT 3
#define WGM01_MASK 8
These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 51 and “Modes of Operation” on page 80.
#define COM00_BIT 4
#define COM00_MASK 16
These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set in order to enable the output driver. When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 52 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM)
#define COM01_BIT 5
#define COM01_MASK 32
These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set in order to enable the output driver. When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 52 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM)
#define WGM00_BIT 6
#define WGM00_MASK 64
These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 51 and “Modes of Operation” on page 80.
#define FOC0_BIT 7
#define FOC0_MASK 128
The FOC0 bit is only active when the WGM bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode. When writing a logical one to the FOC0 bit, an immediate compare match is forced on the waveform generation unit. The OC0 output is changed accord-ing to its COM01:0 bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the value present in the COM01:0 bits that determines the effect of the forced compare. A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0 as TOP. The FOC0 bit is always read as zero.
sfrb TCNT0 = $32;
#define TCNT0_0_BIT 0
#define TCNT0_0_MASK 1
#define TCNT0_1_BIT 1
#define TCNT0_1_MASK 2
#define TCNT0_2_BIT 2
#define TCNT0_2_MASK 4
#define TCNT0_3_BIT 3
#define TCNT0_3_MASK 8
#define TCNT0_4_BIT 4
#define TCNT0_4_MASK 16
#define TCNT0_5_BIT 5
#define TCNT0_5_MASK 32
#define TCNT0_6_BIT 6
#define TCNT0_6_MASK 64
#define TCNT0_7_BIT 7
#define TCNT0_7_MASK 128
sfrb OCR0 = $31;
#define OCR0_0_BIT 0
#define OCR0_0_MASK 1
#define OCR0_1_BIT 1
#define OCR0_1_MASK 2
#define OCR0_2_BIT 2
#define OCR0_2_MASK 4
#define OCR0_3_BIT 3
#define OCR0_3_MASK 8
#define OCR0_4_BIT 4
#define OCR0_4_MASK 16
#define OCR0_5_BIT 5
#define OCR0_5_MASK 32
#define OCR0_6_BIT 6
#define OCR0_6_MASK 64
#define OCR0_7_BIT 7
#define OCR0_7_MASK 128
sfrb TIMSK = $39;
#define OCIE0_BIT 0
#define OCIE0_MASK 1
When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, i.e. when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define TOIE0_BIT 1
#define TOIE0_MASK 2
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e. when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
sfrb TIFR = $38;
#define OCF0_BIT 0
#define OCF0_MASK 1
The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0 and the data in OCR0 - Output Compare Register0. OCF0 is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF0 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare match Interrupt Enable), and OCF0 are set (one), the Timer/Counter0 Compare match Interrupt is executed.
#define TOV0_BIT 1
#define TOV0_MASK 2
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter0 changes counting direction at $00.
sfrb SFIOR = $30;
#define PSR10_BIT 0
#define PSR10_MASK 1
When this bit is set (one)the Timer/Counter1 and Timer/Counter0 prescaler will be reset.The bit will be cleared by hard ware after the operation is performed.Writing a zero to this bit will have no effect.Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.This bit will always be read as zero.
The 8-bit Timer/Counter2 can select clock source from CK, prescaled CK, or external crystal input TOSC1. It can also be stopped as described in the section “Timer/Counter2 Control Register - TCCR2”. The status flags (overflow and compare match) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Register TCCR2. The interrupt enable/disable settings are found in “The Timer/Counter Interrupt Mask Register - TIMSK”. When Timer/Counter2 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. This module features a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. Timer/Counter2 can also be used as an 8-bit Pulse Width Modulator. In this mode, Timer/Counter2 and the output compare register serve as a glitch-free, stand-alone PWM with centered puls
sfrb TIMSK = $39;
#define OCIE2_BIT 2
#define OCIE2_MASK 4
When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt (at vector $006) is executed if a compare match in Timer/Counter2 occurs, i.e. when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define TOIE2_BIT 4
#define TOIE2_MASK 16
When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is
sfrb TIFR = $38;
#define OCF2_BIT 2
#define OCF2_MASK 4
The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2 - Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2 Compare match Interrupt Enable), and the OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed.
#define TOV2_BIT 4
#define TOV2_MASK 16
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In up/down PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00.
sfrb TCCR2 = $27;
#define CS20_BIT 0
#define CS20_MASK 1
The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.
#define CS21_BIT 1
#define CS21_MASK 2
The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.
#define CS22_BIT 2
#define CS22_MASK 4
The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.
#define CTC2_BIT 3
#define CTC2_MASK 8
These bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information.
#define COM20_BIT 4
#define COM20_MASK 16
The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function
#define COM21_BIT 5
#define COM21_MASK 32
The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function
#define PWM2_BIT 6
#define PWM2_MASK 64
#define FOC2_BIT 7
#define FOC2_MASK 128
Writing a logical one to this bit, forces a change in the compare match output pin PD7 (OC2) according to the values already set in COM21 and COM20. If the COM21 and COM20 bits are written in the same cycle as FOC2, the new settings will not take effect until next compare match or forced output compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM21 and COM20 happens as if a Compare Match had occurred, but no interrupt is generated, and the Timer/Counter will not be cleared even if CTC2 is set. The corresponding I/O pin must be set as an output pin for the FOC2 bit to have effect on the pin. The FOC2 bit will always be read as zero. Setting the FOC2 bit has no effect in PWM mode
sfrb TCNT2 = $23;
#define TCNT2-0_BIT 0
#define TCNT2-0_MASK 1
#define TCNT2-1_BIT 1
#define TCNT2-1_MASK 2
#define TCNT2-2_BIT 2
#define TCNT2-2_MASK 4
#define TCNT2-3_BIT 3
#define TCNT2-3_MASK 8
#define TCNT2-4_BIT 4
#define TCNT2-4_MASK 16
#define TCNT2-5_BIT 5
#define TCNT2-5_MASK 32
#define TCNT2-6_BIT 6
#define TCNT2-6_MASK 64
#define TCNT2-7_BIT 7
#define TCNT2-7_MASK 128
sfrb OCR2 = $22;
#define OCR2-0_BIT 0
#define OCR2-0_MASK 1
#define OCR2-1_BIT 1
#define OCR2-1_MASK 2
#define OCR2-2_BIT 2
#define OCR2-2_MASK 4
#define OCR2-3_BIT 3
#define OCR2-3_MASK 8
#define OCR2-4_BIT 4
#define OCR2-4_MASK 16
#define OCR2-5_BIT 5
#define OCR2-5_MASK 32
#define OCR2-6_BIT 6
#define OCR2-6_MASK 64
#define OCR2-7_BIT 7
#define OCR2-7_MASK 128
sfrb ASSR = $26;
#define TCR2UB_BIT 0
#define TCR2UB_MASK 1
When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set (one). When TCCR2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that TCCR2 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter2 registers while its update busy flag is set (one), the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary storage register is rea
#define OCR2UB_BIT 1
#define OCR2UB_MASK 2
When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set (one). When OCR2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that OCR2 is ready to be updated with a new value.
#define TCN2UB_BIT 2
#define TCN2UB_MASK 4
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set (one). When TCNT2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.
#define AS2_BIT 3
#define AS2_MASK 8
When AS2 is cleared (zero), Timer/Counter2 is clocked from the internal system clock, CK. When AS2 is set (one), Timer/Counter2 is clocked from the PC6(TOSC1) pin. Pins PC6 and PC7 are connected to a crystal oscillator and cannot be used as general I/O pins. When the value of this bit is changed, the contents of TCNT2, OCR2, and TCCR2 might be corrupted.
sfrb SFIOR = $30;
#define PSR2_BIT 1
#define PSR2_MASK 2
When this bit is set (one)the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.
sfrb TIMSK = $39;
#define TICIE1_BIT 3
#define TICIE1_MASK 8
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define OCIE1B_BIT 5
#define OCIE1B_MASK 32
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define OCIE1A_BIT 6
#define OCIE1A_MASK 64
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
#define TOIE1_BIT 7
#define TOIE1_MASK 128
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
sfrb TIFR = $38;
#define ICF1_BIT 3
#define ICF1_MASK 8
The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.
#define OCF1B_BIT 5
#define OCF1B_MASK 32
The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.
#define OCF1A_BIT 6
#define OCF1A_MASK 64
The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed.
#define TOV1_BIT 7
#define TOV1_MASK 128
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.
sfrb TCCR1A = $2F;
#define WGM10_BIT 0
#define WGM10_MASK 1
Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.
#define WGM11_BIT 1
#define WGM11_MASK 2
Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.
#define FOC1B_BIT 2
#define FOC1B_MASK 4
Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM1B1 and COM1B0.If the COM1B1 and COM1B0 bits are written in the same cycle as FOC1B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1B1 and COM1B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC1B bit to have effect on the pin. The FOC1B bit will always be read as zero. The setting of the FOC1B bit has no effect in PWM mode
#define FOC1A_BIT 3
#define FOC1A_MASK 8
Writing a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM1A1 and COM1A0.If the COM1A1 and COM1A0 bits are written in the same cycle as FOC1A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1A1 and COM1A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC1 in TCCR1B is set. The corresponding I/O pin must be set as an output pin for the FOC1A bit to have effect on the pin. The FOC1A bit will always be read as zero. The setting of the FOC1A bit has no effect in PWM mod
#define COM1B0_BIT 4
#define COM1B0_MASK 16
The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.
#define COM1B1_BIT 5
#define COM1B1_MASK 32
The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.
#define COM1A0_BIT 6
#define COM1A0_MASK 64
The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.
#define COM1A1_BIT 7
#define COM1A1_MASK 128
The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.
sfrb TCCR1B = $2E;
#define CS10_BIT 0
#define CS10_MASK 1
Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.
#define CS11_BIT 1
#define CS11_MASK 2
Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.
#define CS12_BIT 2
#define CS12_MASK 4
Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.
#define CTC1_BIT 3
#define CTC1_MASK 8
#define ICES1_BIT 6
#define ICES1_MASK 64
While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.
#define ICNC1_BIT 7
#define ICNC1_MASK 128
When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.
sfrb TCNT1H = $2D;
#define TCNT1H0_BIT 0
#define TCNT1H0_MASK 1
#define TCNT1H1_BIT 1
#define TCNT1H1_MASK 2
#define TCNT1H2_BIT 2
#define TCNT1H2_MASK 4
#define TCNT1H3_BIT 3
#define TCNT1H3_MASK 8
#define TCNT1H4_BIT 4
#define TCNT1H4_MASK 16
#define TCNT1H5_BIT 5
#define TCNT1H5_MASK 32
#define TCNT1H6_BIT 6
#define TCNT1H6_MASK 64
#define TCNT1H7_BIT 7
#define TCNT1H7_MASK 128
sfrb TCNT1L = $2C;
#define TCNT1L0_BIT 0
#define TCNT1L0_MASK 1
#define TCNT1L1_BIT 1
#define TCNT1L1_MASK 2
#define TCNT1L2_BIT 2
#define TCNT1L2_MASK 4
#define TCNT1L3_BIT 3
#define TCNT1L3_MASK 8
#define TCNT1L4_BIT 4
#define TCNT1L4_MASK 16
#define TCNT1L5_BIT 5
#define TCNT1L5_MASK 32
#define TCNT1L6_BIT 6
#define TCNT1L6_MASK 64
#define TCNT1L7_BIT 7
#define TCNT1L7_MASK 128
sfrb OCR1AH = $2B;
#define OCR1AH0_BIT 0
#define OCR1AH0_MASK 1
#define OCR1AH1_BIT 1
#define OCR1AH1_MASK 2
#define OCR1AH2_BIT 2
#define OCR1AH2_MASK 4
#define OCR1AH3_BIT 3
#define OCR1AH3_MASK 8
#define OCR1AH4_BIT 4
#define OCR1AH4_MASK 16
#define OCR1AH5_BIT 5
#define OCR1AH5_MASK 32
#define OCR1AH6_BIT 6
#define OCR1AH6_MASK 64
#define OCR1AH7_BIT 7
#define OCR1AH7_MASK 128
sfrb OCR1AL = $2A;
#define OCR1AL0_BIT 0
#define OCR1AL0_MASK 1
#define OCR1AL1_BIT 1
#define OCR1AL1_MASK 2
#define OCR1AL2_BIT 2
#define OCR1AL2_MASK 4
#define OCR1AL3_BIT 3
#define OCR1AL3_MASK 8
#define OCR1AL4_BIT 4
#define OCR1AL4_MASK 16
#define OCR1AL5_BIT 5
#define OCR1AL5_MASK 32
#define OCR1AL6_BIT 6
#define OCR1AL6_MASK 64
#define OCR1AL7_BIT 7
#define OCR1AL7_MASK 128
sfrb OCR1BH = $29;
#define OCR1BH0_BIT 0
#define OCR1BH0_MASK 1
#define OCR1BH1_BIT 1
#define OCR1BH1_MASK 2
#define OCR1BH2_BIT 2
#define OCR1BH2_MASK 4
#define OCR1BH3_BIT 3
#define OCR1BH3_MASK 8
#define OCR1BH4_BIT 4
#define OCR1BH4_MASK 16
#define OCR1BH5_BIT 5
#define OCR1BH5_MASK 32
#define OCR1BH6_BIT 6
#define OCR1BH6_MASK 64
#define OCR1BH7_BIT 7
#define OCR1BH7_MASK 128
sfrb OCR1BL = $28;
#define OCR1BL0_BIT 0
#define OCR1BL0_MASK 1
#define OCR1BL1_BIT 1
#define OCR1BL1_MASK 2
#define OCR1BL2_BIT 2
#define OCR1BL2_MASK 4
#define OCR1BL3_BIT 3
#define OCR1BL3_MASK 8
#define OCR1BL4_BIT 4
#define OCR1BL4_MASK 16
#define OCR1BL5_BIT 5
#define OCR1BL5_MASK 32
#define OCR1BL6_BIT 6
#define OCR1BL6_MASK 64
#define OCR1BL7_BIT 7
#define OCR1BL7_MASK 128
sfrb ICR1H = $25;
#define ICR1H0_BIT 0
#define ICR1H0_MASK 1
#define ICR1H1_BIT 1
#define ICR1H1_MASK 2
#define ICR1H2_BIT 2
#define ICR1H2_MASK 4
#define ICR1H3_BIT 3
#define ICR1H3_MASK 8
#define ICR1H4_BIT 4
#define ICR1H4_MASK 16
#define ICR1H5_BIT 5
#define ICR1H5_MASK 32
#define ICR1H6_BIT 6
#define ICR1H6_MASK 64
#define ICR1H7_BIT 7
#define ICR1H7_MASK 128
sfrb ICR1L = $24;
#define ICR1L0_BIT 0
#define ICR1L0_MASK 1
#define ICR1L1_BIT 1
#define ICR1L1_MASK 2
#define ICR1L2_BIT 2
#define ICR1L2_MASK 4
#define ICR1L3_BIT 3
#define ICR1L3_MASK 8
#define ICR1L4_BIT 4
#define ICR1L4_MASK 16
#define ICR1L5_BIT 5
#define ICR1L5_MASK 32
#define ICR1L6_BIT 6
#define ICR1L6_MASK 64
#define ICR1L7_BIT 7
#define ICR1L7_MASK 128
sfrb WDTCR = $21;
#define WDP0_BIT 0
#define WDP0_MASK 1
#define WDP1_BIT 1
#define WDP1_MASK 2
#define WDP2_BIT 2
#define WDP2_MASK 4
#define WDE_BIT 3
#define WDE_MASK 8
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog
#define WDTOE_BIT 4
#define WDTOE_MASK 16
This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.