This documentation was generated automatically from the AVR Studio part description file ATtiny28.pdf
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sfrb PORTD = $12;
#define PORTD0_BIT 0
#define PORTD0_MASK 1
#define PORTD1_BIT 1
#define PORTD1_MASK 2
#define PORTD2_BIT 2
#define PORTD2_MASK 4
#define PORTD3_BIT 3
#define PORTD3_MASK 8
#define PORTD4_BIT 4
#define PORTD4_MASK 16
#define PORTD5_BIT 5
#define PORTD5_MASK 32
#define PORTD6_BIT 6
#define PORTD6_MASK 64
#define PORTD7_BIT 7
#define PORTD7_MASK 128
sfrb DDRD = $11;
#define DDD0_BIT 0
#define DDD0_MASK 1
#define DDD1_BIT 1
#define DDD1_MASK 2
#define DDD2_BIT 2
#define DDD2_MASK 4
#define DDD3_BIT 3
#define DDD3_MASK 8
#define DDD4_BIT 4
#define DDD4_MASK 16
#define DDD5_BIT 5
#define DDD5_MASK 32
#define DDD6_BIT 6
#define DDD6_MASK 64
#define DDD7_BIT 7
#define DDD7_MASK 128
sfrb PIND = $10;
#define PIND0_BIT 0
#define PIND0_MASK 1
#define PIND1_BIT 1
#define PIND1_MASK 2
#define PIND2_BIT 2
#define PIND2_MASK 4
#define PIND3_BIT 3
#define PIND3_MASK 8
#define PIND4_BIT 4
#define PIND4_MASK 16
#define PIND5_BIT 5
#define PIND5_MASK 32
#define PIND6_BIT 6
#define PIND6_MASK 64
#define PIND7_BIT 7
#define PIND7_MASK 128
sfrb SREG = $3F;
sfrb ICR = $06;
#define ISC00_BIT 0
#define ISC00_MASK 1
#define ISC01_BIT 1
#define ISC01_MASK 2
#define ICS10_BIT 2
#define ICS10_MASK 4
#define ICS11_BIT 3
#define ICS11_MASK 8
sfrb MCUCS = $07;
#define PORF_BIT 0
#define PORF_MASK 1
This bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchanged
#define EXTRF_BIT 1
#define EXTRF_MASK 2
After a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged.
#define WDRF_BIT 3
#define WDRF_MASK 8
#define SM_BIT 4
#define SM_MASK 16
This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode. When SM is set (one), Power Down mode is selected as sleep mode. For details, refer to the section “Sleep Modes” on page 25.
#define SE_BIT 5
#define SE_MASK 32
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.
#define PLUPB_BIT 7
#define PLUPB_MASK 128
When the PLUPB bit is set (one), pull-up resistors are enabled on all Port B input pins.
sfrb OSCCAL = $00;
#define CAL0_BIT 0
#define CAL0_MASK 1
#define CAL1_BIT 1
#define CAL1_MASK 2
#define CAL2_BIT 2
#define CAL2_MASK 4
#define CAL3_BIT 3
#define CAL3_MASK 8
#define CAL4_BIT 4
#define CAL4_MASK 16
#define CAL5_BIT 5
#define CAL5_MASK 32
#define CAL6_BIT 6
#define CAL6_MASK 64
#define CAL7_BIT 7
#define CAL7_MASK 128
The analog comparator compares the input values on the positive input PB2 (AIN0) and negative input PB3 (AIN1). When the voltage on the positive input PB2 (AIN0) is higher than the voltage on the negative input PB3 (AIN1), the Analog Com-parator Output, ACO is set (one). The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Inter-rupt triggering on comparator output rise, fall or toggle
sfrb ACSR = $08;
#define ACIS0_BIT 0
#define ACIS0_MASK 1
These bits determine which comparator events that trigger the Analog Comparator interrupt.
#define ACIS1_BIT 1
#define ACIS1_MASK 2
These bits determine which comparator events that trigger the Analog Comparator interrupt.
#define ACIE_BIT 3
#define ACIE_MASK 8
When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the analog comparator interrupt is activated. When Cleared (Zero), the interrupt is disabled.
#define ACI_BIT 4
#define ACI_MASK 16
This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. Observe however, that if another bit in this register is modified using the SBI or CBI instruction, ACI will be cleared if it has become set before the operation
#define ACO_BIT 5
#define ACO_MASK 32
When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
#define ACD_BIT 7
#define ACD_MASK 128
When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in “Timer/Counter0 Control Register - TCCR0” on page 35. The overflow status flag is found in “The Timer/Counter Interrupt Flag Register - TIFR” on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in “The Timer/Counter Interrupt Mask Regis-ter - TIMSK” on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions
sfrb ICR = $06;
#define TOIE0_BIT 4
#define TOIE0_MASK 16
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
sfrb IFR = $05;
#define TOV0_BIT 4
#define TOV0_MASK 16
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.
sfrb TCCR0 = $04;
#define CS00_BIT 0
#define CS00_MASK 1
#define CS01_BIT 1
#define CS01_MASK 2
#define CS02_BIT 2
#define CS02_MASK 4
#define OOM00_BIT 3
#define OOM00_MASK 8
The OOM01 and OOM00 control bits determine any output pin action following an overflow or a forced overflow in Timer/Counter0.
#define OOM01_BIT 4
#define OOM01_MASK 16
The OOM01 and OOM00 control bits determine any output pin action following an overflow or a forced overflow in Timer/Counter0.
#define FOV0_BIT 7
#define FOV0_MASK 128
Writing a logical "1" to this bit forces a change on the overflow output pin PA2 according to the values already set in OOM01 and OOM00.
sfrb TCNT0 = $03;
#define TCNT00_BIT 0
#define TCNT00_MASK 1
#define TCNT01_BIT 1
#define TCNT01_MASK 2
#define TCNT02_BIT 2
#define TCNT02_MASK 4
#define TCNT03_BIT 3
#define TCNT03_MASK 8
#define TCNT04_BIT 4
#define TCNT04_MASK 16
#define TCNT05_BIT 5
#define TCNT05_MASK 32
#define TCNT06_BIT 6
#define TCNT06_MASK 64
#define TCNT07_BIT 7
#define TCNT07_MASK 128
sfrb WDTCR = $01;
#define WDP0_BIT 0
#define WDP0_MASK 1
#define WDP1_BIT 1
#define WDP1_MASK 2
#define WDP2_BIT 2
#define WDP2_MASK 4
#define WDE_BIT 3
#define WDE_MASK 8
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog
#define WDTOE_BIT 4
#define WDTOE_MASK 16
This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.
sfrb ICR = $06;
#define LLIE_BIT 5
#define LLIE_MASK 32
When the LLIE is set (one) and the I-bit in the status register (SREG) is set (one), the interrupt on low-level input is activated. Any of the Port B pins pulled low will then cause an interrupt.
#define INT0_BIT 6
#define INT0_MASK 64
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.The interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) define whether the external interrupt is activated on rising or falling edge, on pin change or low level of the INT0 pin.
#define INT1_BIT 7
#define INT1_MASK 128
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.The interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) define whether the external interrupt is activated on rising or falling edge, on pin change or low level of the INT0 pin.
sfrb IFR = $05;
#define INTF0_BIT 6
#define INTF0_MASK 64
When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in ICR are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
#define INTF1_BIT 7
#define INTF1_MASK 128
When the INT1 bit is set (one) and I-bit in the Status Register (SREG) is set (one), the external pin interrupt 1 is enabled.
sfrb PORTA = $1B;
#define PORTA0_BIT 0
#define PORTA0_MASK 1
#define PORTA1_BIT 1
#define PORTA1_MASK 2
#define PORTA2_BIT 2
#define PORTA2_MASK 4
#define PORTA3_BIT 3
#define PORTA3_MASK 8
sfrb PACR = $1A;
#define DDA0_BIT 0
#define DDA0_MASK 1
#define DDA1_BIT 1
#define DDA1_MASK 2
#define PA2HC_BIT 2
#define PA2HC_MASK 4
#define DDA3_BIT 3
#define DDA3_MASK 8
sfrb PINA = $19;
#define PINA0_BIT 0
#define PINA0_MASK 1
#define PINA1_BIT 1
#define PINA1_MASK 2
#define PINA3_BIT 3
#define PINA3_MASK 8
sfrb PINB = $16;
#define PINB0_BIT 0
#define PINB0_MASK 1
#define PINB1_BIT 1
#define PINB1_MASK 2
#define PINB2_BIT 2
#define PINB2_MASK 4
#define PINB3_BIT 3
#define PINB3_MASK 8
#define PINB4_BIT 4
#define PINB4_MASK 16
#define PINB5_BIT 5
#define PINB5_MASK 32
#define PINB6_BIT 6
#define PINB6_MASK 64
#define PINB7_BIT 7
#define PINB7_MASK 128
sfrb MODCR = $02;
#define MCONF0_BIT 0
#define MCONF0_MASK 1
MODCONF[2:0] determine the relationship between the on- and off-times of the modulat or , and thereby the duty-cycle.
#define MCONF1_BIT 1
#define MCONF1_MASK 2
MODCONF[2:0] determine the relationship between the on- and off-times of the modulat or , and thereby the duty-cycle.
#define MCONF2_BIT 2
#define MCONF2_MASK 4
MODCONF[2:0] determine the relationship between the on- and off-times of the modulat or , and thereby the duty-cycle.
#define ONTIM0_BIT 3
#define ONTIM0_MASK 8
ONTIM[4:0] +1 determines the number of clock cycles the output pin PA2 is active (low)
#define ONTIM1_BIT 4
#define ONTIM1_MASK 16
ONTIM[4:0] +1 determines the number of clock cycles the output pin PA2 is active (low)
#define ONTIM2_BIT 5
#define ONTIM2_MASK 32
ONTIM[4:0] +1 determines the number of clock cycles the output pin PA2 is active (low)
#define OTIM3_BIT 6
#define OTIM3_MASK 64
ONTIM[4:0] +1 determines the number of clock cycles the output pin PA2 is active (low)
#define ONTIM4_BIT 7
#define ONTIM4_MASK 128
ONTIM[4:0] +1 determines the number of clock cycles the output pin PA2 is active (low)