NXP LPC1000 CPU Support Package
This package contains project templates and system files for the NXP LPC1000.
Package Installation Instructions
CrossWorks Version 2.x Installation Instructions
To install this support package using CrossStudio:
- Click the Tools > Package Manager menu option to open the package manager window.
- Right click on the NXP LPC1000 CPU Support Package entry and select Install Selected Packages.
- Click Next to take you to the summary page.
- Click Next to install the package.
- Click Finish to close the package manager window.
Alternatively, to manually install this support package:
- Download the file LPC1000.hzq using your web browser.
- Click the Tools > Manually Install Packages menu option.
- Select the file you have just downloaded to install the package.
Package Version History
1.17
- Added support for LPC11Uxx devices.
1.16
- Fixed debugging of IAP functions on LPC177x/8x devices running at 120MHz.
1.15
- Added support for LPC11D14/302 and LPC12D27/301 devices.
- Updated LPC11Cxx and LPC11xx support files.
- Added EABI versions of libraries.
1.14
- Corrected definition of LPC13xx USB device interrupt registers.
- Corrected definition of __NVIC_PRIO_BITS in LPC11xx.h CMSIS file.
- Simulator now works with latest reset script.
1.13
- Added support for LPC111x/102/202/302 (LPC1100L series), LPC11C22/301 and LPC11C24/301 devices.
- Compiling LPC1000.h with an invalid __TARGET_PROCESSOR definition now generates an error.
1.12
- Added support for LPC122x devices.
- Now using CMSIS version 2.0.
- Updated LPC177x and LPC178x support files.
1.11
- Reset scripts now work with devices without nSRST.
1.10
- Fixed externally built executable project template.
- Updated LPC177x and LPC178x support files.
1.9
- Added support for LPC177x and LPC178x devices.
1.8
- Fixed LPC1111/101 and LPC1112/101 loader.
- Added support for LPC11C12 and LPC11C14.
- Corrected definition of LPC17xx CAN BTR register.
- Corrected definition of LPC17xx EMAC MRDD register.
- Corrected definition of LPC17xx USB USBDevIntClr and USBDevIntSet registers.
- Corrected definition of LPC17xx I2SSTATE, I2SDMA1, I2SDMA2, I2SIRQ registers.
- Corrected definition of I2C MMCTRL register.
- Corrected definition of UART FIFOLVL register.
- Renamed LPC17xx ADTRIM register to AD0TRM.
- LPC17xx simulator will now finish executing CMSIS startup code.
1.7
- Corrected definition of PCONP register.
- Added IAP status code definitions to liblpc1000.h.
- Updated CMSIS files to latest version. Note that you will need to add the -fms-extensions compiler option to existing projects to avoid anonymous structure warnings.
- Now uses CMSIS startup code. Existing projects will need to add the $(TargetsDir)/LPC1000/include/CMSIS/system_LPC11xx.c, $(TargetsDir)/LPC1000/include/CMSIS/system_LPC13xx.c or $(TargetsDir)/LPC1000/include/CMSIS/system_LPC17xx.c file in order to build.
- Added LPC17xx peripheral bit-band definitions.
1.6
- Added support for LPC1763.
1.5
- Corrected the definition of the SCKLOC register in the LPC13xx header and memory map files.
- Added support for LPC1111/101, LPC1112/101, LPC1113/201 and LPC1114/201 devices.
- Boot loader initialization code is now run on reset.
- Added missing LPC1100 loader startup code.
1.4
- Added support for LPC11xx devices. Please note that LPC11xx support requires CrossWorks for ARM version 2.0.5 or later.
1.3
- Corrected the definition of the UxFIFOLVL register.
- Corrected the definition of the EXTERNAL bit in the DFSR register.
- Updated LPC17xx.h CMSIS header file to latest version.
- Fixed bug in LPC1300 startup code.
1.2
- Added support for LPC13xx devices.
- Added support for latest revisions of existing LPC17xx devices.
- Added support for LPC1759, LPC1767 and LPC1769.
- Corrected memory maps for LPC17xx devices with 32K of SRAM.
- The vector table offset register is now always configured to allow the start address of FLASH configuration programs to be moved away from 0x00000000 without modification of startup code.
1.1
- Startup code now configures CCLK to 100MHz with a 4MHz main clock.
- Startup code now configures CCLK to 100MHz rather than 72MHz with a 12MHz main clock.
1.0
- Initial Release.