Package Title LPC1000 CPU Support Package
Package Version 1.4
Required Additional Packages None
CPU NXP LPC1000
Required CrossStudio Version 2.0 or later

This package contains project templates and system files for the LPC1000.

Package Installation Instructions

CrossWorks Version 2.x Installation Instructions

To install this support package using CrossStudio:

  1. Click the Tools > Package Manager menu option to open the package manager window.
  2. Right click on the LPC1000 CPU Support Package entry and select Install Selected Packages.
  3. Click Next to take you to the summary page.
  4. Click Next to install the package.
  5. Click Finish to close the package manager window.

Alternatively, to manually install this support package:

  1. Download the file LPC1000.hzq using your web browser.
  2. Click the Tools > Manually Install Packages menu option.
  3. Select the file you have just downloaded to install the package.

Supported Targets

LPC1111, LPC1112, LPC1113, LPC1114, LPC1311, LPC1313, LPC1342, LPC1343, LPC1751, LPC1752, LPC1754, LPC1756, LPC1758, LPC1759, LPC1764, LPC1765, LPC1766, LPC1767, LPC1768, LPC1769.

Package Version History

1.4

  • Added support for LPC11xx devices. Please note that LPC11xx support requires CrossWorks for ARM version 2.0.5 or later.

1.3

  • Corrected the definition of the UxFIFOLVL register.
  • Corrected the definition of the EXTERNAL bit in the DFSR register.
  • Updated LPC17xx.h CMSIS header file to latest version.
  • Fixed bug in LPC1300 startup code.

1.2

  • Added support for LPC13xx devices.
  • Added support for latest revisions of existing LPC17xx devices.
  • Added support for LPC1759, LPC1767 and LPC1769.
  • Corrected memory maps for LPC17xx devices with 32K of SRAM.
  • The vector table offset register is now always configured to allow the start address of FLASH configuration programs to be moved away from 0x00000000 without modification of startup code.

1.1

  • Startup code now configures CCLK to 100MHz with a 4MHz main clock.
  • Startup code now configures CCLK to 100MHz rather than 72MHz with a 12MHz main clock.

1.0

  • Initial Release.