The ARM Simulator target interface provides access to CrossStudio's ARM instruction set simulator (ISS). The ISS simulates the ARM V4T, ARM V5TE, ARM V6-M, ARM V7-M, ARM V7-EM, ARM V7A and ARMV7R instruction sets, as defined in the appropriate ARM Architecture Reference Manuals. The ARM architecture, core type and memory byte order to be simulated are specified by the project's code-generation properties.
The ISS supports a limited subset of VFP instructions (CP10 and CP11) that enables C programs that use the VFP to execute. NEON instructions are not simulated.
The instruction set simulator (ISS) supports MCR and MRC access to the 16 primary registers of the System Control coprocessor (CP15), as defined in the ARM Architecture Reference Manual. The ISS supports MCR and MRC access to the Debug Communication Channel (CP14), as defined in the ARM7TDMI Technical Reference Manual.
The instruction set simulator (ISS) simulates the PPB, bit banding and systick capabilities of the ARM V6-M, ARM V7-M and ARM V7-EM architectures.
The memory system simulated by the ISS is implemented by the dynamic link library specified by the Memory Simulation Filename and Memory Simulation Parameter defined in the project's simulator properties. Any access to memory not defined by the memory system is reported as an error.
The ISS supports program loading and debugging with an unlimited number of breakpoints. The ISS supports instruction tracing, execution counts, exception-vector trapping, and exception-vector triggering.